From patchwork Tue Apr 9 12:53:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhen Lei X-Patchwork-Id: 161976 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp4908228jan; Tue, 9 Apr 2019 05:54:21 -0700 (PDT) X-Google-Smtp-Source: APXvYqwJmTL91OZGlPftxudxTLrKYJ7UhU6MsAponm9A4nUAUEzCVFoO7fwAVt+lg+1bYSaE1Yg7 X-Received: by 2002:a63:243:: with SMTP id 64mr34329110pgc.214.1554814461217; Tue, 09 Apr 2019 05:54:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1554814461; cv=none; d=google.com; s=arc-20160816; b=yU9/yRxEF2r37KHKP+3RATjq5L44vNkoVUnfQUslZG+eTTN2Fdd1ltX5BD51OByUcs 9nQAjtsGt6aNCDUXP4U8byvZDa6wp1ILYQiXyLaJ5ZisAsCgA1W2yLkMVDZ3/1bExrpk 8sfHDzn0qOzCVT55VlBB220fLopmcCtz2Eitf9Qj6O11eiJRHX09UyehO7zvOJ7WSWLj JcR1sr25IO4UchVUvcBeYAyBof9RgRQfyGOUSZ6llg/b9Ogb/o0xIX2YSa5sLh026U7M XM/CG3kJrTBTPUkIyTjLZM3aB52HxOlMEn6ez8eR30yxaVoeYlB02QCzUqA4mA/6/vc8 HlBA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=ymkthyqzd4LqW49qGhcBPUApx3sNSlhPVYf4gLep4u8=; b=skM5a0uS45Gc9uAcp5vx7Ra177NFAcXoij6I9uLisaiWfa+QjCzK9Cjzw1goEYGOTM ZW1VunBHMqmjPp3uDxoYiAQgx1UqP1KDPPrwTjlo2RwBs8qUAW3kKFIFgMnjQJVbP+Xj 2GvBOkY2iuFYVK+7OVkR3vA7diG51wUq4aGFZ22cWKnpXn6+TN5L83R+SqYwRQE/HlFT fvyM5zyowQQIsu7g8VvkLvISKK9kGQ47pibfFGAlejhJJkoy8yLoaG8p0gQlOKLgk4Y4 WHwcSZ2UkK0mrUa1aUkQoG+iFFp/Gqab7YIo+zx4cHZLLJIBfnNw1AVoSRBINQNJXpzs TEug== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g136si31089845pfb.29.2019.04.09.05.54.20; Tue, 09 Apr 2019 05:54:21 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727302AbfDIMyT (ORCPT + 31 others); Tue, 9 Apr 2019 08:54:19 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:44310 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726875AbfDIMyS (ORCPT ); Tue, 9 Apr 2019 08:54:18 -0400 Received: from DGGEMS414-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 4A97C6D5654AA5909F20; Tue, 9 Apr 2019 20:54:10 +0800 (CST) Received: from HGHY1l002753561.china.huawei.com (10.177.23.164) by DGGEMS414-HUB.china.huawei.com (10.3.19.214) with Microsoft SMTP Server id 14.3.408.0; Tue, 9 Apr 2019 20:54:01 +0800 From: Zhen Lei To: Jean-Philippe Brucker , John Garry , Robin Murphy , Will Deacon , Joerg Roedel , Jonathan Corbet , linux-doc , Sebastian Ott , Gerald Schaefer , "Martin Schwidefsky" , Heiko Carstens , Benjamin Herrenschmidt , Paul Mackerras , "Michael Ellerman" , Tony Luck , Fenghua Yu , Thomas Gleixner , Ingo Molnar , Borislav Petkov , "H . Peter Anvin" , David Woodhouse , iommu , linux-kernel , linux-s390 , linuxppc-dev , x86 , linux-ia64 CC: Zhen Lei , Hanjun Guo Subject: [PATCH v5 1/6] iommu: add generic boot option iommu.dma_mode Date: Tue, 9 Apr 2019 20:53:03 +0800 Message-ID: <20190409125308.18304-2-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.19.2.windows.1 In-Reply-To: <20190409125308.18304-1-thunder.leizhen@huawei.com> References: <20190409125308.18304-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.23.164] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Currently the IOMMU dma contains 3 modes: passthrough, lazy, strict. The passthrough mode bypass the IOMMU, the lazy mode defer the invalidation of hardware TLBs, and the strict mode invalidate IOMMU hardware TLBs synchronously. The three modes are mutually exclusive. But the current boot options are confused, such as: iommu.passthrough and iommu.strict, because they are no good to be coexist. So add iommu.dma_mode. Signed-off-by: Zhen Lei --- Documentation/admin-guide/kernel-parameters.txt | 19 ++++++++ drivers/iommu/iommu.c | 59 ++++++++++++++++++++----- include/linux/iommu.h | 5 +++ 3 files changed, 71 insertions(+), 12 deletions(-) -- 1.8.3 diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index 2b8ee90bb64470d..f7766f8ac8b9084 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -1811,6 +1811,25 @@ 1 - Bypass the IOMMU for DMA. unset - Use value of CONFIG_IOMMU_DEFAULT_PASSTHROUGH. + iommu.dma_mode= Configure default dma mode. if unset, use the value + of CONFIG_IOMMU_DEFAULT_PASSTHROUGH to determine + passthrough or not. + Note: For historical reasons, ARM64/S390/PPC/X86 have + their specific options. Currently, only ARM64 support + this boot option, and hope other ARCHs to use this as + generic boot option. + passthrough + Configure DMA to bypass the IOMMU by default. + lazy + Request that DMA unmap operations use deferred + invalidation of hardware TLBs, for increased + throughput at the cost of reduced device isolation. + Will fall back to strict mode if not supported by + the relevant IOMMU driver. + strict + DMA unmap operations invalidate IOMMU hardware TLBs + synchronously. + io7= [HW] IO7 for Marvel based alpha systems See comment before marvel_specify_io7 in arch/alpha/kernel/core_marvel.c. diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index 109de67d5d727c2..df1ce8e22385b48 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -38,12 +38,13 @@ static struct kset *iommu_group_kset; static DEFINE_IDA(iommu_group_ida); + #ifdef CONFIG_IOMMU_DEFAULT_PASSTHROUGH -static unsigned int iommu_def_domain_type = IOMMU_DOMAIN_IDENTITY; +#define IOMMU_DEFAULT_DMA_MODE IOMMU_DMA_MODE_PASSTHROUGH #else -static unsigned int iommu_def_domain_type = IOMMU_DOMAIN_DMA; +#define IOMMU_DEFAULT_DMA_MODE IOMMU_DMA_MODE_STRICT #endif -static bool iommu_dma_strict __read_mostly = true; +static int iommu_default_dma_mode __read_mostly = IOMMU_DEFAULT_DMA_MODE; struct iommu_callback_data { const struct iommu_ops *ops; @@ -147,20 +148,51 @@ static int __init iommu_set_def_domain_type(char *str) int ret; ret = kstrtobool(str, &pt); - if (ret) - return ret; + if (!ret && pt) + iommu_default_dma_mode = IOMMU_DMA_MODE_PASSTHROUGH; - iommu_def_domain_type = pt ? IOMMU_DOMAIN_IDENTITY : IOMMU_DOMAIN_DMA; - return 0; + return ret; } early_param("iommu.passthrough", iommu_set_def_domain_type); static int __init iommu_dma_setup(char *str) { - return kstrtobool(str, &iommu_dma_strict); + bool strict; + int ret; + + ret = kstrtobool(str, &strict); + if (!ret) + iommu_default_dma_mode = strict ? + IOMMU_DMA_MODE_STRICT : IOMMU_DMA_MODE_LAZY; + + return ret; } early_param("iommu.strict", iommu_dma_setup); +static int __init iommu_dma_mode_setup(char *str) +{ + if (!str) + goto fail; + + if (!strncmp(str, "passthrough", 11)) + iommu_default_dma_mode = IOMMU_DMA_MODE_PASSTHROUGH; + else if (!strncmp(str, "lazy", 4)) + iommu_default_dma_mode = IOMMU_DMA_MODE_LAZY; + else if (!strncmp(str, "strict", 6)) + iommu_default_dma_mode = IOMMU_DMA_MODE_STRICT; + else + goto fail; + + pr_info("Force dma mode to be %d\n", iommu_default_dma_mode); + + return 0; + +fail: + pr_debug("Boot option iommu.dma_mode is incorrect, ignored\n"); + return -EINVAL; +} +early_param("iommu.dma_mode", iommu_dma_mode_setup); + static ssize_t iommu_group_attr_show(struct kobject *kobj, struct attribute *__attr, char *buf) { @@ -1102,14 +1134,17 @@ struct iommu_group *iommu_group_get_for_dev(struct device *dev) */ if (!group->default_domain) { struct iommu_domain *dom; + int def_domain_type = + (iommu_default_dma_mode == IOMMU_DMA_MODE_PASSTHROUGH) + ? IOMMU_DOMAIN_IDENTITY : IOMMU_DOMAIN_DMA; - dom = __iommu_domain_alloc(dev->bus, iommu_def_domain_type); - if (!dom && iommu_def_domain_type != IOMMU_DOMAIN_DMA) { + dom = __iommu_domain_alloc(dev->bus, def_domain_type); + if (!dom && def_domain_type != IOMMU_DOMAIN_DMA) { dom = __iommu_domain_alloc(dev->bus, IOMMU_DOMAIN_DMA); if (dom) { dev_warn(dev, "failed to allocate default IOMMU domain of type %u; falling back to IOMMU_DOMAIN_DMA", - iommu_def_domain_type); + def_domain_type); } } @@ -1117,7 +1152,7 @@ struct iommu_group *iommu_group_get_for_dev(struct device *dev) if (!group->domain) group->domain = dom; - if (dom && !iommu_dma_strict) { + if (dom && (iommu_default_dma_mode == IOMMU_DMA_MODE_LAZY)) { int attr = 1; iommu_domain_set_attr(dom, DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE, diff --git a/include/linux/iommu.h b/include/linux/iommu.h index ffbbc7e39ceeba3..c3f4e3416176496 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -42,6 +42,11 @@ */ #define IOMMU_PRIV (1 << 5) + +#define IOMMU_DMA_MODE_STRICT 0x0 +#define IOMMU_DMA_MODE_LAZY 0x1 +#define IOMMU_DMA_MODE_PASSTHROUGH 0x2 + struct iommu_ops; struct iommu_group; struct bus_type; From patchwork Tue Apr 9 12:53:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhen Lei X-Patchwork-Id: 161977 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp4908291jan; Tue, 9 Apr 2019 05:54:25 -0700 (PDT) X-Google-Smtp-Source: APXvYqw5MAsow8pXHWfHIAc3yrDbXldB7//nUL+gv6biRLu9viymsY4a5+n/9dTb8yHjN6uomZsw X-Received: by 2002:a63:28f:: with SMTP id 137mr34014830pgc.377.1554814465548; Tue, 09 Apr 2019 05:54:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1554814465; cv=none; d=google.com; s=arc-20160816; b=m/H9e0CBMH0aAcbxQwxvyS00ywRvDcl4/gHA8Enjofdl1MHaq+5rBCg73nDDDid3nQ eX34r3FV6hmXOG1x9lVtZMjDjIZdzTy5BfYXpTMMskNaq9HDsVkoHjnlRjWkbCC/MIRr r+QePdGs9Y4SRiy1hdSHgjfJbAnbeCjqNsoMs9pPflgSpfn9DvbRUxzUfoTiYjq72PUP W/6jpgoNM8ZJFDN96mWMhPUp6KjO3SQ7TuMCu3HM9G28txyp1Qg4QXJaXSGe0z4JwMT8 rUAi+MZ3S9SkiyU0/mQ65jN1GuNn7uKsfMaB2TAowYYp+H4x+VWj7HGPeW8bU/BMpQGv RgGw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=n9MxK2qgbst+c6vdOm6J7JZiCUW/6odB8aLV6YA072s=; b=oO5ztVc7NK6aP/aPr8CjccSl2E577SPavn0Frhg+tl7hk3tYl42WU7Oh8l8Wps5FNG 95dWgNZgaGbFUVr0gRmNo6FOqtL52t0fc/Fn3i5h7cjD8KrG8pTLq+hdxkLRFMYzJtDQ H6fXSxv8D1h9du6lIGaFoojbol53yRSgiGK2Ol1VGCLYoGiu7W4sRTnTSjpIPeD3nTVb qQxNwzOScVTJw8EBaTboSKp1Ety6FaaFcd3YIM2hc1zd/U5E/GN/hGJfHacge17SHJ9s AjHzjei0kExo1mFckVFMX1kLrrW65hvZzMqGagSTNdPAAlYk6NYiMzzkzlzo25CD4g2x 1vMQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g136si31089845pfb.29.2019.04.09.05.54.25; Tue, 09 Apr 2019 05:54:25 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727323AbfDIMyY (ORCPT + 31 others); Tue, 9 Apr 2019 08:54:24 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:44348 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726112AbfDIMyT (ORCPT ); Tue, 9 Apr 2019 08:54:19 -0400 Received: from DGGEMS414-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 56FD4951C8FD7825B0D0; Tue, 9 Apr 2019 20:54:10 +0800 (CST) Received: from HGHY1l002753561.china.huawei.com (10.177.23.164) by DGGEMS414-HUB.china.huawei.com (10.3.19.214) with Microsoft SMTP Server id 14.3.408.0; Tue, 9 Apr 2019 20:54:03 +0800 From: Zhen Lei To: Jean-Philippe Brucker , John Garry , Robin Murphy , Will Deacon , Joerg Roedel , Jonathan Corbet , linux-doc , Sebastian Ott , Gerald Schaefer , "Martin Schwidefsky" , Heiko Carstens , Benjamin Herrenschmidt , Paul Mackerras , "Michael Ellerman" , Tony Luck , Fenghua Yu , Thomas Gleixner , Ingo Molnar , Borislav Petkov , "H . Peter Anvin" , David Woodhouse , iommu , linux-kernel , linux-s390 , linuxppc-dev , x86 , linux-ia64 CC: Zhen Lei , Hanjun Guo Subject: [PATCH v5 2/6] iommu: add build options corresponding to iommu.dma_mode Date: Tue, 9 Apr 2019 20:53:04 +0800 Message-ID: <20190409125308.18304-3-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.19.2.windows.1 In-Reply-To: <20190409125308.18304-1-thunder.leizhen@huawei.com> References: <20190409125308.18304-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.23.164] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org First, add build option IOMMU_DEFAULT_{LAZY|STRICT}, so that we have the opportunity to set {lazy|strict} mode as default at build time. Then put the three config options in an choice, make people can only choose one of the three at a time, the same to the boot options iommu.dma_mode. Signed-off-by: Zhen Lei --- Documentation/admin-guide/kernel-parameters.txt | 6 ++-- drivers/iommu/Kconfig | 43 +++++++++++++++++++++---- drivers/iommu/iommu.c | 4 ++- 3 files changed, 42 insertions(+), 11 deletions(-) -- 1.8.3 diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index f7766f8ac8b9084..92d1b3151d003c2 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -1811,9 +1811,9 @@ 1 - Bypass the IOMMU for DMA. unset - Use value of CONFIG_IOMMU_DEFAULT_PASSTHROUGH. - iommu.dma_mode= Configure default dma mode. if unset, use the value - of CONFIG_IOMMU_DEFAULT_PASSTHROUGH to determine - passthrough or not. + iommu.dma_mode= Configure default dma mode. if unset, use the build + options(such as CONFIG_IOMMU_DEFAULT_PASSTHROUGH) to + choose which mode to be used. Note: For historical reasons, ARM64/S390/PPC/X86 have their specific options. Currently, only ARM64 support this boot option, and hope other ARCHs to use this as diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig index 6f07f3b21816c64..1986f9767da488b 100644 --- a/drivers/iommu/Kconfig +++ b/drivers/iommu/Kconfig @@ -74,17 +74,46 @@ config IOMMU_DEBUGFS debug/iommu directory, and then populate a subdirectory with entries as required. -config IOMMU_DEFAULT_PASSTHROUGH - bool "IOMMU passthrough by default" +choice + prompt "IOMMU dma mode" depends on IOMMU_API - help - Enable passthrough by default, removing the need to pass in - iommu.passthrough=on or iommu=pt through command line. If this - is enabled, you can still disable with iommu.passthrough=off - or iommu=nopt depending on the architecture. + default IOMMU_DEFAULT_STRICT + help + This option allows IOMMU dma mode to be chose at build time, to + override the default dma mode of each ARCHs, removing the need to + pass in kernel parameters through command line. You can still use the + generic boot option iommu.dma_mode or ARCHs specific boot options to + override this option again. + +config IOMMU_DEFAULT_PASSTHROUGH + bool "passthrough" + help + In this mode, the dma access through IOMMU without any addresses + transformation. That means, the wrong or illegal dma access can not + be caught, no error information will be reported. If unsure, say N here. +config IOMMU_DEFAULT_LAZY + bool "lazy" + help + Support lazy mode, where for every IOMMU DMA unmap operation, the + flush operation of IOTLB and the free operation of IOVA are deferred. + They are only guaranteed to be done before the related IOVA will be + reused. + +config IOMMU_DEFAULT_STRICT + bool "strict" + help + For every IOMMU DMA unmap operation, the flush operation of IOTLB and + the free operation of IOVA are guaranteed to be done in the unmap + function. + + This mode is safer than the two above, but it maybe slow in some high + performace scenarios. + +endchoice + config OF_IOMMU def_bool y depends on OF && IOMMU_API diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index df1ce8e22385b48..f4171bf4b46eaeb 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -39,8 +39,10 @@ static struct kset *iommu_group_kset; static DEFINE_IDA(iommu_group_ida); -#ifdef CONFIG_IOMMU_DEFAULT_PASSTHROUGH +#if defined(CONFIG_IOMMU_DEFAULT_PASSTHROUGH) #define IOMMU_DEFAULT_DMA_MODE IOMMU_DMA_MODE_PASSTHROUGH +#elif defined(CONFIG_IOMMU_DEFAULT_LAZY) +#define IOMMU_DEFAULT_DMA_MODE IOMMU_DMA_MODE_LAZY #else #define IOMMU_DEFAULT_DMA_MODE IOMMU_DMA_MODE_STRICT #endif From patchwork Tue Apr 9 12:53:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhen Lei X-Patchwork-Id: 161978 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp4908422jan; Tue, 9 Apr 2019 05:54:35 -0700 (PDT) X-Google-Smtp-Source: APXvYqx38xZaU92kCpXzZPuxGNrByCMa/vhcJBKWdwyhFMA5mDkWdQSV/VrOXXEd6WJ9rHAzaV8O X-Received: by 2002:a65:62c9:: with SMTP id m9mr32126175pgv.309.1554814475061; Tue, 09 Apr 2019 05:54:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1554814475; cv=none; d=google.com; s=arc-20160816; b=PvXn211r2AmTmauDonuZLDjIjwbWUxzl9rl9Y2jahNS/f35mS5ejyX8LBqkDu9Z52q VO31eevlIuF3dB3o6rfx4bRKuQtHxsj1iTZm/OHpVgZ5uixStS7u8MrJ9FkL/hoJ0tRj YcGoxyJQl/MJaUp752gDraBs+EXcy2g6x/SEF+CfsS0Y+PyqEJvOexATe60Tu9RZOvoH 4iI8nhbSc9b+4Ze7HgnPTiWI80Sn1OCoQC1dqIj+wG8eHwmAefvs/fr+yfue4VsULccL RKRIrZLeQC9F/EHUrInXYl9xT7n9oXk3dp+vQhuq7eUITaRgnmFfQXwjHfxtNCiGd99y xzgg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=mzqzfWBcwUEVjS6JKDTPORaNV8F9sxYMwrB2wEdzZjY=; b=KI/eKvagvgkHfy/oh9QQdUou4ZIIn6SBQ5EZs02XeJ9KIVIP9gZZ5cchM7QoWLKxX4 ChWT+bfX6/58EnQhtV5EG+5MwR5+L211H9TslkmmFPz/YKatQXid7UX94R+4aAHKBerG sOc3qKoubDP6sZiCUr6WjWgtJeGQHrrXQUyz2SymwsbDroXcUEs83JlQHCX8Z/suiejW FvVCPdBBODkdBYTcrpzdghdcxSAJvfuIE8cV1LZA8vmG86CJlB6II+Z5LUUd1Ybm5L18 DxvxFd9cljlLO985ygrFE6D+3BO489Sadf0PCEeHh8m7GPuEAhKXDItKx0eWM4pgnPNa QktA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Peter Anvin" , David Woodhouse , iommu , linux-kernel , linux-s390 , linuxppc-dev , x86 , linux-ia64 CC: Zhen Lei , Hanjun Guo Subject: [PATCH v5 3/6] iommu: add iommu_default_dma_mode_get/set() helper Date: Tue, 9 Apr 2019 20:53:05 +0800 Message-ID: <20190409125308.18304-4-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.19.2.windows.1 In-Reply-To: <20190409125308.18304-1-thunder.leizhen@huawei.com> References: <20190409125308.18304-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.23.164] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Also add IOMMU_DMA_MODE_IS_{STRICT|LAZT|PASSTHROUGH}() to make the code looks cleaner. There is no functional change, just prepare for the following patches. Signed-off-by: Zhen Lei --- drivers/iommu/iommu.c | 18 ++++++++++++++---- include/linux/iommu.h | 18 ++++++++++++++++++ 2 files changed, 32 insertions(+), 4 deletions(-) -- 1.8.3 diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index f4171bf4b46eaeb..86239dd46003fd4 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -195,6 +195,17 @@ static int __init iommu_dma_mode_setup(char *str) } early_param("iommu.dma_mode", iommu_dma_mode_setup); +int iommu_default_dma_mode_get(void) +{ + return iommu_default_dma_mode; +} + +void iommu_default_dma_mode_set(int mode) +{ + WARN_ON(mode > IOMMU_DMA_MODE_PASSTHROUGH); + iommu_default_dma_mode = mode; +} + static ssize_t iommu_group_attr_show(struct kobject *kobj, struct attribute *__attr, char *buf) { @@ -1136,9 +1147,8 @@ struct iommu_group *iommu_group_get_for_dev(struct device *dev) */ if (!group->default_domain) { struct iommu_domain *dom; - int def_domain_type = - (iommu_default_dma_mode == IOMMU_DMA_MODE_PASSTHROUGH) - ? IOMMU_DOMAIN_IDENTITY : IOMMU_DOMAIN_DMA; + int def_domain_type = IOMMU_DMA_MODE_IS_PASSTHROUGH() ? + IOMMU_DOMAIN_IDENTITY : IOMMU_DOMAIN_DMA; dom = __iommu_domain_alloc(dev->bus, def_domain_type); if (!dom && def_domain_type != IOMMU_DOMAIN_DMA) { @@ -1154,7 +1164,7 @@ struct iommu_group *iommu_group_get_for_dev(struct device *dev) if (!group->domain) group->domain = dom; - if (dom && (iommu_default_dma_mode == IOMMU_DMA_MODE_LAZY)) { + if (dom && IOMMU_DMA_MODE_IS_LAZY()) { int attr = 1; iommu_domain_set_attr(dom, DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE, diff --git a/include/linux/iommu.h b/include/linux/iommu.h index c3f4e3416176496..3668a8b3846996a 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -46,6 +46,12 @@ #define IOMMU_DMA_MODE_STRICT 0x0 #define IOMMU_DMA_MODE_LAZY 0x1 #define IOMMU_DMA_MODE_PASSTHROUGH 0x2 +#define IOMMU_DMA_MODE_IS_STRICT() \ + (iommu_default_dma_mode_get() == IOMMU_DMA_MODE_STRICT) +#define IOMMU_DMA_MODE_IS_LAZY() \ + (iommu_default_dma_mode_get() == IOMMU_DMA_MODE_LAZY) +#define IOMMU_DMA_MODE_IS_PASSTHROUGH() \ + (iommu_default_dma_mode_get() == IOMMU_DMA_MODE_PASSTHROUGH) struct iommu_ops; struct iommu_group; @@ -421,6 +427,9 @@ static inline void dev_iommu_fwspec_set(struct device *dev, int iommu_probe_device(struct device *dev); void iommu_release_device(struct device *dev); +extern int iommu_default_dma_mode_get(void); +extern void iommu_default_dma_mode_set(int mode); + #else /* CONFIG_IOMMU_API */ struct iommu_ops {}; @@ -705,6 +714,15 @@ const struct iommu_ops *iommu_ops_from_fwnode(struct fwnode_handle *fwnode) return NULL; } +static inline int iommu_default_dma_mode_get(void) +{ + return IOMMU_DMA_MODE_PASSTHROUGH; +} + +static inline void iommu_default_dma_mode_set(int mode) +{ +} + #endif /* CONFIG_IOMMU_API */ #ifdef CONFIG_IOMMU_DEBUGFS From patchwork Tue Apr 9 12:53:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhen Lei X-Patchwork-Id: 161980 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp4910861jan; Tue, 9 Apr 2019 05:57:31 -0700 (PDT) X-Google-Smtp-Source: APXvYqzvzWyUJHiQxRLIM9E+KrhhsrySPPtAjs8DQ5lCAmR8sKMJVRoN8SUYGERJFMi1iT+f/R4u X-Received: by 2002:a65:4341:: with SMTP id k1mr34973067pgq.88.1554814651622; Tue, 09 Apr 2019 05:57:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1554814651; cv=none; d=google.com; s=arc-20160816; b=QZpP1LSUmB2Q77qjx38dkdMtV7Eq3Ff8PQMfo8/iwtT/14CoA0lN9BxSlWCP8hwBQM SbQ8zfhlXV2swH0j64al1Ej53BwvKowRXXS4FixFQqEg33hJb6BRgnlDIQs07sk6a8hN BdZz7VkZkC//5YYlMWSbepwiHex4q98Tsk/UxVZK58hgcwtqTjR40KoO5SlYtEo+Vpls 8IWlp8c+j6B90vS9iWD7gLDBwVVvZLwUbeyTdGDWMD8qbpSUhlwwfH821eahad49WK7q 8PaViPQqtp6RISnguckkgqpCkw6GYDdcRoIuIh7EYI5BSmvc4G+zUoJzu4/TwBiGLN8E ex2A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=UmXWmyeGD3B3vDnObRdPPPKDXrAOO6ia5LjcoJiTiKY=; b=OnGHIuRKG51Vuye75YhbQZgPJcAz+wguTgF3z+D/yzvIEx6j7k6q+4iCi0+mYw9UqL Ytk74J8VXxfAXGaW2vJGl4sA4RfSe2Evo9ilhw6IuVIaT5Jwms0btzkcMC/CpujpL5Dk 9XONIl5dCiHIiTSB+tHr1M30ZVWKk06K2eOe1vG/LfKTzTTImDyA71a4hcCGl01miWsc /OBWeJRxIq3K7JGi3J3M4zpJBhrOy6hhevKjprrOEF1DLGylPlMPNH3eQsOP7CQkS9yX TVOtRSs9+1X0x5aEm7ZrlHpLyM/fAm2FjDDN5Y0A7JrCzjYlBySgR5BaB9jJDr25gxHB e4yg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id p6si30601705pgp.459.2019.04.09.05.57.31; Tue, 09 Apr 2019 05:57:31 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727321AbfDIM5a (ORCPT + 31 others); Tue, 9 Apr 2019 08:57:30 -0400 Received: from szxga07-in.huawei.com ([45.249.212.35]:33590 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727030AbfDIM51 (ORCPT ); Tue, 9 Apr 2019 08:57:27 -0400 Received: from DGGEMS414-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 69556E42FB4B562EA00F; Tue, 9 Apr 2019 20:54:15 +0800 (CST) Received: from HGHY1l002753561.china.huawei.com (10.177.23.164) by DGGEMS414-HUB.china.huawei.com (10.3.19.214) with Microsoft SMTP Server id 14.3.408.0; Tue, 9 Apr 2019 20:54:06 +0800 From: Zhen Lei To: Jean-Philippe Brucker , John Garry , Robin Murphy , Will Deacon , Joerg Roedel , Jonathan Corbet , linux-doc , Sebastian Ott , Gerald Schaefer , "Martin Schwidefsky" , Heiko Carstens , Benjamin Herrenschmidt , Paul Mackerras , "Michael Ellerman" , Tony Luck , Fenghua Yu , Thomas Gleixner , Ingo Molnar , Borislav Petkov , "H . Peter Anvin" , David Woodhouse , iommu , linux-kernel , linux-s390 , linuxppc-dev , x86 , linux-ia64 CC: Zhen Lei , Hanjun Guo Subject: [PATCH v5 4/6] s390/pci: add support for generic boot option iommu.dma_mode Date: Tue, 9 Apr 2019 20:53:06 +0800 Message-ID: <20190409125308.18304-5-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.19.2.windows.1 In-Reply-To: <20190409125308.18304-1-thunder.leizhen@huawei.com> References: <20190409125308.18304-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.23.164] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org s390_iommu=strict is equivalent to iommu.dma_mode=strict. Signed-off-by: Zhen Lei --- Documentation/admin-guide/kernel-parameters.txt | 6 +++--- arch/s390/pci/pci_dma.c | 14 +++++++------- drivers/iommu/Kconfig | 1 + 3 files changed, 11 insertions(+), 10 deletions(-) -- 1.8.3 Acked-by: Sebastian Ott diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index 92d1b3151d003c2..ab8e3c4798c0a2a 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -1815,9 +1815,9 @@ options(such as CONFIG_IOMMU_DEFAULT_PASSTHROUGH) to choose which mode to be used. Note: For historical reasons, ARM64/S390/PPC/X86 have - their specific options. Currently, only ARM64 support - this boot option, and hope other ARCHs to use this as - generic boot option. + their specific options. Currently, only ARM64/S390 + support this boot option, and hope other ARCHs to use + this as generic boot option. passthrough Configure DMA to bypass the IOMMU by default. lazy diff --git a/arch/s390/pci/pci_dma.c b/arch/s390/pci/pci_dma.c index 9e52d1527f71495..f658ca41547eed5 100644 --- a/arch/s390/pci/pci_dma.c +++ b/arch/s390/pci/pci_dma.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -17,7 +18,6 @@ static struct kmem_cache *dma_region_table_cache; static struct kmem_cache *dma_page_table_cache; -static int s390_iommu_strict; static int zpci_refresh_global(struct zpci_dev *zdev) { @@ -193,13 +193,13 @@ static int __dma_purge_tlb(struct zpci_dev *zdev, dma_addr_t dma_addr, if (!zdev->tlb_refresh) return 0; } else { - if (!s390_iommu_strict) + if (!IOMMU_DMA_MODE_IS_STRICT()) return 0; } ret = zpci_refresh_trans((u64) zdev->fh << 32, dma_addr, PAGE_ALIGN(size)); - if (ret == -ENOMEM && !s390_iommu_strict) { + if (ret == -ENOMEM && !IOMMU_DMA_MODE_IS_STRICT()) { /* enable the hypervisor to free some resources */ if (zpci_refresh_global(zdev)) goto out; @@ -278,7 +278,7 @@ static dma_addr_t dma_alloc_address(struct device *dev, int size) spin_lock_irqsave(&zdev->iommu_bitmap_lock, flags); offset = __dma_alloc_iommu(dev, zdev->next_bit, size); if (offset == -1) { - if (!s390_iommu_strict) { + if (!IOMMU_DMA_MODE_IS_STRICT()) { /* global flush before DMA addresses are reused */ if (zpci_refresh_global(zdev)) goto out_error; @@ -313,7 +313,7 @@ static void dma_free_address(struct device *dev, dma_addr_t dma_addr, int size) if (!zdev->iommu_bitmap) goto out; - if (s390_iommu_strict) + if (IOMMU_DMA_MODE_IS_STRICT()) bitmap_clear(zdev->iommu_bitmap, offset, size); else bitmap_set(zdev->lazy_bitmap, offset, size); @@ -584,7 +584,7 @@ int zpci_dma_init_device(struct zpci_dev *zdev) rc = -ENOMEM; goto free_dma_table; } - if (!s390_iommu_strict) { + if (!IOMMU_DMA_MODE_IS_STRICT()) { zdev->lazy_bitmap = vzalloc(zdev->iommu_pages / 8); if (!zdev->lazy_bitmap) { rc = -ENOMEM; @@ -675,7 +675,7 @@ void zpci_dma_exit(void) static int __init s390_iommu_setup(char *str) { if (!strncmp(str, "strict", 6)) - s390_iommu_strict = 1; + iommu_default_dma_mode_set(IOMMU_DMA_MODE_STRICT); return 0; } diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig index 1986f9767da488b..b7173b106cd816a 100644 --- a/drivers/iommu/Kconfig +++ b/drivers/iommu/Kconfig @@ -77,6 +77,7 @@ config IOMMU_DEBUGFS choice prompt "IOMMU dma mode" depends on IOMMU_API + default IOMMU_DEFAULT_LAZY if S390_IOMMU default IOMMU_DEFAULT_STRICT help This option allows IOMMU dma mode to be chose at build time, to From patchwork Tue Apr 9 12:53:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhen Lei X-Patchwork-Id: 161979 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp4910788jan; Tue, 9 Apr 2019 05:57:27 -0700 (PDT) X-Google-Smtp-Source: APXvYqzqIV71RZkTKV+MIFN5Va9rPqozAbWY55aWh1MPcV/9pSQ9ALi9gRMNm/C+WpR3RfaD1jvb X-Received: by 2002:a17:902:1c1:: with SMTP id b59mr19272094plb.182.1554814647323; Tue, 09 Apr 2019 05:57:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1554814647; cv=none; d=google.com; s=arc-20160816; b=P3ibmhxd/U+kdzYY7nTQd7zKoVYqSEE3V5k1dsXKNKGlXyErsmoQ/TIlKJmcnuHdRQ 9zU00hQFIDyGYcS3ISEF1KTNB1qnPMlNJkSzpHbIhP+ufJ+qHM9IK6NdV34OzYFwvL0g p/CdaHlmgTtQLcKVWAHEfOG9oOoZ8VD42F3kc8yFuNTvJH8orsitThzHWL2b8VaCxyT8 O+L8kOcSgQMAvB0BIWCDSyuTlv4SxgGTsFenIyehFXdi0c4gL/Ay7ndp5kRl2b0nPa4O HIGJh3IJN6kpEo6SdoSwRpB0Wsqdri7kOJeSUrXzGNntcaL4B6JIu/dLvlpECsgBm/3M 7/Xg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=nUiOWUlNwn2ScYVtN5qGZNB60YmmFAtsrven/Q8H8bY=; b=L8uFDMbaemWqIWb9MoOLwAmveDdRyya90ItZ+2s/7ftxpkcscFHRds/UXeWQAiqtTw aWXOtpc+itq0TRgGOcc3Z8dMHBbcU3d0bO4MMhs0CpZoXgc/MKzyW/0Rb+qsh74mi05U q8/wGsOyBXLmlEkr3Qyk8Bmd1AzdMIDhobwCl1cs5dNktzd1Lr4VKwBPWrLBxuiFxeJL 6tz4CHSq4Z4awgi1RqIRYSdMe3uHXnCZJN0gfWakKmBu4ebCPHJm3Jyj8xOSqpQKnKYn NjQSKoJoENYcJBXIZw19HjTEfn8Ej8bYKS8I4kRPkPSEROUb+GSK3XK83UL1YUhmnVK8 dCaw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Peter Anvin" , David Woodhouse , iommu , linux-kernel , linux-s390 , linuxppc-dev , x86 , linux-ia64 CC: Zhen Lei , Hanjun Guo Subject: [PATCH v5 5/6] powernv/iommu: add support for generic boot option iommu.dma_mode Date: Tue, 9 Apr 2019 20:53:07 +0800 Message-ID: <20190409125308.18304-6-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.19.2.windows.1 In-Reply-To: <20190409125308.18304-1-thunder.leizhen@huawei.com> References: <20190409125308.18304-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.23.164] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org iommu=nobypass can be replaced with iommu.dma_mode=strict. Signed-off-by: Zhen Lei --- Documentation/admin-guide/kernel-parameters.txt | 2 +- arch/powerpc/platforms/powernv/pci-ioda.c | 5 ++--- drivers/iommu/Kconfig | 1 + 3 files changed, 4 insertions(+), 4 deletions(-) -- 1.8.3 diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index ab8e3c4798c0a2a..176f96032d9d62a 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -1815,7 +1815,7 @@ options(such as CONFIG_IOMMU_DEFAULT_PASSTHROUGH) to choose which mode to be used. Note: For historical reasons, ARM64/S390/PPC/X86 have - their specific options. Currently, only ARM64/S390 + their specific options. Currently, only ARM64/S390/PPC support this boot option, and hope other ARCHs to use this as generic boot option. passthrough diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c b/arch/powerpc/platforms/powernv/pci-ioda.c index 3ead4c237ed0ec9..8862885d866418f 100644 --- a/arch/powerpc/platforms/powernv/pci-ioda.c +++ b/arch/powerpc/platforms/powernv/pci-ioda.c @@ -85,7 +85,6 @@ void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, va_end(args); } -static bool pnv_iommu_bypass_disabled __read_mostly; static bool pci_reset_phbs __read_mostly; static int __init iommu_setup(char *str) @@ -95,7 +94,7 @@ static int __init iommu_setup(char *str) while (*str) { if (!strncmp(str, "nobypass", 8)) { - pnv_iommu_bypass_disabled = true; + iommu_default_dma_mode_set(IOMMU_DMA_MODE_STRICT); pr_info("PowerNV: IOMMU bypass window disabled.\n"); break; } @@ -2456,7 +2455,7 @@ static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe) return rc; } - if (!pnv_iommu_bypass_disabled) + if (IOMMU_DMA_MODE_IS_PASSTHROUGH()) pnv_pci_ioda2_set_bypass(pe, true); return 0; diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig index b7173b106cd816a..5dca666b22e6cd5 100644 --- a/drivers/iommu/Kconfig +++ b/drivers/iommu/Kconfig @@ -77,6 +77,7 @@ config IOMMU_DEBUGFS choice prompt "IOMMU dma mode" depends on IOMMU_API + default IOMMU_DEFAULT_PASSTHROUGH if (PPC_POWERNV && PCI) default IOMMU_DEFAULT_LAZY if S390_IOMMU default IOMMU_DEFAULT_STRICT help From patchwork Tue Apr 9 12:53:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhen Lei X-Patchwork-Id: 161981 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp4910890jan; Tue, 9 Apr 2019 05:57:34 -0700 (PDT) X-Google-Smtp-Source: APXvYqyNTSaReHLzQVzhkh8OT6kcNRefycNCJJrxsCHpc+yXn+QCSTEmMsNgv0hZIKaDxc9PDJzO X-Received: by 2002:a65:4589:: with SMTP id o9mr17278404pgq.381.1554814653992; Tue, 09 Apr 2019 05:57:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1554814653; cv=none; d=google.com; s=arc-20160816; b=CzAabmYDjyyDCUdJ2R3GZVlb0/2NVX5aQQGgGbIVSEwnzoo5qtP4uLzRofzq4gWT7h +5d/cWdoMN5h+S/sA8IvXv+8CiUaan63EYGy95mpkqE+oQAjr0ZHC/mIbB6op3UcCNMG pHK/x5rZi6srB1P5u8e3N5izDh6phcjJO+Zk3DakRmlvBE7++w5TDCDiQD3Tu+qiKQEf WJ7aq8JF+ZV3PIebxHoJdSLlO9neLemkAdGlp4fXEsGgz8BcMXQQcvjHWJss8duLzY+t VSc26kn1XTQw75uulxhOv4bg1j05yspXdhqUNqhertKoZOATEb2Ldqnmd6r9R1CQg3qY wtKA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=bE+fvKaAKn+HuqZuBmXJDEcLr7EDkmuRZkxgGCKl4fM=; b=LyYcj4pbzSpptpjhjKdfYZNFl/QFgLPz9swiW2f47GDBC7noDQ5MR1ABE/7xB5FP6A UwAVTNL6G4Td4lF7Idav7Fa9pFv+Rus7JG2j2Kqqg/JiuDQ4j6aYnPFUc6mRQEXa/hlY aAvDm/U9l8TAJ+TMmKe9+QL48LkqcMx0krES0OWCyJJmsjPpH/2XZ9sxpcT8M6GQfySV IP54AMlM8XzUcvW0lm0HrWj7JXwBZknnIUZJ5Wb+zO5YBGz3ez4Nxu9SIZhgX6vzmfF0 /g90StL+8Zj8C7r2SgJ4helxm38JYyNM2RC2M5Kyg7yYbh+fWhVfV/1eALDV+1EQfhhd Dbpw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id o2si28890703pll.388.2019.04.09.05.57.33; Tue, 09 Apr 2019 05:57:33 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727359AbfDIM5b (ORCPT + 31 others); Tue, 9 Apr 2019 08:57:31 -0400 Received: from szxga07-in.huawei.com ([45.249.212.35]:33512 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726908AbfDIM5a (ORCPT ); Tue, 9 Apr 2019 08:57:30 -0400 Received: from DGGEMS414-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 502FCF91CEADC68235D3; Tue, 9 Apr 2019 20:54:15 +0800 (CST) Received: from HGHY1l002753561.china.huawei.com (10.177.23.164) by DGGEMS414-HUB.china.huawei.com (10.3.19.214) with Microsoft SMTP Server id 14.3.408.0; Tue, 9 Apr 2019 20:54:09 +0800 From: Zhen Lei To: Jean-Philippe Brucker , John Garry , Robin Murphy , Will Deacon , Joerg Roedel , Jonathan Corbet , linux-doc , Sebastian Ott , Gerald Schaefer , "Martin Schwidefsky" , Heiko Carstens , Benjamin Herrenschmidt , Paul Mackerras , "Michael Ellerman" , Tony Luck , Fenghua Yu , Thomas Gleixner , Ingo Molnar , Borislav Petkov , "H . Peter Anvin" , David Woodhouse , iommu , linux-kernel , linux-s390 , linuxppc-dev , x86 , linux-ia64 CC: Zhen Lei , Hanjun Guo Subject: [PATCH v5 6/6] x86/iommu: add support for generic boot option iommu.dma_mode Date: Tue, 9 Apr 2019 20:53:08 +0800 Message-ID: <20190409125308.18304-7-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.19.2.windows.1 In-Reply-To: <20190409125308.18304-1-thunder.leizhen@huawei.com> References: <20190409125308.18304-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.23.164] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following equivalence or replacement relationship exists: iommu=pt <--> iommu.dma_mode=passthrough. iommu=nopt can be replaced with iommu.dma_mode=lazy. intel_iommu=strict <--> iommu.dma_mode=strict. amd_iommu=fullflush <--> iommu.dma_mode=strict. Signed-off-by: Zhen Lei --- Documentation/admin-guide/kernel-parameters.txt | 6 ++--- arch/ia64/include/asm/iommu.h | 2 -- arch/ia64/kernel/pci-dma.c | 2 -- arch/x86/include/asm/iommu.h | 1 - arch/x86/kernel/pci-dma.c | 35 ++++++++++++------------- drivers/iommu/Kconfig | 2 +- drivers/iommu/amd_iommu.c | 10 +++---- drivers/iommu/amd_iommu_init.c | 4 +-- drivers/iommu/amd_iommu_types.h | 6 ----- drivers/iommu/intel-iommu.c | 9 +++---- 10 files changed, 31 insertions(+), 46 deletions(-) -- 1.8.3 diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index 176f96032d9d62a..ca6edc529d6a614 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -1815,9 +1815,9 @@ options(such as CONFIG_IOMMU_DEFAULT_PASSTHROUGH) to choose which mode to be used. Note: For historical reasons, ARM64/S390/PPC/X86 have - their specific options. Currently, only ARM64/S390/PPC - support this boot option, and hope other ARCHs to use - this as generic boot option. + their specific options, but strongly recommended switch + to use this one, the new ARCHs should use this generic + boot option. passthrough Configure DMA to bypass the IOMMU by default. lazy diff --git a/arch/ia64/include/asm/iommu.h b/arch/ia64/include/asm/iommu.h index 7429a72f3f92199..92aceef63710861 100644 --- a/arch/ia64/include/asm/iommu.h +++ b/arch/ia64/include/asm/iommu.h @@ -8,10 +8,8 @@ extern void no_iommu_init(void); #ifdef CONFIG_INTEL_IOMMU extern int force_iommu, no_iommu; -extern int iommu_pass_through; extern int iommu_detected; #else -#define iommu_pass_through (0) #define no_iommu (1) #define iommu_detected (0) #endif diff --git a/arch/ia64/kernel/pci-dma.c b/arch/ia64/kernel/pci-dma.c index fe988c49f01ce6a..f5d49cd3fbb01a9 100644 --- a/arch/ia64/kernel/pci-dma.c +++ b/arch/ia64/kernel/pci-dma.c @@ -22,8 +22,6 @@ int force_iommu __read_mostly; #endif -int iommu_pass_through; - static int __init pci_iommu_init(void) { if (iommu_detected) diff --git a/arch/x86/include/asm/iommu.h b/arch/x86/include/asm/iommu.h index baedab8ac5385f7..b91623d521d9f0f 100644 --- a/arch/x86/include/asm/iommu.h +++ b/arch/x86/include/asm/iommu.h @@ -4,7 +4,6 @@ extern int force_iommu, no_iommu; extern int iommu_detected; -extern int iommu_pass_through; /* 10 seconds */ #define DMAR_OPERATION_TIMEOUT ((cycles_t) tsc_khz*10*1000) diff --git a/arch/x86/kernel/pci-dma.c b/arch/x86/kernel/pci-dma.c index d460998ae828514..fc64928e47cb860 100644 --- a/arch/x86/kernel/pci-dma.c +++ b/arch/x86/kernel/pci-dma.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include @@ -34,21 +35,6 @@ /* Set this to 1 if there is a HW IOMMU in the system */ int iommu_detected __read_mostly = 0; -/* - * This variable becomes 1 if iommu=pt is passed on the kernel command line. - * If this variable is 1, IOMMU implementations do no DMA translation for - * devices and allow every device to access to whole physical memory. This is - * useful if a user wants to use an IOMMU only for KVM device assignment to - * guests and not for driver dma translation. - * It is also possible to disable by default in kernel config, and enable with - * iommu=nopt at boot time. - */ -#ifdef CONFIG_IOMMU_DEFAULT_PASSTHROUGH -int iommu_pass_through __read_mostly = 1; -#else -int iommu_pass_through __read_mostly; -#endif - extern struct iommu_table_entry __iommu_table[], __iommu_table_end[]; /* Dummy device used for NULL arguments (normally ISA). */ @@ -139,10 +125,23 @@ static __init int iommu_setup(char *p) if (!strncmp(p, "soft", 4)) swiotlb = 1; #endif + + /* + * IOMMU implementations do no DMA translation for devices and + * allow every device to access to whole physical memory. This + * is useful if a user wants to use an IOMMU only for KVM + * device assignment to guests and not for driver dma + * translation. + */ if (!strncmp(p, "pt", 2)) - iommu_pass_through = 1; - if (!strncmp(p, "nopt", 4)) - iommu_pass_through = 0; + iommu_default_dma_mode_set(IOMMU_DMA_MODE_PASSTHROUGH); + + /* + * The default dma mode is lazy on X86. And if dma mode is + * already nopt, keep it no change. + */ + if (!strncmp(p, "nopt", 4) && IOMMU_DMA_MODE_IS_PASSTHROUGH()) + iommu_default_dma_mode_set(IOMMU_DMA_MODE_LAZY); gart_parse_options(p); diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig index 5dca666b22e6cd5..ace8cb467d742f9 100644 --- a/drivers/iommu/Kconfig +++ b/drivers/iommu/Kconfig @@ -78,7 +78,7 @@ choice prompt "IOMMU dma mode" depends on IOMMU_API default IOMMU_DEFAULT_PASSTHROUGH if (PPC_POWERNV && PCI) - default IOMMU_DEFAULT_LAZY if S390_IOMMU + default IOMMU_DEFAULT_LAZY if (AMD_IOMMU || INTEL_IOMMU || S390_IOMMU) default IOMMU_DEFAULT_STRICT help This option allows IOMMU dma mode to be chose at build time, to diff --git a/drivers/iommu/amd_iommu.c b/drivers/iommu/amd_iommu.c index f7cdd2ab7f11f6c..44be42f1e887ea4 100644 --- a/drivers/iommu/amd_iommu.c +++ b/drivers/iommu/amd_iommu.c @@ -448,7 +448,7 @@ static int iommu_init_device(struct device *dev) * invalid address), we ignore the capability for the device so * it'll be forced to go into translation mode. */ - if ((iommu_pass_through || !amd_iommu_force_isolation) && + if ((IOMMU_DMA_MODE_IS_PASSTHROUGH() || !amd_iommu_force_isolation) && dev_is_pci(dev) && pci_iommuv2_capable(to_pci_dev(dev))) { struct amd_iommu *iommu; @@ -2274,7 +2274,7 @@ static int amd_iommu_add_device(struct device *dev) BUG_ON(!dev_data); - if (iommu_pass_through || dev_data->iommu_v2) + if (IOMMU_DMA_MODE_IS_PASSTHROUGH() || dev_data->iommu_v2) iommu_request_dm_for_dev(dev); /* Domains are initialized for this device - have a look what we ended up with */ @@ -2479,7 +2479,7 @@ static void __unmap_single(struct dma_ops_domain *dma_dom, start += PAGE_SIZE; } - if (amd_iommu_unmap_flush) { + if (IOMMU_DMA_MODE_IS_STRICT()) { domain_flush_tlb(&dma_dom->domain); domain_flush_complete(&dma_dom->domain); dma_ops_free_iova(dma_dom, dma_addr, pages); @@ -2853,10 +2853,10 @@ int __init amd_iommu_init_api(void) int __init amd_iommu_init_dma_ops(void) { - swiotlb = (iommu_pass_through || sme_me_mask) ? 1 : 0; + swiotlb = (IOMMU_DMA_MODE_IS_PASSTHROUGH() || sme_me_mask) ? 1 : 0; iommu_detected = 1; - if (amd_iommu_unmap_flush) + if (IOMMU_DMA_MODE_IS_STRICT()) pr_info("IO/TLB flush on unmap enabled\n"); else pr_info("Lazy IO/TLB flushing enabled\n"); diff --git a/drivers/iommu/amd_iommu_init.c b/drivers/iommu/amd_iommu_init.c index 1b1378619fc9ec2..eae18aae2bafd39 100644 --- a/drivers/iommu/amd_iommu_init.c +++ b/drivers/iommu/amd_iommu_init.c @@ -166,8 +166,6 @@ struct ivmd_header { to handle */ LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings we find in ACPI */ -bool amd_iommu_unmap_flush; /* if true, flush on every unmap */ - LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the system */ @@ -2857,7 +2855,7 @@ static int __init parse_amd_iommu_options(char *str) { for (; *str; ++str) { if (strncmp(str, "fullflush", 9) == 0) - amd_iommu_unmap_flush = true; + iommu_default_dma_mode_set(IOMMU_DMA_MODE_STRICT); if (strncmp(str, "off", 3) == 0) amd_iommu_disabled = true; if (strncmp(str, "force_isolation", 15) == 0) diff --git a/drivers/iommu/amd_iommu_types.h b/drivers/iommu/amd_iommu_types.h index 87965e4d964771b..724182f158523a1 100644 --- a/drivers/iommu/amd_iommu_types.h +++ b/drivers/iommu/amd_iommu_types.h @@ -743,12 +743,6 @@ struct unity_map_entry { /* allocation bitmap for domain ids */ extern unsigned long *amd_iommu_pd_alloc_bitmap; -/* - * If true, the addresses will be flushed on unmap time, not when - * they are reused - */ -extern bool amd_iommu_unmap_flush; - /* Smallest max PASID supported by any IOMMU in the system */ extern u32 amd_iommu_max_pasid; diff --git a/drivers/iommu/intel-iommu.c b/drivers/iommu/intel-iommu.c index 28cb713d728ceef..57203f895382831 100644 --- a/drivers/iommu/intel-iommu.c +++ b/drivers/iommu/intel-iommu.c @@ -362,7 +362,6 @@ static int domain_detach_iommu(struct dmar_domain *domain, static int dmar_map_gfx = 1; static int dmar_forcedac; -static int intel_iommu_strict; static int intel_iommu_superpage = 1; static int intel_iommu_sm; static int iommu_identity_mapping; @@ -453,7 +452,7 @@ static int __init intel_iommu_setup(char *str) dmar_forcedac = 1; } else if (!strncmp(str, "strict", 6)) { pr_info("Disable batched IOTLB flush\n"); - intel_iommu_strict = 1; + iommu_default_dma_mode_set(IOMMU_DMA_MODE_STRICT); } else if (!strncmp(str, "sp_off", 6)) { pr_info("Disable supported super page\n"); intel_iommu_superpage = 0; @@ -3408,7 +3407,7 @@ static int __init init_dmars(void) iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH); } - if (iommu_pass_through) + if (IOMMU_DMA_MODE_IS_PASSTHROUGH()) iommu_identity_mapping |= IDENTMAP_ALL; #ifdef CONFIG_INTEL_IOMMU_BROKEN_GFX_WA @@ -3749,7 +3748,7 @@ static void intel_unmap(struct device *dev, dma_addr_t dev_addr, size_t size) freelist = domain_unmap(domain, start_pfn, last_pfn); - if (intel_iommu_strict) { + if (IOMMU_DMA_MODE_IS_STRICT()) { iommu_flush_iotlb_psi(iommu, domain, start_pfn, nrpages, !freelist, 0); /* free iova */ @@ -5460,7 +5459,7 @@ static void quirk_calpella_no_shadow_gtt(struct pci_dev *dev) } else if (dmar_map_gfx) { /* we have to ensure the gfx device is idle before we flush */ pci_info(dev, "Disabling batched IOTLB flush on Ironlake\n"); - intel_iommu_strict = 1; + iommu_default_dma_mode_set(IOMMU_DMA_MODE_STRICT); } } DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0040, quirk_calpella_no_shadow_gtt);