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[82.243.161.21]) by smtp.googlemail.com with ESMTPSA id c20sm98716866wre.28.2019.04.17.13.44.08 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 17 Apr 2019 13:44:09 -0700 (PDT) From: Jerome Brunet To: Ulf Hansson , Kevin Hilman Cc: Jerome Brunet , linux-mmc@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/7] mmc: meson-gx: irq is not shared Date: Wed, 17 Apr 2019 22:43:51 +0200 Message-Id: <20190417204355.469-4-jbrunet@baylibre.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190417204355.469-1-jbrunet@baylibre.com> References: <20190417204355.469-1-jbrunet@baylibre.com> MIME-Version: 1.0 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org There is no reason for another device to request the MMC irq. It should only be used the MMC device. Signed-off-by: Jerome Brunet --- drivers/mmc/host/meson-gx-mmc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.20.1 diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c index 8b690ecde4c5..3df50b53f834 100644 --- a/drivers/mmc/host/meson-gx-mmc.c +++ b/drivers/mmc/host/meson-gx-mmc.c @@ -1328,7 +1328,7 @@ static int meson_mmc_probe(struct platform_device *pdev) host->regs + SD_EMMC_IRQ_EN); ret = request_threaded_irq(host->irq, meson_mmc_irq, - meson_mmc_irq_thread, IRQF_SHARED, + meson_mmc_irq_thread, IRQF_ONESHOT, dev_name(&pdev->dev), host); if (ret) goto err_init_clk; From patchwork Wed Apr 17 20:43:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 162426 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp5955685jan; Wed, 17 Apr 2019 13:44:35 -0700 (PDT) X-Google-Smtp-Source: APXvYqyylV+toodqofExQCp5wUxw55LhekNg490D0IUR9XkIw+FZLVAYZypt2MZyAVgo9Hx6RqGP X-Received: by 2002:a17:902:3e5:: with SMTP id d92mr87109400pld.11.1555533875570; Wed, 17 Apr 2019 13:44:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1555533875; cv=none; d=google.com; s=arc-20160816; b=eVRyAn4Z5VeIkthxKMVwvXzPpQsc+pucSJzkW2ACWgj5UPkvXKh7YRnCYQp7x7iMM9 pb17PkDtk5vsCISrsfjN2mXimpNOGmuBJ0lPCYGhjbzYjt/t6x5gYs003eo0Bt0Jtyi5 wKThnkbYIfjSMNsv/F8X/2Vch4KdAhvTBfztFaZZ6OPi7wfMoDt5x1hvTuP8ry1BlWEw Q581N6eE7kif7dHgdYLo6Iw0N4cuqLzD728d0/rC0+7+4Tb0UJLehXu7pnRefb2Uo4h3 OQaov5tGdWlv8ErkFMlbwDPJpuuzChBng4jIxaJR0Iq48P4L5qZTeKXaBoxDeREkmXsZ jMWw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Lh/dg7Ph5gI3fwf6VslQBt0/ChaA/QQP0d5LUMjUu4Y=; b=QjCzF9Ohy59mEUUECnkcYoA15E+mmyfG69B82ftxF38c5vJZj1bQVeAENcKsax2oHb Y2mxMJEPoJTWw0TyrQBMCt5IJhUK51ORayDcOdGCBtx8sjUz0P4Lj0OAiDXlnLv5VX0v YibF1zXn01+NXdP6iP+ZaQM1MpU3sbF6SUQyhko0Hb1MOmu3TegMdbEhQkitJ3iMRnQu lDI7cNj1iGQygjxKZTXJDLPUel3nHL96EFOwWYmHjNLm2EyLxhMmPd1ii1HdZzf691QY wJQTTKpqCEVQ+aXXnXdnAzw/ZPzAQWr5YUbCG6apK8uKjZPAzyUjwPi5uVsQogck50Ac 76XA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=1mPpeghD; spf=pass (google.com: best guess record for domain of linux-mmc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-mmc-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[82.243.161.21]) by smtp.googlemail.com with ESMTPSA id c20sm98716866wre.28.2019.04.17.13.44.10 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 17 Apr 2019 13:44:10 -0700 (PDT) From: Jerome Brunet To: Ulf Hansson , Kevin Hilman Cc: Jerome Brunet , linux-mmc@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/7] mmc: meson-gx: disable HS400 Date: Wed, 17 Apr 2019 22:43:52 +0200 Message-Id: <20190417204355.469-5-jbrunet@baylibre.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190417204355.469-1-jbrunet@baylibre.com> References: <20190417204355.469-1-jbrunet@baylibre.com> MIME-Version: 1.0 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org At the moment, all our attempts to enable HS400 on Amlogic chipsets have been unsuccessful or unreliable. Until we can figure out how to enable this mode safely and reliably, let's force it off. Signed-off-by: Jerome Brunet --- drivers/mmc/host/meson-gx-mmc.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) -- 2.20.1 diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c index 3df50b53f834..118f09da8dfb 100644 --- a/drivers/mmc/host/meson-gx-mmc.c +++ b/drivers/mmc/host/meson-gx-mmc.c @@ -823,10 +823,6 @@ static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) if (meson_mmc_timing_is_ddr(ios)) val |= CFG_DDR; - val &= ~CFG_CHK_DS; - if (ios->timing == MMC_TIMING_MMC_HS400) - val |= CFG_CHK_DS; - err = meson_mmc_clk_set(host, ios); if (err) dev_err(host->dev, "Failed to set clock: %d\n,", err); @@ -1339,6 +1335,13 @@ static int meson_mmc_probe(struct platform_device *pdev) mmc->max_segs = SD_EMMC_DESC_BUF_LEN / sizeof(struct sd_emmc_desc); mmc->max_seg_size = mmc->max_req_size; + /* + * At the moment, we don't know how to reliably enable HS400. + * From the different datasheets, it is not even clear if this mode + * is officially supported by any of the SoCs + */ + mmc->caps2 &= ~MMC_CAP2_HS400; + /* data bounce buffer */ host->bounce_buf_size = mmc->max_req_size; host->bounce_buf = From patchwork Wed Apr 17 20:43:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 162424 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp5955435jan; Wed, 17 Apr 2019 13:44:20 -0700 (PDT) X-Google-Smtp-Source: APXvYqwMO/zki9yRhJy2TUDb+jLmLVBDF0JEbouuARsL2b1e+L3NDgsK0vkorXO8hnUTZ3ZDKysq X-Received: by 2002:a17:902:e70c:: with SMTP id co12mr1927455plb.339.1555533860048; Wed, 17 Apr 2019 13:44:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1555533860; cv=none; d=google.com; s=arc-20160816; b=VJWAbgRw9pEH/yZ6dbYGqP3yHqBVvNtX4YaFe90e6RdSeJc13CRL+s3A1zJvCiJWrf j1ts6VnZxKG94SQomFjiWty5bhA5a4vAWQvD5/LGzFoHKwSxWtPEbitKjM1HrbN2j3M2 l2ac9iokHNa6ls9NTk4VqDj2A829L+vpQjN6l2nXiQIJ9sbRkwCk+Cn+GUvinpZXUUOV ci0BTyjnCAdHfqUqoTt/gCSzoYSi9toWa6fywRcgKFUADofhge3Qo/auqfbHw3hcb9GE 2b6KhV5fc1OmW+wntU+aqGHb1kQ4dxsKSseDvgcs9OB5zfwCcD2qdWXwnyghYujPjWms 79+w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=2PG4RVUDpV3B0qjRGkkQWtaaCze4HgvXH3Z70Qm9O/U=; b=aGBaG9cyxShfFveSU7iZbbvHhR3ykO1fCgd2g///OCTXH6t3KJiig/RxRQOe61d8vH Zy2ZDFgcdAuXDZtEMoIoK2ExBCc/dpP022nJcy7sSm6R/IXfLbcQ98ezyXfEUxj7ERez C5KRLmvV2ug2yoj5W8GaQNXHBMYo7gqZr+YUyB+2DpEW/iiKDod4zBRUkBuo05H43s7Z 4hdcdkYcNOrcWmCCj1C/kggjyjnP6p1MNacsSemRuTH+YG2yJ4GZATwlhTe8V923HgI4 XdlyX5EI+6s9QNDIxfAeJdY4Br8J5UH70mW8CUiYjN+BN8/dTIiW1Fe5PEdQyRqpeend Zlzg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=warLkyBW; spf=pass (google.com: best guess record for domain of linux-mmc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-mmc-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[82.243.161.21]) by smtp.googlemail.com with ESMTPSA id c20sm98716866wre.28.2019.04.17.13.44.13 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 17 Apr 2019 13:44:14 -0700 (PDT) From: Jerome Brunet To: Ulf Hansson , Kevin Hilman Cc: Jerome Brunet , linux-mmc@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 7/7] mmc: meson-gx: add signal resampling tuning Date: Wed, 17 Apr 2019 22:43:55 +0200 Message-Id: <20190417204355.469-8-jbrunet@baylibre.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190417204355.469-1-jbrunet@baylibre.com> References: <20190417204355.469-1-jbrunet@baylibre.com> MIME-Version: 1.0 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Use signal resampling tuning for the UHS and HS200 modes. Instead of trying to get the *best* resampling setting with complex window calculation, we just stop on the first working setting. If the tuning setting later proves unstable, we will just continue the tuning where we left it. Signed-off-by: Jerome Brunet --- drivers/mmc/host/meson-gx-mmc.c | 73 +++++++++++++++++++++++++++++++-- 1 file changed, 70 insertions(+), 3 deletions(-) -- 2.20.1 diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c index 50b03c167435..207c65b3ddf1 100644 --- a/drivers/mmc/host/meson-gx-mmc.c +++ b/drivers/mmc/host/meson-gx-mmc.c @@ -488,6 +488,61 @@ static int meson_mmc_clk_init(struct meson_host *host) return clk_prepare_enable(host->mmc_clk); } +static void meson_mmc_disable_resampling(struct meson_host *host) +{ + unsigned int val = readl(host->regs + host->data->adjust); + + val &= ~ADJUST_ADJ_EN; + writel(val, host->regs + host->data->adjust); +} + +static void meson_mmc_reset_resampling(struct meson_host *host) +{ + unsigned int val; + + meson_mmc_disable_resampling(host); + + val = readl(host->regs + host->data->adjust); + val &= ~ADJUST_ADJ_DELAY_MASK; + writel(val, host->regs + host->data->adjust); +} + +static int meson_mmc_resampling_tuning(struct mmc_host *mmc, u32 opcode) +{ + struct meson_host *host = mmc_priv(mmc); + unsigned int val, dly, max_dly, i; + int ret; + + /* Resampling is done using the source clock */ + max_dly = DIV_ROUND_UP(clk_get_rate(host->mux_clk), + clk_get_rate(host->mmc_clk)); + + val = readl(host->regs + host->data->adjust); + val |= ADJUST_ADJ_EN; + writel(val, host->regs + host->data->adjust); + + if (mmc->doing_retune) + dly = FIELD_GET(ADJUST_ADJ_DELAY_MASK, val) + 1; + else + dly = 0; + + for (i = 0; i < max_dly; i++) { + val &= ~ADJUST_ADJ_DELAY_MASK; + val |= FIELD_PREP(ADJUST_ADJ_DELAY_MASK, (dly + i) % max_dly); + writel(val, host->regs + host->data->adjust); + + ret = mmc_send_tuning(mmc, opcode, NULL); + if (!ret) { + dev_dbg(mmc_dev(mmc), "resampling delay: %u\n", + (dly + i) % max_dly); + return 0; + } + } + + meson_mmc_reset_resampling(host); + return -EIO; +} + static int meson_mmc_prepare_ios_clock(struct meson_host *host, struct mmc_ios *ios) { @@ -507,6 +562,19 @@ static int meson_mmc_prepare_ios_clock(struct meson_host *host, return meson_mmc_clk_set(host, ios->clock, ddr); } +static void meson_mmc_check_resampling(struct meson_host *host, + struct mmc_ios *ios) +{ + switch (ios->timing) { + case MMC_TIMING_LEGACY: + case MMC_TIMING_MMC_HS: + case MMC_TIMING_SD_HS: + case MMC_TIMING_MMC_DDR52: + meson_mmc_disable_resampling(host); + break; + } +} + static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) { struct meson_host *host = mmc_priv(mmc); @@ -533,9 +601,6 @@ static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) if (!IS_ERR(mmc->supply.vmmc)) mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); - /* disable signal resampling */ - writel(0, host->regs + host->data->adjust); - break; case MMC_POWER_ON: @@ -573,6 +638,7 @@ static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) val &= ~CFG_BUS_WIDTH_MASK; val |= FIELD_PREP(CFG_BUS_WIDTH_MASK, bus_width); + meson_mmc_check_resampling(host, ios); err = meson_mmc_prepare_ios_clock(host, ios); if (err) dev_err(host->dev, "Failed to set clock: %d\n,", err); @@ -962,6 +1028,7 @@ static const struct mmc_host_ops meson_mmc_ops = { .get_cd = meson_mmc_get_cd, .pre_req = meson_mmc_pre_req, .post_req = meson_mmc_post_req, + .execute_tuning = meson_mmc_resampling_tuning, .card_busy = meson_mmc_card_busy, .start_signal_voltage_switch = meson_mmc_voltage_switch, };