From patchwork Thu Apr 18 13:38:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gilad Ben-Yossef X-Patchwork-Id: 162468 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp759825jan; Thu, 18 Apr 2019 06:39:34 -0700 (PDT) X-Google-Smtp-Source: APXvYqzyFWp4Kj1HRvrs6z8QGXp95zQlznXePN9fq1mQZqfc0Y7xzpjKBV/YyECbaYfWd35ObvmP X-Received: by 2002:a63:1548:: with SMTP id 8mr83327887pgv.277.1555594774874; Thu, 18 Apr 2019 06:39:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1555594774; cv=none; d=google.com; s=arc-20160816; b=x15G+ot8gM8w8+eOk7h2/YmO+NEV+Mu5MStOLsBPE88vkD8NF0QVOpMkVmb5EGqe40 yvKJlxU24+xg3RlAtunIWg9TjTy7JEVoqL1iWXoad8o/leRXl2La7zbEljCGEIEiR2zL eKrLguUlTogn6xkEtc+VRgVftrIwMT08SNVMg+u+oN4gp0vEz1CDNPSdGG3jZELP+us2 jKTvRNFCGIys+VDWqb+SXK+XF7ib+r/sACDpXSd+CGTAIB2mNjiO+JSi9zhHAmAbxBcS 0BQbN3DIv56eXEBZsMk31xF5K4q3+AyrpSH3DkcEFr8fVUyVUwNCuEqMFNhHbg8K6K1S D/gQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=LSyX+9BSL3146ydQ7R0hW9z9RJjiH51me1acj4avsMs=; b=zH577P+Sx2a8IqSP/7DWqJcDMHUBx2O2PFc/lctp3PWMpUL7f9Vy07toO8mZHHdGr1 qMMwrxfq5jxXnoWksYkEq1CSZasAfkMiMiEUQKvUxytAmHgNSNw/tVreUZHanZTcs45s h0Kit6OdaJQnYKRn1omIzzPGtUme3HUYCL6hIeQmDlXzP9elBnsC60kjLBMXgEQ/l9k8 kIHx4yjuVJucEzK+R9C4cfAk6GrZ8YXoZZLPnQBcosY8GVI/Qqtcg6hkJzedtWLDy4Em dZA6kr9h8ATcy9irm3OAL2DLeRr6DjSXU8Yh7Q9JhAS+++w/1Vn02GL4XByfkrb8ljSs D/sg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-crypto-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f127si2329115pfc.176.2019.04.18.06.39.34; Thu, 18 Apr 2019 06:39:34 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-crypto-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-crypto-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389041AbfDRNje (ORCPT + 3 others); Thu, 18 Apr 2019 09:39:34 -0400 Received: from foss.arm.com ([217.140.101.70]:33440 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1733192AbfDRNjd (ORCPT ); Thu, 18 Apr 2019 09:39:33 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 05E8680D; Thu, 18 Apr 2019 06:39:33 -0700 (PDT) Received: from e110176-lin.kfn.arm.com (e110176-lin.kfn.arm.com [10.50.4.178]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 5490E3F5AF; Thu, 18 Apr 2019 06:39:31 -0700 (PDT) From: Gilad Ben-Yossef To: Herbert Xu , "David S. Miller" Cc: Ofir Drang , linux-crypto@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 02/35] crypto: ccree: move key load desc. before flow desc. Date: Thu, 18 Apr 2019 16:38:37 +0300 Message-Id: <20190418133913.9122-3-gilad@benyossef.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190418133913.9122-1-gilad@benyossef.com> References: <20190418133913.9122-1-gilad@benyossef.com> MIME-Version: 1.0 Sender: linux-crypto-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Refactor the descriptor setup code in order to move the key loading descriptor to one before last position. This has no effect on current functionality but is needed for later support of Content Protection Policy keys. Signed-off-by: Gilad Ben-Yossef --- drivers/crypto/ccree/cc_cipher.c | 107 +++++++++++++++++++++---------- 1 file changed, 73 insertions(+), 34 deletions(-) -- 2.21.0 diff --git a/drivers/crypto/ccree/cc_cipher.c b/drivers/crypto/ccree/cc_cipher.c index 0abcdc224ab0..dcab96861d6f 100644 --- a/drivers/crypto/ccree/cc_cipher.c +++ b/drivers/crypto/ccree/cc_cipher.c @@ -399,7 +399,7 @@ static int cc_cipher_setkey(struct crypto_skcipher *sktfm, const u8 *key, return 0; } -static void cc_setup_cipher_desc(struct crypto_tfm *tfm, +static void cc_setup_state_desc(struct crypto_tfm *tfm, struct cipher_req_ctx *req_ctx, unsigned int ivsize, unsigned int nbytes, struct cc_hw_desc desc[], @@ -423,11 +423,13 @@ static void cc_setup_cipher_desc(struct crypto_tfm *tfm, du_size = cc_alg->data_unit; switch (cipher_mode) { + case DRV_CIPHER_ECB: + break; case DRV_CIPHER_CBC: case DRV_CIPHER_CBC_CTS: case DRV_CIPHER_CTR: case DRV_CIPHER_OFB: - /* Load cipher state */ + /* Load IV */ hw_desc_init(&desc[*seq_size]); set_din_type(&desc[*seq_size], DMA_DLLI, iv_dma_addr, ivsize, NS_BIT); @@ -441,7 +443,71 @@ static void cc_setup_cipher_desc(struct crypto_tfm *tfm, set_setup_mode(&desc[*seq_size], SETUP_LOAD_STATE0); } (*seq_size)++; - /*FALLTHROUGH*/ + break; + case DRV_CIPHER_XTS: + case DRV_CIPHER_ESSIV: + case DRV_CIPHER_BITLOCKER: + /* load XEX key */ + hw_desc_init(&desc[*seq_size]); + set_cipher_mode(&desc[*seq_size], cipher_mode); + set_cipher_config0(&desc[*seq_size], direction); + if (cc_is_hw_key(tfm)) { + set_hw_crypto_key(&desc[*seq_size], + ctx_p->hw.key2_slot); + } else { + set_din_type(&desc[*seq_size], DMA_DLLI, + (key_dma_addr + (key_len / 2)), + (key_len / 2), NS_BIT); + } + set_xex_data_unit_size(&desc[*seq_size], du_size); + set_flow_mode(&desc[*seq_size], S_DIN_to_AES2); + set_key_size_aes(&desc[*seq_size], (key_len / 2)); + set_setup_mode(&desc[*seq_size], SETUP_LOAD_XEX_KEY); + (*seq_size)++; + + /* Load IV */ + hw_desc_init(&desc[*seq_size]); + set_setup_mode(&desc[*seq_size], SETUP_LOAD_STATE1); + set_cipher_mode(&desc[*seq_size], cipher_mode); + set_cipher_config0(&desc[*seq_size], direction); + set_key_size_aes(&desc[*seq_size], (key_len / 2)); + set_flow_mode(&desc[*seq_size], flow_mode); + set_din_type(&desc[*seq_size], DMA_DLLI, iv_dma_addr, + CC_AES_BLOCK_SIZE, NS_BIT); + (*seq_size)++; + break; + default: + dev_err(dev, "Unsupported cipher mode (%d)\n", cipher_mode); + } +} + + +static void cc_setup_key_desc(struct crypto_tfm *tfm, + struct cipher_req_ctx *req_ctx, + unsigned int nbytes, struct cc_hw_desc desc[], + unsigned int *seq_size) +{ + struct cc_cipher_ctx *ctx_p = crypto_tfm_ctx(tfm); + struct device *dev = drvdata_to_dev(ctx_p->drvdata); + int cipher_mode = ctx_p->cipher_mode; + int flow_mode = ctx_p->flow_mode; + int direction = req_ctx->gen_ctx.op_type; + dma_addr_t key_dma_addr = ctx_p->user.key_dma_addr; + unsigned int key_len = ctx_p->keylen; + unsigned int du_size = nbytes; + + struct cc_crypto_alg *cc_alg = + container_of(tfm->__crt_alg, struct cc_crypto_alg, + skcipher_alg.base); + + if (cc_alg->data_unit) + du_size = cc_alg->data_unit; + + switch (cipher_mode) { + case DRV_CIPHER_CBC: + case DRV_CIPHER_CBC_CTS: + case DRV_CIPHER_CTR: + case DRV_CIPHER_OFB: case DRV_CIPHER_ECB: /* Load key */ hw_desc_init(&desc[*seq_size]); @@ -486,35 +552,6 @@ static void cc_setup_cipher_desc(struct crypto_tfm *tfm, set_flow_mode(&desc[*seq_size], flow_mode); set_setup_mode(&desc[*seq_size], SETUP_LOAD_KEY0); (*seq_size)++; - - /* load XEX key */ - hw_desc_init(&desc[*seq_size]); - set_cipher_mode(&desc[*seq_size], cipher_mode); - set_cipher_config0(&desc[*seq_size], direction); - if (cc_is_hw_key(tfm)) { - set_hw_crypto_key(&desc[*seq_size], - ctx_p->hw.key2_slot); - } else { - set_din_type(&desc[*seq_size], DMA_DLLI, - (key_dma_addr + (key_len / 2)), - (key_len / 2), NS_BIT); - } - set_xex_data_unit_size(&desc[*seq_size], du_size); - set_flow_mode(&desc[*seq_size], S_DIN_to_AES2); - set_key_size_aes(&desc[*seq_size], (key_len / 2)); - set_setup_mode(&desc[*seq_size], SETUP_LOAD_XEX_KEY); - (*seq_size)++; - - /* Set state */ - hw_desc_init(&desc[*seq_size]); - set_setup_mode(&desc[*seq_size], SETUP_LOAD_STATE1); - set_cipher_mode(&desc[*seq_size], cipher_mode); - set_cipher_config0(&desc[*seq_size], direction); - set_key_size_aes(&desc[*seq_size], (key_len / 2)); - set_flow_mode(&desc[*seq_size], flow_mode); - set_din_type(&desc[*seq_size], DMA_DLLI, iv_dma_addr, - CC_AES_BLOCK_SIZE, NS_BIT); - (*seq_size)++; break; default: dev_err(dev, "Unsupported cipher mode (%d)\n", cipher_mode); @@ -755,8 +792,10 @@ static int cc_cipher_process(struct skcipher_request *req, /* STAT_PHASE_2: Create sequence */ - /* Setup processing */ - cc_setup_cipher_desc(tfm, req_ctx, ivsize, nbytes, desc, &seq_len); + /* Setup IV and XEX key used */ + cc_setup_state_desc(tfm, req_ctx, ivsize, nbytes, desc, &seq_len); + /* Setup key */ + cc_setup_key_desc(tfm, req_ctx, nbytes, desc, &seq_len); /* Data processing */ cc_setup_cipher_data(tfm, req_ctx, dst, src, nbytes, req, desc, &seq_len); From patchwork Thu Apr 18 13:38:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gilad Ben-Yossef X-Patchwork-Id: 162472 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp760366jan; Thu, 18 Apr 2019 06:39:58 -0700 (PDT) X-Google-Smtp-Source: APXvYqw2jKZyE4CVWu6lakMqrdewWiAwxA8dIk7rDZdpzdB4hM5dSv2j7WfnRkTBZWVz8f/mtFzi X-Received: by 2002:a63:c54a:: with SMTP id g10mr88266110pgd.71.1555594798104; Thu, 18 Apr 2019 06:39:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1555594798; cv=none; d=google.com; s=arc-20160816; b=ULda4YEAvHzGWR1iyKo56UIyYvM3+lKJjcw+GUODRXpPPEc4Fmw9IPHyv1XWrG98Vx pUcDLLf3Q0QzYZor2qsIehlJh0+ZuWH//8MjR156NTy4AiqPhC1Psv1DX2hulP+cfvvK yToxVtGHrvVFmspQ4Yhkx8jzTy9yF8nCx7Dt2A9gVfaPc9FapYfdKfKNcJIcujWXfeN5 tPsXpRHBqcXgiByQ4Y9kSEJ9kxr9RsGOUnZhxZDIM5PJ8RDbobgeIQ/zUX5k42NvPr/1 i2cSk6CIVud1o1X42/Mp7NG0eVpFsBCUee3HGx/CAWgKGlj9dciUc/FhefnN5fvjTNLv kNMw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; 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[209.132.180.67]) by mx.google.com with ESMTP id c22si2201776plo.412.2019.04.18.06.39.57; Thu, 18 Apr 2019 06:39:58 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-crypto-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-crypto-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389235AbfDRNj5 (ORCPT + 3 others); Thu, 18 Apr 2019 09:39:57 -0400 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:33512 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389005AbfDRNj4 (ORCPT ); Thu, 18 Apr 2019 09:39:56 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 25F4380D; Thu, 18 Apr 2019 06:39:56 -0700 (PDT) Received: from e110176-lin.kfn.arm.com (e110176-lin.kfn.arm.com [10.50.4.178]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 7DDFC3F5AF; Thu, 18 Apr 2019 06:39:54 -0700 (PDT) From: Gilad Ben-Yossef To: Herbert Xu , "David S. Miller" Cc: Ofir Drang , linux-crypto@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 06/35] crypto: ccree: add remaining logic for CPP Date: Thu, 18 Apr 2019 16:38:41 +0300 Message-Id: <20190418133913.9122-7-gilad@benyossef.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190418133913.9122-1-gilad@benyossef.com> References: <20190418133913.9122-1-gilad@benyossef.com> MIME-Version: 1.0 Sender: linux-crypto-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Add the missing logic to set usage policy protections for keys. This enables key policy protection for AES. Signed-off-by: Gilad Ben-Yossef --- drivers/crypto/ccree/cc_cipher.c | 186 +++++++++++++++++------- drivers/crypto/ccree/cc_hw_queue_defs.h | 37 +++++ drivers/crypto/ccree/cc_kernel_regs.h | 6 + 3 files changed, 178 insertions(+), 51 deletions(-) -- 2.21.0 diff --git a/drivers/crypto/ccree/cc_cipher.c b/drivers/crypto/ccree/cc_cipher.c index 8a9c664390f0..d1754d1156ee 100644 --- a/drivers/crypto/ccree/cc_cipher.c +++ b/drivers/crypto/ccree/cc_cipher.c @@ -34,6 +34,18 @@ struct cc_hw_key_info { enum cc_hw_crypto_key key2_slot; }; +struct cc_cpp_key_info { + u8 slot; + enum cc_cpp_alg alg; +}; + +enum cc_key_type { + CC_UNPROTECTED_KEY, /* User key */ + CC_HW_PROTECTED_KEY, /* HW (FDE) key */ + CC_POLICY_PROTECTED_KEY, /* CPP key */ + CC_INVALID_PROTECTED_KEY /* Invalid key */ +}; + struct cc_cipher_ctx { struct cc_drvdata *drvdata; int keylen; @@ -41,19 +53,22 @@ struct cc_cipher_ctx { int cipher_mode; int flow_mode; unsigned int flags; - bool hw_key; + enum cc_key_type key_type; struct cc_user_key_info user; - struct cc_hw_key_info hw; + union { + struct cc_hw_key_info hw; + struct cc_cpp_key_info cpp; + }; struct crypto_shash *shash_tfm; }; static void cc_cipher_complete(struct device *dev, void *cc_req, int err); -static inline bool cc_is_hw_key(struct crypto_tfm *tfm) +static inline enum cc_key_type cc_key_type(struct crypto_tfm *tfm) { struct cc_cipher_ctx *ctx_p = crypto_tfm_ctx(tfm); - return ctx_p->hw_key; + return ctx_p->key_type; } static int validate_keys_sizes(struct cc_cipher_ctx *ctx_p, u32 size) @@ -232,7 +247,7 @@ struct tdes_keys { u8 key3[DES_KEY_SIZE]; }; -static enum cc_hw_crypto_key cc_slot_to_hw_key(int slot_num) +static enum cc_hw_crypto_key cc_slot_to_hw_key(u8 slot_num) { switch (slot_num) { case 0: @@ -247,6 +262,22 @@ static enum cc_hw_crypto_key cc_slot_to_hw_key(int slot_num) return END_OF_KEYS; } +static u8 cc_slot_to_cpp_key(u8 slot_num) +{ + return (slot_num - CC_FIRST_CPP_KEY_SLOT); +} + +static inline enum cc_key_type cc_slot_to_key_type(u8 slot_num) +{ + if (slot_num >= CC_FIRST_HW_KEY_SLOT && slot_num <= CC_LAST_HW_KEY_SLOT) + return CC_HW_PROTECTED_KEY; + else if (slot_num >= CC_FIRST_CPP_KEY_SLOT && + slot_num <= CC_LAST_CPP_KEY_SLOT) + return CC_POLICY_PROTECTED_KEY; + else + return CC_INVALID_PROTECTED_KEY; +} + static int cc_cipher_sethkey(struct crypto_skcipher *sktfm, const u8 *key, unsigned int keylen) { @@ -261,18 +292,13 @@ static int cc_cipher_sethkey(struct crypto_skcipher *sktfm, const u8 *key, /* STAT_PHASE_0: Init and sanity checks */ - /* This check the size of the hardware key token */ + /* This check the size of the protected key token */ if (keylen != sizeof(hki)) { - dev_err(dev, "Unsupported HW key size %d.\n", keylen); + dev_err(dev, "Unsupported protected key size %d.\n", keylen); crypto_tfm_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN); return -EINVAL; } - if (ctx_p->flow_mode != S_DIN_to_AES) { - dev_err(dev, "HW key not supported for non-AES flows\n"); - return -EINVAL; - } - memcpy(&hki, key, keylen); /* The real key len for crypto op is the size of the HW key @@ -286,31 +312,70 @@ static int cc_cipher_sethkey(struct crypto_skcipher *sktfm, const u8 *key, return -EINVAL; } - ctx_p->hw.key1_slot = cc_slot_to_hw_key(hki.hw_key1); - if (ctx_p->hw.key1_slot == END_OF_KEYS) { - dev_err(dev, "Unsupported hw key1 number (%d)\n", hki.hw_key1); - return -EINVAL; - } + ctx_p->keylen = keylen; - if (ctx_p->cipher_mode == DRV_CIPHER_XTS || - ctx_p->cipher_mode == DRV_CIPHER_ESSIV || - ctx_p->cipher_mode == DRV_CIPHER_BITLOCKER) { - if (hki.hw_key1 == hki.hw_key2) { - dev_err(dev, "Illegal hw key numbers (%d,%d)\n", - hki.hw_key1, hki.hw_key2); + switch (cc_slot_to_key_type(hki.hw_key1)) { + case CC_HW_PROTECTED_KEY: + if (ctx_p->flow_mode == S_DIN_to_SM4) { + dev_err(dev, "Only AES HW protected keys are supported\n"); return -EINVAL; } - ctx_p->hw.key2_slot = cc_slot_to_hw_key(hki.hw_key2); - if (ctx_p->hw.key2_slot == END_OF_KEYS) { - dev_err(dev, "Unsupported hw key2 number (%d)\n", - hki.hw_key2); + + ctx_p->hw.key1_slot = cc_slot_to_hw_key(hki.hw_key1); + if (ctx_p->hw.key1_slot == END_OF_KEYS) { + dev_err(dev, "Unsupported hw key1 number (%d)\n", + hki.hw_key1); return -EINVAL; } - } - ctx_p->keylen = keylen; - ctx_p->hw_key = true; - dev_dbg(dev, "cc_is_hw_key ret 0"); + if (ctx_p->cipher_mode == DRV_CIPHER_XTS || + ctx_p->cipher_mode == DRV_CIPHER_ESSIV || + ctx_p->cipher_mode == DRV_CIPHER_BITLOCKER) { + if (hki.hw_key1 == hki.hw_key2) { + dev_err(dev, "Illegal hw key numbers (%d,%d)\n", + hki.hw_key1, hki.hw_key2); + return -EINVAL; + } + + ctx_p->hw.key2_slot = cc_slot_to_hw_key(hki.hw_key2); + if (ctx_p->hw.key2_slot == END_OF_KEYS) { + dev_err(dev, "Unsupported hw key2 number (%d)\n", + hki.hw_key2); + return -EINVAL; + } + } + + ctx_p->key_type = CC_HW_PROTECTED_KEY; + dev_dbg(dev, "HW protected key %d/%d set\n.", + ctx_p->hw.key1_slot, ctx_p->hw.key2_slot); + break; + + case CC_POLICY_PROTECTED_KEY: + if (ctx_p->drvdata->hw_rev < CC_HW_REV_713) { + dev_err(dev, "CPP keys not supported in this hardware revision.\n"); + return -EINVAL; + } + + if (ctx_p->cipher_mode != DRV_CIPHER_CBC && + ctx_p->cipher_mode != DRV_CIPHER_CTR) { + dev_err(dev, "CPP keys only supported in CBC or CTR modes.\n"); + return -EINVAL; + } + + ctx_p->cpp.slot = cc_slot_to_cpp_key(hki.hw_key1); + if (ctx_p->flow_mode == S_DIN_to_AES) + ctx_p->cpp.alg = CC_CPP_AES; + else /* Must be SM4 since due to sethkey registration */ + ctx_p->cpp.alg = CC_CPP_SM4; + ctx_p->key_type = CC_POLICY_PROTECTED_KEY; + dev_dbg(dev, "policy protedcted key alg: %d slot: %d.\n", + ctx_p->cpp.alg, ctx_p->cpp.slot); + break; + + default: + dev_err(dev, "Unsupported protected key (%d)\n", hki.hw_key1); + return -EINVAL; + } return 0; } @@ -338,7 +403,7 @@ static int cc_cipher_setkey(struct crypto_skcipher *sktfm, const u8 *key, return -EINVAL; } - ctx_p->hw_key = false; + ctx_p->key_type = CC_UNPROTECTED_KEY; /* * Verify DES weak keys @@ -451,7 +516,7 @@ static void cc_setup_state_desc(struct crypto_tfm *tfm, hw_desc_init(&desc[*seq_size]); set_cipher_mode(&desc[*seq_size], cipher_mode); set_cipher_config0(&desc[*seq_size], direction); - if (cc_is_hw_key(tfm)) { + if (cc_key_type(tfm) == CC_HW_PROTECTED_KEY) { set_hw_crypto_key(&desc[*seq_size], ctx_p->hw.key2_slot); } else { @@ -495,6 +560,7 @@ static void cc_setup_key_desc(struct crypto_tfm *tfm, dma_addr_t key_dma_addr = ctx_p->user.key_dma_addr; unsigned int key_len = ctx_p->keylen; unsigned int du_size = nbytes; + unsigned int din_size; struct cc_crypto_alg *cc_alg = container_of(tfm->__crt_alg, struct cc_crypto_alg, @@ -511,27 +577,38 @@ static void cc_setup_key_desc(struct crypto_tfm *tfm, case DRV_CIPHER_ECB: /* Load key */ hw_desc_init(&desc[*seq_size]); - set_cipher_mode(&desc[*seq_size], cipher_mode); - set_cipher_config0(&desc[*seq_size], direction); - if (flow_mode == S_DIN_to_AES) { - if (cc_is_hw_key(tfm)) { - set_hw_crypto_key(&desc[*seq_size], - ctx_p->hw.key1_slot); + if (cc_key_type(tfm) == CC_POLICY_PROTECTED_KEY) { + set_cpp_crypto_key(&desc[*seq_size], ctx_p->cpp.alg, + cipher_mode, ctx_p->cpp.slot); + } else { + set_cipher_mode(&desc[*seq_size], cipher_mode); + set_cipher_config0(&desc[*seq_size], direction); + if (flow_mode == S_DIN_to_AES) { + if (cc_key_type(tfm) == CC_HW_PROTECTED_KEY) { + set_hw_crypto_key(&desc[*seq_size], + ctx_p->hw.key1_slot); + } else { + /* CC_POLICY_UNPROTECTED_KEY + * Invalid keys are filtered out in + * sethkey() + */ + din_size = (key_len == 24) ? + AES_MAX_KEY_SIZE : key_len; + + set_din_type(&desc[*seq_size], DMA_DLLI, + key_dma_addr, din_size, + NS_BIT); + } + set_key_size_aes(&desc[*seq_size], key_len); } else { + /*des*/ set_din_type(&desc[*seq_size], DMA_DLLI, - key_dma_addr, ((key_len == 24) ? - AES_MAX_KEY_SIZE : - key_len), NS_BIT); + key_dma_addr, key_len, NS_BIT); + set_key_size_des(&desc[*seq_size], key_len); } - set_key_size_aes(&desc[*seq_size], key_len); - } else { - /*des*/ - set_din_type(&desc[*seq_size], DMA_DLLI, key_dma_addr, - key_len, NS_BIT); - set_key_size_des(&desc[*seq_size], key_len); + set_flow_mode(&desc[*seq_size], flow_mode); + set_setup_mode(&desc[*seq_size], SETUP_LOAD_KEY0); } - set_flow_mode(&desc[*seq_size], flow_mode); - set_setup_mode(&desc[*seq_size], SETUP_LOAD_KEY0); (*seq_size)++; break; case DRV_CIPHER_XTS: @@ -541,7 +618,7 @@ static void cc_setup_key_desc(struct crypto_tfm *tfm, hw_desc_init(&desc[*seq_size]); set_cipher_mode(&desc[*seq_size], cipher_mode); set_cipher_config0(&desc[*seq_size], direction); - if (cc_is_hw_key(tfm)) { + if (cc_key_type(tfm) == CC_HW_PROTECTED_KEY) { set_hw_crypto_key(&desc[*seq_size], ctx_p->hw.key1_slot); } else { @@ -789,6 +866,13 @@ static int cc_cipher_process(struct skcipher_request *req, cc_req.user_cb = (void *)cc_cipher_complete; cc_req.user_arg = (void *)req; + /* Setup CPP operation details */ + if (ctx_p->key_type == CC_POLICY_PROTECTED_KEY) { + cc_req.cpp.is_cpp = true; + cc_req.cpp.alg = ctx_p->cpp.alg; + cc_req.cpp.slot = ctx_p->cpp.slot; + } + /* Setup request context */ req_ctx->gen_ctx.op_type = direction; diff --git a/drivers/crypto/ccree/cc_hw_queue_defs.h b/drivers/crypto/ccree/cc_hw_queue_defs.h index 7a9b90db7db7..2c8cd907d8db 100644 --- a/drivers/crypto/ccree/cc_hw_queue_defs.h +++ b/drivers/crypto/ccree/cc_hw_queue_defs.h @@ -28,11 +28,13 @@ GENMASK(CC_REG_HIGH(word, name), CC_REG_LOW(word, name)) #define WORD0_VALUE CC_GENMASK(0, VALUE) +#define WORD0_CPP_CIPHER_MODE CC_GENMASK(0, CPP_CIPHER_MODE) #define WORD1_DIN_CONST_VALUE CC_GENMASK(1, DIN_CONST_VALUE) #define WORD1_DIN_DMA_MODE CC_GENMASK(1, DIN_DMA_MODE) #define WORD1_DIN_SIZE CC_GENMASK(1, DIN_SIZE) #define WORD1_NOT_LAST CC_GENMASK(1, NOT_LAST) #define WORD1_NS_BIT CC_GENMASK(1, NS_BIT) +#define WORD1_LOCK_QUEUE CC_GENMASK(1, LOCK_QUEUE) #define WORD2_VALUE CC_GENMASK(2, VALUE) #define WORD3_DOUT_DMA_MODE CC_GENMASK(3, DOUT_DMA_MODE) #define WORD3_DOUT_LAST_IND CC_GENMASK(3, DOUT_LAST_IND) @@ -53,6 +55,8 @@ #define WORD4_DATA_FLOW_MODE CC_GENMASK(4, DATA_FLOW_MODE) #define WORD4_KEY_SIZE CC_GENMASK(4, KEY_SIZE) #define WORD4_SETUP_OPERATION CC_GENMASK(4, SETUP_OPERATION) +#define WORD4_CPP_ALG CC_GENMASK(4, CPP_ALG) +#define WORD4_CPP_SLOT CC_GENMASK(4, CPP_SLOT) #define WORD5_DIN_ADDR_HIGH CC_GENMASK(5, DIN_ADDR_HIGH) #define WORD5_DOUT_ADDR_HIGH CC_GENMASK(5, DOUT_ADDR_HIGH) @@ -176,6 +180,15 @@ enum cc_hw_crypto_key { END_OF_KEYS = S32_MAX, }; +#define CC_NUM_HW_KEY_SLOTS 4 +#define CC_FIRST_HW_KEY_SLOT 0 +#define CC_LAST_HW_KEY_SLOT (CC_FIRST_HW_KEY_SLOT + CC_NUM_HW_KEY_SLOTS - 1) + +#define CC_NUM_CPP_KEY_SLOTS 8 +#define CC_FIRST_CPP_KEY_SLOT 16 +#define CC_LAST_CPP_KEY_SLOT (CC_FIRST_CPP_KEY_SLOT + \ + CC_NUM_CPP_KEY_SLOTS - 1) + enum cc_hw_aes_key_size { AES_128_KEY = 0, AES_192_KEY = 1, @@ -189,6 +202,8 @@ enum cc_hash_cipher_pad { HASH_CIPHER_DO_PADDING_RESERVE32 = S32_MAX, }; +#define CC_CPP_DESC_INDICATOR 0xFF0000UL + /*****************************/ /* Descriptor packing macros */ /*****************************/ @@ -248,6 +263,28 @@ static inline void set_din_no_dma(struct cc_hw_desc *pdesc, u32 addr, u32 size) pdesc->word[1] |= FIELD_PREP(WORD1_DIN_SIZE, size); } +/* + * Setup the special CPP descriptor + * + * @pdesc: pointer HW descriptor struct + * @alg: cipher used (AES / SM4) + * @mode: mode used (CTR or CBC) + * @slot: slot number + * @ksize: key size + */ +static inline void set_cpp_crypto_key(struct cc_hw_desc *pdesc, + enum cc_cpp_alg alg, + enum drv_cipher_mode mode, u8 slot) +{ + u8 mode_val = (mode == DRV_CIPHER_CBC ? 0 : 1); + + pdesc->word[1] |= FIELD_PREP(WORD1_DIN_SIZE, CC_CPP_DESC_INDICATOR); + pdesc->word[1] |= FIELD_PREP(WORD1_LOCK_QUEUE, 1); + pdesc->word[0] |= FIELD_PREP(WORD0_CPP_CIPHER_MODE, mode_val); + pdesc->word[4] |= FIELD_PREP(WORD4_CPP_ALG, alg); + pdesc->word[4] |= FIELD_PREP(WORD4_CPP_SLOT, slot); +} + /* * Set the DIN field of a HW descriptors to SRAM mode. * Note: No need to check SRAM alignment since host requests do not use SRAM and diff --git a/drivers/crypto/ccree/cc_kernel_regs.h b/drivers/crypto/ccree/cc_kernel_regs.h index 8d7262a35156..f148d13c4b65 100644 --- a/drivers/crypto/ccree/cc_kernel_regs.h +++ b/drivers/crypto/ccree/cc_kernel_regs.h @@ -31,6 +31,8 @@ #define CC_DSCRPTR_QUEUE_WORD0_REG_OFFSET 0xE80UL #define CC_DSCRPTR_QUEUE_WORD0_VALUE_BIT_SHIFT 0x0UL #define CC_DSCRPTR_QUEUE_WORD0_VALUE_BIT_SIZE 0x20UL +#define CC_DSCRPTR_QUEUE_WORD0_CPP_CIPHER_MODE_BIT_SHIFT 0x5UL +#define CC_DSCRPTR_QUEUE_WORD0_CPP_CIPHER_MODE_BIT_SIZE 0x3UL #define CC_DSCRPTR_QUEUE_WORD1_REG_OFFSET 0xE84UL #define CC_DSCRPTR_QUEUE_WORD1_DIN_DMA_MODE_BIT_SHIFT 0x0UL #define CC_DSCRPTR_QUEUE_WORD1_DIN_DMA_MODE_BIT_SIZE 0x2UL @@ -97,6 +99,10 @@ #define CC_DSCRPTR_QUEUE_WORD4_WORD_SWAP_BIT_SIZE 0x1UL #define CC_DSCRPTR_QUEUE_WORD4_BYTES_SWAP_BIT_SHIFT 0x1FUL #define CC_DSCRPTR_QUEUE_WORD4_BYTES_SWAP_BIT_SIZE 0x1UL +#define CC_DSCRPTR_QUEUE_WORD4_CPP_SLOT_BIT_SHIFT 0xAUL +#define CC_DSCRPTR_QUEUE_WORD4_CPP_SLOT_BIT_SIZE 0x3UL +#define CC_DSCRPTR_QUEUE_WORD4_CPP_ALG_BIT_SHIFT 0xDUL +#define CC_DSCRPTR_QUEUE_WORD4_CPP_ALG_BIT_SIZE 0x1UL #define CC_DSCRPTR_QUEUE_WORD5_REG_OFFSET 0xE94UL #define CC_DSCRPTR_QUEUE_WORD5_DIN_ADDR_HIGH_BIT_SHIFT 0x0UL #define CC_DSCRPTR_QUEUE_WORD5_DIN_ADDR_HIGH_BIT_SIZE 0x10UL From patchwork Thu Apr 18 13:38:47 2019 Content-Type: text/plain; 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[209.132.180.67]) by mx.google.com with ESMTP id l25si2384191pfi.9.2019.04.18.06.40.33; Thu, 18 Apr 2019 06:40:34 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-crypto-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-crypto-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389310AbfDRNkb (ORCPT + 3 others); Thu, 18 Apr 2019 09:40:31 -0400 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:33576 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389319AbfDRNkb (ORCPT ); Thu, 18 Apr 2019 09:40:31 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id BC32480D; Thu, 18 Apr 2019 06:40:30 -0700 (PDT) Received: from e110176-lin.kfn.arm.com (e110176-lin.kfn.arm.com [10.50.4.178]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 506F93F5AF; Thu, 18 Apr 2019 06:40:29 -0700 (PDT) From: Gilad Ben-Yossef To: Herbert Xu , "David S. Miller" Cc: Ofir Drang , linux-crypto@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 12/35] crypto: ccree: use proper callback completion api Date: Thu, 18 Apr 2019 16:38:47 +0300 Message-Id: <20190418133913.9122-13-gilad@benyossef.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190418133913.9122-1-gilad@benyossef.com> References: <20190418133913.9122-1-gilad@benyossef.com> MIME-Version: 1.0 Sender: linux-crypto-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Use proper hash callback completion API instead of open coding it. Signed-off-by: Gilad Ben-Yossef --- drivers/crypto/ccree/cc_hash.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) -- 2.21.0 diff --git a/drivers/crypto/ccree/cc_hash.c b/drivers/crypto/ccree/cc_hash.c index e824ab60b59c..8f15ce3deecd 100644 --- a/drivers/crypto/ccree/cc_hash.c +++ b/drivers/crypto/ccree/cc_hash.c @@ -286,7 +286,7 @@ static void cc_update_complete(struct device *dev, void *cc_req, int err) cc_unmap_req(dev, state, ctx); } - req->base.complete(&req->base, err); + ahash_request_complete(req, err); } static void cc_digest_complete(struct device *dev, void *cc_req, int err) @@ -306,7 +306,7 @@ static void cc_digest_complete(struct device *dev, void *cc_req, int err) cc_unmap_req(dev, state, ctx); } - req->base.complete(&req->base, err); + ahash_request_complete(req, err); } static void cc_hash_complete(struct device *dev, void *cc_req, int err) @@ -326,7 +326,7 @@ static void cc_hash_complete(struct device *dev, void *cc_req, int err) cc_unmap_req(dev, state, ctx); } - req->base.complete(&req->base, err); + ahash_request_complete(req, err); } static int cc_fin_result(struct cc_hw_desc *desc, struct ahash_request *req, From patchwork Thu Apr 18 13:38:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gilad Ben-Yossef X-Patchwork-Id: 162485 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp761767jan; Thu, 18 Apr 2019 06:41:12 -0700 (PDT) X-Google-Smtp-Source: APXvYqy0mNdrOQ+tU5SVWj7OVc6ozu27qpRuKiAi3NR7uV9XSwOYRN4HUmIE++efXQhSFwKstcf1 X-Received: by 2002:a17:902:2de4:: with SMTP id p91mr93504291plb.191.1555594872488; Thu, 18 Apr 2019 06:41:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1555594872; cv=none; d=google.com; s=arc-20160816; b=AnQZJ/ygSsVFcyWfZeJYtb/Rr8zsYRXDdtqcP43feJSNPSeXH27c2aH9caMYakiGe0 h2Iv3Y5sX1+foHz0mcYXyFW7fczmVbFWD5Cjf0Cj0oR0gluC9dtHdTP6whvoZejbPfG6 SoTPmUQkQRvmCFNfMhxqPZUZSLIKQqZMiBz720gbiBBUDs2ucP7ywmeBsFtL/r64zplC /9B4x9wnXJGZ53cAK/2rjXH2ItMADDz3qWUOmw9R/AbOAfM2OdeWZLwxF8P8pyewuBx0 Q/VsTwvryhRq2h3ZYv2kB6lZfJKXzLQwAELRdMsMA02vPT9VEzFG+WxfygujVupnHJrT Oy+Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=tQv7p9q/HwVPu7wBM2A2BgXwPDsjOd1bgZbCHo0ojzM=; b=zM3XGTewA4wXJyMr3VV/TAvE37l8sLprB9THsKXK2yGXyUK+aFGMrg80iVUtaArXop CQ65UR68OFQPW+i5Ywx/Q8TgDUvWhDqLV8efYJsF4rVY3TcH83HLuocEme2xKeXpb1o5 ImIIwPzeIp1EnXtJeJOgmnUY94Yoj6srd5yka+To34fu9N3NZxPryoQ/imhRQ1739dfi EvCQok0/yimhfWcSc+gtZgC5Y5BamBo1J5E3Pnc/7Wf2CS3FGHtFruiRiYH8cts0DEEG h+RU5vz+okQjte+mcn762Cm19+ii6e9t1Yp1W6LkRBRrfG20YCwYLfyp3+lP4PSO0IQ5 13Ag== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-crypto-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id z143si2486889pfc.64.2019.04.18.06.41.12; Thu, 18 Apr 2019 06:41:12 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-crypto-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-crypto-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389387AbfDRNlL (ORCPT + 3 others); Thu, 18 Apr 2019 09:41:11 -0400 Received: from foss.arm.com ([217.140.101.70]:33644 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388582AbfDRNlK (ORCPT ); Thu, 18 Apr 2019 09:41:10 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EC0251688; Thu, 18 Apr 2019 06:41:09 -0700 (PDT) Received: from e110176-lin.kfn.arm.com (e110176-lin.kfn.arm.com [10.50.4.178]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 809E83F5AF; Thu, 18 Apr 2019 06:41:08 -0700 (PDT) From: Gilad Ben-Yossef To: Herbert Xu , "David S. Miller" Cc: Ofir Drang , linux-crypto@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 19/35] crypto: ccree: zero out internal struct before use Date: Thu, 18 Apr 2019 16:38:54 +0300 Message-Id: <20190418133913.9122-20-gilad@benyossef.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190418133913.9122-1-gilad@benyossef.com> References: <20190418133913.9122-1-gilad@benyossef.com> MIME-Version: 1.0 Sender: linux-crypto-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org We did not zero out the internal struct before use causing problem in some rare error code paths. Signed-off-by: Gilad Ben-Yossef --- drivers/crypto/ccree/cc_aead.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) -- 2.21.0 diff --git a/drivers/crypto/ccree/cc_aead.c b/drivers/crypto/ccree/cc_aead.c index ed306a612c0f..0fa676b5603c 100644 --- a/drivers/crypto/ccree/cc_aead.c +++ b/drivers/crypto/ccree/cc_aead.c @@ -2062,6 +2062,8 @@ static int cc_aead_encrypt(struct aead_request *req) struct aead_req_ctx *areq_ctx = aead_request_ctx(req); int rc; + memset(areq_ctx, 0, sizeof(*areq_ctx)); + /* No generated IV required */ areq_ctx->backup_iv = req->iv; areq_ctx->backup_giv = NULL; @@ -2091,6 +2093,8 @@ static int cc_rfc4309_ccm_encrypt(struct aead_request *req) goto out; } + memset(areq_ctx, 0, sizeof(*areq_ctx)); + /* No generated IV required */ areq_ctx->backup_iv = req->iv; areq_ctx->backup_giv = NULL; @@ -2110,6 +2114,8 @@ static int cc_aead_decrypt(struct aead_request *req) struct aead_req_ctx *areq_ctx = aead_request_ctx(req); int rc; + memset(areq_ctx, 0, sizeof(*areq_ctx)); + /* No generated IV required */ areq_ctx->backup_iv = req->iv; areq_ctx->backup_giv = NULL; @@ -2137,6 +2143,8 @@ static int cc_rfc4309_ccm_decrypt(struct aead_request *req) goto out; } + memset(areq_ctx, 0, sizeof(*areq_ctx)); + /* No generated IV required */ areq_ctx->backup_iv = req->iv; areq_ctx->backup_giv = NULL; @@ -2254,6 +2262,8 @@ static int cc_rfc4106_gcm_encrypt(struct aead_request *req) goto out; } + memset(areq_ctx, 0, sizeof(*areq_ctx)); + /* No generated IV required */ areq_ctx->backup_iv = req->iv; areq_ctx->backup_giv = NULL; @@ -2277,6 +2287,8 @@ static int cc_rfc4543_gcm_encrypt(struct aead_request *req) struct aead_req_ctx *areq_ctx = aead_request_ctx(req); int rc; + memset(areq_ctx, 0, sizeof(*areq_ctx)); + //plaintext is not encryped with rfc4543 areq_ctx->plaintext_authenticate_only = true; @@ -2309,6 +2321,8 @@ static int cc_rfc4106_gcm_decrypt(struct aead_request *req) goto out; } + memset(areq_ctx, 0, sizeof(*areq_ctx)); + /* No generated IV required */ areq_ctx->backup_iv = req->iv; areq_ctx->backup_giv = NULL; @@ -2332,6 +2346,8 @@ static int cc_rfc4543_gcm_decrypt(struct aead_request *req) struct aead_req_ctx *areq_ctx = aead_request_ctx(req); int rc; + memset(areq_ctx, 0, sizeof(*areq_ctx)); + //plaintext is not decryped with rfc4543 areq_ctx->plaintext_authenticate_only = true; From patchwork Thu Apr 18 13:38:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gilad Ben-Yossef X-Patchwork-Id: 162489 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp762127jan; Thu, 18 Apr 2019 06:41:34 -0700 (PDT) X-Google-Smtp-Source: APXvYqz+ydcryK8WBNmpqAztt5z9CseY8YYXRPq0puWioq+erwsR8gL/1OISOf7+wqHdhhbKCbhO X-Received: by 2002:aa7:8a92:: with SMTP id a18mr6711309pfc.218.1555594894525; Thu, 18 Apr 2019 06:41:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1555594894; cv=none; d=google.com; s=arc-20160816; b=Tf+u7bIXbMecLT2t51ZU4eSZwWF/pF5RPOIfWx4dfYVrx4oY7HReHR590pcWdiB/+L 0ZfqK7FWFOO/C1nT0ilHQ2K221ar3Fyio73/jgNAJvHlGZ96b53yaQyxPqMjRG6xNw0m lS2YKBHz4kz3xDOVADhzSuIRyOTFqchNgK/TSFBHe085XuMqIqtlllI4KkSoqjC2s7i6 pzOeZdu8Xc++OUo1x0l7r66NBCc3+IrNOjxSZVipBIrNx0pB0ixXC+cOqn2alIMQY5qA 8DsKhSFJMy543irR3vIUKR8Gz6CoP+ddGZT9BoEwj8WDTNil8LWJ1Rya2oh3fUkUb4eJ 7xNA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=zhmaUxP/QDrutczUl+Tp6hZcB7wrv5cdjuk1xc2HyBs=; b=BO5QkvW7LEKgRGbDB87HCBrAGqIcmamsxOYYBVSwdvShuJR8ZqPoxo0tx49Dbom3/w tCMDAhnNIPvR1Oddjo3yd8d49SjKl8ru1wZy5sqiDZn0hUw5VHhl/vSXN6Yy6XO6GGJl ed5wUp0BBDwAXx1Vk4YJxw5CxP1JX7jnkjXr5qo72iAtcpKyadNgy0l7Ev0jUs8ZhCuQ FWux8Rskn1NcjvcY4+desBzGwfTkjOtPZFC5REWJwpnrtm8OivRoZkvB8HLlqjADiflJ m7UcTKQuUw5J0pnHb0fPqyLEfYIX0IpMx+HvL55uMElRIvoGJ8GYE2GdWd96+iZF5zYQ +KTg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-crypto-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r6si2114325plo.349.2019.04.18.06.41.34; Thu, 18 Apr 2019 06:41:34 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-crypto-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-crypto-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389200AbfDRNld (ORCPT + 3 others); Thu, 18 Apr 2019 09:41:33 -0400 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:33692 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388375AbfDRNlc (ORCPT ); Thu, 18 Apr 2019 09:41:32 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4F0891688; Thu, 18 Apr 2019 06:41:32 -0700 (PDT) Received: from e110176-lin.kfn.arm.com (e110176-lin.kfn.arm.com [10.50.4.178]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D7CBF3F5AF; Thu, 18 Apr 2019 06:41:30 -0700 (PDT) From: Gilad Ben-Yossef To: Herbert Xu , "David S. Miller" Cc: Ofir Drang , linux-crypto@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 23/35] crypto: ccree: simplify AEAD ICV addr calculation Date: Thu, 18 Apr 2019 16:38:58 +0300 Message-Id: <20190418133913.9122-24-gilad@benyossef.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190418133913.9122-1-gilad@benyossef.com> References: <20190418133913.9122-1-gilad@benyossef.com> MIME-Version: 1.0 Sender: linux-crypto-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org The function cc_prepare_aead_data_dlli() which calculates ICV addresses was needlessly complicate it. This patch simplifies it without altering its functionality. Signed-off-by: Gilad Ben-Yossef --- drivers/crypto/ccree/cc_buffer_mgr.c | 28 +++++++++++----------------- 1 file changed, 11 insertions(+), 17 deletions(-) -- 2.21.0 diff --git a/drivers/crypto/ccree/cc_buffer_mgr.c b/drivers/crypto/ccree/cc_buffer_mgr.c index 8269474cb9fa..8554cfb2963a 100644 --- a/drivers/crypto/ccree/cc_buffer_mgr.c +++ b/drivers/crypto/ccree/cc_buffer_mgr.c @@ -749,27 +749,21 @@ static void cc_prepare_aead_data_dlli(struct aead_request *req, struct aead_req_ctx *areq_ctx = aead_request_ctx(req); enum drv_crypto_direction direct = areq_ctx->gen_ctx.op_type; unsigned int authsize = areq_ctx->req_authsize; + struct scatterlist *sg; + ssize_t offset; areq_ctx->is_icv_fragmented = false; - if (req->src == req->dst) { - /*INPLACE*/ - areq_ctx->icv_dma_addr = sg_dma_address(areq_ctx->src_sgl) + - (*src_last_bytes - authsize); - areq_ctx->icv_virt_addr = sg_virt(areq_ctx->src_sgl) + - (*src_last_bytes - authsize); - } else if (direct == DRV_CRYPTO_DIRECTION_DECRYPT) { - /*NON-INPLACE and DECRYPT*/ - areq_ctx->icv_dma_addr = sg_dma_address(areq_ctx->src_sgl) + - (*src_last_bytes - authsize); - areq_ctx->icv_virt_addr = sg_virt(areq_ctx->src_sgl) + - (*src_last_bytes - authsize); + + if ((req->src == req->dst) || direct == DRV_CRYPTO_DIRECTION_DECRYPT) { + sg = areq_ctx->src_sgl; + offset = *src_last_bytes - authsize; } else { - /*NON-INPLACE and ENCRYPT*/ - areq_ctx->icv_dma_addr = sg_dma_address(areq_ctx->dst_sgl) + - (*dst_last_bytes - authsize); - areq_ctx->icv_virt_addr = sg_virt(areq_ctx->dst_sgl) + - (*dst_last_bytes - authsize); + sg = areq_ctx->dst_sgl; + offset = *dst_last_bytes - authsize; } + + areq_ctx->icv_dma_addr = sg_dma_address(sg) + offset; + areq_ctx->icv_virt_addr = sg_virt(sg) + offset; } static void cc_prepare_aead_data_mlli(struct cc_drvdata *drvdata, From patchwork Thu Apr 18 13:39:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gilad Ben-Yossef X-Patchwork-Id: 162494 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp762652jan; Thu, 18 Apr 2019 06:42:03 -0700 (PDT) X-Google-Smtp-Source: APXvYqxKP+FU7WV22IbepvEKdG1qXExbiRSRFjTp8LEfLrkzHl6NgY+cq2jNn8jrpguTMtxOyiae X-Received: by 2002:aa7:91d5:: with SMTP id z21mr14341606pfa.222.1555594923620; Thu, 18 Apr 2019 06:42:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1555594923; cv=none; d=google.com; s=arc-20160816; b=d7kGjnTt1UuApulgGdDwLFss/SmzAfpv+Vz/2u5Eu3PHOVRXvEtZX5ZwVMuB3rG8k7 ALFqzsBuHC0baREQExqyL9lwcGv+g0gwYeg2uC/eYYZn/7qTOZD3TNePyk7wxBWertJT oKOHIAdyqTFFPT6msoQx/vFaVKzTBevDf9AFluOBZu4iL0ai9HcdeevcQ2gNDRGeoYff c/1DBAaAhkKOS7a4w3jR1yo0TKiWGGjkC1GWgux9oS0wIs2BgXHDYwp8+4g4FHnJVi/B /OGKPdNUEkgYcDcbNPk879IwvDFHttBoZtecx7ZG/d1eAsOxal3HEhG3NoahrCryAMhq 7v2A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=LPt34BOdFAYvX3nYPAhuqouYqNb/dDq4nDI4LgTEt9I=; b=RcewQrc1sbdNHz8oIxjyqGqCfpGTt7nymMVPKGlXEPekaex5sFpqlfoLG7LnSi3dXt T2XbYSDGZiMWQ+uiZCHlCOm2UgcVLMnsl3Hfa+bQmw2aOiZQVrX7+on4i8/aSkuChvDQ 4DCS/AWX1/ZUT/fKQFbi6zU5fnwxz9qw+ND9YkHFBTvcttHyND0SIjh6wJB2uQRiMUgC rXgYzpni0ftSwYfe8tQVXkrYohkWMVuzbkLfRujXjaInezW/ypzZyTsh7bSs8xZQMSn7 jYf+Hr3KaZVUXPuwCPK4xsmCIgsMP96h4WZifrNtx6qNOtRqn4ZyzFeomHJmGwiN0xPr GRwA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-crypto-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id p16si2384236pff.85.2019.04.18.06.42.03; Thu, 18 Apr 2019 06:42:03 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-crypto-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-crypto-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389226AbfDRNmB (ORCPT + 3 others); Thu, 18 Apr 2019 09:42:01 -0400 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:33734 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388858AbfDRNmB (ORCPT ); Thu, 18 Apr 2019 09:42:01 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E669B1688; Thu, 18 Apr 2019 06:42:00 -0700 (PDT) Received: from e110176-lin.kfn.arm.com (e110176-lin.kfn.arm.com [10.50.4.178]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 7AAE83F5AF; Thu, 18 Apr 2019 06:41:59 -0700 (PDT) From: Gilad Ben-Yossef To: Herbert Xu , "David S. Miller" Cc: Ofir Drang , linux-crypto@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 28/35] crypto: ccree: allow more AEAD assoc data fragments Date: Thu, 18 Apr 2019 16:39:03 +0300 Message-Id: <20190418133913.9122-29-gilad@benyossef.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190418133913.9122-1-gilad@benyossef.com> References: <20190418133913.9122-1-gilad@benyossef.com> MIME-Version: 1.0 Sender: linux-crypto-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Increase the maximum supported AEAD associated data fragments. Signed-off-by: Gilad Ben-Yossef --- drivers/crypto/ccree/cc_lli_defs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.21.0 diff --git a/drivers/crypto/ccree/cc_lli_defs.h b/drivers/crypto/ccree/cc_lli_defs.h index 43aca6b79b9b..f891ab813f41 100644 --- a/drivers/crypto/ccree/cc_lli_defs.h +++ b/drivers/crypto/ccree/cc_lli_defs.h @@ -14,7 +14,7 @@ #define CC_MAX_MLLI_ENTRY_SIZE 0xFFFF #define LLI_MAX_NUM_OF_DATA_ENTRIES 128 -#define LLI_MAX_NUM_OF_ASSOC_DATA_ENTRIES 4 +#define LLI_MAX_NUM_OF_ASSOC_DATA_ENTRIES 8 #define MLLI_TABLE_MIN_ALIGNMENT 4 /* 32 bit alignment */ #define MAX_NUM_OF_BUFFERS_IN_MLLI 4 #define MAX_NUM_OF_TOTAL_MLLI_ENTRIES \ From patchwork Thu Apr 18 13:39:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gilad Ben-Yossef X-Patchwork-Id: 162498 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp763094jan; Thu, 18 Apr 2019 06:42:27 -0700 (PDT) X-Google-Smtp-Source: APXvYqwhOsEWoCq4WbFwERMHeAnVeL+45P6gUVK509/Xd6Z3Wj8+Ajm8H9g3s4PWyyJZS14XdLkO X-Received: by 2002:a65:6295:: with SMTP id f21mr82834018pgv.129.1555594947642; Thu, 18 Apr 2019 06:42:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1555594947; cv=none; d=google.com; s=arc-20160816; b=EtapS+3wey+8v73y7wPpGTZiawK7j7AA4l69f/eAjp2Vqt2UAfszF3YAQ3duKj3HXV Ia3qmh6s9axEG4DHt7lIWXs2xXUZSt6efxW3hyKSJc5AihY61nLuAbBZpbvr6un7iiLG uaMw4YhAGnrgw3X37BS5p4OwM/sOsSFSMDboQgJeohbIOPtpvcZ+lQOID6zgQR4buMzO V6U5QkiYVx7zcGLXdPfCgKsp3zjWuZQUng5E8JBsqqk4N+NfQO1WRqlmII6WXLIXG4Dh fVTr4gn0VCA6ckJiLyVDdrwOWzowG2XI/ThUwAqVrajvfZskjoLy/Yhi7kvsNX7+YLfF lWrQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=Mb5dj/ORixnyhLNhb/doY+CyPPR+PD+jKjedu9i1iS4=; b=bmRX8KBdrhCD3D+VjhVyKcXOJE9brpkjMJrE74AbLTrbeGcAqVAXHbPkKYtkOaxW+p KZf9tPboUVv98Rb2g9YBPlkiQYi/WN2pp0PrwxX7axeBnpyHHlZy9E33+PLjQNEAfwy+ oAXJ/ITBTQ6ZEtJW+rB7p9BLEki1WrwNOP3aBw94rq1Mgv4Z10gkaLBNAr0gQFk+tCEA L2Sx5+59y2KeB+IpRT9P+duTOQnTxeUsrpPvYGU4/Sa5uknUcZOovC34d/G6uwNPI0yr zwdERE7DG1tX+xD0h7CrIu5rsJ70+q+G4YG2NEMx/NUrHWAsdnGhOJ7tiQxb5gYbz2es wEQg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-crypto-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b4si1957362pgg.581.2019.04.18.06.42.27; Thu, 18 Apr 2019 06:42:27 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-crypto-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-crypto-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389146AbfDRNmZ (ORCPT + 3 others); Thu, 18 Apr 2019 09:42:25 -0400 Received: from foss.arm.com ([217.140.101.70]:33778 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389270AbfDRNmY (ORCPT ); Thu, 18 Apr 2019 09:42:24 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C6E5380D; Thu, 18 Apr 2019 06:42:23 -0700 (PDT) Received: from e110176-lin.kfn.arm.com (e110176-lin.kfn.arm.com [10.50.4.178]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 5B2363F5AF; Thu, 18 Apr 2019 06:42:22 -0700 (PDT) From: Gilad Ben-Yossef To: Herbert Xu , "David S. Miller" Cc: Ofir Drang , linux-crypto@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 32/35] crypto: ccree: remove cc7x3 obsoleted AXIM configs Date: Thu, 18 Apr 2019 16:39:07 +0300 Message-Id: <20190418133913.9122-33-gilad@benyossef.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190418133913.9122-1-gilad@benyossef.com> References: <20190418133913.9122-1-gilad@benyossef.com> MIME-Version: 1.0 Sender: linux-crypto-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org From: Ofir Drang AXIM configuration register modified in cc7x3 and no longer includes AXI interrupt masking fields. Signed-off-by: Ofir Drang Signed-off-by: Gilad Ben-Yossef --- drivers/crypto/ccree/cc_driver.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) -- 2.21.0 diff --git a/drivers/crypto/ccree/cc_driver.c b/drivers/crypto/ccree/cc_driver.c index a28548192211..902f196d4be1 100644 --- a/drivers/crypto/ccree/cc_driver.c +++ b/drivers/crypto/ccree/cc_driver.c @@ -193,11 +193,14 @@ int init_cc_regs(struct cc_drvdata *drvdata, bool is_probe) unsigned int val, cache_params; struct device *dev = drvdata_to_dev(drvdata); - /* Unmask all AXI interrupt sources AXI_CFG1 register */ - val = cc_ioread(drvdata, CC_REG(AXIM_CFG)); - cc_iowrite(drvdata, CC_REG(AXIM_CFG), val & ~CC_AXI_IRQ_MASK); - dev_dbg(dev, "AXIM_CFG=0x%08X\n", - cc_ioread(drvdata, CC_REG(AXIM_CFG))); + /* Unmask all AXI interrupt sources AXI_CFG1 register */ + /* AXI interrupt config are obsoleted startign at cc7x3 */ + if (drvdata->hw_rev <= CC_HW_REV_712) { + val = cc_ioread(drvdata, CC_REG(AXIM_CFG)); + cc_iowrite(drvdata, CC_REG(AXIM_CFG), val & ~CC_AXI_IRQ_MASK); + dev_dbg(dev, "AXIM_CFG=0x%08X\n", + cc_ioread(drvdata, CC_REG(AXIM_CFG))); + } /* Clear all pending interrupts */ val = cc_ioread(drvdata, CC_REG(HOST_IRR));