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[86.31.179.135]) by smtp.gmail.com with ESMTPSA id t76sm5700147wmt.8.2019.04.19.01.35.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 19 Apr 2019 01:35:03 -0700 (PDT) From: Peter Griffin To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, john.stultz@linaro.org, airlied@linux.ie, daniel@ffwll.ch, robh+dt@kernel.org, mark.rutland@arm.com, p.zabel@pengutronix.de, xuwei5@hisilicon.com, mturquette@baylibre.com, sboyd@kernel.org, yuq825@gmail.com Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, lima@lists.freedesktop.org Subject: [PATCH v2 1/6] dt-bindings: gpu: mali-utgard: add hisilicon, hi6220-mali compatible Date: Fri, 19 Apr 2019 09:32:56 +0100 Message-Id: <1555662781-22570-2-git-send-email-peter.griffin@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1555662781-22570-1-git-send-email-peter.griffin@linaro.org> References: <1555662781-22570-1-git-send-email-peter.griffin@linaro.org> The Hisilicon hi6220 uses a Mali-450MP4 with 4 PPs, so add a compatible for it. Signed-off-by: Peter Griffin Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt | 5 +++++ 1 file changed, 5 insertions(+) -- 2.7.4 diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt index 3f128e4..2a16b0c 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt +++ b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt @@ -21,6 +21,7 @@ Required properties: + rockchip,rk3228-mali + rockchip,rk3328-mali + stericsson,db8500-mali + + hisilicon,hi6220-mali - reg: Physical base address and length of the GPU registers @@ -91,6 +92,10 @@ to specify one more vendor-specific compatible, among: * interrupt-names and interrupts: + combined: combined interrupt of all of the above lines + - hisilicon,hi6220-mali + Required properties: + * resets: phandles to the reset lines for the GPU + Example: mali: gpu@1c40000 { From patchwork Fri Apr 19 08:32:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Griffin X-Patchwork-Id: 162519 Delivered-To: patches@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp1750395jan; Fri, 19 Apr 2019 01:35:06 -0700 (PDT) X-Received: by 2002:a1c:4e0a:: with SMTP id g10mr1870158wmh.128.1555662906178; Fri, 19 Apr 2019 01:35:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1555662906; cv=none; d=google.com; s=arc-20160816; b=feKkBpQagFc33Zhsgsyc9akiarvsdx6bjNUL1xLLxky8o3X2bvY+1Jv8FFHQPlSQZZ 6hFpybHfI2549u9VHL+E1nTTrTrBK1qZk1DatcF5dwc3S8dVFX+SuxPrVLA524gTGNip gmT3QkVtzvHK1K/2AKiRiEKTH/VRJY9D+geeYO7AAYRCulRPHpsinFMLOl/hNvF7zK3i 2iwhJ/wxLHNp/3l3G3M7f8UUWStXhUpI1hc2BrBWx29M1ffh4X2q6AnYtZ/JUfIlfGjz sKBDq0yIWjN4R5bL/dJuc4f2/NIxFAf+CzLRUsAzTBkvBRqiNqCaLiBd/B8hFGdg0dba sPug== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=R+rJiqbMseAY0oDXLdqiRPHEvayMMhzkPPex8gF7dgU=; b=LxwqsdgonLOe6chFBJGmdq02EoEbznHO2TrPmoJRBE++FlSqVhhfq/x6Q8NS+p70vL q7+KfIy4NUtixtV9b10v7+ZMCbQWaAu+FxqQZe3L1m0L7WGcB9dnWYXMWDXhEh4MvcEE /9NycDWsciUkeB6VnsBvqtC+IK75jXqUCPgGlN+ZFUSXOE9xfaPYbFCjfxLhLFe8de16 pkW8ji2MzpWvezEjmbKpqcm+4jyjj4O5qapD9/qBFz7kByjegU8W7+qk9DbkcXRn4YQk XDEZ04/npBiIWIr+JnO2H/xPRcBAsEuOCKdgVDqt4bIZzhYKzctWuUtFyVcTjfGcNIWm kd3Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QfQHEsBY; spf=pass (google.com: domain of peter.griffin@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=peter.griffin@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from mail-sor-f65.google.com (mail-sor-f65.google.com. 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[86.31.179.135]) by smtp.gmail.com with ESMTPSA id t76sm5700147wmt.8.2019.04.19.01.35.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 19 Apr 2019 01:35:05 -0700 (PDT) From: Peter Griffin To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, john.stultz@linaro.org, airlied@linux.ie, daniel@ffwll.ch, robh+dt@kernel.org, mark.rutland@arm.com, p.zabel@pengutronix.de, xuwei5@hisilicon.com, mturquette@baylibre.com, sboyd@kernel.org, yuq825@gmail.com Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, lima@lists.freedesktop.org Subject: [PATCH v2 2/6] dt-bindings: reset: hisilicon: Update compatible documentation Date: Fri, 19 Apr 2019 09:32:57 +0100 Message-Id: <1555662781-22570-3-git-send-email-peter.griffin@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1555662781-22570-1-git-send-email-peter.griffin@linaro.org> References: <1555662781-22570-1-git-send-email-peter.griffin@linaro.org> The reset driver now supports the ao reset controller, so update the documentation to match. Signed-off-by: Peter Griffin Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt | 1 + 1 file changed, 1 insertion(+) -- 2.7.4 diff --git a/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt b/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt index c25da39..ea0a6a9 100644 --- a/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt +++ b/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt @@ -11,6 +11,7 @@ Required properties: - compatible: should be one of the following: - "hisilicon,hi6220-sysctrl", "syscon" : For peripheral reset controller. - "hisilicon,hi6220-mediactrl", "syscon" : For media reset controller. + - "hisilicon,hi6220-aoctrl", "syscon" : For ao reset controller. - reg: should be register base and length as documented in the datasheet - #reset-cells: 1, see below From patchwork Fri Apr 19 08:32:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Griffin X-Patchwork-Id: 162520 Delivered-To: patches@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp1750410jan; Fri, 19 Apr 2019 01:35:07 -0700 (PDT) X-Received: by 2002:a7b:cb58:: with SMTP id v24mr1718815wmj.121.1555662907509; Fri, 19 Apr 2019 01:35:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1555662907; cv=none; d=google.com; s=arc-20160816; b=zmJscx9L09u1mxusDIbRRjyNqtz63BODyt8F4MfsxudLapbJkb/io0PSDS6wzx1sI+ Jk54jdHRqI+MsKDT7WT83KrKCUh78jRIerSOcLEQfnntVcZeHAZ6kvyC2A7Ty8bqpv86 KxYHDSqwUsYFiDRimd9veirli9kyl3qx/e+6VlcxvWLQu+Uq7DG5HyMdCF14RPpym20S hp8v6ey1ip5xIh0j+BvmJLa9+YXLBcN9iPwiFxwi9BTENWGEJ2SfFekjVsEWHR/+lToR wsAIJfYIj0iqvP49vMltIopoup95NnWZeeyesIsfTiXyFeYj0n0P/ijZior4b6SupseP ajYg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=U+1RhXgibSnIdgZgBtIFJvFDwIprDWg0GFwO76wEX90=; b=NSi3BHrBYiS3Hbxf930bLNSTGUFIsBH1a9nJZ5wZFIvHZ+sQmuxOnBe9/Wh9N9uTAi 9UWx0DbAHo8OZU04VogYxBPsWj2qP6ot4AThmkOAOIFOAklm3hxtycjfA/ON3nmf70VR 3CrppnSlifl+qCxd5vAbz/8ykrUZE24R/yaNREg69Ghc06KQKnCvwat4kFvr1wpvHBZE ruAoUHex1nNtNf41PBKnFdO54YXQbixg4Szeb6YZ6ot8tIC54XZRSPr/FD8tyXOenWln yQohm2Zh4y0Fmet8RfzOqvRPbVyEdF2I1Y48p90Rs2LLSxC6NieEwA3fiLCjdIAXoj8v Eovw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ggTiLMIo; spf=pass (google.com: domain of peter.griffin@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=peter.griffin@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from mail-sor-f65.google.com (mail-sor-f65.google.com. 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[86.31.179.135]) by smtp.gmail.com with ESMTPSA id t76sm5700147wmt.8.2019.04.19.01.35.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 19 Apr 2019 01:35:06 -0700 (PDT) From: Peter Griffin To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, john.stultz@linaro.org, airlied@linux.ie, daniel@ffwll.ch, robh+dt@kernel.org, mark.rutland@arm.com, p.zabel@pengutronix.de, xuwei5@hisilicon.com, mturquette@baylibre.com, sboyd@kernel.org, yuq825@gmail.com Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, lima@lists.freedesktop.org Subject: [PATCH v2 3/6] arm64: dts: hisilicon: Add Mali-450 MP4 GPU DT entry Date: Fri, 19 Apr 2019 09:32:58 +0100 Message-Id: <1555662781-22570-4-git-send-email-peter.griffin@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1555662781-22570-1-git-send-email-peter.griffin@linaro.org> References: <1555662781-22570-1-git-send-email-peter.griffin@linaro.org> hi6220 has a Mali450 MP4 so lets add it into the DT. Signed-off-by: Peter Griffin --- arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 37 +++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) -- 2.7.4 diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index aec9e37..2defc19 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -1019,6 +1019,43 @@ clock-names = "apb_pclk"; cpu = <&cpu7>; }; + + mali: gpu@f4080000 { + compatible = "hisilicon,hi6220-mali", "arm,mali-450"; + reg = <0x0 0xf4080000 0x0 0x00040000>; + interrupt-parent = <&gic>; + interrupts = , + , + , + , + , + , + , + , + , + , + ; + + interrupt-names = "gp", + "gpmmu", + "pp", + "pp0", + "ppmmu0", + "pp1", + "ppmmu1", + "pp2", + "ppmmu2", + "pp3", + "ppmmu3"; + clocks = <&media_ctrl HI6220_G3D_CLK>, + <&media_ctrl HI6220_G3D_PCLK>; + clock-names = "core", "bus"; + assigned-clocks = <&media_ctrl HI6220_G3D_CLK>, + <&media_ctrl HI6220_G3D_PCLK>; + assigned-clock-rates = <500000000>, <144000000>; + reset-names = "ao_g3d", "media_g3d"; + resets = <&ao_ctrl AO_G3D>, <&media_ctrl MEDIA_G3D>; + }; }; }; From patchwork Fri Apr 19 08:32:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Griffin X-Patchwork-Id: 162521 Delivered-To: patches@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp1750427jan; Fri, 19 Apr 2019 01:35:09 -0700 (PDT) X-Received: by 2002:adf:d848:: with SMTP id k8mr2221635wrl.185.1555662909280; Fri, 19 Apr 2019 01:35:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1555662909; cv=none; d=google.com; s=arc-20160816; b=u9hHZTtCf7KAt/inwxbLcM7LpWIWYS4LHI+JN0JvgrJnmLQVmUprDYQhmpxma0YeWE EGDtdKNnrqEa7BBA5qKDM9zgJrWUiPFHLCQL3JulR99hUfw2IYeI5lfzABdymN+NOB36 /MqenCEbaipmOIbHc6lzBvc9YVEFYy0AmvaR2s2ORknCFPpsHhpgC1j5/JKMNSArouc8 8k0pfeE1OLPfaOi4bqztk1lQ4qIMKJoPyvQOAzygjYyOzmiwhtGVuzrcttSGqgD8+jqU UNgwd4HIxIsCN/sSpuNRNh5KXiQVmPQuGKZjBDBKwULJx478zgHVilEKTdYFb9+Wgeln kQlw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ynOU9D+n/C593aR3+aH7h2j53IirX4AgmFGNr7usCrU=; b=qMetikMUQApN8/Yw70ypL/+UWsE6Bu+xUKMOJh3nx8+JCmysT6a5HtU5VDHk4Xrntp ga+Eyx5/v1qL/77TvHdlZz78C1V4p4Yx6iKbvxVphqvXjszrYwOsuG91RXpT9Y9nQMJu MpYjzXdNnhCUL8WAULZc7Ljv4pq0pGi7MKcX0Lq9M6jKP2wYUZr8KIK9kI2D2ckzzuMd VuKVcCKOXwQDbKLTGTA7pgaRRkB/LJa3/PgiTivg0mCjuBTS1CkEcJTcEkrPMNSmK7bK 12QExLQxoLz0A90slLrgZePmBVJqmvSXx57mnQKC1UjPE+vtJw/IFBqLK1KOq+z9hEi/ I4rQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=byTpf8Qo; spf=pass (google.com: domain of peter.griffin@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=peter.griffin@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from mail-sor-f65.google.com (mail-sor-f65.google.com. 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[86.31.179.135]) by smtp.gmail.com with ESMTPSA id t76sm5700147wmt.8.2019.04.19.01.35.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 19 Apr 2019 01:35:07 -0700 (PDT) From: Peter Griffin To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, john.stultz@linaro.org, airlied@linux.ie, daniel@ffwll.ch, robh+dt@kernel.org, mark.rutland@arm.com, p.zabel@pengutronix.de, xuwei5@hisilicon.com, mturquette@baylibre.com, sboyd@kernel.org, yuq825@gmail.com Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, lima@lists.freedesktop.org Subject: [PATCH v2 4/6] reset: hi6220: Add support for AO reset controller Date: Fri, 19 Apr 2019 09:32:59 +0100 Message-Id: <1555662781-22570-5-git-send-email-peter.griffin@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1555662781-22570-1-git-send-email-peter.griffin@linaro.org> References: <1555662781-22570-1-git-send-email-peter.griffin@linaro.org> This is required to bring Mali450 gpu out of reset. Also we now use CLK_OF_DECLARE_DRIVER to probe in both the clock and reset drivers. The clock and reset parts have been done as one atomic commit to avoid a bisection hole. Signed-off-by: Peter Griffin Cc: Stephen Boyd --- arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 1 + drivers/clk/hisilicon/clk-hi6220.c | 3 +- drivers/reset/hisilicon/hi6220_reset.c | 65 ++++++++++++++++++++++++++++++- 3 files changed, 67 insertions(+), 2 deletions(-) -- 2.7.4 diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index 2defc19..66a3746 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -260,6 +260,7 @@ compatible = "hisilicon,hi6220-aoctrl", "syscon"; reg = <0x0 0xf7800000 0x0 0x2000>; #clock-cells = <1>; + #reset-cells = <1>; }; sys_ctrl: sys_ctrl@f7030000 { diff --git a/drivers/clk/hisilicon/clk-hi6220.c b/drivers/clk/hisilicon/clk-hi6220.c index a87809d..3dde9d3 100644 --- a/drivers/clk/hisilicon/clk-hi6220.c +++ b/drivers/clk/hisilicon/clk-hi6220.c @@ -89,8 +89,9 @@ static void __init hi6220_clk_ao_init(struct device_node *np) hisi_clk_register_gate_sep(hi6220_separated_gate_clks_ao, ARRAY_SIZE(hi6220_separated_gate_clks_ao), clk_data_ao); } -CLK_OF_DECLARE(hi6220_clk_ao, "hisilicon,hi6220-aoctrl", hi6220_clk_ao_init); +/* reset driver also probes and uses these registers */ +CLK_OF_DECLARE_DRIVER(hi6220_clk_ao, "hisilicon,hi6220-aoctrl", hi6220_clk_ao_init); /* clocks in sysctrl */ static const char *mmc0_mux0_p[] __initdata = { "pll_ddr_gate", "syspll", }; diff --git a/drivers/reset/hisilicon/hi6220_reset.c b/drivers/reset/hisilicon/hi6220_reset.c index d5e5229..ccd5e0a 100644 --- a/drivers/reset/hisilicon/hi6220_reset.c +++ b/drivers/reset/hisilicon/hi6220_reset.c @@ -36,6 +36,7 @@ enum hi6220_reset_ctrl_type { PERIPHERAL, MEDIA, + AO, }; struct hi6220_reset_data { @@ -95,6 +96,61 @@ static const struct reset_control_ops hi6220_media_reset_ops = { .deassert = hi6220_media_deassert, }; +#define AO_SCTRL_SC_PW_CLKEN0 0x800 +#define AO_SCTRL_SC_PW_CLKDIS0 0x804 + +#define AO_SCTRL_SC_PW_RSTEN0 0x810 +#define AO_SCTRL_SC_PW_RSTDIS0 0x814 + +#define AO_SCTRL_SC_PW_ISOEN0 0x820 +#define AO_SCTRL_SC_PW_ISODIS0 0x824 +#define AO_MAX_INDEX 12 + +static int hi6220_ao_assert(struct reset_controller_dev *rc_dev, + unsigned long idx) +{ + struct hi6220_reset_data *data = to_reset_data(rc_dev); + struct regmap *regmap = data->regmap; + int ret; + + ret = regmap_write(regmap, AO_SCTRL_SC_PW_RSTEN0, BIT(idx)); + if (ret) + return ret; + + ret = regmap_write(regmap, AO_SCTRL_SC_PW_ISOEN0, BIT(idx)); + if (ret) + return ret; + + ret = regmap_write(regmap, AO_SCTRL_SC_PW_CLKDIS0, BIT(idx)); + if (ret) + return ret; +} + +static int hi6220_ao_deassert(struct reset_controller_dev *rc_dev, + unsigned long idx) +{ + struct hi6220_reset_data *data = to_reset_data(rc_dev); + struct regmap *regmap = data->regmap; + int ret; + + ret = regmap_write(regmap, AO_SCTRL_SC_PW_RSTDIS0, BIT(idx)); + if (ret) + return ret; + + ret = regmap_write(regmap, AO_SCTRL_SC_PW_ISODIS0, BIT(idx)); + if (ret) + return ret; + + ret = regmap_write(regmap, AO_SCTRL_SC_PW_CLKEN0, BIT(idx)); + if (ret) + return ret; +} + +static const struct reset_control_ops hi6220_ao_reset_ops = { + .assert = hi6220_ao_assert, + .deassert = hi6220_ao_deassert, +}; + static int hi6220_reset_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; @@ -120,9 +176,12 @@ static int hi6220_reset_probe(struct platform_device *pdev) if (type == MEDIA) { data->rc_dev.ops = &hi6220_media_reset_ops; data->rc_dev.nr_resets = MEDIA_MAX_INDEX; - } else { + } else if (type == PERIPHERAL) { data->rc_dev.ops = &hi6220_peripheral_reset_ops; data->rc_dev.nr_resets = PERIPH_MAX_INDEX; + } else { + data->rc_dev.ops = &hi6220_ao_reset_ops; + data->rc_dev.nr_resets = AO_MAX_INDEX; } return reset_controller_register(&data->rc_dev); @@ -137,6 +196,10 @@ static const struct of_device_id hi6220_reset_match[] = { .compatible = "hisilicon,hi6220-mediactrl", .data = (void *)MEDIA, }, + { + .compatible = "hisilicon,hi6220-aoctrl", + .data = (void *)AO, + }, { /* sentinel */ }, }; MODULE_DEVICE_TABLE(of, hi6220_reset_match); From patchwork Fri Apr 19 08:33:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Griffin X-Patchwork-Id: 162522 Delivered-To: patches@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp1750436jan; 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[86.31.179.135]) by smtp.gmail.com with ESMTPSA id t76sm5700147wmt.8.2019.04.19.01.35.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 19 Apr 2019 01:35:08 -0700 (PDT) From: Peter Griffin To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, john.stultz@linaro.org, airlied@linux.ie, daniel@ffwll.ch, robh+dt@kernel.org, mark.rutland@arm.com, p.zabel@pengutronix.de, xuwei5@hisilicon.com, mturquette@baylibre.com, sboyd@kernel.org, yuq825@gmail.com Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, lima@lists.freedesktop.org Subject: [PATCH v2 5/6] dt-bindings: reset: hisilicon: Add ao reset controller Date: Fri, 19 Apr 2019 09:33:00 +0100 Message-Id: <1555662781-22570-6-git-send-email-peter.griffin@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1555662781-22570-1-git-send-email-peter.griffin@linaro.org> References: <1555662781-22570-1-git-send-email-peter.griffin@linaro.org> This is required to bring Mali450 gpu out of reset. Signed-off-by: Peter Griffin Reviewed-by: Rob Herring --- include/dt-bindings/reset/hisi,hi6220-resets.h | 7 +++++++ 1 file changed, 7 insertions(+) -- 2.7.4 diff --git a/include/dt-bindings/reset/hisi,hi6220-resets.h b/include/dt-bindings/reset/hisi,hi6220-resets.h index e7c362a8..63aff7d 100644 --- a/include/dt-bindings/reset/hisi,hi6220-resets.h +++ b/include/dt-bindings/reset/hisi,hi6220-resets.h @@ -73,4 +73,11 @@ #define MEDIA_MMU 6 #define MEDIA_XG2RAM1 7 +#define AO_G3D 1 +#define AO_CODECISP 2 +#define AO_MCPU 4 +#define AO_BBPHARQMEM 5 +#define AO_HIFI 8 +#define AO_ACPUSCUL2C 12 + #endif /*_DT_BINDINGS_RESET_CONTROLLER_HI6220*/ From patchwork Fri Apr 19 08:33:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Griffin X-Patchwork-Id: 162523 Delivered-To: patches@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp1750451jan; Fri, 19 Apr 2019 01:35:11 -0700 (PDT) X-Received: by 2002:a5d:6a0f:: with SMTP id m15mr1949606wru.309.1555662911234; Fri, 19 Apr 2019 01:35:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1555662911; cv=none; d=google.com; s=arc-20160816; b=Gqv6/9Rc80ujfDeee6yjTmRRC8bYEEfuujTqo63mzVf0c71W33BNDxZD1z6DvV5wxt lud/KeJbUQE5FQ40cKPfXVlczHg+/SHWtRM17qOAuNpROs2gYnJGXjCyM/FF08LPNt+j x9MVzAwhPjIyLdTZTGSwskdWuUUmywtovTFQGbzOQGCWE3M9FwNLJ0oOUSmOdT5q8cjr ZMhrqkUhkcAyN+SYdP3KfRC6UMwO0EJDO/yvJKLc+umUSRWNOraw8yNEG5fW1Bi8n6zG 2f2rvvuPbLVlw86SlukIH6Ya0zCNrQvTCcec37M3w2TUS6DUzb6RBC2fsRaVL6aU2XFw bhxA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Ce+xsHXl4yFXBVy1VUWq5FJ/Ala/Os2pJsWh4xCgH2Q=; b=hd/vJKGRTPrvlcqmZOSL2UTkiMfD6Qfw+eHzdu8K9bEPXEJjfyjLi/kzJxg1nE+Dj7 5QGNk7D/khBbqUAeosVUK8p7IMy4LcNg4o9D3o8nq1EYwq1plm9XygEkvQfPvF/YxwOX 3ISXYToNN/AWOOpPGMm80nW430cfx8TKYzds2qqsA3xztVfcwUow/ucvArr+kNdcXIMZ TFe0p6Gvv09XrA2NKpHDJ9lzFvotf//84HqvsJNobqapDwQHYNh5SQQWn+Y37z5dNtpr gzKGltywmi/6sVew0Dm3UNhTiuZxNdSntRLe6fASOxESt1/8RlFGCnDAswqxE/t31A0X 8dGQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IE8Ds0UE; spf=pass (google.com: domain of peter.griffin@linaro.org designates 209.85.220.65 as permitted sender) smtp.mailfrom=peter.griffin@linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from mail-sor-f65.google.com (mail-sor-f65.google.com. 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[86.31.179.135]) by smtp.gmail.com with ESMTPSA id t76sm5700147wmt.8.2019.04.19.01.35.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 19 Apr 2019 01:35:10 -0700 (PDT) From: Peter Griffin To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, john.stultz@linaro.org, airlied@linux.ie, daniel@ffwll.ch, robh+dt@kernel.org, mark.rutland@arm.com, p.zabel@pengutronix.de, xuwei5@hisilicon.com, mturquette@baylibre.com, sboyd@kernel.org, yuq825@gmail.com Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, lima@lists.freedesktop.org, Rob Herring Subject: [PATCH v2 6/6] drm/lima: handle shared irq case for lima_pp_bcast_irq_handler Date: Fri, 19 Apr 2019 09:33:01 +0100 Message-Id: <1555662781-22570-7-git-send-email-peter.griffin@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1555662781-22570-1-git-send-email-peter.griffin@linaro.org> References: <1555662781-22570-1-git-send-email-peter.griffin@linaro.org> On Hikey board all lima ip blocks are shared with one irq. This patch avoids a NULL ptr deref crash on this platform on startup. Tested with Weston and kmscube. Signed-off-by: Peter Griffin Cc: Rob Herring Cc: Daniel Vetter Cc: Qiang Yu --- drivers/gpu/drm/lima/lima_pp.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) -- 2.7.4 diff --git a/drivers/gpu/drm/lima/lima_pp.c b/drivers/gpu/drm/lima/lima_pp.c index d29721e..8fef224 100644 --- a/drivers/gpu/drm/lima/lima_pp.c +++ b/drivers/gpu/drm/lima/lima_pp.c @@ -64,7 +64,13 @@ static irqreturn_t lima_pp_bcast_irq_handler(int irq, void *data) struct lima_ip *pp_bcast = data; struct lima_device *dev = pp_bcast->dev; struct lima_sched_pipe *pipe = dev->pipe + lima_pipe_pp; - struct drm_lima_m450_pp_frame *frame = pipe->current_task->frame; + struct drm_lima_m450_pp_frame *frame; + + /* for shared irq case */ + if (!pipe->current_task) + return IRQ_NONE; + + frame = pipe->current_task->frame; for (i = 0; i < frame->num_pp; i++) { struct lima_ip *ip = pipe->processor[i];