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[90.63.244.31]) by smtp.googlemail.com with ESMTPSA id z23sm12361894wma.0.2019.04.23.02.02.48 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 23 Apr 2019 02:02:48 -0700 (PDT) From: Jerome Brunet To: Ulf Hansson , Kevin Hilman Cc: Jerome Brunet , linux-mmc@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 4/7] mmc: meson-gx: disable HS400 Date: Tue, 23 Apr 2019 11:02:32 +0200 Message-Id: <20190423090235.17244-5-jbrunet@baylibre.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190423090235.17244-1-jbrunet@baylibre.com> References: <20190423090235.17244-1-jbrunet@baylibre.com> MIME-Version: 1.0 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org At the moment, all our attempts to enable HS400 on Amlogic chipsets have been unsuccessful or unreliable. Until we can figure out how to enable this mode safely and reliably, let's force it off. Signed-off-by: Jerome Brunet --- drivers/mmc/host/meson-gx-mmc.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) -- 2.20.1 Acked-by: Martin Blumenstingl diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c index 3df50b53f834..118f09da8dfb 100644 --- a/drivers/mmc/host/meson-gx-mmc.c +++ b/drivers/mmc/host/meson-gx-mmc.c @@ -823,10 +823,6 @@ static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) if (meson_mmc_timing_is_ddr(ios)) val |= CFG_DDR; - val &= ~CFG_CHK_DS; - if (ios->timing == MMC_TIMING_MMC_HS400) - val |= CFG_CHK_DS; - err = meson_mmc_clk_set(host, ios); if (err) dev_err(host->dev, "Failed to set clock: %d\n,", err); @@ -1339,6 +1335,13 @@ static int meson_mmc_probe(struct platform_device *pdev) mmc->max_segs = SD_EMMC_DESC_BUF_LEN / sizeof(struct sd_emmc_desc); mmc->max_seg_size = mmc->max_req_size; + /* + * At the moment, we don't know how to reliably enable HS400. + * From the different datasheets, it is not even clear if this mode + * is officially supported by any of the SoCs + */ + mmc->caps2 &= ~MMC_CAP2_HS400; + /* data bounce buffer */ host->bounce_buf_size = mmc->max_req_size; host->bounce_buf = From patchwork Tue Apr 23 09:02:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 162669 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp3541086jan; Tue, 23 Apr 2019 02:03:04 -0700 (PDT) X-Google-Smtp-Source: APXvYqwD3vHRRxzHhLZB/ahNCKV4ZcF6YGZw84nWEYU3qQA+4U1F+sIQUlEcBzIAkxXNnU3N19H0 X-Received: by 2002:a17:902:9006:: with SMTP id a6mr18447349plp.259.1556010183972; Tue, 23 Apr 2019 02:03:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556010183; cv=none; d=google.com; s=arc-20160816; b=q4deMwXpfAAHx7z40/VqY9XfhcD4IwsI8hrElqo4x+OO8PKDx10zu4u8Bw02bZU1ZD 8I1DMHhnB/ZYteVmvcAbdcyRdXRnDXIAuTQK4eO6EbxS0KtuOAUU2AbdM3dvmI9kvPqJ x6o22xEdmrrZcVx/29zEA9aJQfpkgzzKA05kOuZKog+m/4mqE99vNYzz7Ea+hGNW7Yiy sisDNXs8t+O6EcoSCEhQOoAy3jgYYs8b8IjdBmvNf+Kws29xNTDLjKq2lmTgnGEfGudE NfWYbcs/oUAKrVp6fnF+/EmBen/gY6x0COlgWymXu+OWM1xOT6bz3ODMF4SARoV8K+dO zEYA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=a2NNf2UNkHCYlSEUhojNPJKAy7RIBEN/uvTpac68Irc=; b=RG+0sgRSptoOCbV7MbzMqzgG3sHyFWl4HgA3r+ZrXwEsphnoQDzzgnSsKGeO19uoOZ O9wSY9bDqt+EU7xS+guFz8wKhv4UcT36HQJc7+HG4c6MNZYjzjiiwZqe/aetVm6byb3/ BchpNGQ/v9IkOH3HbO8/soGSmKbzQS7WoOEKpNTxO3ET+/YULtQb1AHRj6JSyQWz9u2k SuZkN6vTaaaDhIS3XyvZg0j4PmgrMZmd/iykPaINWYMp4RfoNSpd+uU4I6wqwzO5B0v1 5C4KmPURQemjaWtMNUCXFiJSWhj6PxTDENTXGDovNNb7RTuy9Fa19VPDKnadaXmZ8c1r +BXA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=pZVAggBK; spf=pass (google.com: best guess record for domain of linux-mmc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-mmc-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[90.63.244.31]) by smtp.googlemail.com with ESMTPSA id z23sm12361894wma.0.2019.04.23.02.02.53 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 23 Apr 2019 02:02:53 -0700 (PDT) From: Jerome Brunet To: Ulf Hansson , Kevin Hilman Cc: Jerome Brunet , linux-mmc@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 7/7] mmc: meson-gx: add signal resampling tuning Date: Tue, 23 Apr 2019 11:02:35 +0200 Message-Id: <20190423090235.17244-8-jbrunet@baylibre.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190423090235.17244-1-jbrunet@baylibre.com> References: <20190423090235.17244-1-jbrunet@baylibre.com> MIME-Version: 1.0 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Use signal resampling tuning for the UHS and HS200 modes. Instead of trying to get the *best* resampling setting with complex window calculation, we just stop on the first working setting. If the tuning setting later proves unstable, we will just continue the tuning where we left it. Signed-off-by: Jerome Brunet --- drivers/mmc/host/meson-gx-mmc.c | 73 +++++++++++++++++++++++++++++++-- 1 file changed, 70 insertions(+), 3 deletions(-) -- 2.20.1 Tested-by: Martin Blumenstingl diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c index acdc5520d02c..c5a8af4ca76b 100644 --- a/drivers/mmc/host/meson-gx-mmc.c +++ b/drivers/mmc/host/meson-gx-mmc.c @@ -488,6 +488,61 @@ static int meson_mmc_clk_init(struct meson_host *host) return clk_prepare_enable(host->mmc_clk); } +static void meson_mmc_disable_resampling(struct meson_host *host) +{ + unsigned int val = readl(host->regs + host->data->adjust); + + val &= ~ADJUST_ADJ_EN; + writel(val, host->regs + host->data->adjust); +} + +static void meson_mmc_reset_resampling(struct meson_host *host) +{ + unsigned int val; + + meson_mmc_disable_resampling(host); + + val = readl(host->regs + host->data->adjust); + val &= ~ADJUST_ADJ_DELAY_MASK; + writel(val, host->regs + host->data->adjust); +} + +static int meson_mmc_resampling_tuning(struct mmc_host *mmc, u32 opcode) +{ + struct meson_host *host = mmc_priv(mmc); + unsigned int val, dly, max_dly, i; + int ret; + + /* Resampling is done using the source clock */ + max_dly = DIV_ROUND_UP(clk_get_rate(host->mux_clk), + clk_get_rate(host->mmc_clk)); + + val = readl(host->regs + host->data->adjust); + val |= ADJUST_ADJ_EN; + writel(val, host->regs + host->data->adjust); + + if (mmc->doing_retune) + dly = FIELD_GET(ADJUST_ADJ_DELAY_MASK, val) + 1; + else + dly = 0; + + for (i = 0; i < max_dly; i++) { + val &= ~ADJUST_ADJ_DELAY_MASK; + val |= FIELD_PREP(ADJUST_ADJ_DELAY_MASK, (dly + i) % max_dly); + writel(val, host->regs + host->data->adjust); + + ret = mmc_send_tuning(mmc, opcode, NULL); + if (!ret) { + dev_dbg(mmc_dev(mmc), "resampling delay: %u\n", + (dly + i) % max_dly); + return 0; + } + } + + meson_mmc_reset_resampling(host); + return -EIO; +} + static int meson_mmc_prepare_ios_clock(struct meson_host *host, struct mmc_ios *ios) { @@ -507,6 +562,19 @@ static int meson_mmc_prepare_ios_clock(struct meson_host *host, return meson_mmc_clk_set(host, ios->clock, ddr); } +static void meson_mmc_check_resampling(struct meson_host *host, + struct mmc_ios *ios) +{ + switch (ios->timing) { + case MMC_TIMING_LEGACY: + case MMC_TIMING_MMC_HS: + case MMC_TIMING_SD_HS: + case MMC_TIMING_MMC_DDR52: + meson_mmc_disable_resampling(host); + break; + } +} + static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) { struct meson_host *host = mmc_priv(mmc); @@ -533,9 +601,6 @@ static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) if (!IS_ERR(mmc->supply.vmmc)) mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); - /* disable signal resampling */ - writel(0, host->regs + host->data->adjust); - break; case MMC_POWER_ON: @@ -574,6 +639,7 @@ static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) val |= FIELD_PREP(CFG_BUS_WIDTH_MASK, bus_width); writel(val, host->regs + SD_EMMC_CFG); + meson_mmc_check_resampling(host, ios); err = meson_mmc_prepare_ios_clock(host, ios); if (err) dev_err(host->dev, "Failed to set clock: %d\n,", err); @@ -963,6 +1029,7 @@ static const struct mmc_host_ops meson_mmc_ops = { .get_cd = meson_mmc_get_cd, .pre_req = meson_mmc_pre_req, .post_req = meson_mmc_post_req, + .execute_tuning = meson_mmc_resampling_tuning, .card_busy = meson_mmc_card_busy, .start_signal_voltage_switch = meson_mmc_voltage_switch, };