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[209.132.180.67]) by mx.google.com with ESMTP id v25si15753274pfe.22.2019.04.23.06.09.26; Tue, 23 Apr 2019 06:09:27 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=fSZJG3up; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727843AbfDWNJZ (ORCPT + 30 others); Tue, 23 Apr 2019 09:09:25 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:58086 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727458AbfDWNJY (ORCPT ); Tue, 23 Apr 2019 09:09:24 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x3ND9H64066380; Tue, 23 Apr 2019 08:09:17 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1556024957; bh=RZpK4r4tMtcaK9B3fLOobijRLwasK0ESgE2/q0ZKUUY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=fSZJG3upM7Ig5EFen+uTCbZE9ZC8CuZUVVseJibrA30FSrOFqpU900KNhZ6hO7wbD +vaNNJOgVWCbO2lZRYJLyoaidSPzPfgQkD4VodlwLZMDVE709cV4wPnAtf9IrHSAWk KJ55pZbA1VXWip1KMg5srv3Z63U8gFzianF5jx0g= Received: from DLEE108.ent.ti.com (dlee108.ent.ti.com [157.170.170.38]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x3ND9Hrw067110 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 23 Apr 2019 08:09:17 -0500 Received: from DLEE111.ent.ti.com (157.170.170.22) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Tue, 23 Apr 2019 08:09:17 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Tue, 23 Apr 2019 08:09:17 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x3ND9GhT125938; Tue, 23 Apr 2019 08:09:16 -0500 From: Grygorii Strashko To: , Ilias Apalodimas , "David S . Miller" , Ivan Khoronzhuk CC: Florian Fainelli , Andrew Lunn , Sekhar Nori , , , Murali Karicheri , Grygorii Strashko Subject: [PATCH net-next 02/19] net: ethernet: ti: cpsw: drop TI_DAVINCI_CPDMA config option Date: Tue, 23 Apr 2019 16:08:53 +0300 Message-ID: <1556024950-20752-3-git-send-email-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1556024950-20752-1-git-send-email-grygorii.strashko@ti.com> References: <1556024950-20752-1-git-send-email-grygorii.strashko@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Both drivers CPSW and EMAC can't work without CPDMA, hence simplify build of those drivers by always linking davinci_cpdma and drop TI_DAVINCI_CPDMA config option. Note. the davinci_emac driver module was changed to "ti_davinci_emac" to make build work. Signed-off-by: Grygorii Strashko --- drivers/net/ethernet/ti/Kconfig | 12 ------------ drivers/net/ethernet/ti/Makefile | 6 +++--- drivers/net/ethernet/ti/davinci_cpdma.c | 26 ------------------------- 3 files changed, 3 insertions(+), 41 deletions(-) -- 2.17.1 diff --git a/drivers/net/ethernet/ti/Kconfig b/drivers/net/ethernet/ti/Kconfig index 8b21b40a9fe5..46f253aadcdd 100644 --- a/drivers/net/ethernet/ti/Kconfig +++ b/drivers/net/ethernet/ti/Kconfig @@ -20,7 +20,6 @@ config TI_DAVINCI_EMAC tristate "TI DaVinci EMAC Support" depends on ARM && ( ARCH_DAVINCI || ARCH_OMAP3 ) || COMPILE_TEST select TI_DAVINCI_MDIO - select TI_DAVINCI_CPDMA select PHYLIB ---help--- This driver supports TI's DaVinci Ethernet . @@ -38,16 +37,6 @@ config TI_DAVINCI_MDIO To compile this driver as a module, choose M here: the module will be called davinci_mdio. This is recommended. -config TI_DAVINCI_CPDMA - tristate "TI DaVinci CPDMA Support" - depends on ARCH_DAVINCI || ARCH_OMAP2PLUS || COMPILE_TEST - select GENERIC_ALLOCATOR - ---help--- - This driver supports TI's DaVinci CPDMA dma engine. - - To compile this driver as a module, choose M here: the module - will be called davinci_cpdma. This is recommended. - config TI_CPSW_PHY_SEL bool "TI CPSW Phy mode Selection (DEPRECATED)" default n @@ -63,7 +52,6 @@ config TI_CPSW_ALE config TI_CPSW tristate "TI CPSW Switch Support" depends on ARCH_DAVINCI || ARCH_OMAP2PLUS || COMPILE_TEST - select TI_DAVINCI_CPDMA select TI_DAVINCI_MDIO select TI_CPSW_ALE select MFD_SYSCON diff --git a/drivers/net/ethernet/ti/Makefile b/drivers/net/ethernet/ti/Makefile index 0be551de821c..a763e1b27304 100644 --- a/drivers/net/ethernet/ti/Makefile +++ b/drivers/net/ethernet/ti/Makefile @@ -8,14 +8,14 @@ obj-$(CONFIG_TI_DAVINCI_EMAC) += cpsw-common.o obj-$(CONFIG_TLAN) += tlan.o obj-$(CONFIG_CPMAC) += cpmac.o -obj-$(CONFIG_TI_DAVINCI_EMAC) += davinci_emac.o +obj-$(CONFIG_TI_DAVINCI_EMAC) += ti_davinci_emac.o +ti_davinci_emac-y := davinci_emac.o davinci_cpdma.o obj-$(CONFIG_TI_DAVINCI_MDIO) += davinci_mdio.o -obj-$(CONFIG_TI_DAVINCI_CPDMA) += davinci_cpdma.o obj-$(CONFIG_TI_CPSW_PHY_SEL) += cpsw-phy-sel.o obj-$(CONFIG_TI_CPSW_ALE) += cpsw_ale.o obj-$(CONFIG_TI_CPTS_MOD) += cpts.o obj-$(CONFIG_TI_CPSW) += ti_cpsw.o -ti_cpsw-y := cpsw.o +ti_cpsw-y := cpsw.o davinci_cpdma.o obj-$(CONFIG_TI_KEYSTONE_NETCP) += keystone_netcp.o keystone_netcp-y := netcp_core.o diff --git a/drivers/net/ethernet/ti/davinci_cpdma.c b/drivers/net/ethernet/ti/davinci_cpdma.c index 41203714eda4..d43c32968ee9 100644 --- a/drivers/net/ethernet/ti/davinci_cpdma.c +++ b/drivers/net/ethernet/ti/davinci_cpdma.c @@ -520,7 +520,6 @@ struct cpdma_ctlr *cpdma_ctlr_create(struct cpdma_params *params) ctlr->num_chan = CPDMA_MAX_CHANNELS; return ctlr; } -EXPORT_SYMBOL_GPL(cpdma_ctlr_create); int cpdma_ctlr_start(struct cpdma_ctlr *ctlr) { @@ -581,7 +580,6 @@ int cpdma_ctlr_start(struct cpdma_ctlr *ctlr) spin_unlock_irqrestore(&ctlr->lock, flags); return 0; } -EXPORT_SYMBOL_GPL(cpdma_ctlr_start); int cpdma_ctlr_stop(struct cpdma_ctlr *ctlr) { @@ -614,7 +612,6 @@ int cpdma_ctlr_stop(struct cpdma_ctlr *ctlr) spin_unlock_irqrestore(&ctlr->lock, flags); return 0; } -EXPORT_SYMBOL_GPL(cpdma_ctlr_stop); int cpdma_ctlr_destroy(struct cpdma_ctlr *ctlr) { @@ -632,7 +629,6 @@ int cpdma_ctlr_destroy(struct cpdma_ctlr *ctlr) cpdma_desc_pool_destroy(ctlr); return ret; } -EXPORT_SYMBOL_GPL(cpdma_ctlr_destroy); int cpdma_ctlr_int_ctrl(struct cpdma_ctlr *ctlr, bool enable) { @@ -653,25 +649,21 @@ int cpdma_ctlr_int_ctrl(struct cpdma_ctlr *ctlr, bool enable) spin_unlock_irqrestore(&ctlr->lock, flags); return 0; } -EXPORT_SYMBOL_GPL(cpdma_ctlr_int_ctrl); void cpdma_ctlr_eoi(struct cpdma_ctlr *ctlr, u32 value) { dma_reg_write(ctlr, CPDMA_MACEOIVECTOR, value); } -EXPORT_SYMBOL_GPL(cpdma_ctlr_eoi); u32 cpdma_ctrl_rxchs_state(struct cpdma_ctlr *ctlr) { return dma_reg_read(ctlr, CPDMA_RXINTSTATMASKED); } -EXPORT_SYMBOL_GPL(cpdma_ctrl_rxchs_state); u32 cpdma_ctrl_txchs_state(struct cpdma_ctlr *ctlr) { return dma_reg_read(ctlr, CPDMA_TXINTSTATMASKED); } -EXPORT_SYMBOL_GPL(cpdma_ctrl_txchs_state); static void cpdma_chan_set_descs(struct cpdma_ctlr *ctlr, int rx, int desc_num, @@ -767,7 +759,6 @@ int cpdma_chan_split_pool(struct cpdma_ctlr *ctlr) return 0; } -EXPORT_SYMBOL_GPL(cpdma_chan_split_pool); /* cpdma_chan_set_weight - set weight of a channel in percentage. @@ -800,7 +791,6 @@ int cpdma_chan_set_weight(struct cpdma_chan *ch, int weight) spin_unlock_irqrestore(&ctlr->lock, flags); return ret; } -EXPORT_SYMBOL_GPL(cpdma_chan_set_weight); /* cpdma_chan_get_min_rate - get minimum allowed rate for channel * Should be called before cpdma_chan_set_rate. @@ -815,7 +805,6 @@ u32 cpdma_chan_get_min_rate(struct cpdma_ctlr *ctlr) return DIV_ROUND_UP(divident, divisor); } -EXPORT_SYMBOL_GPL(cpdma_chan_get_min_rate); /* cpdma_chan_set_rate - limits bandwidth for transmit channel. * The bandwidth * limited channels have to be in order beginning from lowest. @@ -860,7 +849,6 @@ int cpdma_chan_set_rate(struct cpdma_chan *ch, u32 rate) spin_unlock_irqrestore(&ctlr->lock, flags); return ret; } -EXPORT_SYMBOL_GPL(cpdma_chan_set_rate); u32 cpdma_chan_get_rate(struct cpdma_chan *ch) { @@ -873,7 +861,6 @@ u32 cpdma_chan_get_rate(struct cpdma_chan *ch) return rate; } -EXPORT_SYMBOL_GPL(cpdma_chan_get_rate); struct cpdma_chan *cpdma_chan_create(struct cpdma_ctlr *ctlr, int chan_num, cpdma_handler_fn handler, int rx_type) @@ -933,7 +920,6 @@ struct cpdma_chan *cpdma_chan_create(struct cpdma_ctlr *ctlr, int chan_num, spin_unlock_irqrestore(&ctlr->lock, flags); return chan; } -EXPORT_SYMBOL_GPL(cpdma_chan_create); int cpdma_chan_get_rx_buf_num(struct cpdma_chan *chan) { @@ -946,7 +932,6 @@ int cpdma_chan_get_rx_buf_num(struct cpdma_chan *chan) return desc_num; } -EXPORT_SYMBOL_GPL(cpdma_chan_get_rx_buf_num); int cpdma_chan_destroy(struct cpdma_chan *chan) { @@ -968,7 +953,6 @@ int cpdma_chan_destroy(struct cpdma_chan *chan) spin_unlock_irqrestore(&ctlr->lock, flags); return 0; } -EXPORT_SYMBOL_GPL(cpdma_chan_destroy); int cpdma_chan_get_stats(struct cpdma_chan *chan, struct cpdma_chan_stats *stats) @@ -981,7 +965,6 @@ int cpdma_chan_get_stats(struct cpdma_chan *chan, spin_unlock_irqrestore(&chan->lock, flags); return 0; } -EXPORT_SYMBOL_GPL(cpdma_chan_get_stats); static void __cpdma_chan_submit(struct cpdma_chan *chan, struct cpdma_desc __iomem *desc) @@ -1088,7 +1071,6 @@ int cpdma_chan_submit(struct cpdma_chan *chan, void *token, void *data, spin_unlock_irqrestore(&chan->lock, flags); return ret; } -EXPORT_SYMBOL_GPL(cpdma_chan_submit); bool cpdma_check_free_tx_desc(struct cpdma_chan *chan) { @@ -1103,7 +1085,6 @@ bool cpdma_check_free_tx_desc(struct cpdma_chan *chan) spin_unlock_irqrestore(&chan->lock, flags); return free_tx_desc; } -EXPORT_SYMBOL_GPL(cpdma_check_free_tx_desc); static void __cpdma_chan_free(struct cpdma_chan *chan, struct cpdma_desc __iomem *desc, @@ -1197,7 +1178,6 @@ int cpdma_chan_process(struct cpdma_chan *chan, int quota) } return used; } -EXPORT_SYMBOL_GPL(cpdma_chan_process); int cpdma_chan_start(struct cpdma_chan *chan) { @@ -1217,7 +1197,6 @@ int cpdma_chan_start(struct cpdma_chan *chan) return 0; } -EXPORT_SYMBOL_GPL(cpdma_chan_start); int cpdma_chan_stop(struct cpdma_chan *chan) { @@ -1280,7 +1259,6 @@ int cpdma_chan_stop(struct cpdma_chan *chan) spin_unlock_irqrestore(&chan->lock, flags); return 0; } -EXPORT_SYMBOL_GPL(cpdma_chan_stop); int cpdma_chan_int_ctrl(struct cpdma_chan *chan, bool enable) { @@ -1322,25 +1300,21 @@ int cpdma_control_set(struct cpdma_ctlr *ctlr, int control, int value) return ret; } -EXPORT_SYMBOL_GPL(cpdma_control_set); int cpdma_get_num_rx_descs(struct cpdma_ctlr *ctlr) { return ctlr->num_rx_desc; } -EXPORT_SYMBOL_GPL(cpdma_get_num_rx_descs); int cpdma_get_num_tx_descs(struct cpdma_ctlr *ctlr) { return ctlr->num_tx_desc; } -EXPORT_SYMBOL_GPL(cpdma_get_num_tx_descs); void cpdma_set_num_rx_descs(struct cpdma_ctlr *ctlr, int num_rx_desc) { ctlr->num_rx_desc = num_rx_desc; ctlr->num_tx_desc = ctlr->pool->num_desc - ctlr->num_rx_desc; } -EXPORT_SYMBOL_GPL(cpdma_set_num_rx_descs); MODULE_LICENSE("GPL"); From patchwork Tue Apr 23 13:08:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grygorii Strashko X-Patchwork-Id: 162693 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp3773022jan; Tue, 23 Apr 2019 06:12:17 -0700 (PDT) X-Google-Smtp-Source: APXvYqy+qK4vbJYbGT+42rJw35zWOs2Kmr+2futXKEgtRd0YBoqnUvpz04lCt6l56A1sF1mknaIw X-Received: by 2002:a17:902:8d89:: with SMTP id v9mr26694276plo.230.1556025137916; Tue, 23 Apr 2019 06:12:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556025137; cv=none; d=google.com; s=arc-20160816; b=VR4aztRgwtn1SwJ1LpXXBrZG3i8s/yqQQsHiGj2lx8fd0zWBaQeXix2MRYrW16StQy j6yRHPiTeHtCK/Aj21VGPEBXKgQ3Z+yg7HcfoveFxnGqT8w/vS84h+ZlRuNGahyD9FBH 9BymRhJclGg0yN7rNkdOomPMHVA01X19RL8b+hHnJcI75g/qZ9L9rRXtQalKuS1JoHut 8TtgEq0l4CKqPzh0+pnXNhYfpzGdqduJi/2TVGEnlKcgqKf/Mr+CmSkmSX2yA8OJKpKW RKnKu350ueVqtEKjkNKRPcGPTxoCR8139JF186W05srxtsrZB7oI5kL9mv6M1gvgezUc PteQ== ARC-Message-Signature: i=1; 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Miller" , Ivan Khoronzhuk CC: Florian Fainelli , Andrew Lunn , Sekhar Nori , , , Murali Karicheri , Grygorii Strashko Subject: [PATCH net-next 03/19] net: ethernet: ti: cpsw: drop CONFIG_TI_CPSW_ALE config option Date: Tue, 23 Apr 2019 16:08:54 +0300 Message-ID: <1556024950-20752-4-git-send-email-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1556024950-20752-1-git-send-email-grygorii.strashko@ti.com> References: <1556024950-20752-1-git-send-email-grygorii.strashko@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org All TI drivers CPSW/NETCP can't work without ALE, hence simplify build of those drivers by always linking cpsw_ale and drop CONFIG_TI_CPSW_ALE config option. Signed-off-by: Grygorii Strashko --- drivers/net/ethernet/ti/Kconfig | 7 ------- drivers/net/ethernet/ti/Makefile | 5 ++--- drivers/net/ethernet/ti/cpsw_ale.c | 14 -------------- 3 files changed, 2 insertions(+), 24 deletions(-) -- 2.17.1 diff --git a/drivers/net/ethernet/ti/Kconfig b/drivers/net/ethernet/ti/Kconfig index 46f253aadcdd..afbdc9744230 100644 --- a/drivers/net/ethernet/ti/Kconfig +++ b/drivers/net/ethernet/ti/Kconfig @@ -44,16 +44,10 @@ config TI_CPSW_PHY_SEL This driver supports configuring of the phy mode connected to the CPSW. DEPRECATED: use PHY_TI_GMII_SEL. -config TI_CPSW_ALE - tristate "TI CPSW ALE Support" - ---help--- - This driver supports TI's CPSW ALE module. - config TI_CPSW tristate "TI CPSW Switch Support" depends on ARCH_DAVINCI || ARCH_OMAP2PLUS || COMPILE_TEST select TI_DAVINCI_MDIO - select TI_CPSW_ALE select MFD_SYSCON select REGMAP ---help--- @@ -82,7 +76,6 @@ config TI_CPTS_MOD config TI_KEYSTONE_NETCP tristate "TI Keystone NETCP Core Support" - select TI_CPSW_ALE select TI_DAVINCI_MDIO depends on OF depends on KEYSTONE_NAVIGATOR_DMA && KEYSTONE_NAVIGATOR_QMSS diff --git a/drivers/net/ethernet/ti/Makefile b/drivers/net/ethernet/ti/Makefile index a763e1b27304..2f159a71f88e 100644 --- a/drivers/net/ethernet/ti/Makefile +++ b/drivers/net/ethernet/ti/Makefile @@ -12,12 +12,11 @@ obj-$(CONFIG_TI_DAVINCI_EMAC) += ti_davinci_emac.o ti_davinci_emac-y := davinci_emac.o davinci_cpdma.o obj-$(CONFIG_TI_DAVINCI_MDIO) += davinci_mdio.o obj-$(CONFIG_TI_CPSW_PHY_SEL) += cpsw-phy-sel.o -obj-$(CONFIG_TI_CPSW_ALE) += cpsw_ale.o obj-$(CONFIG_TI_CPTS_MOD) += cpts.o obj-$(CONFIG_TI_CPSW) += ti_cpsw.o -ti_cpsw-y := cpsw.o davinci_cpdma.o +ti_cpsw-y := cpsw.o davinci_cpdma.o cpsw_ale.o obj-$(CONFIG_TI_KEYSTONE_NETCP) += keystone_netcp.o -keystone_netcp-y := netcp_core.o +keystone_netcp-y := netcp_core.o cpsw_ale.o obj-$(CONFIG_TI_KEYSTONE_NETCP_ETHSS) += keystone_netcp_ethss.o keystone_netcp_ethss-y := netcp_ethss.o netcp_sgmii.o netcp_xgbepcsr.o diff --git a/drivers/net/ethernet/ti/cpsw_ale.c b/drivers/net/ethernet/ti/cpsw_ale.c index 1142fcfce566..3ef5257c9bc7 100644 --- a/drivers/net/ethernet/ti/cpsw_ale.c +++ b/drivers/net/ethernet/ti/cpsw_ale.c @@ -289,7 +289,6 @@ int cpsw_ale_flush_multicast(struct cpsw_ale *ale, int port_mask, int vid) } return 0; } -EXPORT_SYMBOL_GPL(cpsw_ale_flush_multicast); static inline void cpsw_ale_set_vlan_entry_type(u32 *ale_entry, int flags, u16 vid) @@ -327,7 +326,6 @@ int cpsw_ale_add_ucast(struct cpsw_ale *ale, const u8 *addr, int port, cpsw_ale_write(ale, idx, ale_entry); return 0; } -EXPORT_SYMBOL_GPL(cpsw_ale_add_ucast); int cpsw_ale_del_ucast(struct cpsw_ale *ale, const u8 *addr, int port, int flags, u16 vid) @@ -343,7 +341,6 @@ int cpsw_ale_del_ucast(struct cpsw_ale *ale, const u8 *addr, int port, cpsw_ale_write(ale, idx, ale_entry); return 0; } -EXPORT_SYMBOL_GPL(cpsw_ale_del_ucast); int cpsw_ale_add_mcast(struct cpsw_ale *ale, const u8 *addr, int port_mask, int flags, u16 vid, int mcast_state) @@ -377,7 +374,6 @@ int cpsw_ale_add_mcast(struct cpsw_ale *ale, const u8 *addr, int port_mask, cpsw_ale_write(ale, idx, ale_entry); return 0; } -EXPORT_SYMBOL_GPL(cpsw_ale_add_mcast); int cpsw_ale_del_mcast(struct cpsw_ale *ale, const u8 *addr, int port_mask, int flags, u16 vid) @@ -400,7 +396,6 @@ int cpsw_ale_del_mcast(struct cpsw_ale *ale, const u8 *addr, int port_mask, cpsw_ale_write(ale, idx, ale_entry); return 0; } -EXPORT_SYMBOL_GPL(cpsw_ale_del_mcast); /* ALE NetCP NU switch specific vlan functions */ static void cpsw_ale_set_vlan_mcast(struct cpsw_ale *ale, u32 *ale_entry, @@ -451,7 +446,6 @@ int cpsw_ale_add_vlan(struct cpsw_ale *ale, u16 vid, int port, int untag, cpsw_ale_write(ale, idx, ale_entry); return 0; } -EXPORT_SYMBOL_GPL(cpsw_ale_add_vlan); int cpsw_ale_del_vlan(struct cpsw_ale *ale, u16 vid, int port_mask) { @@ -473,7 +467,6 @@ int cpsw_ale_del_vlan(struct cpsw_ale *ale, u16 vid, int port_mask) cpsw_ale_write(ale, idx, ale_entry); return 0; } -EXPORT_SYMBOL_GPL(cpsw_ale_del_vlan); void cpsw_ale_set_allmulti(struct cpsw_ale *ale, int allmulti) { @@ -506,7 +499,6 @@ void cpsw_ale_set_allmulti(struct cpsw_ale *ale, int allmulti) cpsw_ale_write(ale, idx, ale_entry); } } -EXPORT_SYMBOL_GPL(cpsw_ale_set_allmulti); struct ale_control_info { const char *name; @@ -732,7 +724,6 @@ int cpsw_ale_control_set(struct cpsw_ale *ale, int port, int control, return 0; } -EXPORT_SYMBOL_GPL(cpsw_ale_control_set); int cpsw_ale_control_get(struct cpsw_ale *ale, int port, int control) { @@ -756,7 +747,6 @@ int cpsw_ale_control_get(struct cpsw_ale *ale, int port, int control) tmp = readl_relaxed(ale->params.ale_regs + offset) >> shift; return tmp & BITMASK(info->bits); } -EXPORT_SYMBOL_GPL(cpsw_ale_control_get); static void cpsw_ale_timer(struct timer_list *t) { @@ -781,14 +771,12 @@ void cpsw_ale_start(struct cpsw_ale *ale) add_timer(&ale->timer); } } -EXPORT_SYMBOL_GPL(cpsw_ale_start); void cpsw_ale_stop(struct cpsw_ale *ale) { del_timer_sync(&ale->timer); cpsw_ale_control_set(ale, 0, ALE_ENABLE, 0); } -EXPORT_SYMBOL_GPL(cpsw_ale_stop); struct cpsw_ale *cpsw_ale_create(struct cpsw_ale_params *params) { @@ -872,7 +860,6 @@ struct cpsw_ale *cpsw_ale_create(struct cpsw_ale_params *params) return ale; } -EXPORT_SYMBOL_GPL(cpsw_ale_create); void cpsw_ale_dump(struct cpsw_ale *ale, u32 *data) { @@ -883,7 +870,6 @@ void cpsw_ale_dump(struct cpsw_ale *ale, u32 *data) data += ALE_ENTRY_WORDS; } } -EXPORT_SYMBOL_GPL(cpsw_ale_dump); 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Miller" , Ivan Khoronzhuk CC: Florian Fainelli , Andrew Lunn , Sekhar Nori , , , Murali Karicheri , Grygorii Strashko Subject: [PATCH net-next 04/19] net: ethernet: ti: cpsw: update cpsw_split_res() to accept cpsw_common Date: Tue, 23 Apr 2019 16:08:55 +0300 Message-ID: <1556024950-20752-5-git-send-email-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1556024950-20752-1-git-send-email-grygorii.strashko@ti.com> References: <1556024950-20752-1-git-send-email-grygorii.strashko@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Update cpsw_split_res() to accept struct cpsw_common instead of struct net_device to simplify code. Signed-off-by: Grygorii Strashko --- drivers/net/ethernet/ti/cpsw.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) -- 2.17.1 diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c index 1c04c16e279b..13a339c64892 100644 --- a/drivers/net/ethernet/ti/cpsw.c +++ b/drivers/net/ethernet/ti/cpsw.c @@ -963,11 +963,9 @@ static void cpsw_rx_handler(void *token, int len, int status) dev_kfree_skb_any(new_skb); } -static void cpsw_split_res(struct net_device *ndev) +static void cpsw_split_res(struct cpsw_common *cpsw) { - struct cpsw_priv *priv = netdev_priv(ndev); u32 consumed_rate = 0, bigest_rate = 0; - struct cpsw_common *cpsw = priv->cpsw; struct cpsw_vector *txv = cpsw->txv; int i, ch_weight, rlim_ch_num = 0; int budget, bigest_rate_ch = 0; @@ -1341,7 +1339,7 @@ static void cpsw_adjust_link(struct net_device *ndev) if (link) { if (cpsw_need_resplit(cpsw)) - cpsw_split_res(ndev); + cpsw_split_res(cpsw); netif_carrier_on(ndev); if (netif_running(ndev)) @@ -2107,7 +2105,7 @@ static int cpsw_ndo_stop(struct net_device *ndev) for_each_slave(priv, cpsw_slave_stop, cpsw); if (cpsw_need_resplit(cpsw)) - cpsw_split_res(ndev); + cpsw_split_res(cpsw); cpsw->usage_count--; pm_runtime_put_sync(cpsw->dev); @@ -2594,7 +2592,7 @@ static int cpsw_ndo_set_tx_maxrate(struct net_device *ndev, int queue, u32 rate) netdev_get_tx_queue(slave->ndev, queue)->tx_maxrate = rate; } - cpsw_split_res(ndev); + cpsw_split_res(cpsw); return ret; } @@ -3063,7 +3061,7 @@ static int cpsw_set_channels(struct net_device *ndev, } if (cpsw->usage_count) - cpsw_split_res(ndev); + cpsw_split_res(cpsw); ret = cpsw_resume_data_pass(ndev); if (!ret) @@ -3698,7 +3696,7 @@ static int cpsw_probe(struct platform_device *pdev) netif_tx_napi_add(ndev, &cpsw->napi_tx, cpsw->quirk_irq ? cpsw_tx_poll : cpsw_tx_mq_poll, CPSW_POLL_WEIGHT); - cpsw_split_res(ndev); + cpsw_split_res(cpsw); /* register the network device */ SET_NETDEV_DEV(ndev, &pdev->dev); From patchwork Tue Apr 23 13:08:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grygorii Strashko X-Patchwork-Id: 162690 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp3772397jan; Tue, 23 Apr 2019 06:11:42 -0700 (PDT) X-Google-Smtp-Source: APXvYqwRI4c99bngS7Hs09tnJ5ht7kAZURlCzrPo5iwmu7zskolkNsNtyHonU9eJc4682QXK/VQo X-Received: by 2002:a65:5206:: with SMTP id o6mr8268325pgp.341.1556025102496; Tue, 23 Apr 2019 06:11:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556025102; cv=none; d=google.com; s=arc-20160816; b=anFtbOr8VxSfUCd7PDZwhUDMoowAEkCgCHeBCCDLQFr77eGGuzKeoqu4jv7KCJLojt wFCrT+nFnezsu9hZxMVmVmVS0BZ7fnGSxRmV8Od5ph38p7DcOvp9hIUYd0ZRqGhVitKk hVjyXrFUJYS0xrZiaSS7CxeGocEt+ZChOJrn5oqnIzWyaRfNuBFtYSMCLFsyzaHjf4LH IR4wUipT61zfaceZmaSD9OC3etDpZtEBy1WhtiZ3UNn15KN9YV56KZYaTb48LVYfO/KC TbnMUjE7IqHLf3p+ThNfaeG8pjX/wMh/tQQNKD0qTzAkHgz3x3Ca+P7E4UcCl87TkpI3 3jmQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=dcFdP7/tstT/6WcnK3TElLZH2V6USJ97aKCJntDrij0=; b=dn6FmXL2uUaImGcTJ7omPzSz8+UGfZau8tHvvxmHHJr8VKNZlil/qOzz/l4JocRJY2 3uNcDEm10niybNZNMBbLHYkWv97+FxHUbc0YbeTqedvZ8G2AtGL/pVmFmNVgwGoQBZhD WQ/Hie7ZM43KkKlDB9iHRJ1b5H00OLKwfsfOjTkuXlktz7fcsgp9F58qpFfolU0dZXEo 8Qe6YSDfOZbvc5L/wUiI7OfGGc7TMpsSei9yqdbvjgA4JE/EIZSzAiuuIsT3BX903lJI mijyA1xNG4JFGUv9XUqWoWMkhWsYcFnehpNFdcU4Pllb4LRWKdZqsAADrxxTCxxTZEr1 /3pw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=MG8otxIZ; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Miller" , Ivan Khoronzhuk CC: Florian Fainelli , Andrew Lunn , Sekhar Nori , , , Murali Karicheri , Grygorii Strashko Subject: [PATCH net-next 05/19] net: ethernet: ti: cpsw: use local var dev in probe Date: Tue, 23 Apr 2019 16:08:56 +0300 Message-ID: <1556024950-20752-6-git-send-email-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1556024950-20752-1-git-send-email-grygorii.strashko@ti.com> References: <1556024950-20752-1-git-send-email-grygorii.strashko@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Use local variable struct device *dev in probe to simplify code. Signed-off-by: Grygorii Strashko --- drivers/net/ethernet/ti/cpsw.c | 65 +++++++++++++++++----------------- 1 file changed, 33 insertions(+), 32 deletions(-) -- 2.17.1 diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c index 13a339c64892..0b8cc4e6d9cd 100644 --- a/drivers/net/ethernet/ti/cpsw.c +++ b/drivers/net/ethernet/ti/cpsw.c @@ -3458,6 +3458,7 @@ static const struct soc_device_attribute cpsw_soc_devices[] = { static int cpsw_probe(struct platform_device *pdev) { + struct device *dev = &pdev->dev; struct clk *clk; struct cpsw_platform_data *data; struct net_device *ndev; @@ -3474,15 +3475,15 @@ static int cpsw_probe(struct platform_device *pdev) int ret = 0, i, ch; int irq; - cpsw = devm_kzalloc(&pdev->dev, sizeof(struct cpsw_common), GFP_KERNEL); + cpsw = devm_kzalloc(dev, sizeof(struct cpsw_common), GFP_KERNEL); if (!cpsw) return -ENOMEM; - cpsw->dev = &pdev->dev; + cpsw->dev = dev; ndev = alloc_etherdev_mq(sizeof(struct cpsw_priv), CPSW_MAX_QUEUES); if (!ndev) { - dev_err(&pdev->dev, "error allocating net_device\n"); + dev_err(dev, "error allocating net_device\n"); return -ENOMEM; } @@ -3490,31 +3491,31 @@ static int cpsw_probe(struct platform_device *pdev) priv = netdev_priv(ndev); priv->cpsw = cpsw; priv->ndev = ndev; - priv->dev = &ndev->dev; + priv->dev = dev; priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG); cpsw->rx_packet_max = max(rx_packet_max, 128); - mode = devm_gpiod_get_array_optional(&pdev->dev, "mode", GPIOD_OUT_LOW); + mode = devm_gpiod_get_array_optional(dev, "mode", GPIOD_OUT_LOW); if (IS_ERR(mode)) { ret = PTR_ERR(mode); - dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret); + dev_err(dev, "gpio request failed, ret %d\n", ret); goto clean_ndev_ret; } /* * This may be required here for child devices. */ - pm_runtime_enable(&pdev->dev); + pm_runtime_enable(dev); /* Select default pin state */ - pinctrl_pm_select_default_state(&pdev->dev); + pinctrl_pm_select_default_state(dev); /* Need to enable clocks with runtime PM api to access module * registers */ - ret = pm_runtime_get_sync(&pdev->dev); + ret = pm_runtime_get_sync(dev); if (ret < 0) { - pm_runtime_put_noidle(&pdev->dev); + pm_runtime_put_noidle(dev); goto clean_runtime_disable_ret; } @@ -3528,15 +3529,15 @@ static int cpsw_probe(struct platform_device *pdev) if (is_valid_ether_addr(data->slave_data[0].mac_addr)) { memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN); - dev_info(&pdev->dev, "Detected MACID = %pM\n", priv->mac_addr); + dev_info(dev, "Detected MACID = %pM\n", priv->mac_addr); } else { eth_random_addr(priv->mac_addr); - dev_info(&pdev->dev, "Random MACID = %pM\n", priv->mac_addr); + dev_info(dev, "Random MACID = %pM\n", priv->mac_addr); } memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN); - cpsw->slaves = devm_kcalloc(&pdev->dev, + cpsw->slaves = devm_kcalloc(dev, data->slaves, sizeof(struct cpsw_slave), GFP_KERNEL); if (!cpsw->slaves) { @@ -3549,16 +3550,16 @@ static int cpsw_probe(struct platform_device *pdev) cpsw->slaves[0].ndev = ndev; priv->emac_port = 0; - clk = devm_clk_get(&pdev->dev, "fck"); + clk = devm_clk_get(dev, "fck"); if (IS_ERR(clk)) { - dev_err(priv->dev, "fck is not found\n"); + dev_err(dev, "fck is not found\n"); ret = -ENODEV; goto clean_dt_ret; } cpsw->bus_freq_mhz = clk_get_rate(clk) / 1000000; ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - ss_regs = devm_ioremap_resource(&pdev->dev, ss_res); + ss_regs = devm_ioremap_resource(dev, ss_res); if (IS_ERR(ss_regs)) { ret = PTR_ERR(ss_regs); goto clean_dt_ret; @@ -3568,7 +3569,7 @@ static int cpsw_probe(struct platform_device *pdev) cpsw->version = readl(&cpsw->regs->id_ver); res = platform_get_resource(pdev, IORESOURCE_MEM, 1); - cpsw->wr_regs = devm_ioremap_resource(&pdev->dev, res); + cpsw->wr_regs = devm_ioremap_resource(dev, res); if (IS_ERR(cpsw->wr_regs)) { ret = PTR_ERR(cpsw->wr_regs); goto clean_dt_ret; @@ -3606,7 +3607,7 @@ static int cpsw_probe(struct platform_device *pdev) (u32 __force) ss_res->start + CPSW2_BD_OFFSET; break; default: - dev_err(priv->dev, "unknown version 0x%08x\n", cpsw->version); + dev_err(dev, "unknown version 0x%08x\n", cpsw->version); ret = -ENODEV; goto clean_dt_ret; } @@ -3618,7 +3619,7 @@ static int cpsw_probe(struct platform_device *pdev) sliver_offset += SLIVER_SIZE; } - dma_params.dev = &pdev->dev; + dma_params.dev = dev; dma_params.rxthresh = dma_params.dmaregs + CPDMA_RXTHRESH; dma_params.rxfree = dma_params.dmaregs + CPDMA_RXFREE; dma_params.rxhdp = dma_params.txhdp + CPDMA_RXHDP; @@ -3637,7 +3638,7 @@ static int cpsw_probe(struct platform_device *pdev) cpsw->dma = cpdma_ctlr_create(&dma_params); if (!cpsw->dma) { - dev_err(priv->dev, "error initializing dma\n"); + dev_err(dev, "error initializing dma\n"); ret = -ENOMEM; goto clean_dt_ret; } @@ -3649,26 +3650,26 @@ static int cpsw_probe(struct platform_device *pdev) ch = cpsw->quirk_irq ? 0 : 7; cpsw->txv[0].ch = cpdma_chan_create(cpsw->dma, ch, cpsw_tx_handler, 0); if (IS_ERR(cpsw->txv[0].ch)) { - dev_err(priv->dev, "error initializing tx dma channel\n"); + dev_err(dev, "error initializing tx dma channel\n"); ret = PTR_ERR(cpsw->txv[0].ch); goto clean_dma_ret; } cpsw->rxv[0].ch = cpdma_chan_create(cpsw->dma, 0, cpsw_rx_handler, 1); if (IS_ERR(cpsw->rxv[0].ch)) { - dev_err(priv->dev, "error initializing rx dma channel\n"); + dev_err(dev, "error initializing rx dma channel\n"); ret = PTR_ERR(cpsw->rxv[0].ch); goto clean_dma_ret; } - ale_params.dev = &pdev->dev; + ale_params.dev = dev; ale_params.ale_ageout = ale_ageout; ale_params.ale_entries = data->ale_entries; ale_params.ale_ports = CPSW_ALE_PORTS_NUM; cpsw->ale = cpsw_ale_create(&ale_params); if (!cpsw->ale) { - dev_err(priv->dev, "error initializing ale engine\n"); + dev_err(dev, "error initializing ale engine\n"); ret = -ENODEV; goto clean_dma_ret; } @@ -3681,7 +3682,7 @@ static int cpsw_probe(struct platform_device *pdev) ndev->irq = platform_get_irq(pdev, 1); if (ndev->irq < 0) { - dev_err(priv->dev, "error getting irq resource\n"); + dev_err(dev, "error getting irq resource\n"); ret = ndev->irq; goto clean_dma_ret; } @@ -3699,10 +3700,10 @@ static int cpsw_probe(struct platform_device *pdev) cpsw_split_res(cpsw); /* register the network device */ - SET_NETDEV_DEV(ndev, &pdev->dev); + SET_NETDEV_DEV(ndev, dev); ret = register_netdev(ndev); if (ret) { - dev_err(priv->dev, "error registering net device\n"); + dev_err(dev, "error registering net device\n"); ret = -ENODEV; goto clean_dma_ret; } @@ -3731,10 +3732,10 @@ static int cpsw_probe(struct platform_device *pdev) } cpsw->irqs_table[0] = irq; - ret = devm_request_irq(&pdev->dev, irq, cpsw_rx_interrupt, - 0, dev_name(&pdev->dev), cpsw); + ret = devm_request_irq(dev, irq, cpsw_rx_interrupt, + 0, dev_name(dev), cpsw); if (ret < 0) { - dev_err(priv->dev, "error attaching irq (%d)\n", ret); + dev_err(dev, "error attaching irq (%d)\n", ret); goto clean_dma_ret; } @@ -3746,10 +3747,10 @@ static int cpsw_probe(struct platform_device *pdev) } cpsw->irqs_table[1] = irq; - ret = devm_request_irq(&pdev->dev, irq, cpsw_tx_interrupt, + ret = devm_request_irq(dev, irq, cpsw_tx_interrupt, 0, dev_name(&pdev->dev), cpsw); if (ret < 0) { - dev_err(priv->dev, "error attaching irq (%d)\n", ret); + dev_err(dev, "error attaching irq (%d)\n", ret); goto clean_dma_ret; } From patchwork Tue Apr 23 13:08:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grygorii Strashko X-Patchwork-Id: 162691 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp3772459jan; Tue, 23 Apr 2019 06:11:45 -0700 (PDT) X-Google-Smtp-Source: APXvYqy28NJYfBn06O+ra0jfY6KDdeuivxObFxnAH08RmQBAN4BdvJBtPJn/6ElcEYoKa/zgZudG X-Received: by 2002:a63:bf0d:: with SMTP id v13mr1651909pgf.186.1556025105547; Tue, 23 Apr 2019 06:11:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556025105; cv=none; d=google.com; s=arc-20160816; b=X/M9/JbJHthWj3gzvJZ05FF4Y4K9cr91EqsuKpsKoQwa1242G6mLXKIg+CQy6d0RAJ e6zsiPd5uHLhkejwngUROBEz8uwc0o3zvtm2iv5WkZJUbNgOoyC3qhunLloBzUuH1CIF Onct2cAwucSg3cIoUTqo3hsGpaaRH5M3rIlMEZzQ9bzdRnPp9B5unuvmY8rvYYHA7qPb ffL/5LHgMwV/tO5pYsOA48LhsEOi4knN2UIlrdkmTaCHw8y3IpEniocvtcaVxS/CrUQE Y1GstAEyuu1MiWc8m7uNkbg2+Sbd5C8yLyzdgdNtgfDvoHZSBvPwNeiBK9HWr0Si4DO2 DoCw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=XZorYBakLXjWZwDXheepjeRKRXXYJNlPp/uX0z6AJN0=; b=BFnhjXF1ZV3QWIJPOpHue+i9lMpGPgIWZQviaGmGo3iu1+clv1lkjvlrX5oNiusUaF L2PFtscABz1pN+TIKeorAv9HvPzRjdRHJ001uhJMUqAcwIv86jo03Zvecbv6eidJ5ZwY HxajJQAEGHgAJkJ7/C0mOpXvSdSdx7RmtsAAxUUH0XsM9N8Nsx6fy9fCovj6cmumAhEw hQZVVPNvAP8cfqYF71GTmmQX7CsTYZsS8t5gfURlimfFf4Oece75q53nOsrdFQ0B9a// Me6GmJH70hlLEGUjKuk3p45gyOsS/3sDmM3vIfjQRolDG2J8LxNuRxURbNWzBx5h32WB hQyw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=ZuoEFSq+; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Miller" , Ivan Khoronzhuk CC: Florian Fainelli , Andrew Lunn , Sekhar Nori , , , Murali Karicheri , Grygorii Strashko Subject: [PATCH net-next 06/19] net: ethernet: ti: cpsw: drop pinctrl_pm_select_default_state call Date: Tue, 23 Apr 2019 16:08:57 +0300 Message-ID: <1556024950-20752-7-git-send-email-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1556024950-20752-1-git-send-email-grygorii.strashko@ti.com> References: <1556024950-20752-1-git-send-email-grygorii.strashko@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Drop pinctrl_pm_select_default_state call from probe as default pinctrl state is set by DD core. Signed-off-by: Grygorii Strashko --- drivers/net/ethernet/ti/cpsw.c | 3 --- 1 file changed, 3 deletions(-) -- 2.17.1 diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c index 0b8cc4e6d9cd..17dd81f25f5e 100644 --- a/drivers/net/ethernet/ti/cpsw.c +++ b/drivers/net/ethernet/ti/cpsw.c @@ -3507,9 +3507,6 @@ static int cpsw_probe(struct platform_device *pdev) */ pm_runtime_enable(dev); - /* Select default pin state */ - pinctrl_pm_select_default_state(dev); - /* Need to enable clocks with runtime PM api to access module * registers */ From patchwork Tue Apr 23 13:08:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grygorii Strashko X-Patchwork-Id: 162689 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp3772164jan; Tue, 23 Apr 2019 06:11:30 -0700 (PDT) X-Google-Smtp-Source: APXvYqyqVu3AjGK1dBADtvklinUYINzQN1IopnePhL33DGlJIOuKO3vix+6+Z9BMPwCnRunT+w4W X-Received: by 2002:a62:2541:: with SMTP id l62mr4501651pfl.243.1556025090206; Tue, 23 Apr 2019 06:11:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556025090; cv=none; d=google.com; s=arc-20160816; b=ob9QJnOv6rc79hRiasO+G82k6uTSzE6jb5+nasOC6ffaedYI+NanzZVQi1Fx/QS+FK yOswOCuvcgkSKLUylNh05+Y6lH3ZcAQJtqa7tiHwDgd6194QDz5ytoIjmsCoWl9fx9h2 w6vvxHEC0aVQryiLHLJDhvXRMfxRFYOtlJzCQVMwnHjUmqezuKza/5LFWqNm+BsVm8V4 g6ugYGUzAusK+qdGRdHoCPtMibaryP416UWGLToXxRicQ/EoUvvuIt4QDsJVwbfKEes1 ghaE6gA+y055g6JpXtWegWIE5CaXuJid0lo8rtri4UAKh1qG+tVZmImXOHNuvjSiikPy QOxQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=u1SHPJmYCJP27BMPAbTUHo3jU/kt4nI6ZfcbGHQ5VsE=; b=bjSvgQ25y/VrpJeoVIEBGXbaEbZep7RGWFwGNvyMKoitqsZ1BhypXDfPfWTi6U1V5O xD0FXqgShn3FHc8yE8MXcVdsk5YEcbDR5lVZ08M6TlBXWvuh68Ie25/M2RoMrmPZOGEW H2WLk5AOagN3mB1t2VVyUdO9HncGXu/YyVob2nXJUVc5kxrusC2czg4ZFabMyQ8l0Fdv qoD+/SGJfymMrgv48tZ3ngh1P8nhQwVHSC7EA7kK2QKwL00HHr/smHHn586SIDhuZZlP TLGab/R99YRXfeA+H80UQ+K+kICOq7vN0hBXg5ikskX5sxybYxdYwXbRtHRPB+e1jVxw m/cg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="n/xD416J"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Miller" , Ivan Khoronzhuk CC: Florian Fainelli , Andrew Lunn , Sekhar Nori , , , Murali Karicheri , Grygorii Strashko Subject: [PATCH net-next 08/19] net: ethernet: ti: cpsw: drop cpsw_tx_packet_submit() Date: Tue, 23 Apr 2019 16:08:59 +0300 Message-ID: <1556024950-20752-9-git-send-email-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1556024950-20752-1-git-send-email-grygorii.strashko@ti.com> References: <1556024950-20752-1-git-send-email-grygorii.strashko@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Drop unnecessary wrapper function cpsw_tx_packet_submit() which is used only in one place. Signed-off-by: Grygorii Strashko --- drivers/net/ethernet/ti/cpsw.c | 15 +++------------ 1 file changed, 3 insertions(+), 12 deletions(-) -- 2.17.1 diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c index e714b8f4739c..fe3d145846d2 100644 --- a/drivers/net/ethernet/ti/cpsw.c +++ b/drivers/net/ethernet/ti/cpsw.c @@ -1500,17 +1500,6 @@ static void cpsw_get_ethtool_stats(struct net_device *ndev, } } -static inline int cpsw_tx_packet_submit(struct cpsw_priv *priv, - struct sk_buff *skb, - struct cpdma_chan *txch) -{ - struct cpsw_common *cpsw = priv->cpsw; - - skb_tx_timestamp(skb); - return cpdma_chan_submit(txch, skb, skb->data, skb->len, - priv->emac_port + cpsw->data.dual_emac); -} - static inline void cpsw_add_dual_emac_def_ale_entries( struct cpsw_priv *priv, struct cpsw_slave *slave, u32 slave_port) @@ -2138,7 +2127,9 @@ static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb, txch = cpsw->txv[q_idx].ch; txq = netdev_get_tx_queue(ndev, q_idx); - ret = cpsw_tx_packet_submit(priv, skb, txch); + skb_tx_timestamp(skb); + ret = cpdma_chan_submit(txch, skb, skb->data, skb->len, + priv->emac_port + cpsw->data.dual_emac); if (unlikely(ret != 0)) { cpsw_err(priv, tx_err, "desc submit failed\n"); goto fail; From patchwork Tue Apr 23 13:09:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grygorii Strashko X-Patchwork-Id: 162678 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp3769957jan; Tue, 23 Apr 2019 06:09:37 -0700 (PDT) X-Google-Smtp-Source: APXvYqxRd7Q3YnkTMEGR7eMYxUptaaKSldtf0YCU+LIEFh0cgG789U8Q7FgEzAtdDa1U5R2R32Eh X-Received: by 2002:aa7:8e0d:: with SMTP id c13mr27301013pfr.193.1556024977707; Tue, 23 Apr 2019 06:09:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556024977; cv=none; d=google.com; s=arc-20160816; b=BUjxzywUUe6AcQUJY0x4/pKzdENpJVMH7kC2+5aGy2qhJIUv/63TP/w1AOE8YSWpyx cqXV5xFwL1pyrftdQ7PRdcvRZX1/2Viohe/jLUy+dim8MNnpApd4way7EzUOLq9kR0e4 +0haJBzXhZC00IJXMI54y0PpaFOCXDIsrTGmMsAimty4e2HtXmv4Jiz5gWGoQ0rI7bPX HpGAH+tISTjPcILSmNiFT8Fa2m3KE6oSlY6zdvwvtSYOoruK/RNHgrqhPcZ0NvzdKSgE +pbjCgDOkLvrWSzr3RbU37gUD3tmpphPJyjkxrpJnAqXg+djRugTA3ThFyHcU3k6s3UC LGUQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=XpaFr+l9BVrOYfWgZAClN8nnBFE0HPwgX6ZoUxwVuNc=; b=Q9Ual6pSAHZqnKD2pMyGv3gxlFC3aoGQd1IvqnohfmC+KwfUQkU+zUkOh3InjbstJO SJvdYnUdSEhDtaMv72UAAOlarfUoj3KoGduPThtlFK6IfgCPunvuiXo16JnlGRR0z8mr gqPa18tH0A6jMpGXoFfQZtlJZkgwD335oqzlb1Bz/oOmQwj2lqOlOf3BqbMWFByqM3+S oUOztz7bkicHHipHjyK4TatPQnH2Mr7zWKcobOGPZVKEDASh6d0xKUnJbsHrCKoBNRA5 4x+9Ra6ogCEwKTJwfSdgEA2IlwyN9QnEzB4uUx+Xbb8Hjql8gnGbTdZL1LUVL/+Hi2Yz QLiA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=UgxlkvzG; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Miller" , Ivan Khoronzhuk CC: Florian Fainelli , Andrew Lunn , Sekhar Nori , , , Murali Karicheri , Grygorii Strashko Subject: [PATCH net-next 09/19] net: ethernet: ti: ale: fix mcast super setting Date: Tue, 23 Apr 2019 16:09:00 +0300 Message-ID: <1556024950-20752-10-git-send-email-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1556024950-20752-1-git-send-email-grygorii.strashko@ti.com> References: <1556024950-20752-1-git-send-email-grygorii.strashko@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Use correct define ALE_SUPER for ALE Multicast Address Table Entry Supervisory Packet (SUPER) bit setting instead of ALE_BLOCKED. No issues were observed till now as it have never been set, but it's going to be used by new CPSW switch driver. Signed-off-by: Grygorii Strashko --- drivers/net/ethernet/ti/cpsw_ale.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.17.1 diff --git a/drivers/net/ethernet/ti/cpsw_ale.c b/drivers/net/ethernet/ti/cpsw_ale.c index 3ef5257c9bc7..7ac0c5ae0c92 100644 --- a/drivers/net/ethernet/ti/cpsw_ale.c +++ b/drivers/net/ethernet/ti/cpsw_ale.c @@ -355,7 +355,7 @@ int cpsw_ale_add_mcast(struct cpsw_ale *ale, const u8 *addr, int port_mask, cpsw_ale_set_vlan_entry_type(ale_entry, flags, vid); cpsw_ale_set_addr(ale_entry, addr); - cpsw_ale_set_super(ale_entry, (flags & ALE_BLOCKED) ? 1 : 0); + cpsw_ale_set_super(ale_entry, (flags & ALE_SUPER) ? 1 : 0); cpsw_ale_set_mcast_state(ale_entry, mcast_state); mask = cpsw_ale_get_port_mask(ale_entry, From patchwork Tue Apr 23 13:09:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grygorii Strashko X-Patchwork-Id: 162688 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp3771843jan; Tue, 23 Apr 2019 06:11:13 -0700 (PDT) X-Google-Smtp-Source: APXvYqyNVyKrPcRsP6E80aQcT/OTrq5JT0He3GpFMuSPpz6KXyQYPriGIU7/9+mkpV9nckrsjl02 X-Received: by 2002:a17:902:2b88:: with SMTP id l8mr25949323plb.262.1556025073383; Tue, 23 Apr 2019 06:11:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556025073; cv=none; d=google.com; s=arc-20160816; b=jwE0NBQ8FVqIKKuQrjrl0fxyQTdNNbKZObkoOqGNZ8P89naxe+nDRpbA8CHKQ4II6j 90H1Fmu4JNtT2esorNT5EOMh3pzyybCKgd7yr8t8vCSPRoALGgvR1F5dIlvB5eHwcsEc y2djH4OnRhr6x1uSkpDxjpZKHcGUO8MsJKBS/xzyhDuGtQTFdnTTq/0bUhWTtRnb00VG thlmku1Lu6lMtdJnrL/sqeDpGxgtoF3SPdDiv67/6WXPLtX+ptrvSztwGvfFFYp028wu RkO5qRvUkg0O6UzlRG4PV4oEZSO3Wa3BZ1n2LsmmbxGQwfQQaJVyRPdFCay+zB8TfHRp D9jA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=3Sd+0+IAB5WaDGreXx7707W4ctxgY0rxsF/1Amf0TEA=; b=ftgdjZgrXFUIDwLssDqejLUDTf4UnA1cOmYJdqf/APdqt6io6lR8eMKJckC3mDqrWk TvqW/p9uklZBaUO9VTEbP95JmbTluEiHX7CYguiNE8EbAqUWCXD6fysA1e//Bx7P3+bp QHecuU0AIzDtSuxYh4217Ch6n6P29Khs9jkvfW0LxFwjKOIKr8Iyt9QsIYVGBnrAh9s3 sCe03Db6XCDFHlQKNkDnLwIZPiVso6NU7MBiiVCR2t0hBq5Mt3cXPyZ8MpRut0tUDQkw uZKuZMZNDmdZ+yilAhHUoSI6Z/+B1QCulADRTu6+Q9zSPr5E+fWuzn//BT1/DFIvIe6U H+eQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="rwZE7/B8"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Miller" , Ivan Khoronzhuk CC: Florian Fainelli , Andrew Lunn , Sekhar Nori , , , Murali Karicheri , Grygorii Strashko Subject: [PATCH net-next 10/19] net: ethernet: ti: ale: use define for host port in cpsw_ale_set_allmulti() Date: Tue, 23 Apr 2019 16:09:01 +0300 Message-ID: <1556024950-20752-11-git-send-email-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1556024950-20752-1-git-send-email-grygorii.strashko@ti.com> References: <1556024950-20752-1-git-send-email-grygorii.strashko@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Use ALE_PORT_HOST define for host port in cpsw_ale_set_allmulti() instead of constants. Signed-off-by: Grygorii Strashko --- drivers/net/ethernet/ti/cpsw_ale.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/drivers/net/ethernet/ti/cpsw_ale.c b/drivers/net/ethernet/ti/cpsw_ale.c index 7ac0c5ae0c92..83ccb422dddd 100644 --- a/drivers/net/ethernet/ti/cpsw_ale.c +++ b/drivers/net/ethernet/ti/cpsw_ale.c @@ -491,9 +491,9 @@ void cpsw_ale_set_allmulti(struct cpsw_ale *ale, int allmulti) cpsw_ale_get_vlan_unreg_mcast(ale_entry, ale->vlan_field_bits); if (allmulti) - unreg_mcast |= 1; + unreg_mcast |= ALE_PORT_HOST; else - unreg_mcast &= ~1; + unreg_mcast &= ~ALE_PORT_HOST; cpsw_ale_set_vlan_unreg_mcast(ale_entry, unreg_mcast, ale->vlan_field_bits); cpsw_ale_write(ale, idx, ale_entry); From patchwork Tue Apr 23 13:09:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grygorii Strashko X-Patchwork-Id: 162679 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp3770010jan; Tue, 23 Apr 2019 06:09:40 -0700 (PDT) X-Google-Smtp-Source: APXvYqwVPv++b4fEMD1sYGqR70VhQEhXdSk2rSBbe/6BpYU3gW6Vjpv7fouPTZpoPx/caZkPDrCj X-Received: by 2002:a17:902:ab87:: with SMTP id f7mr26253981plr.85.1556024980132; Tue, 23 Apr 2019 06:09:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556024980; cv=none; d=google.com; s=arc-20160816; b=VLV3a/5+2VRd0Q6xcYmO2ytSc6JW8AEyMus2hze2UmV9Dbn48ukNptAeg3S2X+yGqa mZMmZPZ/D7erjYMeO9S8i3NNKEwOMI4lrLiwYTFNAXLTbD3wkjpOVLd53S0oHuSG2Xd/ MpktdSbxOloqlT2BWz49Fgc2+PSotOwyftmyhWXpoPVHpe8H5KJtxycOakzbnfGViKWZ hM7hMM13djAtoGzQJm1/xGfWD8hPMC3AIe6X6SjuH5l+gNnYAv0letuDP0M4XLhe6GKa C7uBWqFw5GGKqKFttfjsJuCdfxiMajDtVR6ZZwG+emH7PT+h/6fTsMpf6pN6ISAoJ98m 7okQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=hta9GhaPluM9fjd73h2oN8Xx7kdbrlYa7Vd+T3ltXO0=; b=wh25NFzNQ/iMrhDFFRI0Cyhhozff1liASQgyVub3x18TdeIwLrLnx7MmMi6JP/RC2u fadVczXjl5LKLXazJQaZWPlo3wn1zHQ54bLuvd/jUNURarwk+IR3b519jwCxA4GL6nnB FQXYTpVxLVbzMJRZ+QK6VMTFQK56b+1lE+Qb53nrl2Q9ET5YXMShEMI4r+c6HI+gXQMu 3HXajxEAyOiRdUdFjffLXzCncgpkH7G2km4aPoIm77Wc7mfryCyjLYdGg3E/p+thu+MV Xpa7Ei7rVvc8gB0cQS71neEAulgX21a0Y2YdeOGfQ9/oq47gfas1PyzKqVJwP7NXdyLU E00Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=RRUtw+V0; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Miller" , Ivan Khoronzhuk CC: Florian Fainelli , Andrew Lunn , Sekhar Nori , , , Murali Karicheri , Grygorii Strashko Subject: [PATCH net-next 11/19] net: ethernet: ti: cpsw: fix allmulti cfg in dual_mac mode Date: Tue, 23 Apr 2019 16:09:02 +0300 Message-ID: <1556024950-20752-12-git-send-email-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1556024950-20752-1-git-send-email-grygorii.strashko@ti.com> References: <1556024950-20752-1-git-send-email-grygorii.strashko@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Now CPSW ALE will set/clean Host port bit in Unregistered Multicast Flood Mask (UNREG_MCAST_FLOOD_MASK) for every VLAN without checking if this port belongs to VLAN or not when ALLMULTI mode flag is set for nedev. This is working in non dual_mac mode, but in dual_mac - it causes enabling/disabling ALLMULTI flag for both ports. Hence fix it by adding additional parameter to cpsw_ale_set_allmulti() to specify ALE port number for which ALLMULTI has to be enabled and check if port belongs to VLAN before modifying UNREG_MCAST_FLOOD_MASK. Signed-off-by: Grygorii Strashko --- drivers/net/ethernet/ti/cpsw.c | 12 +++++++++--- drivers/net/ethernet/ti/cpsw_ale.c | 12 ++++++++++-- drivers/net/ethernet/ti/cpsw_ale.h | 2 +- 3 files changed, 20 insertions(+), 6 deletions(-) -- 2.17.1 diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c index fe3d145846d2..c497992f01f7 100644 --- a/drivers/net/ethernet/ti/cpsw.c +++ b/drivers/net/ethernet/ti/cpsw.c @@ -793,12 +793,17 @@ static int cpsw_purge_all_mc(struct net_device *ndev, const u8 *addr, int num) static void cpsw_ndo_set_rx_mode(struct net_device *ndev) { - struct cpsw_common *cpsw = ndev_to_cpsw(ndev); + struct cpsw_priv *priv = netdev_priv(ndev); + struct cpsw_common *cpsw = priv->cpsw; + int slave_port = -1; + + if (cpsw->data.dual_emac) + slave_port = priv->emac_port + 1; if (ndev->flags & IFF_PROMISC) { /* Enable promiscuous mode */ cpsw_set_promiscious(ndev, true); - cpsw_ale_set_allmulti(cpsw->ale, IFF_ALLMULTI); + cpsw_ale_set_allmulti(cpsw->ale, IFF_ALLMULTI, slave_port); return; } else { /* Disable promiscuous mode */ @@ -806,7 +811,8 @@ static void cpsw_ndo_set_rx_mode(struct net_device *ndev) } /* Restore allmulti on vlans if necessary */ - cpsw_ale_set_allmulti(cpsw->ale, ndev->flags & IFF_ALLMULTI); + cpsw_ale_set_allmulti(cpsw->ale, + ndev->flags & IFF_ALLMULTI, slave_port); /* add/remove mcast address either for real netdev or for vlan */ __hw_addr_ref_sync_dev(&ndev->mc, ndev, cpsw_add_mc_addr, diff --git a/drivers/net/ethernet/ti/cpsw_ale.c b/drivers/net/ethernet/ti/cpsw_ale.c index 83ccb422dddd..f7369982ae33 100644 --- a/drivers/net/ethernet/ti/cpsw_ale.c +++ b/drivers/net/ethernet/ti/cpsw_ale.c @@ -468,11 +468,11 @@ int cpsw_ale_del_vlan(struct cpsw_ale *ale, u16 vid, int port_mask) return 0; } -void cpsw_ale_set_allmulti(struct cpsw_ale *ale, int allmulti) +void cpsw_ale_set_allmulti(struct cpsw_ale *ale, int allmulti, int port) { u32 ale_entry[ALE_ENTRY_WORDS]; - int type, idx; int unreg_mcast = 0; + int type, idx; /* Only bother doing the work if the setting is actually changing */ if (ale->allmulti == allmulti) @@ -482,10 +482,18 @@ void cpsw_ale_set_allmulti(struct cpsw_ale *ale, int allmulti) ale->allmulti = allmulti; for (idx = 0; idx < ale->params.ale_entries; idx++) { + int vlan_members; + cpsw_ale_read(ale, idx, ale_entry); type = cpsw_ale_get_entry_type(ale_entry); if (type != ALE_TYPE_VLAN) continue; + vlan_members = + cpsw_ale_get_vlan_member_list(ale_entry, + ale->vlan_field_bits); + + if (port != -1 && !(vlan_members & BIT(port))) + continue; unreg_mcast = cpsw_ale_get_vlan_unreg_mcast(ale_entry, diff --git a/drivers/net/ethernet/ti/cpsw_ale.h b/drivers/net/ethernet/ti/cpsw_ale.h index 4777d626fac8..8a0d25950dc1 100644 --- a/drivers/net/ethernet/ti/cpsw_ale.h +++ b/drivers/net/ethernet/ti/cpsw_ale.h @@ -109,7 +109,7 @@ int cpsw_ale_del_mcast(struct cpsw_ale *ale, const u8 *addr, int port_mask, int cpsw_ale_add_vlan(struct cpsw_ale *ale, u16 vid, int port, int untag, int reg_mcast, int unreg_mcast); int cpsw_ale_del_vlan(struct cpsw_ale *ale, u16 vid, int port); -void cpsw_ale_set_allmulti(struct cpsw_ale *ale, int allmulti); +void cpsw_ale_set_allmulti(struct cpsw_ale *ale, int allmulti, int port); int cpsw_ale_control_get(struct cpsw_ale *ale, int port, int control); int cpsw_ale_control_set(struct cpsw_ale *ale, int port, From patchwork Tue Apr 23 13:09:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grygorii Strashko X-Patchwork-Id: 162681 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp3770104jan; Tue, 23 Apr 2019 06:09:44 -0700 (PDT) X-Google-Smtp-Source: APXvYqxlfOTTDmCAEYBzAQZkJy9fCAt3LsF1liRBzpvffl0V65PKhiYQC+AtelBmfazTc0kPb8Fi X-Received: by 2002:a62:e10e:: with SMTP id q14mr9105927pfh.161.1556024984464; Tue, 23 Apr 2019 06:09:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556024984; cv=none; d=google.com; s=arc-20160816; b=Bc7FKcEdSEJB9ahuPtgaQ8ysJ1mCkCzWonM/4AJ1mq3B76heEk7+rFGnqRDo42b3DX 5TEDeOs9wk4OYNJIU+Aj+W+9lkWpb64K1VTmzLsTn/mXc9HuX9BdOCbKV+0fkJ2Tof/N X4YnHRq3M+ljziAbd6OeYBxyJlCNSns6/+7G+TAayM6b2gWgV5TZUMcmSkUDk7eoSBDH /91LlaVXfXwLlidXm4rwXGzc6ZpIobvYNPSSET41upwzkvjK+pxSbqlW5YRj5pX0iuHC YhYrBJ0D0wqJ+wyDqfWrR98Pbk+pg/z8FIp5/hA8KllkV/SRTI7X63l5QQo4pNqynqO/ lrIg== ARC-Message-Signature: i=1; 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Miller" , Ivan Khoronzhuk CC: Florian Fainelli , Andrew Lunn , Sekhar Nori , , , Murali Karicheri , Grygorii Strashko Subject: [PATCH net-next 12/19] net: ethernet: ti: ale: do not auto delete mcast super entries Date: Tue, 23 Apr 2019 16:09:03 +0300 Message-ID: <1556024950-20752-13-git-send-email-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1556024950-20752-1-git-send-email-grygorii.strashko@ti.com> References: <1556024950-20752-1-git-send-email-grygorii.strashko@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Do not delete multicast supervisory packet's (SUPER) entries while flushing multicast addresses from ALE table cpsw_ale_flush_multicast(). Those entries have to be added/removed only explicitly. Signed-off-by: Grygorii Strashko --- drivers/net/ethernet/ti/cpsw_ale.c | 3 +++ 1 file changed, 3 insertions(+) -- 2.17.1 diff --git a/drivers/net/ethernet/ti/cpsw_ale.c b/drivers/net/ethernet/ti/cpsw_ale.c index f7369982ae33..d09768368dbd 100644 --- a/drivers/net/ethernet/ti/cpsw_ale.c +++ b/drivers/net/ethernet/ti/cpsw_ale.c @@ -280,6 +280,9 @@ int cpsw_ale_flush_multicast(struct cpsw_ale *ale, int port_mask, int vid) if (cpsw_ale_get_mcast(ale_entry)) { u8 addr[6]; + if (cpsw_ale_get_super(ale_entry)) + continue; + cpsw_ale_get_addr(ale_entry, addr); if (!is_broadcast_ether_addr(addr)) cpsw_ale_flush_mcast(ale, ale_entry, port_mask); From patchwork Tue Apr 23 13:09:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grygorii Strashko X-Patchwork-Id: 162687 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp3771180jan; Tue, 23 Apr 2019 06:10:38 -0700 (PDT) X-Google-Smtp-Source: APXvYqza3oAvC4+CtupjBCN04WkJ8o9wvWWwHb1I67ZYhoxeBMuii8tgsVTnhe4bzfKz+BZwXXtg X-Received: by 2002:a65:64c8:: with SMTP id t8mr7808937pgv.248.1556025038200; Tue, 23 Apr 2019 06:10:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556025038; cv=none; d=google.com; s=arc-20160816; b=RyT17HHygPuuxqi4xSkT2JE4GxgNT5SVzcOJNBsW0fZT9dylDqarEtuSyO5/bm+3hn HcpK2OoZv75dJJJMOFo4X0LIK9nvEGMCSbQJA2AGhH3VAldBW8zKk1Gdo95tj/Ieigsz SyYHZRKe6LQ4F2Mt19AVnqAAOlo6M4cYdjakcHVr0SYs1tTtONpXRB122IUXB/DOYBfz NMHv6ipCdTPDq2PYWG2oiE0i7iAgSfBdmPDw36pYMDciFnb5cWjVsPgaPXae1vj1jXqM Ec4jK2JDC7uWWckJAa+pn7Dwb7PU50EK2O3TJYqmwYT65lzOSmAp4JLkRFFAiZ9Ad0de sV8w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=VfH5noIGkBBuwxnZEcIzR4ny7Yk/uNiCh8CmTrOF5q0=; b=USjj4IN4ol0K3F1g3SKexnW+1651w8vsoqHRwzmagL8euV3hWlEWTAK0o7Nr08A9aZ xQ+cbOc8EnES32zZleEO4F9su9G1SW+yuF958OL1QQ+qBsK0U9LeKTBE/rxE7tRtaeWv D/FPDyg9LiJMR6uPBKuE0RLogfptcN7HUlMvC4UrdHfdQ+PPpVJf3wKy/WiNzlkgkvB6 rhEGvGEgrq+z+uy7ycyP8RulVauHH6by4QilYk0Pa894VB17Hkr8Tt0Ospzv6QUX9lUQ iBDsa6XFfkbufRIFBGeDRc/lXIH82vBtq1Vb7s6mN9Kg6XMjnEP6YuA2/g2OVlCOde5U m3lA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=NJ8ION3X; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Miller" , Ivan Khoronzhuk CC: Florian Fainelli , Andrew Lunn , Sekhar Nori , , , Murali Karicheri , Grygorii Strashko Subject: [PATCH net-next 14/19] net: ethernet: ti: cpsw: refactor probe to group common hw initialization Date: Tue, 23 Apr 2019 16:09:05 +0300 Message-ID: <1556024950-20752-15-git-send-email-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1556024950-20752-1-git-send-email-grygorii.strashko@ti.com> References: <1556024950-20752-1-git-send-email-grygorii.strashko@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Rework probe to group common hw initialization: - group resources request at the beginning of the probe - move net device initialization and registration at the end of the probe - drop cpsw_slave_init as preparation of refactoring of common hw initialization code to separate function. Signed-off-by: Grygorii Strashko --- drivers/net/ethernet/ti/cpsw.c | 213 +++++++++++++++------------------ 1 file changed, 97 insertions(+), 116 deletions(-) -- 2.17.1 diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c index c497992f01f7..ddc11f940d66 100644 --- a/drivers/net/ethernet/ti/cpsw.c +++ b/drivers/net/ethernet/ti/cpsw.c @@ -3181,19 +3181,6 @@ static const struct ethtool_ops cpsw_ethtool_ops = { .set_ringparam = cpsw_set_ringparam, }; -static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_common *cpsw, - u32 slave_reg_ofs, u32 sliver_reg_ofs) -{ - void __iomem *regs = cpsw->regs; - int slave_num = slave->slave_num; - struct cpsw_slave_data *data = cpsw->data.slave_data + slave_num; - - slave->data = data; - slave->regs = regs + slave_reg_ofs; - slave->sliver = regs + sliver_reg_ofs; - slave->port_vlan = data->dual_emac_res_vlan; -} - static int cpsw_probe_dt(struct cpsw_platform_data *data, struct platform_device *pdev) { @@ -3476,21 +3463,6 @@ static int cpsw_probe(struct platform_device *pdev) cpsw->dev = dev; - ndev = devm_alloc_etherdev_mqs(dev, sizeof(struct cpsw_priv), - CPSW_MAX_QUEUES, CPSW_MAX_QUEUES); - if (!ndev) { - dev_err(dev, "error allocating net_device\n"); - return -ENOMEM; - } - - platform_set_drvdata(pdev, ndev); - priv = netdev_priv(ndev); - priv->cpsw = cpsw; - priv->ndev = ndev; - priv->dev = dev; - priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG); - cpsw->rx_packet_max = max(rx_packet_max, 128); - mode = devm_gpiod_get_array_optional(dev, "mode", GPIOD_OUT_LOW); if (IS_ERR(mode)) { ret = PTR_ERR(mode); @@ -3498,6 +3470,37 @@ static int cpsw_probe(struct platform_device *pdev) return ret; } + clk = devm_clk_get(dev, "fck"); + if (IS_ERR(clk)) { + ret = PTR_ERR(mode); + dev_err(dev, "fck is not found %d\n", ret); + return ret; + } + cpsw->bus_freq_mhz = clk_get_rate(clk) / 1000000; + + ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + ss_regs = devm_ioremap_resource(dev, ss_res); + if (IS_ERR(ss_regs)) + return PTR_ERR(ss_regs); + cpsw->regs = ss_regs; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + cpsw->wr_regs = devm_ioremap_resource(dev, res); + if (IS_ERR(cpsw->wr_regs)) + return PTR_ERR(cpsw->wr_regs); + + /* RX IRQ */ + irq = platform_get_irq(pdev, 1); + if (irq < 0) + return irq; + cpsw->irqs_table[0] = irq; + + /* TX IRQ */ + irq = platform_get_irq(pdev, 2); + if (irq < 0) + return irq; + cpsw->irqs_table[1] = irq; + /* * This may be required here for child devices. */ @@ -3516,20 +3519,11 @@ static int cpsw_probe(struct platform_device *pdev) if (ret) goto clean_dt_ret; - data = &cpsw->data; - cpsw->rx_ch_num = 1; - cpsw->tx_ch_num = 1; - - if (is_valid_ether_addr(data->slave_data[0].mac_addr)) { - memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN); - dev_info(dev, "Detected MACID = %pM\n", priv->mac_addr); - } else { - eth_random_addr(priv->mac_addr); - dev_info(dev, "Random MACID = %pM\n", priv->mac_addr); - } - - memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN); + soc = soc_device_match(cpsw_soc_devices); + if (soc) + cpsw->quirk_irq = 1; + data = &cpsw->data; cpsw->slaves = devm_kcalloc(dev, data->slaves, sizeof(struct cpsw_slave), GFP_KERNEL); @@ -3537,37 +3531,14 @@ static int cpsw_probe(struct platform_device *pdev) ret = -ENOMEM; goto clean_dt_ret; } - for (i = 0; i < data->slaves; i++) - cpsw->slaves[i].slave_num = i; - cpsw->slaves[0].ndev = ndev; - priv->emac_port = 0; + cpsw->rx_packet_max = max(rx_packet_max, CPSW_MAX_PACKET_SIZE); - clk = devm_clk_get(dev, "fck"); - if (IS_ERR(clk)) { - dev_err(dev, "fck is not found\n"); - ret = -ENODEV; - goto clean_dt_ret; - } - cpsw->bus_freq_mhz = clk_get_rate(clk) / 1000000; - - ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - ss_regs = devm_ioremap_resource(dev, ss_res); - if (IS_ERR(ss_regs)) { - ret = PTR_ERR(ss_regs); - goto clean_dt_ret; - } - cpsw->regs = ss_regs; + cpsw->rx_ch_num = 1; + cpsw->tx_ch_num = 1; cpsw->version = readl(&cpsw->regs->id_ver); - res = platform_get_resource(pdev, IORESOURCE_MEM, 1); - cpsw->wr_regs = devm_ioremap_resource(dev, res); - if (IS_ERR(cpsw->wr_regs)) { - ret = PTR_ERR(cpsw->wr_regs); - goto clean_dt_ret; - } - memset(&dma_params, 0, sizeof(dma_params)); memset(&ale_params, 0, sizeof(ale_params)); @@ -3604,14 +3575,33 @@ static int cpsw_probe(struct platform_device *pdev) ret = -ENODEV; goto clean_dt_ret; } + for (i = 0; i < cpsw->data.slaves; i++) { struct cpsw_slave *slave = &cpsw->slaves[i]; + void __iomem *regs = cpsw->regs; + + slave->slave_num = i; + slave->data = &cpsw->data.slave_data[i]; + slave->regs = regs + slave_offset; + slave->sliver = regs + sliver_offset; + slave->port_vlan = slave->data->dual_emac_res_vlan; - cpsw_slave_init(slave, cpsw, slave_offset, sliver_offset); slave_offset += slave_size; sliver_offset += SLIVER_SIZE; } + ale_params.dev = dev; + ale_params.ale_ageout = ale_ageout; + ale_params.ale_entries = data->ale_entries; + ale_params.ale_ports = CPSW_ALE_PORTS_NUM; + + cpsw->ale = cpsw_ale_create(&ale_params); + if (!cpsw->ale) { + dev_err(dev, "error initializing ale engine\n"); + ret = -ENODEV; + goto clean_dt_ret; + } + dma_params.dev = dev; dma_params.rxthresh = dma_params.dmaregs + CPDMA_RXTHRESH; dma_params.rxfree = dma_params.dmaregs + CPDMA_RXFREE; @@ -3636,50 +3626,56 @@ static int cpsw_probe(struct platform_device *pdev) goto clean_dt_ret; } - soc = soc_device_match(cpsw_soc_devices); - if (soc) - cpsw->quirk_irq = 1; + cpsw->cpts = cpts_create(cpsw->dev, cpts_regs, cpsw->dev->of_node); + if (IS_ERR(cpsw->cpts)) { + ret = PTR_ERR(cpsw->cpts); + goto clean_dma_ret; + } ch = cpsw->quirk_irq ? 0 : 7; cpsw->txv[0].ch = cpdma_chan_create(cpsw->dma, ch, cpsw_tx_handler, 0); if (IS_ERR(cpsw->txv[0].ch)) { dev_err(dev, "error initializing tx dma channel\n"); ret = PTR_ERR(cpsw->txv[0].ch); - goto clean_dma_ret; + goto clean_cpts; } cpsw->rxv[0].ch = cpdma_chan_create(cpsw->dma, 0, cpsw_rx_handler, 1); if (IS_ERR(cpsw->rxv[0].ch)) { dev_err(dev, "error initializing rx dma channel\n"); ret = PTR_ERR(cpsw->rxv[0].ch); - goto clean_dma_ret; + goto clean_cpts; } + cpsw_split_res(cpsw); - ale_params.dev = dev; - ale_params.ale_ageout = ale_ageout; - ale_params.ale_entries = data->ale_entries; - ale_params.ale_ports = CPSW_ALE_PORTS_NUM; - - cpsw->ale = cpsw_ale_create(&ale_params); - if (!cpsw->ale) { - dev_err(dev, "error initializing ale engine\n"); - ret = -ENODEV; - goto clean_dma_ret; + /* setup netdev */ + ndev = devm_alloc_etherdev_mqs(dev, sizeof(struct cpsw_priv), + CPSW_MAX_QUEUES, CPSW_MAX_QUEUES); + if (!ndev) { + dev_err(dev, "error allocating net_device\n"); + goto clean_cpts; } - cpsw->cpts = cpts_create(cpsw->dev, cpts_regs, cpsw->dev->of_node); - if (IS_ERR(cpsw->cpts)) { - ret = PTR_ERR(cpsw->cpts); - goto clean_dma_ret; - } + platform_set_drvdata(pdev, ndev); + priv = netdev_priv(ndev); + priv->cpsw = cpsw; + priv->ndev = ndev; + priv->dev = dev; + priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG); + priv->emac_port = 0; - ndev->irq = platform_get_irq(pdev, 1); - if (ndev->irq < 0) { - dev_err(dev, "error getting irq resource\n"); - ret = ndev->irq; - goto clean_dma_ret; + if (is_valid_ether_addr(data->slave_data[0].mac_addr)) { + memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN); + dev_info(dev, "Detected MACID = %pM\n", priv->mac_addr); + } else { + eth_random_addr(priv->mac_addr); + dev_info(dev, "Random MACID = %pM\n", priv->mac_addr); } + memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN); + + cpsw->slaves[0].ndev = ndev; + ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_VLAN_CTAG_RX; ndev->netdev_ops = &cpsw_netdev_ops; @@ -3690,7 +3686,6 @@ static int cpsw_probe(struct platform_device *pdev) netif_tx_napi_add(ndev, &cpsw->napi_tx, cpsw->quirk_irq ? cpsw_tx_poll : cpsw_tx_mq_poll, CPSW_POLL_WEIGHT); - cpsw_split_res(cpsw); /* register the network device */ SET_NETDEV_DEV(ndev, dev); @@ -3698,7 +3693,7 @@ static int cpsw_probe(struct platform_device *pdev) if (ret) { dev_err(dev, "error registering net device\n"); ret = -ENODEV; - goto clean_dma_ret; + goto clean_cpts; } if (cpsw->data.dual_emac) { @@ -3716,40 +3711,24 @@ static int cpsw_probe(struct platform_device *pdev) * If anyone wants to implement support for those, make sure to * first request and append them to irqs_table array. */ - - /* RX IRQ */ - irq = platform_get_irq(pdev, 1); - if (irq < 0) { - ret = irq; - goto clean_dma_ret; - } - - cpsw->irqs_table[0] = irq; - ret = devm_request_irq(dev, irq, cpsw_rx_interrupt, + ret = devm_request_irq(dev, cpsw->irqs_table[0], cpsw_rx_interrupt, 0, dev_name(dev), cpsw); if (ret < 0) { dev_err(dev, "error attaching irq (%d)\n", ret); - goto clean_dma_ret; + goto clean_unregister_netdev_ret; } - /* TX IRQ */ - irq = platform_get_irq(pdev, 2); - if (irq < 0) { - ret = irq; - goto clean_dma_ret; - } - cpsw->irqs_table[1] = irq; - ret = devm_request_irq(dev, irq, cpsw_tx_interrupt, + ret = devm_request_irq(dev, cpsw->irqs_table[1], cpsw_tx_interrupt, 0, dev_name(&pdev->dev), cpsw); if (ret < 0) { dev_err(dev, "error attaching irq (%d)\n", ret); - goto clean_dma_ret; + goto clean_unregister_netdev_ret; } cpsw_notice(priv, probe, "initialized device (regs %pa, irq %d, pool size %d)\n", - &ss_res->start, ndev->irq, dma_params.descs_pool_size); + &ss_res->start, cpsw->irqs_table[0], descs_pool_size); pm_runtime_put(&pdev->dev); @@ -3757,6 +3736,8 @@ static int cpsw_probe(struct platform_device *pdev) clean_unregister_netdev_ret: unregister_netdev(ndev); +clean_cpts: + cpts_release(cpsw->cpts); clean_dma_ret: cpdma_ctlr_destroy(cpsw->dma); clean_dt_ret: From patchwork Tue Apr 23 13:09:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grygorii Strashko X-Patchwork-Id: 162685 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp3770751jan; Tue, 23 Apr 2019 06:10:16 -0700 (PDT) X-Google-Smtp-Source: APXvYqyouCLMJzFZ3GFtaC63ovo/9gtRrNfsUa05Fqmr2rL+zxC5Yn0I5VqbZoxNxJlJN5MveRQP X-Received: by 2002:a65:4342:: with SMTP id k2mr24764799pgq.178.1556025015947; Tue, 23 Apr 2019 06:10:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556025015; cv=none; d=google.com; s=arc-20160816; b=sqxC6P5lpXBYAdnt3fCeh3YQdpIr27b6/uDf/Vz0M9fDz4ReBkw8Yu2iMGQYnbaq58 +AcfVzp6Zt2HEYuPVWgWhUYE1rqr+VrN81Up4KDBL4iu2+tpL9bMJqSkbi62MxVOk6kI WUh3zBVNQWke9GNUH0UxkEyoYwiSeLTOl6hLgMglimGHQ9Mfi1ihi8kkstQUmpoUAVPv v9lKUVeoWCKxaYYDtfpc5jCKDAH3oUh8VMJz6JhEwzabkD9lXAIlbyE0OG8FjLy5ELd7 BWQeDw+d7RZIGS3Jwsk2JZn1bgLtFKFW2rmVc4wVAKYZn4wgaoWpjwlNoytwHCMK7FuO BVew== ARC-Message-Signature: i=1; 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Miller" , Ivan Khoronzhuk CC: Florian Fainelli , Andrew Lunn , Sekhar Nori , , , Murali Karicheri , Grygorii Strashko Subject: [PATCH net-next 15/19] net: ethernet: ti: cpsw: move cpsw definitions in priv header Date: Tue, 23 Apr 2019 16:09:06 +0300 Message-ID: <1556024950-20752-16-git-send-email-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1556024950-20752-1-git-send-email-grygorii.strashko@ti.com> References: <1556024950-20752-1-git-send-email-grygorii.strashko@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org As a preparatory patch to add a switchdev based cpsw driver move the common header definitions to cpsw_priv.h. The plan is to develop a new driver on switchdev driver model and obsolete the current cpsw driver after all required functions are added to the new driver. This patch allows the same header file to be re-used on both drivers during the transition period. Signed-off-by: Ilias Apalodimas Signed-off-by: Grygorii Strashko --- drivers/net/ethernet/ti/cpsw.c | 440 +-------------------------- drivers/net/ethernet/ti/cpsw_priv.h | 450 ++++++++++++++++++++++++++++ 2 files changed, 451 insertions(+), 439 deletions(-) create mode 100644 drivers/net/ethernet/ti/cpsw_priv.h -- 2.17.1 diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c index ddc11f940d66..7dffc67f0cf4 100644 --- a/drivers/net/ethernet/ti/cpsw.c +++ b/drivers/net/ethernet/ti/cpsw.c @@ -37,138 +37,12 @@ #include "cpsw.h" #include "cpsw_ale.h" +#include "cpsw_priv.h" #include "cpts.h" #include "davinci_cpdma.h" #include -#define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \ - NETIF_MSG_DRV | NETIF_MSG_LINK | \ - NETIF_MSG_IFUP | NETIF_MSG_INTR | \ - NETIF_MSG_PROBE | NETIF_MSG_TIMER | \ - NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \ - NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \ - NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \ - NETIF_MSG_RX_STATUS) - -#define cpsw_info(priv, type, format, ...) \ -do { \ - if (netif_msg_##type(priv) && net_ratelimit()) \ - dev_info(priv->dev, format, ## __VA_ARGS__); \ -} while (0) - -#define cpsw_err(priv, type, format, ...) \ -do { \ - if (netif_msg_##type(priv) && net_ratelimit()) \ - dev_err(priv->dev, format, ## __VA_ARGS__); \ -} while (0) - -#define cpsw_dbg(priv, type, format, ...) \ -do { \ - if (netif_msg_##type(priv) && net_ratelimit()) \ - dev_dbg(priv->dev, format, ## __VA_ARGS__); \ -} while (0) - -#define cpsw_notice(priv, type, format, ...) \ -do { \ - if (netif_msg_##type(priv) && net_ratelimit()) \ - dev_notice(priv->dev, format, ## __VA_ARGS__); \ -} while (0) - -#define ALE_ALL_PORTS 0x7 - -#define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7) -#define CPSW_MINOR_VERSION(reg) (reg & 0xff) -#define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f) - -#define CPSW_VERSION_1 0x19010a -#define CPSW_VERSION_2 0x19010c -#define CPSW_VERSION_3 0x19010f -#define CPSW_VERSION_4 0x190112 - -#define HOST_PORT_NUM 0 -#define CPSW_ALE_PORTS_NUM 3 -#define SLIVER_SIZE 0x40 - -#define CPSW1_HOST_PORT_OFFSET 0x028 -#define CPSW1_SLAVE_OFFSET 0x050 -#define CPSW1_SLAVE_SIZE 0x040 -#define CPSW1_CPDMA_OFFSET 0x100 -#define CPSW1_STATERAM_OFFSET 0x200 -#define CPSW1_HW_STATS 0x400 -#define CPSW1_CPTS_OFFSET 0x500 -#define CPSW1_ALE_OFFSET 0x600 -#define CPSW1_SLIVER_OFFSET 0x700 - -#define CPSW2_HOST_PORT_OFFSET 0x108 -#define CPSW2_SLAVE_OFFSET 0x200 -#define CPSW2_SLAVE_SIZE 0x100 -#define CPSW2_CPDMA_OFFSET 0x800 -#define CPSW2_HW_STATS 0x900 -#define CPSW2_STATERAM_OFFSET 0xa00 -#define CPSW2_CPTS_OFFSET 0xc00 -#define CPSW2_ALE_OFFSET 0xd00 -#define CPSW2_SLIVER_OFFSET 0xd80 -#define CPSW2_BD_OFFSET 0x2000 - -#define CPDMA_RXTHRESH 0x0c0 -#define CPDMA_RXFREE 0x0e0 -#define CPDMA_TXHDP 0x00 -#define CPDMA_RXHDP 0x20 -#define CPDMA_TXCP 0x40 -#define CPDMA_RXCP 0x60 - -#define CPSW_POLL_WEIGHT 64 -#define CPSW_RX_VLAN_ENCAP_HDR_SIZE 4 -#define CPSW_MIN_PACKET_SIZE (VLAN_ETH_ZLEN) -#define CPSW_MAX_PACKET_SIZE (VLAN_ETH_FRAME_LEN +\ - ETH_FCS_LEN +\ - CPSW_RX_VLAN_ENCAP_HDR_SIZE) - -#define RX_PRIORITY_MAPPING 0x76543210 -#define TX_PRIORITY_MAPPING 0x33221100 -#define CPDMA_TX_PRIORITY_MAP 0x76543210 - -#define CPSW_VLAN_AWARE BIT(1) -#define CPSW_RX_VLAN_ENCAP BIT(2) -#define CPSW_ALE_VLAN_AWARE 1 - -#define CPSW_FIFO_NORMAL_MODE (0 << 16) -#define CPSW_FIFO_DUAL_MAC_MODE (1 << 16) -#define CPSW_FIFO_RATE_LIMIT_MODE (2 << 16) - -#define CPSW_INTPACEEN (0x3f << 16) -#define CPSW_INTPRESCALE_MASK (0x7FF << 0) -#define CPSW_CMINTMAX_CNT 63 -#define CPSW_CMINTMIN_CNT 2 -#define CPSW_CMINTMAX_INTVL (1000 / CPSW_CMINTMIN_CNT) -#define CPSW_CMINTMIN_INTVL ((1000 / CPSW_CMINTMAX_CNT) + 1) - -#define cpsw_slave_index(cpsw, priv) \ - ((cpsw->data.dual_emac) ? priv->emac_port : \ - cpsw->data.active_slave) -#define IRQ_NUM 2 -#define CPSW_MAX_QUEUES 8 -#define CPSW_CPDMA_DESCS_POOL_SIZE_DEFAULT 256 -#define CPSW_FIFO_QUEUE_TYPE_SHIFT 16 -#define CPSW_FIFO_SHAPE_EN_SHIFT 16 -#define CPSW_FIFO_RATE_EN_SHIFT 20 -#define CPSW_TC_NUM 4 -#define CPSW_FIFO_SHAPERS_NUM (CPSW_TC_NUM - 1) -#define CPSW_PCT_MASK 0x7f - -#define CPSW_RX_VLAN_ENCAP_HDR_PRIO_SHIFT 29 -#define CPSW_RX_VLAN_ENCAP_HDR_PRIO_MSK GENMASK(2, 0) -#define CPSW_RX_VLAN_ENCAP_HDR_VID_SHIFT 16 -#define CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_SHIFT 8 -#define CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_MSK GENMASK(1, 0) -enum { - CPSW_RX_VLAN_ENCAP_HDR_PKT_VLAN_TAG = 0, - CPSW_RX_VLAN_ENCAP_HDR_PKT_RESERV, - CPSW_RX_VLAN_ENCAP_HDR_PKT_PRIO_TAG, - CPSW_RX_VLAN_ENCAP_HDR_PKT_UNTAG, -}; - static int debug_level; module_param(debug_level, int, 0); MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)"); @@ -185,288 +59,6 @@ static int descs_pool_size = CPSW_CPDMA_DESCS_POOL_SIZE_DEFAULT; module_param(descs_pool_size, int, 0444); MODULE_PARM_DESC(descs_pool_size, "Number of CPDMA CPPI descriptors in pool"); -struct cpsw_wr_regs { - u32 id_ver; - u32 soft_reset; - u32 control; - u32 int_control; - u32 rx_thresh_en; - u32 rx_en; - u32 tx_en; - u32 misc_en; - u32 mem_allign1[8]; - u32 rx_thresh_stat; - u32 rx_stat; - u32 tx_stat; - u32 misc_stat; - u32 mem_allign2[8]; - u32 rx_imax; - u32 tx_imax; - -}; - -struct cpsw_ss_regs { - u32 id_ver; - u32 control; - u32 soft_reset; - u32 stat_port_en; - u32 ptype; - u32 soft_idle; - u32 thru_rate; - u32 gap_thresh; - u32 tx_start_wds; - u32 flow_control; - u32 vlan_ltype; - u32 ts_ltype; - u32 dlr_ltype; -}; - -/* CPSW_PORT_V1 */ -#define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */ -#define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */ -#define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */ -#define CPSW1_PORT_VLAN 0x0c /* VLAN Register */ -#define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */ -#define CPSW1_TS_CTL 0x14 /* Time Sync Control */ -#define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */ -#define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */ - -/* CPSW_PORT_V2 */ -#define CPSW2_CONTROL 0x00 /* Control Register */ -#define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */ -#define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */ -#define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */ -#define CPSW2_PORT_VLAN 0x14 /* VLAN Register */ -#define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */ -#define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */ - -/* CPSW_PORT_V1 and V2 */ -#define SA_LO 0x20 /* CPGMAC_SL Source Address Low */ -#define SA_HI 0x24 /* CPGMAC_SL Source Address High */ -#define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */ - -/* CPSW_PORT_V2 only */ -#define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */ -#define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */ -#define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */ -#define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */ -#define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */ -#define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */ -#define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */ -#define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */ - -/* Bit definitions for the CPSW2_CONTROL register */ -#define PASS_PRI_TAGGED BIT(24) /* Pass Priority Tagged */ -#define VLAN_LTYPE2_EN BIT(21) /* VLAN LTYPE 2 enable */ -#define VLAN_LTYPE1_EN BIT(20) /* VLAN LTYPE 1 enable */ -#define DSCP_PRI_EN BIT(16) /* DSCP Priority Enable */ -#define TS_107 BIT(15) /* Tyme Sync Dest IP Address 107 */ -#define TS_320 BIT(14) /* Time Sync Dest Port 320 enable */ -#define TS_319 BIT(13) /* Time Sync Dest Port 319 enable */ -#define TS_132 BIT(12) /* Time Sync Dest IP Addr 132 enable */ -#define TS_131 BIT(11) /* Time Sync Dest IP Addr 131 enable */ -#define TS_130 BIT(10) /* Time Sync Dest IP Addr 130 enable */ -#define TS_129 BIT(9) /* Time Sync Dest IP Addr 129 enable */ -#define TS_TTL_NONZERO BIT(8) /* Time Sync Time To Live Non-zero enable */ -#define TS_ANNEX_F_EN BIT(6) /* Time Sync Annex F enable */ -#define TS_ANNEX_D_EN BIT(4) /* Time Sync Annex D enable */ -#define TS_LTYPE2_EN BIT(3) /* Time Sync LTYPE 2 enable */ -#define TS_LTYPE1_EN BIT(2) /* Time Sync LTYPE 1 enable */ -#define TS_TX_EN BIT(1) /* Time Sync Transmit Enable */ -#define TS_RX_EN BIT(0) /* Time Sync Receive Enable */ - -#define CTRL_V2_TS_BITS \ - (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\ - TS_TTL_NONZERO | TS_ANNEX_D_EN | TS_LTYPE1_EN | VLAN_LTYPE1_EN) - -#define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN) -#define CTRL_V2_TX_TS_BITS (CTRL_V2_TS_BITS | TS_TX_EN) -#define CTRL_V2_RX_TS_BITS (CTRL_V2_TS_BITS | TS_RX_EN) - - -#define CTRL_V3_TS_BITS \ - (TS_107 | TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\ - TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\ - TS_LTYPE1_EN | VLAN_LTYPE1_EN) - -#define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN) -#define CTRL_V3_TX_TS_BITS (CTRL_V3_TS_BITS | TS_TX_EN) -#define CTRL_V3_RX_TS_BITS (CTRL_V3_TS_BITS | TS_RX_EN) - -/* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */ -#define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */ -#define TS_SEQ_ID_OFFSET_MASK (0x3f) -#define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */ -#define TS_MSG_TYPE_EN_MASK (0xffff) - -/* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */ -#define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3)) - -/* Bit definitions for the CPSW1_TS_CTL register */ -#define CPSW_V1_TS_RX_EN BIT(0) -#define CPSW_V1_TS_TX_EN BIT(4) -#define CPSW_V1_MSG_TYPE_OFS 16 - -/* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */ -#define CPSW_V1_SEQ_ID_OFS_SHIFT 16 - -#define CPSW_MAX_BLKS_TX 15 -#define CPSW_MAX_BLKS_TX_SHIFT 4 -#define CPSW_MAX_BLKS_RX 5 - -struct cpsw_host_regs { - u32 max_blks; - u32 blk_cnt; - u32 tx_in_ctl; - u32 port_vlan; - u32 tx_pri_map; - u32 cpdma_tx_pri_map; - u32 cpdma_rx_chan_map; -}; - -struct cpsw_sliver_regs { - u32 id_ver; - u32 mac_control; - u32 mac_status; - u32 soft_reset; - u32 rx_maxlen; - u32 __reserved_0; - u32 rx_pause; - u32 tx_pause; - u32 __reserved_1; - u32 rx_pri_map; -}; - -struct cpsw_hw_stats { - u32 rxgoodframes; - u32 rxbroadcastframes; - u32 rxmulticastframes; - u32 rxpauseframes; - u32 rxcrcerrors; - u32 rxaligncodeerrors; - u32 rxoversizedframes; - u32 rxjabberframes; - u32 rxundersizedframes; - u32 rxfragments; - u32 __pad_0[2]; - u32 rxoctets; - u32 txgoodframes; - u32 txbroadcastframes; - u32 txmulticastframes; - u32 txpauseframes; - u32 txdeferredframes; - u32 txcollisionframes; - u32 txsinglecollframes; - u32 txmultcollframes; - u32 txexcessivecollisions; - u32 txlatecollisions; - u32 txunderrun; - u32 txcarriersenseerrors; - u32 txoctets; - u32 octetframes64; - u32 octetframes65t127; - u32 octetframes128t255; - u32 octetframes256t511; - u32 octetframes512t1023; - u32 octetframes1024tup; - u32 netoctets; - u32 rxsofoverruns; - u32 rxmofoverruns; - u32 rxdmaoverruns; -}; - -struct cpsw_slave_data { - struct device_node *phy_node; - char phy_id[MII_BUS_ID_SIZE]; - int phy_if; - u8 mac_addr[ETH_ALEN]; - u16 dual_emac_res_vlan; /* Reserved VLAN for DualEMAC */ - struct phy *ifphy; -}; - -struct cpsw_platform_data { - struct cpsw_slave_data *slave_data; - u32 ss_reg_ofs; /* Subsystem control register offset */ - u32 channels; /* number of cpdma channels (symmetric) */ - u32 slaves; /* number of slave cpgmac ports */ - u32 active_slave; /* time stamping, ethtool and SIOCGMIIPHY slave */ - u32 ale_entries; /* ale table size */ - u32 bd_ram_size; /*buffer descriptor ram size */ - u32 mac_control; /* Mac control register */ - u16 default_vlan; /* Def VLAN for ALE lookup in VLAN aware mode*/ - bool dual_emac; /* Enable Dual EMAC mode */ -}; - -struct cpsw_slave { - void __iomem *regs; - struct cpsw_sliver_regs __iomem *sliver; - int slave_num; - u32 mac_control; - struct cpsw_slave_data *data; - struct phy_device *phy; - struct net_device *ndev; - u32 port_vlan; -}; - -static inline u32 slave_read(struct cpsw_slave *slave, u32 offset) -{ - return readl_relaxed(slave->regs + offset); -} - -static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset) -{ - writel_relaxed(val, slave->regs + offset); -} - -struct cpsw_vector { - struct cpdma_chan *ch; - int budget; -}; - -struct cpsw_common { - struct device *dev; - struct cpsw_platform_data data; - struct napi_struct napi_rx; - struct napi_struct napi_tx; - struct cpsw_ss_regs __iomem *regs; - struct cpsw_wr_regs __iomem *wr_regs; - u8 __iomem *hw_stats; - struct cpsw_host_regs __iomem *host_port_regs; - u32 version; - u32 coal_intvl; - u32 bus_freq_mhz; - int rx_packet_max; - struct cpsw_slave *slaves; - struct cpdma_ctlr *dma; - struct cpsw_vector txv[CPSW_MAX_QUEUES]; - struct cpsw_vector rxv[CPSW_MAX_QUEUES]; - struct cpsw_ale *ale; - bool quirk_irq; - bool rx_irq_disabled; - bool tx_irq_disabled; - u32 irqs_table[IRQ_NUM]; - struct cpts *cpts; - int rx_ch_num, tx_ch_num; - int speed; - int usage_count; -}; - -struct cpsw_priv { - struct net_device *ndev; - struct device *dev; - u32 msg_enable; - u8 mac_addr[ETH_ALEN]; - bool rx_pause; - bool tx_pause; - bool mqprio_hw; - int fifo_bw[CPSW_TC_NUM]; - int shp_cfg_speed; - int tx_ts_enabled; - int rx_ts_enabled; - u32 emac_port; - struct cpsw_common *cpsw; -}; - struct cpsw_stats { char stat_string[ETH_GSTRING_LEN]; int type; @@ -543,33 +135,10 @@ static const struct cpsw_stats cpsw_gstrings_ch_stats[] = { { "teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) }, }; -#define CPSW_STATS_COMMON_LEN ARRAY_SIZE(cpsw_gstrings_stats) -#define CPSW_STATS_CH_LEN ARRAY_SIZE(cpsw_gstrings_ch_stats) - -#define ndev_to_cpsw(ndev) (((struct cpsw_priv *)netdev_priv(ndev))->cpsw) -#define napi_to_cpsw(napi) container_of(napi, struct cpsw_common, napi) -#define for_each_slave(priv, func, arg...) \ - do { \ - struct cpsw_slave *slave; \ - struct cpsw_common *cpsw = (priv)->cpsw; \ - int n; \ - if (cpsw->data.dual_emac) \ - (func)((cpsw)->slaves + priv->emac_port, ##arg);\ - else \ - for (n = cpsw->data.slaves, \ - slave = cpsw->slaves; \ - n; n--) \ - (func)(slave++, ##arg); \ - } while (0) static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev, __be16 proto, u16 vid); -static inline int cpsw_get_slave_port(u32 slave_num) -{ - return slave_num + 1; -} - static void cpsw_set_promiscious(struct net_device *ndev, bool enable) { struct cpsw_common *cpsw = ndev_to_cpsw(ndev); @@ -646,13 +215,6 @@ static void cpsw_set_promiscious(struct net_device *ndev, bool enable) } } -struct addr_sync_ctx { - struct net_device *ndev; - const u8 *addr; /* address to be synched */ - int consumed; /* number of address instances */ - int flush; /* flush flag */ -}; - /** * cpsw_set_mc - adds multicast entry to the table if it's not added or deletes * if it's not deleted diff --git a/drivers/net/ethernet/ti/cpsw_priv.h b/drivers/net/ethernet/ti/cpsw_priv.h new file mode 100644 index 000000000000..8df9ce68696a --- /dev/null +++ b/drivers/net/ethernet/ti/cpsw_priv.h @@ -0,0 +1,450 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Texas Instruments Ethernet Switch Driver + */ + +#ifndef DRIVERS_NET_ETHERNET_TI_CPSW_PRIV_H_ +#define DRIVERS_NET_ETHERNET_TI_CPSW_PRIV_H_ + +#define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \ + NETIF_MSG_DRV | NETIF_MSG_LINK | \ + NETIF_MSG_IFUP | NETIF_MSG_INTR | \ + NETIF_MSG_PROBE | NETIF_MSG_TIMER | \ + NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \ + NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \ + NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \ + NETIF_MSG_RX_STATUS) + +#define cpsw_info(priv, type, format, ...) \ +do { \ + if (netif_msg_##type(priv) && net_ratelimit()) \ + dev_info(priv->dev, format, ## __VA_ARGS__); \ +} while (0) + +#define cpsw_err(priv, type, format, ...) \ +do { \ + if (netif_msg_##type(priv) && net_ratelimit()) \ + dev_err(priv->dev, format, ## __VA_ARGS__); \ +} while (0) + +#define cpsw_dbg(priv, type, format, ...) \ +do { \ + if (netif_msg_##type(priv) && net_ratelimit()) \ + dev_dbg(priv->dev, format, ## __VA_ARGS__); \ +} while (0) + +#define cpsw_notice(priv, type, format, ...) \ +do { \ + if (netif_msg_##type(priv) && net_ratelimit()) \ + dev_notice(priv->dev, format, ## __VA_ARGS__); \ +} while (0) + +#define ALE_ALL_PORTS 0x7 + +#define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7) +#define CPSW_MINOR_VERSION(reg) (reg & 0xff) +#define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f) + +#define CPSW_VERSION_1 0x19010a +#define CPSW_VERSION_2 0x19010c +#define CPSW_VERSION_3 0x19010f +#define CPSW_VERSION_4 0x190112 + +#define HOST_PORT_NUM 0 +#define CPSW_ALE_PORTS_NUM 3 +#define SLIVER_SIZE 0x40 + +#define CPSW1_HOST_PORT_OFFSET 0x028 +#define CPSW1_SLAVE_OFFSET 0x050 +#define CPSW1_SLAVE_SIZE 0x040 +#define CPSW1_CPDMA_OFFSET 0x100 +#define CPSW1_STATERAM_OFFSET 0x200 +#define CPSW1_HW_STATS 0x400 +#define CPSW1_CPTS_OFFSET 0x500 +#define CPSW1_ALE_OFFSET 0x600 +#define CPSW1_SLIVER_OFFSET 0x700 + +#define CPSW2_HOST_PORT_OFFSET 0x108 +#define CPSW2_SLAVE_OFFSET 0x200 +#define CPSW2_SLAVE_SIZE 0x100 +#define CPSW2_CPDMA_OFFSET 0x800 +#define CPSW2_HW_STATS 0x900 +#define CPSW2_STATERAM_OFFSET 0xa00 +#define CPSW2_CPTS_OFFSET 0xc00 +#define CPSW2_ALE_OFFSET 0xd00 +#define CPSW2_SLIVER_OFFSET 0xd80 +#define CPSW2_BD_OFFSET 0x2000 + +#define CPDMA_RXTHRESH 0x0c0 +#define CPDMA_RXFREE 0x0e0 +#define CPDMA_TXHDP 0x00 +#define CPDMA_RXHDP 0x20 +#define CPDMA_TXCP 0x40 +#define CPDMA_RXCP 0x60 + +#define CPSW_POLL_WEIGHT 64 +#define CPSW_RX_VLAN_ENCAP_HDR_SIZE 4 +#define CPSW_MIN_PACKET_SIZE (VLAN_ETH_ZLEN) +#define CPSW_MAX_PACKET_SIZE (VLAN_ETH_FRAME_LEN +\ + ETH_FCS_LEN +\ + CPSW_RX_VLAN_ENCAP_HDR_SIZE) + +#define RX_PRIORITY_MAPPING 0x76543210 +#define TX_PRIORITY_MAPPING 0x33221100 +#define CPDMA_TX_PRIORITY_MAP 0x76543210 + +#define CPSW_VLAN_AWARE BIT(1) +#define CPSW_RX_VLAN_ENCAP BIT(2) +#define CPSW_ALE_VLAN_AWARE 1 + +#define CPSW_FIFO_NORMAL_MODE (0 << 16) +#define CPSW_FIFO_DUAL_MAC_MODE (1 << 16) +#define CPSW_FIFO_RATE_LIMIT_MODE (2 << 16) + +#define CPSW_INTPACEEN (0x3f << 16) +#define CPSW_INTPRESCALE_MASK (0x7FF << 0) +#define CPSW_CMINTMAX_CNT 63 +#define CPSW_CMINTMIN_CNT 2 +#define CPSW_CMINTMAX_INTVL (1000 / CPSW_CMINTMIN_CNT) +#define CPSW_CMINTMIN_INTVL ((1000 / CPSW_CMINTMAX_CNT) + 1) + +#define IRQ_NUM 2 +#define CPSW_MAX_QUEUES 8 +#define CPSW_CPDMA_DESCS_POOL_SIZE_DEFAULT 256 +#define CPSW_FIFO_QUEUE_TYPE_SHIFT 16 +#define CPSW_FIFO_SHAPE_EN_SHIFT 16 +#define CPSW_FIFO_RATE_EN_SHIFT 20 +#define CPSW_TC_NUM 4 +#define CPSW_FIFO_SHAPERS_NUM (CPSW_TC_NUM - 1) +#define CPSW_PCT_MASK 0x7f + +#define CPSW_RX_VLAN_ENCAP_HDR_PRIO_SHIFT 29 +#define CPSW_RX_VLAN_ENCAP_HDR_PRIO_MSK GENMASK(2, 0) +#define CPSW_RX_VLAN_ENCAP_HDR_VID_SHIFT 16 +#define CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_SHIFT 8 +#define CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_MSK GENMASK(1, 0) +enum { + CPSW_RX_VLAN_ENCAP_HDR_PKT_VLAN_TAG = 0, + CPSW_RX_VLAN_ENCAP_HDR_PKT_RESERV, + CPSW_RX_VLAN_ENCAP_HDR_PKT_PRIO_TAG, + CPSW_RX_VLAN_ENCAP_HDR_PKT_UNTAG, +}; + +struct cpsw_wr_regs { + u32 id_ver; + u32 soft_reset; + u32 control; + u32 int_control; + u32 rx_thresh_en; + u32 rx_en; + u32 tx_en; + u32 misc_en; + u32 mem_allign1[8]; + u32 rx_thresh_stat; + u32 rx_stat; + u32 tx_stat; + u32 misc_stat; + u32 mem_allign2[8]; + u32 rx_imax; + u32 tx_imax; + +}; + +struct cpsw_ss_regs { + u32 id_ver; + u32 control; + u32 soft_reset; + u32 stat_port_en; + u32 ptype; + u32 soft_idle; + u32 thru_rate; + u32 gap_thresh; + u32 tx_start_wds; + u32 flow_control; + u32 vlan_ltype; + u32 ts_ltype; + u32 dlr_ltype; +}; + +/* CPSW_PORT_V1 */ +#define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */ +#define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */ +#define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */ +#define CPSW1_PORT_VLAN 0x0c /* VLAN Register */ +#define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */ +#define CPSW1_TS_CTL 0x14 /* Time Sync Control */ +#define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */ +#define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */ + +/* CPSW_PORT_V2 */ +#define CPSW2_CONTROL 0x00 /* Control Register */ +#define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */ +#define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */ +#define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */ +#define CPSW2_PORT_VLAN 0x14 /* VLAN Register */ +#define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */ +#define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */ + +/* CPSW_PORT_V1 and V2 */ +#define SA_LO 0x20 /* CPGMAC_SL Source Address Low */ +#define SA_HI 0x24 /* CPGMAC_SL Source Address High */ +#define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */ + +/* CPSW_PORT_V2 only */ +#define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */ +#define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */ +#define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */ +#define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */ +#define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */ +#define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */ +#define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */ +#define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */ + +/* Bit definitions for the CPSW2_CONTROL register */ +#define PASS_PRI_TAGGED BIT(24) /* Pass Priority Tagged */ +#define VLAN_LTYPE2_EN BIT(21) /* VLAN LTYPE 2 enable */ +#define VLAN_LTYPE1_EN BIT(20) /* VLAN LTYPE 1 enable */ +#define DSCP_PRI_EN BIT(16) /* DSCP Priority Enable */ +#define TS_107 BIT(15) /* Tyme Sync Dest IP Address 107 */ +#define TS_320 BIT(14) /* Time Sync Dest Port 320 enable */ +#define TS_319 BIT(13) /* Time Sync Dest Port 319 enable */ +#define TS_132 BIT(12) /* Time Sync Dest IP Addr 132 enable */ +#define TS_131 BIT(11) /* Time Sync Dest IP Addr 131 enable */ +#define TS_130 BIT(10) /* Time Sync Dest IP Addr 130 enable */ +#define TS_129 BIT(9) /* Time Sync Dest IP Addr 129 enable */ +#define TS_TTL_NONZERO BIT(8) /* Time Sync Time To Live Non-zero enable */ +#define TS_ANNEX_F_EN BIT(6) /* Time Sync Annex F enable */ +#define TS_ANNEX_D_EN BIT(4) /* Time Sync Annex D enable */ +#define TS_LTYPE2_EN BIT(3) /* Time Sync LTYPE 2 enable */ +#define TS_LTYPE1_EN BIT(2) /* Time Sync LTYPE 1 enable */ +#define TS_TX_EN BIT(1) /* Time Sync Transmit Enable */ +#define TS_RX_EN BIT(0) /* Time Sync Receive Enable */ + +#define CTRL_V2_TS_BITS \ + (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\ + TS_TTL_NONZERO | TS_ANNEX_D_EN | TS_LTYPE1_EN | VLAN_LTYPE1_EN) + +#define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN) +#define CTRL_V2_TX_TS_BITS (CTRL_V2_TS_BITS | TS_TX_EN) +#define CTRL_V2_RX_TS_BITS (CTRL_V2_TS_BITS | TS_RX_EN) + + +#define CTRL_V3_TS_BITS \ + (TS_107 | TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\ + TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\ + TS_LTYPE1_EN | VLAN_LTYPE1_EN) + +#define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN) +#define CTRL_V3_TX_TS_BITS (CTRL_V3_TS_BITS | TS_TX_EN) +#define CTRL_V3_RX_TS_BITS (CTRL_V3_TS_BITS | TS_RX_EN) + +/* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */ +#define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */ +#define TS_SEQ_ID_OFFSET_MASK (0x3f) +#define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */ +#define TS_MSG_TYPE_EN_MASK (0xffff) + +/* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */ +#define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3)) + +/* Bit definitions for the CPSW1_TS_CTL register */ +#define CPSW_V1_TS_RX_EN BIT(0) +#define CPSW_V1_TS_TX_EN BIT(4) +#define CPSW_V1_MSG_TYPE_OFS 16 + +/* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */ +#define CPSW_V1_SEQ_ID_OFS_SHIFT 16 + +#define CPSW_MAX_BLKS_TX 15 +#define CPSW_MAX_BLKS_TX_SHIFT 4 +#define CPSW_MAX_BLKS_RX 5 + +struct cpsw_host_regs { + u32 max_blks; + u32 blk_cnt; + u32 tx_in_ctl; + u32 port_vlan; + u32 tx_pri_map; + u32 cpdma_tx_pri_map; + u32 cpdma_rx_chan_map; +}; + +struct cpsw_sliver_regs { + u32 id_ver; + u32 mac_control; + u32 mac_status; + u32 soft_reset; + u32 rx_maxlen; + u32 __reserved_0; + u32 rx_pause; + u32 tx_pause; + u32 __reserved_1; + u32 rx_pri_map; +}; + +struct cpsw_hw_stats { + u32 rxgoodframes; + u32 rxbroadcastframes; + u32 rxmulticastframes; + u32 rxpauseframes; + u32 rxcrcerrors; + u32 rxaligncodeerrors; + u32 rxoversizedframes; + u32 rxjabberframes; + u32 rxundersizedframes; + u32 rxfragments; + u32 __pad_0[2]; + u32 rxoctets; + u32 txgoodframes; + u32 txbroadcastframes; + u32 txmulticastframes; + u32 txpauseframes; + u32 txdeferredframes; + u32 txcollisionframes; + u32 txsinglecollframes; + u32 txmultcollframes; + u32 txexcessivecollisions; + u32 txlatecollisions; + u32 txunderrun; + u32 txcarriersenseerrors; + u32 txoctets; + u32 octetframes64; + u32 octetframes65t127; + u32 octetframes128t255; + u32 octetframes256t511; + u32 octetframes512t1023; + u32 octetframes1024tup; + u32 netoctets; + u32 rxsofoverruns; + u32 rxmofoverruns; + u32 rxdmaoverruns; +}; + +struct cpsw_slave_data { + struct device_node *phy_node; + char phy_id[MII_BUS_ID_SIZE]; + int phy_if; + u8 mac_addr[ETH_ALEN]; + u16 dual_emac_res_vlan; /* Reserved VLAN for DualEMAC */ + struct phy *ifphy; +}; + +struct cpsw_platform_data { + struct cpsw_slave_data *slave_data; + u32 ss_reg_ofs; /* Subsystem control register offset */ + u32 channels; /* number of cpdma channels (symmetric) */ + u32 slaves; /* number of slave cpgmac ports */ + u32 active_slave; /* time stamping, ethtool and SIOCGMIIPHY slave */ + u32 ale_entries; /* ale table size */ + u32 bd_ram_size; /*buffer descriptor ram size */ + u32 mac_control; /* Mac control register */ + u16 default_vlan; /* Def VLAN for ALE lookup in VLAN aware mode*/ + bool dual_emac; /* Enable Dual EMAC mode */ +}; + +struct cpsw_slave { + void __iomem *regs; + struct cpsw_sliver_regs __iomem *sliver; + int slave_num; + u32 mac_control; + struct cpsw_slave_data *data; + struct phy_device *phy; + struct net_device *ndev; + u32 port_vlan; +}; + +static inline u32 slave_read(struct cpsw_slave *slave, u32 offset) +{ + return readl_relaxed(slave->regs + offset); +} + +static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset) +{ + writel_relaxed(val, slave->regs + offset); +} + +struct cpsw_vector { + struct cpdma_chan *ch; + int budget; +}; + +struct cpsw_common { + struct device *dev; + struct cpsw_platform_data data; + struct napi_struct napi_rx; + struct napi_struct napi_tx; + struct cpsw_ss_regs __iomem *regs; + struct cpsw_wr_regs __iomem *wr_regs; + u8 __iomem *hw_stats; + struct cpsw_host_regs __iomem *host_port_regs; + u32 version; + u32 coal_intvl; + u32 bus_freq_mhz; + int rx_packet_max; + struct cpsw_slave *slaves; + struct cpdma_ctlr *dma; + struct cpsw_vector txv[CPSW_MAX_QUEUES]; + struct cpsw_vector rxv[CPSW_MAX_QUEUES]; + struct cpsw_ale *ale; + bool quirk_irq; + bool rx_irq_disabled; + bool tx_irq_disabled; + u32 irqs_table[IRQ_NUM]; + struct cpts *cpts; + int rx_ch_num, tx_ch_num; + int speed; + int usage_count; +}; + +struct cpsw_priv { + struct net_device *ndev; + struct device *dev; + u32 msg_enable; + u8 mac_addr[ETH_ALEN]; + bool rx_pause; + bool tx_pause; + bool mqprio_hw; + int fifo_bw[CPSW_TC_NUM]; + int shp_cfg_speed; + int tx_ts_enabled; + int rx_ts_enabled; + u32 emac_port; + struct cpsw_common *cpsw; +}; + +#define CPSW_STATS_COMMON_LEN ARRAY_SIZE(cpsw_gstrings_stats) +#define CPSW_STATS_CH_LEN ARRAY_SIZE(cpsw_gstrings_ch_stats) + +#define ndev_to_cpsw(ndev) (((struct cpsw_priv *)netdev_priv(ndev))->cpsw) +#define napi_to_cpsw(napi) container_of(napi, struct cpsw_common, napi) +#define for_each_slave(priv, func, arg...) \ + do { \ + struct cpsw_slave *slave; \ + struct cpsw_common *cpsw = (priv)->cpsw; \ + int n; \ + if (cpsw->data.dual_emac) \ + (func)((cpsw)->slaves + priv->emac_port, ##arg);\ + else \ + for (n = cpsw->data.slaves, \ + slave = cpsw->slaves; \ + n; n--) \ + (func)(slave++, ##arg); \ + } while (0) + +#define cpsw_slave_index(cpsw, priv) \ + ((cpsw->data.dual_emac) ? priv->emac_port : \ + cpsw->data.active_slave) + +static inline int cpsw_get_slave_port(u32 slave_num) +{ + return slave_num + 1; +} + +struct addr_sync_ctx { + struct net_device *ndev; + const u8 *addr; /* address to be synched */ + int consumed; /* number of address instances */ + int flush; /* flush flag */ +}; + +#endif /* DRIVERS_NET_ETHERNET_TI_CPSW_PRIV_H_ */ From patchwork Tue Apr 23 13:09:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit 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Miller" , Ivan Khoronzhuk CC: Florian Fainelli , Andrew Lunn , Sekhar Nori , , , Murali Karicheri , Grygorii Strashko Subject: [PATCH net-next 16/19] net: ethernet: ti: cpsw: move common hw init code in separate func Date: Tue, 23 Apr 2019 16:09:07 +0300 Message-ID: <1556024950-20752-17-git-send-email-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1556024950-20752-1-git-send-email-grygorii.strashko@ti.com> References: <1556024950-20752-1-git-send-email-grygorii.strashko@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org move common hw init code in separate function as preparation for adding new switchdev driver. Signed-off-by: Grygorii Strashko --- drivers/net/ethernet/ti/Makefile | 2 +- drivers/net/ethernet/ti/cpsw.c | 106 ++--------------------- drivers/net/ethernet/ti/cpsw_priv.c | 128 ++++++++++++++++++++++++++++ drivers/net/ethernet/ti/cpsw_priv.h | 3 + 4 files changed, 137 insertions(+), 102 deletions(-) create mode 100644 drivers/net/ethernet/ti/cpsw_priv.c -- 2.17.1 diff --git a/drivers/net/ethernet/ti/Makefile b/drivers/net/ethernet/ti/Makefile index 2f159a71f88e..de1561596646 100644 --- a/drivers/net/ethernet/ti/Makefile +++ b/drivers/net/ethernet/ti/Makefile @@ -14,7 +14,7 @@ obj-$(CONFIG_TI_DAVINCI_MDIO) += davinci_mdio.o obj-$(CONFIG_TI_CPSW_PHY_SEL) += cpsw-phy-sel.o obj-$(CONFIG_TI_CPTS_MOD) += cpts.o obj-$(CONFIG_TI_CPSW) += ti_cpsw.o -ti_cpsw-y := cpsw.o davinci_cpdma.o cpsw_ale.o +ti_cpsw-y := cpsw.o davinci_cpdma.o cpsw_ale.o cpsw_priv.o obj-$(CONFIG_TI_KEYSTONE_NETCP) += keystone_netcp.o keystone_netcp-y := netcp_core.o cpsw_ale.o diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c index 7dffc67f0cf4..a6c3d8be1649 100644 --- a/drivers/net/ethernet/ti/cpsw.c +++ b/drivers/net/ethernet/ti/cpsw.c @@ -3007,16 +3007,12 @@ static int cpsw_probe(struct platform_device *pdev) struct cpsw_platform_data *data; struct net_device *ndev; struct cpsw_priv *priv; - struct cpdma_params dma_params; - struct cpsw_ale_params ale_params; void __iomem *ss_regs; - void __iomem *cpts_regs; struct resource *res, *ss_res; struct gpio_descs *mode; - u32 slave_offset, sliver_offset, slave_size; const struct soc_device_attribute *soc; struct cpsw_common *cpsw; - int ret = 0, i, ch; + int ret = 0, ch; int irq; cpsw = devm_kzalloc(dev, sizeof(struct cpsw_common), GFP_KERNEL); @@ -3096,103 +3092,12 @@ static int cpsw_probe(struct platform_device *pdev) cpsw->rx_packet_max = max(rx_packet_max, CPSW_MAX_PACKET_SIZE); - cpsw->rx_ch_num = 1; - cpsw->tx_ch_num = 1; - cpsw->version = readl(&cpsw->regs->id_ver); - - memset(&dma_params, 0, sizeof(dma_params)); - memset(&ale_params, 0, sizeof(ale_params)); - - switch (cpsw->version) { - case CPSW_VERSION_1: - cpsw->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET; - cpts_regs = ss_regs + CPSW1_CPTS_OFFSET; - cpsw->hw_stats = ss_regs + CPSW1_HW_STATS; - dma_params.dmaregs = ss_regs + CPSW1_CPDMA_OFFSET; - dma_params.txhdp = ss_regs + CPSW1_STATERAM_OFFSET; - ale_params.ale_regs = ss_regs + CPSW1_ALE_OFFSET; - slave_offset = CPSW1_SLAVE_OFFSET; - slave_size = CPSW1_SLAVE_SIZE; - sliver_offset = CPSW1_SLIVER_OFFSET; - dma_params.desc_mem_phys = 0; - break; - case CPSW_VERSION_2: - case CPSW_VERSION_3: - case CPSW_VERSION_4: - cpsw->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET; - cpts_regs = ss_regs + CPSW2_CPTS_OFFSET; - cpsw->hw_stats = ss_regs + CPSW2_HW_STATS; - dma_params.dmaregs = ss_regs + CPSW2_CPDMA_OFFSET; - dma_params.txhdp = ss_regs + CPSW2_STATERAM_OFFSET; - ale_params.ale_regs = ss_regs + CPSW2_ALE_OFFSET; - slave_offset = CPSW2_SLAVE_OFFSET; - slave_size = CPSW2_SLAVE_SIZE; - sliver_offset = CPSW2_SLIVER_OFFSET; - dma_params.desc_mem_phys = - (u32 __force) ss_res->start + CPSW2_BD_OFFSET; - break; - default: - dev_err(dev, "unknown version 0x%08x\n", cpsw->version); - ret = -ENODEV; - goto clean_dt_ret; - } - - for (i = 0; i < cpsw->data.slaves; i++) { - struct cpsw_slave *slave = &cpsw->slaves[i]; - void __iomem *regs = cpsw->regs; - - slave->slave_num = i; - slave->data = &cpsw->data.slave_data[i]; - slave->regs = regs + slave_offset; - slave->sliver = regs + sliver_offset; - slave->port_vlan = slave->data->dual_emac_res_vlan; - - slave_offset += slave_size; - sliver_offset += SLIVER_SIZE; - } - - ale_params.dev = dev; - ale_params.ale_ageout = ale_ageout; - ale_params.ale_entries = data->ale_entries; - ale_params.ale_ports = CPSW_ALE_PORTS_NUM; - - cpsw->ale = cpsw_ale_create(&ale_params); - if (!cpsw->ale) { - dev_err(dev, "error initializing ale engine\n"); - ret = -ENODEV; - goto clean_dt_ret; - } - - dma_params.dev = dev; - dma_params.rxthresh = dma_params.dmaregs + CPDMA_RXTHRESH; - dma_params.rxfree = dma_params.dmaregs + CPDMA_RXFREE; - dma_params.rxhdp = dma_params.txhdp + CPDMA_RXHDP; - dma_params.txcp = dma_params.txhdp + CPDMA_TXCP; - dma_params.rxcp = dma_params.txhdp + CPDMA_RXCP; - - dma_params.num_chan = data->channels; - dma_params.has_soft_reset = true; - dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE; - dma_params.desc_mem_size = data->bd_ram_size; - dma_params.desc_align = 16; - dma_params.has_ext_regs = true; - dma_params.desc_hw_addr = dma_params.desc_mem_phys; - dma_params.bus_freq_mhz = cpsw->bus_freq_mhz; - dma_params.descs_pool_size = descs_pool_size; - - cpsw->dma = cpdma_ctlr_create(&dma_params); - if (!cpsw->dma) { - dev_err(dev, "error initializing dma\n"); - ret = -ENOMEM; + ret = cpsw_init_common(cpsw, ss_regs, ale_ageout, + (u32 __force)ss_res->start + CPSW2_BD_OFFSET, + descs_pool_size); + if (ret) goto clean_dt_ret; - } - - cpsw->cpts = cpts_create(cpsw->dev, cpts_regs, cpsw->dev->of_node); - if (IS_ERR(cpsw->cpts)) { - ret = PTR_ERR(cpsw->cpts); - goto clean_dma_ret; - } ch = cpsw->quirk_irq ? 0 : 7; cpsw->txv[0].ch = cpdma_chan_create(cpsw->dma, ch, cpsw_tx_handler, 0); @@ -3300,7 +3205,6 @@ static int cpsw_probe(struct platform_device *pdev) unregister_netdev(ndev); clean_cpts: cpts_release(cpsw->cpts); -clean_dma_ret: cpdma_ctlr_destroy(cpsw->dma); clean_dt_ret: cpsw_remove_dt(pdev); diff --git a/drivers/net/ethernet/ti/cpsw_priv.c b/drivers/net/ethernet/ti/cpsw_priv.c new file mode 100644 index 000000000000..208c544d0b80 --- /dev/null +++ b/drivers/net/ethernet/ti/cpsw_priv.c @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Texas Instruments Ethernet Switch Driver + * + * Copyright (C) 2019 Texas Instruments + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "cpts.h" +#include "cpsw_ale.h" +#include "cpsw_priv.h" +#include "davinci_cpdma.h" + +int cpsw_init_common(struct cpsw_common *cpsw, void __iomem *ss_regs, + int ale_ageout, u32 desc_mem_phys, int descs_pool_size) +{ + u32 slave_offset, sliver_offset, slave_size; + struct cpsw_ale_params ale_params; + struct cpsw_platform_data *data; + struct cpdma_params dma_params; + struct device *dev = cpsw->dev; + void __iomem *cpts_regs; + int ret = 0, i; + + data = &cpsw->data; + cpsw->rx_ch_num = 1; + cpsw->tx_ch_num = 1; + + cpsw->version = readl(&cpsw->regs->id_ver); + + memset(&dma_params, 0, sizeof(dma_params)); + memset(&ale_params, 0, sizeof(ale_params)); + + switch (cpsw->version) { + case CPSW_VERSION_1: + cpsw->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET; + cpts_regs = ss_regs + CPSW1_CPTS_OFFSET; + cpsw->hw_stats = ss_regs + CPSW1_HW_STATS; + dma_params.dmaregs = ss_regs + CPSW1_CPDMA_OFFSET; + dma_params.txhdp = ss_regs + CPSW1_STATERAM_OFFSET; + ale_params.ale_regs = ss_regs + CPSW1_ALE_OFFSET; + slave_offset = CPSW1_SLAVE_OFFSET; + slave_size = CPSW1_SLAVE_SIZE; + sliver_offset = CPSW1_SLIVER_OFFSET; + dma_params.desc_mem_phys = 0; + break; + case CPSW_VERSION_2: + case CPSW_VERSION_3: + case CPSW_VERSION_4: + cpsw->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET; + cpts_regs = ss_regs + CPSW2_CPTS_OFFSET; + cpsw->hw_stats = ss_regs + CPSW2_HW_STATS; + dma_params.dmaregs = ss_regs + CPSW2_CPDMA_OFFSET; + dma_params.txhdp = ss_regs + CPSW2_STATERAM_OFFSET; + ale_params.ale_regs = ss_regs + CPSW2_ALE_OFFSET; + slave_offset = CPSW2_SLAVE_OFFSET; + slave_size = CPSW2_SLAVE_SIZE; + sliver_offset = CPSW2_SLIVER_OFFSET; + dma_params.desc_mem_phys = desc_mem_phys; + break; + default: + dev_err(dev, "unknown version 0x%08x\n", cpsw->version); + return -ENODEV; + } + + for (i = 0; i < cpsw->data.slaves; i++) { + struct cpsw_slave *slave = &cpsw->slaves[i]; + void __iomem *regs = cpsw->regs; + + slave->slave_num = i; + slave->data = &cpsw->data.slave_data[i]; + slave->regs = regs + slave_offset; + slave->sliver = regs + sliver_offset; + slave->port_vlan = slave->data->dual_emac_res_vlan; + + slave_offset += slave_size; + sliver_offset += SLIVER_SIZE; + } + + ale_params.dev = dev; + ale_params.ale_ageout = ale_ageout; + ale_params.ale_entries = data->ale_entries; + ale_params.ale_ports = CPSW_ALE_PORTS_NUM; + + cpsw->ale = cpsw_ale_create(&ale_params); + if (!cpsw->ale) { + dev_err(dev, "error initializing ale engine\n"); + return -ENODEV; + } + + dma_params.dev = dev; + dma_params.rxthresh = dma_params.dmaregs + CPDMA_RXTHRESH; + dma_params.rxfree = dma_params.dmaregs + CPDMA_RXFREE; + dma_params.rxhdp = dma_params.txhdp + CPDMA_RXHDP; + dma_params.txcp = dma_params.txhdp + CPDMA_TXCP; + dma_params.rxcp = dma_params.txhdp + CPDMA_RXCP; + + dma_params.num_chan = data->channels; + dma_params.has_soft_reset = true; + dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE; + dma_params.desc_mem_size = data->bd_ram_size; + dma_params.desc_align = 16; + dma_params.has_ext_regs = true; + dma_params.desc_hw_addr = dma_params.desc_mem_phys; + dma_params.bus_freq_mhz = cpsw->bus_freq_mhz; + dma_params.descs_pool_size = descs_pool_size; + + cpsw->dma = cpdma_ctlr_create(&dma_params); + if (!cpsw->dma) { + dev_err(dev, "error initializing dma\n"); + return -ENOMEM; + } + + cpsw->cpts = cpts_create(cpsw->dev, cpts_regs, cpsw->dev->of_node); + if (IS_ERR(cpsw->cpts)) { + ret = PTR_ERR(cpsw->cpts); + cpdma_ctlr_destroy(cpsw->dma); + } + + return ret; +} diff --git a/drivers/net/ethernet/ti/cpsw_priv.h b/drivers/net/ethernet/ti/cpsw_priv.h index 8df9ce68696a..4004140fc4d0 100644 --- a/drivers/net/ethernet/ti/cpsw_priv.h +++ b/drivers/net/ethernet/ti/cpsw_priv.h @@ -447,4 +447,7 @@ struct addr_sync_ctx { int flush; /* flush flag */ }; +int cpsw_init_common(struct cpsw_common *cpsw, void __iomem *ss_regs, + int ale_ageout, u32 desc_mem_phys, int descs_pool_size); + #endif /* DRIVERS_NET_ETHERNET_TI_CPSW_PRIV_H_ */ From patchwork Tue Apr 23 13:09:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grygorii Strashko X-Patchwork-Id: 162686 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp3770863jan; Tue, 23 Apr 2019 06:10:22 -0700 (PDT) X-Google-Smtp-Source: APXvYqxlEOVykbolcq7cA3SOrHVCt4swb3Lpyp/5lGn1HoY+r71Nl2dAI3+h4hZUcY7gPDKtY4Hs X-Received: by 2002:a65:420b:: with SMTP id c11mr7657643pgq.24.1556025021767; Tue, 23 Apr 2019 06:10:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556025021; cv=none; d=google.com; s=arc-20160816; b=Fpfgg4WWWhV744c01bobtNW5Na2LALkO8BzNgcAtj7biEFeuwX7rPYwomveBuMyzux 4RfhF6nxHQnDuKFOjvJgaV24gCTIOoP1ee5uCbkZrnPw96igvKpZTQFNycUp7J7+7OSb ye6ADua5bnIJtfp3otMiAQ14rYOsrAGqV3KmsTIbhOB5Ig/fgH2njFTbeglr6vFMhxkH 8ormTm81vWlFzVWmaWkjEAGUN0jCxndwt5JRm/w0kyAsGw/zkG5cObrwY9ORcgeN2aOV b/X9PooBc8FcIixsXduBLBTcOZKNVG+/E/e63QwQpB56HG8FTqxOIAMhz/ejIdwakSD4 zwkg== ARC-Message-Signature: i=1; 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Miller" , Ivan Khoronzhuk CC: Florian Fainelli , Andrew Lunn , Sekhar Nori , , , Murali Karicheri , Grygorii Strashko Subject: [PATCH net-next 17/19] net: ethernet: ti: cpsw: introduce mac sl module api Date: Tue, 23 Apr 2019 16:09:08 +0300 Message-ID: <1556024950-20752-18-git-send-email-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1556024950-20752-1-git-send-email-grygorii.strashko@ti.com> References: <1556024950-20752-1-git-send-email-grygorii.strashko@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The MAC SL submodule has a lot of common functions between many of TI SoCs AM335x/AM437x/DRA7(AM57xx), Keystone 2 66AK2HK/E/L/G and K3 AM654, but there are also differences especially in registers offsets and sets of supported functions. This patch introduces the MAC SL submodule API which is intended to provide a common way to access the MAC SL submodule and hide HW integrations details. Signed-off-by: Grygorii Strashko Signed-off-by: Sekhar Nori --- drivers/net/ethernet/ti/cpsw_sl.c | 327 ++++++++++++++++++++++++++++++ drivers/net/ethernet/ti/cpsw_sl.h | 73 +++++++ 2 files changed, 400 insertions(+) create mode 100644 drivers/net/ethernet/ti/cpsw_sl.c create mode 100644 drivers/net/ethernet/ti/cpsw_sl.h -- 2.17.1 diff --git a/drivers/net/ethernet/ti/cpsw_sl.c b/drivers/net/ethernet/ti/cpsw_sl.c new file mode 100644 index 000000000000..a44dc70bcf4c --- /dev/null +++ b/drivers/net/ethernet/ti/cpsw_sl.c @@ -0,0 +1,327 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Texas Instruments Ethernet Switch media-access-controller (MAC) submodule/ + * Ethernet MAC Sliver (CPGMAC_SL) + * + * Copyright (C) 2019 Texas Instruments + * + */ + +#include +#include + +#include "cpsw_sl.h" + +#define CPSW_SL_REG_NOTUSED U16_MAX + +static const u16 cpsw_sl_reg_map_cpsw[] = { + [CPSW_SL_IDVER] = 0x00, + [CPSW_SL_MACCONTROL] = 0x04, + [CPSW_SL_MACSTATUS] = 0x08, + [CPSW_SL_SOFT_RESET] = 0x0c, + [CPSW_SL_RX_MAXLEN] = 0x10, + [CPSW_SL_BOFFTEST] = 0x14, + [CPSW_SL_RX_PAUSE] = 0x18, + [CPSW_SL_TX_PAUSE] = 0x1c, + [CPSW_SL_EMCONTROL] = 0x20, + [CPSW_SL_RX_PRI_MAP] = 0x24, + [CPSW_SL_TX_GAP] = 0x28, +}; + +static const u16 cpsw_sl_reg_map_66ak2hk[] = { + [CPSW_SL_IDVER] = 0x00, + [CPSW_SL_MACCONTROL] = 0x04, + [CPSW_SL_MACSTATUS] = 0x08, + [CPSW_SL_SOFT_RESET] = 0x0c, + [CPSW_SL_RX_MAXLEN] = 0x10, + [CPSW_SL_BOFFTEST] = CPSW_SL_REG_NOTUSED, + [CPSW_SL_RX_PAUSE] = 0x18, + [CPSW_SL_TX_PAUSE] = 0x1c, + [CPSW_SL_EMCONTROL] = 0x20, + [CPSW_SL_RX_PRI_MAP] = 0x24, + [CPSW_SL_TX_GAP] = CPSW_SL_REG_NOTUSED, +}; + +static const u16 cpsw_sl_reg_map_66ak2x_xgbe[] = { + [CPSW_SL_IDVER] = 0x00, + [CPSW_SL_MACCONTROL] = 0x04, + [CPSW_SL_MACSTATUS] = 0x08, + [CPSW_SL_SOFT_RESET] = 0x0c, + [CPSW_SL_RX_MAXLEN] = 0x10, + [CPSW_SL_BOFFTEST] = CPSW_SL_REG_NOTUSED, + [CPSW_SL_RX_PAUSE] = 0x18, + [CPSW_SL_TX_PAUSE] = 0x1c, + [CPSW_SL_EMCONTROL] = 0x20, + [CPSW_SL_RX_PRI_MAP] = CPSW_SL_REG_NOTUSED, + [CPSW_SL_TX_GAP] = 0x28, +}; + +static const u16 cpsw_sl_reg_map_66ak2elg_am65[] = { + [CPSW_SL_IDVER] = CPSW_SL_REG_NOTUSED, + [CPSW_SL_MACCONTROL] = 0x00, + [CPSW_SL_MACSTATUS] = 0x04, + [CPSW_SL_SOFT_RESET] = 0x08, + [CPSW_SL_RX_MAXLEN] = CPSW_SL_REG_NOTUSED, + [CPSW_SL_BOFFTEST] = 0x0c, + [CPSW_SL_RX_PAUSE] = 0x10, + [CPSW_SL_TX_PAUSE] = 0x40, + [CPSW_SL_EMCONTROL] = 0x70, + [CPSW_SL_RX_PRI_MAP] = CPSW_SL_REG_NOTUSED, + [CPSW_SL_TX_GAP] = 0x74, +}; + +#define CPSW_SL_SOFT_RESET_BIT BIT(0) + +#define CPSW_SL_STATUS_PN_IDLE BIT(31) +#define CPSW_SL_AM65_STATUS_PN_E_IDLE BIT(30) +#define CPSW_SL_AM65_STATUS_PN_P_IDLE BIT(29) +#define CPSW_SL_AM65_STATUS_PN_TX_IDLE BIT(28) + +#define CPSW_SL_STATUS_IDLE_MASK_BASE (CPSW_SL_STATUS_PN_IDLE) + +#define CPSW_SL_STATUS_IDLE_MASK_K3 \ + (CPSW_SL_STATUS_IDLE_MASK_BASE | CPSW_SL_AM65_STATUS_PN_E_IDLE | \ + CPSW_SL_AM65_STATUS_PN_P_IDLE | CPSW_SL_AM65_STATUS_PN_TX_IDLE) + +#define CPSW_SL_CTL_FUNC_BASE \ + (CPSW_SL_CTL_FULLDUPLEX |\ + CPSW_SL_CTL_LOOPBACK |\ + CPSW_SL_CTL_RX_FLOW_EN |\ + CPSW_SL_CTL_TX_FLOW_EN |\ + CPSW_SL_CTL_GMII_EN |\ + CPSW_SL_CTL_TX_PACE |\ + CPSW_SL_CTL_GIG |\ + CPSW_SL_CTL_CMD_IDLE |\ + CPSW_SL_CTL_IFCTL_A |\ + CPSW_SL_CTL_IFCTL_B |\ + CPSW_SL_CTL_GIG_FORCE |\ + CPSW_SL_CTL_EXT_EN |\ + CPSW_SL_CTL_RX_CEF_EN |\ + CPSW_SL_CTL_RX_CSF_EN |\ + CPSW_SL_CTL_RX_CMF_EN) + +struct cpsw_sl { + struct device *dev; + void __iomem *sl_base; + const u16 *regs; + u32 control_features; + u32 idle_mask; +}; + +struct cpsw_sl_dev_id { + const char *device_id; + const u16 *regs; + const u32 control_features; + const u32 regs_offset; + const u32 idle_mask; +}; + +static const struct cpsw_sl_dev_id cpsw_sl_id_match[] = { + { + .device_id = "cpsw", + .regs = cpsw_sl_reg_map_cpsw, + .control_features = CPSW_SL_CTL_FUNC_BASE | + CPSW_SL_CTL_MTEST | + CPSW_SL_CTL_TX_SHORT_GAP_EN | + CPSW_SL_CTL_TX_SG_LIM_EN, + .idle_mask = CPSW_SL_STATUS_IDLE_MASK_BASE, + }, + { + .device_id = "66ak2hk", + .regs = cpsw_sl_reg_map_66ak2hk, + .control_features = CPSW_SL_CTL_FUNC_BASE | + CPSW_SL_CTL_TX_SHORT_GAP_EN, + .idle_mask = CPSW_SL_STATUS_IDLE_MASK_BASE, + }, + { + .device_id = "66ak2x_xgbe", + .regs = cpsw_sl_reg_map_66ak2x_xgbe, + .control_features = CPSW_SL_CTL_FUNC_BASE | + CPSW_SL_CTL_XGIG | + CPSW_SL_CTL_TX_SHORT_GAP_EN | + CPSW_SL_CTL_CRC_TYPE | + CPSW_SL_CTL_XGMII_EN, + .idle_mask = CPSW_SL_STATUS_IDLE_MASK_BASE, + }, + { + .device_id = "66ak2el", + .regs = cpsw_sl_reg_map_66ak2elg_am65, + .regs_offset = 0x330, + .control_features = CPSW_SL_CTL_FUNC_BASE | + CPSW_SL_CTL_MTEST | + CPSW_SL_CTL_TX_SHORT_GAP_EN | + CPSW_SL_CTL_CRC_TYPE | + CPSW_SL_CTL_EXT_EN_RX_FLO | + CPSW_SL_CTL_EXT_EN_TX_FLO | + CPSW_SL_CTL_TX_SG_LIM_EN, + .idle_mask = CPSW_SL_STATUS_IDLE_MASK_BASE, + }, + { + .device_id = "66ak2g", + .regs = cpsw_sl_reg_map_66ak2elg_am65, + .regs_offset = 0x330, + .control_features = CPSW_SL_CTL_FUNC_BASE | + CPSW_SL_CTL_MTEST | + CPSW_SL_CTL_CRC_TYPE | + CPSW_SL_CTL_EXT_EN_RX_FLO | + CPSW_SL_CTL_EXT_EN_TX_FLO, + }, + { + .device_id = "am65", + .regs = cpsw_sl_reg_map_66ak2elg_am65, + .regs_offset = 0x330, + .control_features = CPSW_SL_CTL_FUNC_BASE | + CPSW_SL_CTL_MTEST | + CPSW_SL_CTL_XGIG | + CPSW_SL_CTL_TX_SHORT_GAP_EN | + CPSW_SL_CTL_CRC_TYPE | + CPSW_SL_CTL_XGMII_EN | + CPSW_SL_CTL_EXT_EN_RX_FLO | + CPSW_SL_CTL_EXT_EN_TX_FLO | + CPSW_SL_CTL_TX_SG_LIM_EN | + CPSW_SL_CTL_EXT_EN_XGIG, + .idle_mask = CPSW_SL_STATUS_IDLE_MASK_K3, + }, + { }, +}; + +u32 cpsw_sl_reg_read(struct cpsw_sl *sl, enum cpsw_sl_regs reg) +{ + int val; + + if (sl->regs[reg] == CPSW_SL_REG_NOTUSED) { + dev_err(sl->dev, "cpsw_sl: not sup r reg: %04X\n", + sl->regs[reg]); + return 0; + } + + val = readl(sl->sl_base + sl->regs[reg]); + dev_dbg(sl->dev, "cpsw_sl: reg: %04X r 0x%08X\n", sl->regs[reg], val); + return val; +} + +void cpsw_sl_reg_write(struct cpsw_sl *sl, enum cpsw_sl_regs reg, u32 val) +{ + if (sl->regs[reg] == CPSW_SL_REG_NOTUSED) { + dev_err(sl->dev, "cpsw_sl: not sup w reg: %04X\n", + sl->regs[reg]); + return; + } + + dev_dbg(sl->dev, "cpsw_sl: reg: %04X w 0x%08X\n", sl->regs[reg], val); + writel(val, sl->sl_base + sl->regs[reg]); +} + +static const struct cpsw_sl_dev_id *cpsw_sl_match_id( + const struct cpsw_sl_dev_id *id, + const char *device_id) +{ + if (!id || !device_id) + return NULL; + + while (id->device_id) { + if (strcmp(device_id, id->device_id) == 0) + return id; + id++; + } + return NULL; +} + +struct cpsw_sl *cpsw_sl_get(const char *device_id, struct device *dev, + void __iomem *sl_base) +{ + const struct cpsw_sl_dev_id *sl_dev_id; + struct cpsw_sl *sl; + + sl = devm_kzalloc(dev, sizeof(struct cpsw_sl), GFP_KERNEL); + if (!sl) + return ERR_PTR(-ENOMEM); + sl->dev = dev; + sl->sl_base = sl_base; + + sl_dev_id = cpsw_sl_match_id(cpsw_sl_id_match, device_id); + if (!sl_dev_id) { + dev_err(sl->dev, "cpsw_sl: dev_id %s not found.\n", device_id); + return ERR_PTR(-EINVAL); + } + sl->regs = sl_dev_id->regs; + sl->control_features = sl_dev_id->control_features; + sl->idle_mask = sl_dev_id->idle_mask; + sl->sl_base += sl_dev_id->regs_offset; + + return sl; +} + +void cpsw_sl_reset(struct cpsw_sl *sl, unsigned long tmo) +{ + unsigned long timeout = jiffies + msecs_to_jiffies(tmo); + + /* Set the soft reset bit */ + cpsw_sl_reg_write(sl, CPSW_SL_SOFT_RESET, CPSW_SL_SOFT_RESET_BIT); + + /* Wait for the bit to clear */ + do { + cpu_relax(); + } while ((cpsw_sl_reg_read(sl, CPSW_SL_SOFT_RESET) & + CPSW_SL_SOFT_RESET_BIT) && + time_after(timeout, jiffies)); + + if (cpsw_sl_reg_read(sl, CPSW_SL_SOFT_RESET) & CPSW_SL_SOFT_RESET_BIT) + dev_err(sl->dev, "cpsw_sl failed to soft-reset.\n"); +} + +u32 cpsw_sl_ctl_set(struct cpsw_sl *sl, u32 ctl_funcs) +{ + u32 val; + + if (ctl_funcs & ~sl->control_features) { + dev_err(sl->dev, "cpsw_sl: unsupported func 0x%08X\n", + ctl_funcs & (~sl->control_features)); + return -EINVAL; + } + + val = cpsw_sl_reg_read(sl, CPSW_SL_MACCONTROL); + val |= ctl_funcs; + cpsw_sl_reg_write(sl, CPSW_SL_MACCONTROL, val); + + return 0; +} + +u32 cpsw_sl_ctl_clr(struct cpsw_sl *sl, u32 ctl_funcs) +{ + u32 val; + + if (ctl_funcs & ~sl->control_features) { + dev_err(sl->dev, "cpsw_sl: unsupported func 0x%08X\n", + ctl_funcs & (~sl->control_features)); + return -EINVAL; + } + + val = cpsw_sl_reg_read(sl, CPSW_SL_MACCONTROL); + val &= ~ctl_funcs; + cpsw_sl_reg_write(sl, CPSW_SL_MACCONTROL, val); + + return 0; +} + +void cpsw_sl_ctl_reset(struct cpsw_sl *sl) +{ + cpsw_sl_reg_write(sl, CPSW_SL_MACCONTROL, 0); +} + +int cpsw_sl_wait_for_idle(struct cpsw_sl *sl, unsigned long tmo) +{ + unsigned long timeout = jiffies + msecs_to_jiffies(tmo); + + do { + cpu_relax(); + } while (!(cpsw_sl_reg_read(sl, CPSW_SL_MACSTATUS) & + sl->idle_mask) && time_after(timeout, jiffies)); + + if (!(cpsw_sl_reg_read(sl, CPSW_SL_MACSTATUS) & sl->idle_mask)) { + dev_err(sl->dev, "cpsw_sl failed to soft-reset.\n"); + return -ETIMEDOUT; + } + + return 0; +} diff --git a/drivers/net/ethernet/ti/cpsw_sl.h b/drivers/net/ethernet/ti/cpsw_sl.h new file mode 100644 index 000000000000..a6d06a5a420f --- /dev/null +++ b/drivers/net/ethernet/ti/cpsw_sl.h @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Texas Instruments Ethernet Switch media-access-controller (MAC) submodule/ + * Ethernet MAC Sliver (CPGMAC_SL) APIs + * + * Copyright (C) 2019 Texas Instruments + * + */ + +#ifndef __TI_CPSW_SL_H__ +#define __TI_CPSW_SL_H__ + +#include + +enum cpsw_sl_regs { + CPSW_SL_IDVER, + CPSW_SL_MACCONTROL, + CPSW_SL_MACSTATUS, + CPSW_SL_SOFT_RESET, + CPSW_SL_RX_MAXLEN, + CPSW_SL_BOFFTEST, + CPSW_SL_RX_PAUSE, + CPSW_SL_TX_PAUSE, + CPSW_SL_EMCONTROL, + CPSW_SL_RX_PRI_MAP, + CPSW_SL_TX_GAP, +}; + +enum { + CPSW_SL_CTL_FULLDUPLEX = BIT(0), /* Full Duplex mode */ + CPSW_SL_CTL_LOOPBACK = BIT(1), /* Loop Back Mode */ + CPSW_SL_CTL_MTEST = BIT(2), /* Manufacturing Test mode */ + CPSW_SL_CTL_RX_FLOW_EN = BIT(3), /* Receive Flow Control Enable */ + CPSW_SL_CTL_TX_FLOW_EN = BIT(4), /* Transmit Flow Control Enable */ + CPSW_SL_CTL_GMII_EN = BIT(5), /* GMII Enable */ + CPSW_SL_CTL_TX_PACE = BIT(6), /* Transmit Pacing Enable */ + CPSW_SL_CTL_GIG = BIT(7), /* Gigabit Mode */ + CPSW_SL_CTL_XGIG = BIT(8), /* 10 Gigabit Mode */ + CPSW_SL_CTL_TX_SHORT_GAP_EN = BIT(10), /* Transmit Short Gap Enable */ + CPSW_SL_CTL_CMD_IDLE = BIT(11), /* Command Idle */ + CPSW_SL_CTL_CRC_TYPE = BIT(12), /* Port CRC Type */ + CPSW_SL_CTL_XGMII_EN = BIT(13), /* XGMII Enable */ + CPSW_SL_CTL_IFCTL_A = BIT(15), /* Interface Control A */ + CPSW_SL_CTL_IFCTL_B = BIT(16), /* Interface Control B */ + CPSW_SL_CTL_GIG_FORCE = BIT(17), /* Gigabit Mode Force */ + CPSW_SL_CTL_EXT_EN = BIT(18), /* External Control Enable */ + CPSW_SL_CTL_EXT_EN_RX_FLO = BIT(19), /* Ext RX Flow Control Enable */ + CPSW_SL_CTL_EXT_EN_TX_FLO = BIT(20), /* Ext TX Flow Control Enable */ + CPSW_SL_CTL_TX_SG_LIM_EN = BIT(21), /* TXt Short Gap Limit Enable */ + CPSW_SL_CTL_RX_CEF_EN = BIT(22), /* RX Copy Error Frames Enable */ + CPSW_SL_CTL_RX_CSF_EN = BIT(23), /* RX Copy Short Frames Enable */ + CPSW_SL_CTL_RX_CMF_EN = BIT(24), /* RX Copy MAC Control Frames Enable */ + CPSW_SL_CTL_EXT_EN_XGIG = BIT(25), /* Ext XGIG Control En, k3 only */ + + CPSW_SL_CTL_FUNCS_COUNT +}; + +struct cpsw_sl; + +struct cpsw_sl *cpsw_sl_get(const char *device_id, struct device *dev, + void __iomem *sl_base); + +void cpsw_sl_reset(struct cpsw_sl *sl, unsigned long tmo); + +u32 cpsw_sl_ctl_set(struct cpsw_sl *sl, u32 ctl_funcs); +u32 cpsw_sl_ctl_clr(struct cpsw_sl *sl, u32 ctl_funcs); +void cpsw_sl_ctl_reset(struct cpsw_sl *sl); +int cpsw_sl_wait_for_idle(struct cpsw_sl *sl, unsigned long tmo); + +u32 cpsw_sl_reg_read(struct cpsw_sl *sl, enum cpsw_sl_regs reg); +void cpsw_sl_reg_write(struct cpsw_sl *sl, enum cpsw_sl_regs reg, u32 val); + +#endif /* __TI_CPSW_SL_H__ */ From patchwork Tue Apr 23 13:09:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grygorii Strashko X-Patchwork-Id: 162684 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp3770469jan; Tue, 23 Apr 2019 06:10:02 -0700 (PDT) X-Google-Smtp-Source: APXvYqx97evZT8ClVT4MDU460jS3h2TveQB3qMqxcbtyG+QGkLuT/gU2tgsQlYmDC+NmiiRqj/A3 X-Received: by 2002:a17:902:968b:: with SMTP id n11mr25890409plp.118.1556025001809; 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Miller" , Ivan Khoronzhuk CC: Florian Fainelli , Andrew Lunn , Sekhar Nori , , , Murali Karicheri , Grygorii Strashko Subject: [PATCH net-next 19/19] net: ethernet: ti: cpsw: move ethtool func in separate file Date: Tue, 23 Apr 2019 16:09:10 +0300 Message-ID: <1556024950-20752-20-git-send-email-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1556024950-20752-1-git-send-email-grygorii.strashko@ti.com> References: <1556024950-20752-1-git-send-email-grygorii.strashko@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org As a preparatory patch to add support for a switchdev based cpsw driver, move common ethtool functions to separate cpsw-ethtool.c file so that they can be used across both drivers. It will simplify CPSW driver code maintenance also. Signed-off-by: Grygorii Strashko --- drivers/net/ethernet/ti/Makefile | 2 +- drivers/net/ethernet/ti/cpsw.c | 691 +----------------------- drivers/net/ethernet/ti/cpsw_ethtool.c | 719 +++++++++++++++++++++++++ drivers/net/ethernet/ti/cpsw_priv.h | 83 +-- 4 files changed, 769 insertions(+), 726 deletions(-) create mode 100644 drivers/net/ethernet/ti/cpsw_ethtool.c -- 2.17.1 diff --git a/drivers/net/ethernet/ti/Makefile b/drivers/net/ethernet/ti/Makefile index 0a75c1957626..c3f53a40b48f 100644 --- a/drivers/net/ethernet/ti/Makefile +++ b/drivers/net/ethernet/ti/Makefile @@ -14,7 +14,7 @@ obj-$(CONFIG_TI_DAVINCI_MDIO) += davinci_mdio.o obj-$(CONFIG_TI_CPSW_PHY_SEL) += cpsw-phy-sel.o obj-$(CONFIG_TI_CPTS_MOD) += cpts.o obj-$(CONFIG_TI_CPSW) += ti_cpsw.o -ti_cpsw-y := cpsw.o davinci_cpdma.o cpsw_ale.o cpsw_priv.o cpsw_sl.o +ti_cpsw-y := cpsw.o davinci_cpdma.o cpsw_ale.o cpsw_priv.o cpsw_sl.o cpsw_ethtool.o obj-$(CONFIG_TI_KEYSTONE_NETCP) += keystone_netcp.o keystone_netcp-y := netcp_core.o cpsw_ale.o diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c index ba1fb8578e8d..ca6475c920db 100644 --- a/drivers/net/ethernet/ti/cpsw.c +++ b/drivers/net/ethernet/ti/cpsw.c @@ -60,83 +60,6 @@ static int descs_pool_size = CPSW_CPDMA_DESCS_POOL_SIZE_DEFAULT; module_param(descs_pool_size, int, 0444); MODULE_PARM_DESC(descs_pool_size, "Number of CPDMA CPPI descriptors in pool"); -struct cpsw_stats { - char stat_string[ETH_GSTRING_LEN]; - int type; - int sizeof_stat; - int stat_offset; -}; - -enum { - CPSW_STATS, - CPDMA_RX_STATS, - CPDMA_TX_STATS, -}; - -#define CPSW_STAT(m) CPSW_STATS, \ - FIELD_SIZEOF(struct cpsw_hw_stats, m), \ - offsetof(struct cpsw_hw_stats, m) -#define CPDMA_RX_STAT(m) CPDMA_RX_STATS, \ - FIELD_SIZEOF(struct cpdma_chan_stats, m), \ - offsetof(struct cpdma_chan_stats, m) -#define CPDMA_TX_STAT(m) CPDMA_TX_STATS, \ - FIELD_SIZEOF(struct cpdma_chan_stats, m), \ - offsetof(struct cpdma_chan_stats, m) - -static const struct cpsw_stats cpsw_gstrings_stats[] = { - { "Good Rx Frames", CPSW_STAT(rxgoodframes) }, - { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) }, - { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) }, - { "Pause Rx Frames", CPSW_STAT(rxpauseframes) }, - { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) }, - { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) }, - { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) }, - { "Rx Jabbers", CPSW_STAT(rxjabberframes) }, - { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) }, - { "Rx Fragments", CPSW_STAT(rxfragments) }, - { "Rx Octets", CPSW_STAT(rxoctets) }, - { "Good Tx Frames", CPSW_STAT(txgoodframes) }, - { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) }, - { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) }, - { "Pause Tx Frames", CPSW_STAT(txpauseframes) }, - { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) }, - { "Collisions", CPSW_STAT(txcollisionframes) }, - { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) }, - { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) }, - { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) }, - { "Late Collisions", CPSW_STAT(txlatecollisions) }, - { "Tx Underrun", CPSW_STAT(txunderrun) }, - { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) }, - { "Tx Octets", CPSW_STAT(txoctets) }, - { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) }, - { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) }, - { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) }, - { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) }, - { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) }, - { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) }, - { "Net Octets", CPSW_STAT(netoctets) }, - { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) }, - { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) }, - { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) }, -}; - -static const struct cpsw_stats cpsw_gstrings_ch_stats[] = { - { "head_enqueue", CPDMA_RX_STAT(head_enqueue) }, - { "tail_enqueue", CPDMA_RX_STAT(tail_enqueue) }, - { "pad_enqueue", CPDMA_RX_STAT(pad_enqueue) }, - { "misqueued", CPDMA_RX_STAT(misqueued) }, - { "desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) }, - { "pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) }, - { "runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) }, - { "runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) }, - { "empty_dequeue", CPDMA_RX_STAT(empty_dequeue) }, - { "busy_dequeue", CPDMA_RX_STAT(busy_dequeue) }, - { "good_dequeue", CPDMA_RX_STAT(good_dequeue) }, - { "requeue", CPDMA_RX_STAT(requeue) }, - { "teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) }, -}; - - static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev, __be16 proto, u16 vid); @@ -382,7 +305,7 @@ static void cpsw_ndo_set_rx_mode(struct net_device *ndev) cpsw_del_mc_addr); } -static void cpsw_intr_enable(struct cpsw_common *cpsw) +void cpsw_intr_enable(struct cpsw_common *cpsw) { writel_relaxed(0xFF, &cpsw->wr_regs->tx_en); writel_relaxed(0xFF, &cpsw->wr_regs->rx_en); @@ -391,7 +314,7 @@ static void cpsw_intr_enable(struct cpsw_common *cpsw) return; } -static void cpsw_intr_disable(struct cpsw_common *cpsw) +void cpsw_intr_disable(struct cpsw_common *cpsw) { writel_relaxed(0, &cpsw->wr_regs->tx_en); writel_relaxed(0, &cpsw->wr_regs->rx_en); @@ -400,7 +323,7 @@ static void cpsw_intr_disable(struct cpsw_common *cpsw) return; } -static void cpsw_tx_handler(void *token, int len, int status) +void cpsw_tx_handler(void *token, int len, int status) { struct netdev_queue *txq; struct sk_buff *skb = token; @@ -532,7 +455,7 @@ static void cpsw_rx_handler(void *token, int len, int status) dev_kfree_skb_any(new_skb); } -static void cpsw_split_res(struct cpsw_common *cpsw) +void cpsw_split_res(struct cpsw_common *cpsw) { u32 consumed_rate = 0, bigest_rate = 0; struct cpsw_vector *txv = cpsw->txv; @@ -924,156 +847,6 @@ static void cpsw_adjust_link(struct net_device *ndev) } } -static int cpsw_get_coalesce(struct net_device *ndev, - struct ethtool_coalesce *coal) -{ - struct cpsw_common *cpsw = ndev_to_cpsw(ndev); - - coal->rx_coalesce_usecs = cpsw->coal_intvl; - return 0; -} - -static int cpsw_set_coalesce(struct net_device *ndev, - struct ethtool_coalesce *coal) -{ - struct cpsw_priv *priv = netdev_priv(ndev); - u32 int_ctrl; - u32 num_interrupts = 0; - u32 prescale = 0; - u32 addnl_dvdr = 1; - u32 coal_intvl = 0; - struct cpsw_common *cpsw = priv->cpsw; - - coal_intvl = coal->rx_coalesce_usecs; - - int_ctrl = readl(&cpsw->wr_regs->int_control); - prescale = cpsw->bus_freq_mhz * 4; - - if (!coal->rx_coalesce_usecs) { - int_ctrl &= ~(CPSW_INTPRESCALE_MASK | CPSW_INTPACEEN); - goto update_return; - } - - if (coal_intvl < CPSW_CMINTMIN_INTVL) - coal_intvl = CPSW_CMINTMIN_INTVL; - - if (coal_intvl > CPSW_CMINTMAX_INTVL) { - /* Interrupt pacer works with 4us Pulse, we can - * throttle further by dilating the 4us pulse. - */ - addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale; - - if (addnl_dvdr > 1) { - prescale *= addnl_dvdr; - if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr)) - coal_intvl = (CPSW_CMINTMAX_INTVL - * addnl_dvdr); - } else { - addnl_dvdr = 1; - coal_intvl = CPSW_CMINTMAX_INTVL; - } - } - - num_interrupts = (1000 * addnl_dvdr) / coal_intvl; - writel(num_interrupts, &cpsw->wr_regs->rx_imax); - writel(num_interrupts, &cpsw->wr_regs->tx_imax); - - int_ctrl |= CPSW_INTPACEEN; - int_ctrl &= (~CPSW_INTPRESCALE_MASK); - int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK); - -update_return: - writel(int_ctrl, &cpsw->wr_regs->int_control); - - cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl); - cpsw->coal_intvl = coal_intvl; - - return 0; -} - -static int cpsw_get_sset_count(struct net_device *ndev, int sset) -{ - struct cpsw_common *cpsw = ndev_to_cpsw(ndev); - - switch (sset) { - case ETH_SS_STATS: - return (CPSW_STATS_COMMON_LEN + - (cpsw->rx_ch_num + cpsw->tx_ch_num) * - CPSW_STATS_CH_LEN); - default: - return -EOPNOTSUPP; - } -} - -static void cpsw_add_ch_strings(u8 **p, int ch_num, int rx_dir) -{ - int ch_stats_len; - int line; - int i; - - ch_stats_len = CPSW_STATS_CH_LEN * ch_num; - for (i = 0; i < ch_stats_len; i++) { - line = i % CPSW_STATS_CH_LEN; - snprintf(*p, ETH_GSTRING_LEN, - "%s DMA chan %ld: %s", rx_dir ? "Rx" : "Tx", - (long)(i / CPSW_STATS_CH_LEN), - cpsw_gstrings_ch_stats[line].stat_string); - *p += ETH_GSTRING_LEN; - } -} - -static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data) -{ - struct cpsw_common *cpsw = ndev_to_cpsw(ndev); - u8 *p = data; - int i; - - switch (stringset) { - case ETH_SS_STATS: - for (i = 0; i < CPSW_STATS_COMMON_LEN; i++) { - memcpy(p, cpsw_gstrings_stats[i].stat_string, - ETH_GSTRING_LEN); - p += ETH_GSTRING_LEN; - } - - cpsw_add_ch_strings(&p, cpsw->rx_ch_num, 1); - cpsw_add_ch_strings(&p, cpsw->tx_ch_num, 0); - break; - } -} - -static void cpsw_get_ethtool_stats(struct net_device *ndev, - struct ethtool_stats *stats, u64 *data) -{ - u8 *p; - struct cpsw_common *cpsw = ndev_to_cpsw(ndev); - struct cpdma_chan_stats ch_stats; - int i, l, ch; - - /* Collect Davinci CPDMA stats for Rx and Tx Channel */ - for (l = 0; l < CPSW_STATS_COMMON_LEN; l++) - data[l] = readl(cpsw->hw_stats + - cpsw_gstrings_stats[l].stat_offset); - - for (ch = 0; ch < cpsw->rx_ch_num; ch++) { - cpdma_chan_get_stats(cpsw->rxv[ch].ch, &ch_stats); - for (i = 0; i < CPSW_STATS_CH_LEN; i++, l++) { - p = (u8 *)&ch_stats + - cpsw_gstrings_ch_stats[i].stat_offset; - data[l] = *(u32 *)p; - } - } - - for (ch = 0; ch < cpsw->tx_ch_num; ch++) { - cpdma_chan_get_stats(cpsw->txv[ch].ch, &ch_stats); - for (i = 0; i < CPSW_STATS_CH_LEN; i++, l++) { - p = (u8 *)&ch_stats + - cpsw_gstrings_ch_stats[i].stat_offset; - data[l] = *(u32 *)p; - } - } -} - static inline void cpsw_add_dual_emac_def_ale_entries( struct cpsw_priv *priv, struct cpsw_slave *slave, u32 slave_port) @@ -1245,7 +1018,7 @@ static void cpsw_init_host_port(struct cpsw_priv *priv) } } -static int cpsw_fill_rx_channels(struct cpsw_priv *priv) +int cpsw_fill_rx_channels(struct cpsw_priv *priv) { struct cpsw_common *cpsw = priv->cpsw; struct sk_buff *skb; @@ -1970,18 +1743,6 @@ static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p) return 0; } -#ifdef CONFIG_NET_POLL_CONTROLLER -static void cpsw_ndo_poll_controller(struct net_device *ndev) -{ - struct cpsw_common *cpsw = ndev_to_cpsw(ndev); - - cpsw_intr_disable(cpsw); - cpsw_rx_interrupt(cpsw->irqs_table[0], cpsw); - cpsw_tx_interrupt(cpsw->irqs_table[1], cpsw); - cpsw_intr_enable(cpsw); -} -#endif - static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv, unsigned short vid) { @@ -2247,25 +2008,6 @@ static const struct net_device_ops cpsw_netdev_ops = { .ndo_setup_tc = cpsw_ndo_setup_tc, }; -static int cpsw_get_regs_len(struct net_device *ndev) -{ - struct cpsw_common *cpsw = ndev_to_cpsw(ndev); - - return cpsw->data.ale_entries * ALE_ENTRY_WORDS * sizeof(u32); -} - -static void cpsw_get_regs(struct net_device *ndev, - struct ethtool_regs *regs, void *p) -{ - u32 *reg = p; - struct cpsw_common *cpsw = ndev_to_cpsw(ndev); - - /* update CPSW IP version */ - regs->version = cpsw->version; - - cpsw_ale_dump(cpsw->ale, reg); -} - static void cpsw_get_drvinfo(struct net_device *ndev, struct ethtool_drvinfo *info) { @@ -2277,119 +2019,6 @@ static void cpsw_get_drvinfo(struct net_device *ndev, strlcpy(info->bus_info, pdev->name, sizeof(info->bus_info)); } -static u32 cpsw_get_msglevel(struct net_device *ndev) -{ - struct cpsw_priv *priv = netdev_priv(ndev); - return priv->msg_enable; -} - -static void cpsw_set_msglevel(struct net_device *ndev, u32 value) -{ - struct cpsw_priv *priv = netdev_priv(ndev); - priv->msg_enable = value; -} - -#if IS_ENABLED(CONFIG_TI_CPTS) -static int cpsw_get_ts_info(struct net_device *ndev, - struct ethtool_ts_info *info) -{ - struct cpsw_common *cpsw = ndev_to_cpsw(ndev); - - info->so_timestamping = - SOF_TIMESTAMPING_TX_HARDWARE | - SOF_TIMESTAMPING_TX_SOFTWARE | - SOF_TIMESTAMPING_RX_HARDWARE | - SOF_TIMESTAMPING_RX_SOFTWARE | - SOF_TIMESTAMPING_SOFTWARE | - SOF_TIMESTAMPING_RAW_HARDWARE; - info->phc_index = cpsw->cpts->phc_index; - info->tx_types = - (1 << HWTSTAMP_TX_OFF) | - (1 << HWTSTAMP_TX_ON); - info->rx_filters = - (1 << HWTSTAMP_FILTER_NONE) | - (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) | - (1 << HWTSTAMP_FILTER_PTP_V2_EVENT); - return 0; -} -#else -static int cpsw_get_ts_info(struct net_device *ndev, - struct ethtool_ts_info *info) -{ - info->so_timestamping = - SOF_TIMESTAMPING_TX_SOFTWARE | - SOF_TIMESTAMPING_RX_SOFTWARE | - SOF_TIMESTAMPING_SOFTWARE; - info->phc_index = -1; - info->tx_types = 0; - info->rx_filters = 0; - return 0; -} -#endif - -static int cpsw_get_link_ksettings(struct net_device *ndev, - struct ethtool_link_ksettings *ecmd) -{ - struct cpsw_priv *priv = netdev_priv(ndev); - struct cpsw_common *cpsw = priv->cpsw; - int slave_no = cpsw_slave_index(cpsw, priv); - - if (!cpsw->slaves[slave_no].phy) - return -EOPNOTSUPP; - - phy_ethtool_ksettings_get(cpsw->slaves[slave_no].phy, ecmd); - return 0; -} - -static int cpsw_set_link_ksettings(struct net_device *ndev, - const struct ethtool_link_ksettings *ecmd) -{ - struct cpsw_priv *priv = netdev_priv(ndev); - struct cpsw_common *cpsw = priv->cpsw; - int slave_no = cpsw_slave_index(cpsw, priv); - - if (cpsw->slaves[slave_no].phy) - return phy_ethtool_ksettings_set(cpsw->slaves[slave_no].phy, - ecmd); - else - return -EOPNOTSUPP; -} - -static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) -{ - struct cpsw_priv *priv = netdev_priv(ndev); - struct cpsw_common *cpsw = priv->cpsw; - int slave_no = cpsw_slave_index(cpsw, priv); - - wol->supported = 0; - wol->wolopts = 0; - - if (cpsw->slaves[slave_no].phy) - phy_ethtool_get_wol(cpsw->slaves[slave_no].phy, wol); -} - -static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) -{ - struct cpsw_priv *priv = netdev_priv(ndev); - struct cpsw_common *cpsw = priv->cpsw; - int slave_no = cpsw_slave_index(cpsw, priv); - - if (cpsw->slaves[slave_no].phy) - return phy_ethtool_set_wol(cpsw->slaves[slave_no].phy, wol); - else - return -EOPNOTSUPP; -} - -static void cpsw_get_pauseparam(struct net_device *ndev, - struct ethtool_pauseparam *pause) -{ - struct cpsw_priv *priv = netdev_priv(ndev); - - pause->autoneg = AUTONEG_DISABLE; - pause->rx_pause = priv->rx_pause ? true : false; - pause->tx_pause = priv->tx_pause ? true : false; -} - static int cpsw_set_pauseparam(struct net_device *ndev, struct ethtool_pauseparam *pause) { @@ -2403,316 +2032,10 @@ static int cpsw_set_pauseparam(struct net_device *ndev, return 0; } -static int cpsw_ethtool_op_begin(struct net_device *ndev) -{ - struct cpsw_priv *priv = netdev_priv(ndev); - struct cpsw_common *cpsw = priv->cpsw; - int ret; - - ret = pm_runtime_get_sync(cpsw->dev); - if (ret < 0) { - cpsw_err(priv, drv, "ethtool begin failed %d\n", ret); - pm_runtime_put_noidle(cpsw->dev); - } - - return ret; -} - -static void cpsw_ethtool_op_complete(struct net_device *ndev) -{ - struct cpsw_priv *priv = netdev_priv(ndev); - int ret; - - ret = pm_runtime_put(priv->cpsw->dev); - if (ret < 0) - cpsw_err(priv, drv, "ethtool complete failed %d\n", ret); -} - -static void cpsw_get_channels(struct net_device *ndev, - struct ethtool_channels *ch) -{ - struct cpsw_common *cpsw = ndev_to_cpsw(ndev); - - ch->max_rx = cpsw->quirk_irq ? 1 : CPSW_MAX_QUEUES; - ch->max_tx = cpsw->quirk_irq ? 1 : CPSW_MAX_QUEUES; - ch->max_combined = 0; - ch->max_other = 0; - ch->other_count = 0; - ch->rx_count = cpsw->rx_ch_num; - ch->tx_count = cpsw->tx_ch_num; - ch->combined_count = 0; -} - -static int cpsw_check_ch_settings(struct cpsw_common *cpsw, - struct ethtool_channels *ch) -{ - if (cpsw->quirk_irq) { - dev_err(cpsw->dev, "Maximum one tx/rx queue is allowed"); - return -EOPNOTSUPP; - } - - if (ch->combined_count) - return -EINVAL; - - /* verify we have at least one channel in each direction */ - if (!ch->rx_count || !ch->tx_count) - return -EINVAL; - - if (ch->rx_count > cpsw->data.channels || - ch->tx_count > cpsw->data.channels) - return -EINVAL; - - return 0; -} - -static int cpsw_update_channels_res(struct cpsw_priv *priv, int ch_num, int rx) -{ - struct cpsw_common *cpsw = priv->cpsw; - void (*handler)(void *, int, int); - struct netdev_queue *queue; - struct cpsw_vector *vec; - int ret, *ch, vch; - - if (rx) { - ch = &cpsw->rx_ch_num; - vec = cpsw->rxv; - handler = cpsw_rx_handler; - } else { - ch = &cpsw->tx_ch_num; - vec = cpsw->txv; - handler = cpsw_tx_handler; - } - - while (*ch < ch_num) { - vch = rx ? *ch : 7 - *ch; - vec[*ch].ch = cpdma_chan_create(cpsw->dma, vch, handler, rx); - queue = netdev_get_tx_queue(priv->ndev, *ch); - queue->tx_maxrate = 0; - - if (IS_ERR(vec[*ch].ch)) - return PTR_ERR(vec[*ch].ch); - - if (!vec[*ch].ch) - return -EINVAL; - - cpsw_info(priv, ifup, "created new %d %s channel\n", *ch, - (rx ? "rx" : "tx")); - (*ch)++; - } - - while (*ch > ch_num) { - (*ch)--; - - ret = cpdma_chan_destroy(vec[*ch].ch); - if (ret) - return ret; - - cpsw_info(priv, ifup, "destroyed %d %s channel\n", *ch, - (rx ? "rx" : "tx")); - } - - return 0; -} - -static int cpsw_update_channels(struct cpsw_priv *priv, - struct ethtool_channels *ch) -{ - int ret; - - ret = cpsw_update_channels_res(priv, ch->rx_count, 1); - if (ret) - return ret; - - ret = cpsw_update_channels_res(priv, ch->tx_count, 0); - if (ret) - return ret; - - return 0; -} - -static void cpsw_suspend_data_pass(struct net_device *ndev) -{ - struct cpsw_common *cpsw = ndev_to_cpsw(ndev); - struct cpsw_slave *slave; - int i; - - /* Disable NAPI scheduling */ - cpsw_intr_disable(cpsw); - - /* Stop all transmit queues for every network device. - * Disable re-using rx descriptors with dormant_on. - */ - for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) { - if (!(slave->ndev && netif_running(slave->ndev))) - continue; - - netif_tx_stop_all_queues(slave->ndev); - netif_dormant_on(slave->ndev); - } - - /* Handle rest of tx packets and stop cpdma channels */ - cpdma_ctlr_stop(cpsw->dma); -} - -static int cpsw_resume_data_pass(struct net_device *ndev) -{ - struct cpsw_priv *priv = netdev_priv(ndev); - struct cpsw_common *cpsw = priv->cpsw; - struct cpsw_slave *slave; - int i, ret; - - /* Allow rx packets handling */ - for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) - if (slave->ndev && netif_running(slave->ndev)) - netif_dormant_off(slave->ndev); - - /* After this receive is started */ - if (cpsw->usage_count) { - ret = cpsw_fill_rx_channels(priv); - if (ret) - return ret; - - cpdma_ctlr_start(cpsw->dma); - cpsw_intr_enable(cpsw); - } - - /* Resume transmit for every affected interface */ - for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) - if (slave->ndev && netif_running(slave->ndev)) - netif_tx_start_all_queues(slave->ndev); - - return 0; -} - static int cpsw_set_channels(struct net_device *ndev, struct ethtool_channels *chs) { - struct cpsw_priv *priv = netdev_priv(ndev); - struct cpsw_common *cpsw = priv->cpsw; - struct cpsw_slave *slave; - int i, ret; - - ret = cpsw_check_ch_settings(cpsw, chs); - if (ret < 0) - return ret; - - cpsw_suspend_data_pass(ndev); - ret = cpsw_update_channels(priv, chs); - if (ret) - goto err; - - for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) { - if (!(slave->ndev && netif_running(slave->ndev))) - continue; - - /* Inform stack about new count of queues */ - ret = netif_set_real_num_tx_queues(slave->ndev, - cpsw->tx_ch_num); - if (ret) { - dev_err(priv->dev, "cannot set real number of tx queues\n"); - goto err; - } - - ret = netif_set_real_num_rx_queues(slave->ndev, - cpsw->rx_ch_num); - if (ret) { - dev_err(priv->dev, "cannot set real number of rx queues\n"); - goto err; - } - } - - if (cpsw->usage_count) - cpsw_split_res(cpsw); - - ret = cpsw_resume_data_pass(ndev); - if (!ret) - return 0; -err: - dev_err(priv->dev, "cannot update channels number, closing device\n"); - dev_close(ndev); - return ret; -} - -static int cpsw_get_eee(struct net_device *ndev, struct ethtool_eee *edata) -{ - struct cpsw_priv *priv = netdev_priv(ndev); - struct cpsw_common *cpsw = priv->cpsw; - int slave_no = cpsw_slave_index(cpsw, priv); - - if (cpsw->slaves[slave_no].phy) - return phy_ethtool_get_eee(cpsw->slaves[slave_no].phy, edata); - else - return -EOPNOTSUPP; -} - -static int cpsw_set_eee(struct net_device *ndev, struct ethtool_eee *edata) -{ - struct cpsw_priv *priv = netdev_priv(ndev); - struct cpsw_common *cpsw = priv->cpsw; - int slave_no = cpsw_slave_index(cpsw, priv); - - if (cpsw->slaves[slave_no].phy) - return phy_ethtool_set_eee(cpsw->slaves[slave_no].phy, edata); - else - return -EOPNOTSUPP; -} - -static int cpsw_nway_reset(struct net_device *ndev) -{ - struct cpsw_priv *priv = netdev_priv(ndev); - struct cpsw_common *cpsw = priv->cpsw; - int slave_no = cpsw_slave_index(cpsw, priv); - - if (cpsw->slaves[slave_no].phy) - return genphy_restart_aneg(cpsw->slaves[slave_no].phy); - else - return -EOPNOTSUPP; -} - -static void cpsw_get_ringparam(struct net_device *ndev, - struct ethtool_ringparam *ering) -{ - struct cpsw_priv *priv = netdev_priv(ndev); - struct cpsw_common *cpsw = priv->cpsw; - - /* not supported */ - ering->tx_max_pending = 0; - ering->tx_pending = cpdma_get_num_tx_descs(cpsw->dma); - ering->rx_max_pending = descs_pool_size - CPSW_MAX_QUEUES; - ering->rx_pending = cpdma_get_num_rx_descs(cpsw->dma); -} - -static int cpsw_set_ringparam(struct net_device *ndev, - struct ethtool_ringparam *ering) -{ - struct cpsw_priv *priv = netdev_priv(ndev); - struct cpsw_common *cpsw = priv->cpsw; - int ret; - - /* ignore ering->tx_pending - only rx_pending adjustment is supported */ - - if (ering->rx_mini_pending || ering->rx_jumbo_pending || - ering->rx_pending < CPSW_MAX_QUEUES || - ering->rx_pending > (descs_pool_size - CPSW_MAX_QUEUES)) - return -EINVAL; - - if (ering->rx_pending == cpdma_get_num_rx_descs(cpsw->dma)) - return 0; - - cpsw_suspend_data_pass(ndev); - - cpdma_set_num_rx_descs(cpsw->dma, ering->rx_pending); - - if (cpsw->usage_count) - cpdma_chan_split_pool(cpsw->dma); - - ret = cpsw_resume_data_pass(ndev); - if (!ret) - return 0; - - dev_err(&ndev->dev, "cannot set ring params, closing device\n"); - dev_close(ndev); - return ret; + return cpsw_set_channels_common(ndev, chs, cpsw_rx_handler); } static const struct ethtool_ops cpsw_ethtool_ops = { @@ -3093,7 +2416,7 @@ static int cpsw_probe(struct platform_device *pdev) } cpsw->rx_packet_max = max(rx_packet_max, CPSW_MAX_PACKET_SIZE); - + cpsw->descs_pool_size = descs_pool_size; ret = cpsw_init_common(cpsw, ss_regs, ale_ageout, (u32 __force)ss_res->start + CPSW2_BD_OFFSET, diff --git a/drivers/net/ethernet/ti/cpsw_ethtool.c b/drivers/net/ethernet/ti/cpsw_ethtool.c new file mode 100644 index 000000000000..a4a7ec0d2531 --- /dev/null +++ b/drivers/net/ethernet/ti/cpsw_ethtool.c @@ -0,0 +1,719 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Texas Instruments Ethernet Switch Driver ethtool intf + * + * Copyright (C) 2019 Texas Instruments + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "cpsw.h" +#include "cpts.h" +#include "cpsw_ale.h" +#include "cpsw_priv.h" +#include "davinci_cpdma.h" + +struct cpsw_hw_stats { + u32 rxgoodframes; + u32 rxbroadcastframes; + u32 rxmulticastframes; + u32 rxpauseframes; + u32 rxcrcerrors; + u32 rxaligncodeerrors; + u32 rxoversizedframes; + u32 rxjabberframes; + u32 rxundersizedframes; + u32 rxfragments; + u32 __pad_0[2]; + u32 rxoctets; + u32 txgoodframes; + u32 txbroadcastframes; + u32 txmulticastframes; + u32 txpauseframes; + u32 txdeferredframes; + u32 txcollisionframes; + u32 txsinglecollframes; + u32 txmultcollframes; + u32 txexcessivecollisions; + u32 txlatecollisions; + u32 txunderrun; + u32 txcarriersenseerrors; + u32 txoctets; + u32 octetframes64; + u32 octetframes65t127; + u32 octetframes128t255; + u32 octetframes256t511; + u32 octetframes512t1023; + u32 octetframes1024tup; + u32 netoctets; + u32 rxsofoverruns; + u32 rxmofoverruns; + u32 rxdmaoverruns; +}; + +struct cpsw_stats { + char stat_string[ETH_GSTRING_LEN]; + int type; + int sizeof_stat; + int stat_offset; +}; + +enum { + CPSW_STATS, + CPDMA_RX_STATS, + CPDMA_TX_STATS, +}; + +#define CPSW_STAT(m) CPSW_STATS, \ + FIELD_SIZEOF(struct cpsw_hw_stats, m), \ + offsetof(struct cpsw_hw_stats, m) +#define CPDMA_RX_STAT(m) CPDMA_RX_STATS, \ + FIELD_SIZEOF(struct cpdma_chan_stats, m), \ + offsetof(struct cpdma_chan_stats, m) +#define CPDMA_TX_STAT(m) CPDMA_TX_STATS, \ + FIELD_SIZEOF(struct cpdma_chan_stats, m), \ + offsetof(struct cpdma_chan_stats, m) + +static const struct cpsw_stats cpsw_gstrings_stats[] = { + { "Good Rx Frames", CPSW_STAT(rxgoodframes) }, + { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) }, + { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) }, + { "Pause Rx Frames", CPSW_STAT(rxpauseframes) }, + { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) }, + { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) }, + { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) }, + { "Rx Jabbers", CPSW_STAT(rxjabberframes) }, + { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) }, + { "Rx Fragments", CPSW_STAT(rxfragments) }, + { "Rx Octets", CPSW_STAT(rxoctets) }, + { "Good Tx Frames", CPSW_STAT(txgoodframes) }, + { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) }, + { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) }, + { "Pause Tx Frames", CPSW_STAT(txpauseframes) }, + { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) }, + { "Collisions", CPSW_STAT(txcollisionframes) }, + { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) }, + { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) }, + { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) }, + { "Late Collisions", CPSW_STAT(txlatecollisions) }, + { "Tx Underrun", CPSW_STAT(txunderrun) }, + { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) }, + { "Tx Octets", CPSW_STAT(txoctets) }, + { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) }, + { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) }, + { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) }, + { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) }, + { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) }, + { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) }, + { "Net Octets", CPSW_STAT(netoctets) }, + { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) }, + { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) }, + { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) }, +}; + +static const struct cpsw_stats cpsw_gstrings_ch_stats[] = { + { "head_enqueue", CPDMA_RX_STAT(head_enqueue) }, + { "tail_enqueue", CPDMA_RX_STAT(tail_enqueue) }, + { "pad_enqueue", CPDMA_RX_STAT(pad_enqueue) }, + { "misqueued", CPDMA_RX_STAT(misqueued) }, + { "desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) }, + { "pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) }, + { "runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) }, + { "runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) }, + { "empty_dequeue", CPDMA_RX_STAT(empty_dequeue) }, + { "busy_dequeue", CPDMA_RX_STAT(busy_dequeue) }, + { "good_dequeue", CPDMA_RX_STAT(good_dequeue) }, + { "requeue", CPDMA_RX_STAT(requeue) }, + { "teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) }, +}; + +#define CPSW_STATS_COMMON_LEN ARRAY_SIZE(cpsw_gstrings_stats) +#define CPSW_STATS_CH_LEN ARRAY_SIZE(cpsw_gstrings_ch_stats) + +u32 cpsw_get_msglevel(struct net_device *ndev) +{ + struct cpsw_priv *priv = netdev_priv(ndev); + + return priv->msg_enable; +} + +void cpsw_set_msglevel(struct net_device *ndev, u32 value) +{ + struct cpsw_priv *priv = netdev_priv(ndev); + + priv->msg_enable = value; +} + +int cpsw_get_coalesce(struct net_device *ndev, struct ethtool_coalesce *coal) +{ + struct cpsw_common *cpsw = ndev_to_cpsw(ndev); + + coal->rx_coalesce_usecs = cpsw->coal_intvl; + return 0; +} + +int cpsw_set_coalesce(struct net_device *ndev, struct ethtool_coalesce *coal) +{ + struct cpsw_priv *priv = netdev_priv(ndev); + u32 int_ctrl; + u32 num_interrupts = 0; + u32 prescale = 0; + u32 addnl_dvdr = 1; + u32 coal_intvl = 0; + struct cpsw_common *cpsw = priv->cpsw; + + coal_intvl = coal->rx_coalesce_usecs; + + int_ctrl = readl(&cpsw->wr_regs->int_control); + prescale = cpsw->bus_freq_mhz * 4; + + if (!coal->rx_coalesce_usecs) { + int_ctrl &= ~(CPSW_INTPRESCALE_MASK | CPSW_INTPACEEN); + goto update_return; + } + + if (coal_intvl < CPSW_CMINTMIN_INTVL) + coal_intvl = CPSW_CMINTMIN_INTVL; + + if (coal_intvl > CPSW_CMINTMAX_INTVL) { + /* Interrupt pacer works with 4us Pulse, we can + * throttle further by dilating the 4us pulse. + */ + addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale; + + if (addnl_dvdr > 1) { + prescale *= addnl_dvdr; + if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr)) + coal_intvl = (CPSW_CMINTMAX_INTVL + * addnl_dvdr); + } else { + addnl_dvdr = 1; + coal_intvl = CPSW_CMINTMAX_INTVL; + } + } + + num_interrupts = (1000 * addnl_dvdr) / coal_intvl; + writel(num_interrupts, &cpsw->wr_regs->rx_imax); + writel(num_interrupts, &cpsw->wr_regs->tx_imax); + + int_ctrl |= CPSW_INTPACEEN; + int_ctrl &= (~CPSW_INTPRESCALE_MASK); + int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK); + +update_return: + writel(int_ctrl, &cpsw->wr_regs->int_control); + + cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl); + cpsw->coal_intvl = coal_intvl; + + return 0; +} + +int cpsw_get_sset_count(struct net_device *ndev, int sset) +{ + struct cpsw_common *cpsw = ndev_to_cpsw(ndev); + + switch (sset) { + case ETH_SS_STATS: + return (CPSW_STATS_COMMON_LEN + + (cpsw->rx_ch_num + cpsw->tx_ch_num) * + CPSW_STATS_CH_LEN); + default: + return -EOPNOTSUPP; + } +} + +static void cpsw_add_ch_strings(u8 **p, int ch_num, int rx_dir) +{ + int ch_stats_len; + int line; + int i; + + ch_stats_len = CPSW_STATS_CH_LEN * ch_num; + for (i = 0; i < ch_stats_len; i++) { + line = i % CPSW_STATS_CH_LEN; + snprintf(*p, ETH_GSTRING_LEN, + "%s DMA chan %ld: %s", rx_dir ? "Rx" : "Tx", + (long)(i / CPSW_STATS_CH_LEN), + cpsw_gstrings_ch_stats[line].stat_string); + *p += ETH_GSTRING_LEN; + } +} + +void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data) +{ + struct cpsw_common *cpsw = ndev_to_cpsw(ndev); + u8 *p = data; + int i; + + switch (stringset) { + case ETH_SS_STATS: + for (i = 0; i < CPSW_STATS_COMMON_LEN; i++) { + memcpy(p, cpsw_gstrings_stats[i].stat_string, + ETH_GSTRING_LEN); + p += ETH_GSTRING_LEN; + } + + cpsw_add_ch_strings(&p, cpsw->rx_ch_num, 1); + cpsw_add_ch_strings(&p, cpsw->tx_ch_num, 0); + break; + } +} + +void cpsw_get_ethtool_stats(struct net_device *ndev, + struct ethtool_stats *stats, u64 *data) +{ + u8 *p; + struct cpsw_common *cpsw = ndev_to_cpsw(ndev); + struct cpdma_chan_stats ch_stats; + int i, l, ch; + + /* Collect Davinci CPDMA stats for Rx and Tx Channel */ + for (l = 0; l < CPSW_STATS_COMMON_LEN; l++) + data[l] = readl(cpsw->hw_stats + + cpsw_gstrings_stats[l].stat_offset); + + for (ch = 0; ch < cpsw->rx_ch_num; ch++) { + cpdma_chan_get_stats(cpsw->rxv[ch].ch, &ch_stats); + for (i = 0; i < CPSW_STATS_CH_LEN; i++, l++) { + p = (u8 *)&ch_stats + + cpsw_gstrings_ch_stats[i].stat_offset; + data[l] = *(u32 *)p; + } + } + + for (ch = 0; ch < cpsw->tx_ch_num; ch++) { + cpdma_chan_get_stats(cpsw->txv[ch].ch, &ch_stats); + for (i = 0; i < CPSW_STATS_CH_LEN; i++, l++) { + p = (u8 *)&ch_stats + + cpsw_gstrings_ch_stats[i].stat_offset; + data[l] = *(u32 *)p; + } + } +} + +void cpsw_get_pauseparam(struct net_device *ndev, + struct ethtool_pauseparam *pause) +{ + struct cpsw_priv *priv = netdev_priv(ndev); + + pause->autoneg = AUTONEG_DISABLE; + pause->rx_pause = priv->rx_pause ? true : false; + pause->tx_pause = priv->tx_pause ? true : false; +} + +void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) +{ + struct cpsw_priv *priv = netdev_priv(ndev); + struct cpsw_common *cpsw = priv->cpsw; + int slave_no = cpsw_slave_index(cpsw, priv); + + wol->supported = 0; + wol->wolopts = 0; + + if (cpsw->slaves[slave_no].phy) + phy_ethtool_get_wol(cpsw->slaves[slave_no].phy, wol); +} + +int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) +{ + struct cpsw_priv *priv = netdev_priv(ndev); + struct cpsw_common *cpsw = priv->cpsw; + int slave_no = cpsw_slave_index(cpsw, priv); + + if (cpsw->slaves[slave_no].phy) + return phy_ethtool_set_wol(cpsw->slaves[slave_no].phy, wol); + else + return -EOPNOTSUPP; +} + +int cpsw_get_regs_len(struct net_device *ndev) +{ + struct cpsw_common *cpsw = ndev_to_cpsw(ndev); + + return cpsw->data.ale_entries * ALE_ENTRY_WORDS * sizeof(u32); +} + +void cpsw_get_regs(struct net_device *ndev, struct ethtool_regs *regs, void *p) +{ + u32 *reg = p; + struct cpsw_common *cpsw = ndev_to_cpsw(ndev); + + /* update CPSW IP version */ + regs->version = cpsw->version; + + cpsw_ale_dump(cpsw->ale, reg); +} + +int cpsw_ethtool_op_begin(struct net_device *ndev) +{ + struct cpsw_priv *priv = netdev_priv(ndev); + struct cpsw_common *cpsw = priv->cpsw; + int ret; + + ret = pm_runtime_get_sync(cpsw->dev); + if (ret < 0) { + cpsw_err(priv, drv, "ethtool begin failed %d\n", ret); + pm_runtime_put_noidle(cpsw->dev); + } + + return ret; +} + +void cpsw_ethtool_op_complete(struct net_device *ndev) +{ + struct cpsw_priv *priv = netdev_priv(ndev); + int ret; + + ret = pm_runtime_put(priv->cpsw->dev); + if (ret < 0) + cpsw_err(priv, drv, "ethtool complete failed %d\n", ret); +} + +void cpsw_get_channels(struct net_device *ndev, struct ethtool_channels *ch) +{ + struct cpsw_common *cpsw = ndev_to_cpsw(ndev); + + ch->max_rx = cpsw->quirk_irq ? 1 : CPSW_MAX_QUEUES; + ch->max_tx = cpsw->quirk_irq ? 1 : CPSW_MAX_QUEUES; + ch->max_combined = 0; + ch->max_other = 0; + ch->other_count = 0; + ch->rx_count = cpsw->rx_ch_num; + ch->tx_count = cpsw->tx_ch_num; + ch->combined_count = 0; +} + +int cpsw_get_link_ksettings(struct net_device *ndev, + struct ethtool_link_ksettings *ecmd) +{ + struct cpsw_priv *priv = netdev_priv(ndev); + struct cpsw_common *cpsw = priv->cpsw; + int slave_no = cpsw_slave_index(cpsw, priv); + + if (!cpsw->slaves[slave_no].phy) + return -EOPNOTSUPP; + + phy_ethtool_ksettings_get(cpsw->slaves[slave_no].phy, ecmd); + return 0; +} + +int cpsw_set_link_ksettings(struct net_device *ndev, + const struct ethtool_link_ksettings *ecmd) +{ + struct cpsw_priv *priv = netdev_priv(ndev); + struct cpsw_common *cpsw = priv->cpsw; + int slave_no = cpsw_slave_index(cpsw, priv); + + if (!cpsw->slaves[slave_no].phy) + return -EOPNOTSUPP; + + return phy_ethtool_ksettings_set(cpsw->slaves[slave_no].phy, ecmd); +} + +int cpsw_get_eee(struct net_device *ndev, struct ethtool_eee *edata) +{ + struct cpsw_priv *priv = netdev_priv(ndev); + struct cpsw_common *cpsw = priv->cpsw; + int slave_no = cpsw_slave_index(cpsw, priv); + + if (cpsw->slaves[slave_no].phy) + return phy_ethtool_get_eee(cpsw->slaves[slave_no].phy, edata); + else + return -EOPNOTSUPP; +} + +int cpsw_set_eee(struct net_device *ndev, struct ethtool_eee *edata) +{ + struct cpsw_priv *priv = netdev_priv(ndev); + struct cpsw_common *cpsw = priv->cpsw; + int slave_no = cpsw_slave_index(cpsw, priv); + + if (cpsw->slaves[slave_no].phy) + return phy_ethtool_set_eee(cpsw->slaves[slave_no].phy, edata); + else + return -EOPNOTSUPP; +} + +int cpsw_nway_reset(struct net_device *ndev) +{ + struct cpsw_priv *priv = netdev_priv(ndev); + struct cpsw_common *cpsw = priv->cpsw; + int slave_no = cpsw_slave_index(cpsw, priv); + + if (cpsw->slaves[slave_no].phy) + return genphy_restart_aneg(cpsw->slaves[slave_no].phy); + else + return -EOPNOTSUPP; +} + +static void cpsw_suspend_data_pass(struct net_device *ndev) +{ + struct cpsw_common *cpsw = ndev_to_cpsw(ndev); + struct cpsw_slave *slave; + int i; + + /* Disable NAPI scheduling */ + cpsw_intr_disable(cpsw); + + /* Stop all transmit queues for every network device. + * Disable re-using rx descriptors with dormant_on. + */ + for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) { + if (!(slave->ndev && netif_running(slave->ndev))) + continue; + + netif_tx_stop_all_queues(slave->ndev); + netif_dormant_on(slave->ndev); + } + + /* Handle rest of tx packets and stop cpdma channels */ + cpdma_ctlr_stop(cpsw->dma); +} + +static int cpsw_resume_data_pass(struct net_device *ndev) +{ + struct cpsw_priv *priv = netdev_priv(ndev); + struct cpsw_common *cpsw = priv->cpsw; + struct cpsw_slave *slave; + int i, ret; + + /* Allow rx packets handling */ + for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) + if (slave->ndev && netif_running(slave->ndev)) + netif_dormant_off(slave->ndev); + + /* After this receive is started */ + if (cpsw->usage_count) { + ret = cpsw_fill_rx_channels(priv); + if (ret) + return ret; + + cpdma_ctlr_start(cpsw->dma); + cpsw_intr_enable(cpsw); + } + + /* Resume transmit for every affected interface */ + for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) + if (slave->ndev && netif_running(slave->ndev)) + netif_tx_start_all_queues(slave->ndev); + + return 0; +} + +static int cpsw_check_ch_settings(struct cpsw_common *cpsw, + struct ethtool_channels *ch) +{ + if (cpsw->quirk_irq) { + dev_err(cpsw->dev, "Maximum one tx/rx queue is allowed"); + return -EOPNOTSUPP; + } + + if (ch->combined_count) + return -EINVAL; + + /* verify we have at least one channel in each direction */ + if (!ch->rx_count || !ch->tx_count) + return -EINVAL; + + if (ch->rx_count > cpsw->data.channels || + ch->tx_count > cpsw->data.channels) + return -EINVAL; + + return 0; +} + +static int cpsw_update_channels_res(struct cpsw_priv *priv, int ch_num, int rx, + cpdma_handler_fn rx_handler) +{ + struct cpsw_common *cpsw = priv->cpsw; + void (*handler)(void *, int, int); + struct netdev_queue *queue; + struct cpsw_vector *vec; + int ret, *ch, vch; + + if (rx) { + ch = &cpsw->rx_ch_num; + vec = cpsw->rxv; + handler = rx_handler; + } else { + ch = &cpsw->tx_ch_num; + vec = cpsw->txv; + handler = cpsw_tx_handler; + } + + while (*ch < ch_num) { + vch = rx ? *ch : 7 - *ch; + vec[*ch].ch = cpdma_chan_create(cpsw->dma, vch, handler, rx); + queue = netdev_get_tx_queue(priv->ndev, *ch); + queue->tx_maxrate = 0; + + if (IS_ERR(vec[*ch].ch)) + return PTR_ERR(vec[*ch].ch); + + if (!vec[*ch].ch) + return -EINVAL; + + cpsw_info(priv, ifup, "created new %d %s channel\n", *ch, + (rx ? "rx" : "tx")); + (*ch)++; + } + + while (*ch > ch_num) { + (*ch)--; + + ret = cpdma_chan_destroy(vec[*ch].ch); + if (ret) + return ret; + + cpsw_info(priv, ifup, "destroyed %d %s channel\n", *ch, + (rx ? "rx" : "tx")); + } + + return 0; +} + +int cpsw_set_channels_common(struct net_device *ndev, + struct ethtool_channels *chs, + cpdma_handler_fn rx_handler) +{ + struct cpsw_priv *priv = netdev_priv(ndev); + struct cpsw_common *cpsw = priv->cpsw; + struct cpsw_slave *slave; + int i, ret; + + ret = cpsw_check_ch_settings(cpsw, chs); + if (ret < 0) + return ret; + + cpsw_suspend_data_pass(ndev); + + ret = cpsw_update_channels_res(priv, chs->rx_count, 1, rx_handler); + if (ret) + goto err; + + ret = cpsw_update_channels_res(priv, chs->tx_count, 0, rx_handler); + if (ret) + goto err; + + for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) { + if (!(slave->ndev && netif_running(slave->ndev))) + continue; + + /* Inform stack about new count of queues */ + ret = netif_set_real_num_tx_queues(slave->ndev, + cpsw->tx_ch_num); + if (ret) { + dev_err(priv->dev, "cannot set real number of tx queues\n"); + goto err; + } + + ret = netif_set_real_num_rx_queues(slave->ndev, + cpsw->rx_ch_num); + if (ret) { + dev_err(priv->dev, "cannot set real number of rx queues\n"); + goto err; + } + } + + if (cpsw->usage_count) + cpsw_split_res(cpsw); + + ret = cpsw_resume_data_pass(ndev); + if (!ret) + return 0; +err: + dev_err(priv->dev, "cannot update channels number, closing device\n"); + dev_close(ndev); + return ret; +} + +void cpsw_get_ringparam(struct net_device *ndev, + struct ethtool_ringparam *ering) +{ + struct cpsw_priv *priv = netdev_priv(ndev); + struct cpsw_common *cpsw = priv->cpsw; + + /* not supported */ + ering->tx_max_pending = 0; + ering->tx_pending = cpdma_get_num_tx_descs(cpsw->dma); + ering->rx_max_pending = cpsw->descs_pool_size - CPSW_MAX_QUEUES; + ering->rx_pending = cpdma_get_num_rx_descs(cpsw->dma); +} + +int cpsw_set_ringparam(struct net_device *ndev, + struct ethtool_ringparam *ering) +{ + struct cpsw_priv *priv = netdev_priv(ndev); + struct cpsw_common *cpsw = priv->cpsw; + int ret; + + /* ignore ering->tx_pending - only rx_pending adjustment is supported */ + + if (ering->rx_mini_pending || ering->rx_jumbo_pending || + ering->rx_pending < CPSW_MAX_QUEUES || + ering->rx_pending > (cpsw->descs_pool_size - CPSW_MAX_QUEUES)) + return -EINVAL; + + if (ering->rx_pending == cpdma_get_num_rx_descs(cpsw->dma)) + return 0; + + cpsw_suspend_data_pass(ndev); + + cpdma_set_num_rx_descs(cpsw->dma, ering->rx_pending); + + if (cpsw->usage_count) + cpdma_chan_split_pool(cpsw->dma); + + ret = cpsw_resume_data_pass(ndev); + if (!ret) + return 0; + + dev_err(cpsw->dev, "cannot set ring params, closing device\n"); + dev_close(ndev); + return ret; +} + +#if IS_ENABLED(CONFIG_TI_CPTS) +int cpsw_get_ts_info(struct net_device *ndev, struct ethtool_ts_info *info) +{ + struct cpsw_common *cpsw = ndev_to_cpsw(ndev); + + info->so_timestamping = + SOF_TIMESTAMPING_TX_HARDWARE | + SOF_TIMESTAMPING_TX_SOFTWARE | + SOF_TIMESTAMPING_RX_HARDWARE | + SOF_TIMESTAMPING_RX_SOFTWARE | + SOF_TIMESTAMPING_SOFTWARE | + SOF_TIMESTAMPING_RAW_HARDWARE; + info->phc_index = cpsw->cpts->phc_index; + info->tx_types = + (1 << HWTSTAMP_TX_OFF) | + (1 << HWTSTAMP_TX_ON); + info->rx_filters = + (1 << HWTSTAMP_FILTER_NONE) | + (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) | + (1 << HWTSTAMP_FILTER_PTP_V2_EVENT); + return 0; +} +#else +int cpsw_get_ts_info(struct net_device *ndev, struct ethtool_ts_info *info) +{ + info->so_timestamping = + SOF_TIMESTAMPING_TX_SOFTWARE | + SOF_TIMESTAMPING_RX_SOFTWARE | + SOF_TIMESTAMPING_SOFTWARE; + info->phc_index = -1; + info->tx_types = 0; + info->rx_filters = 0; + return 0; +} +#endif diff --git a/drivers/net/ethernet/ti/cpsw_priv.h b/drivers/net/ethernet/ti/cpsw_priv.h index 74622a50af96..c826fb2c78db 100644 --- a/drivers/net/ethernet/ti/cpsw_priv.h +++ b/drivers/net/ethernet/ti/cpsw_priv.h @@ -6,6 +6,8 @@ #ifndef DRIVERS_NET_ETHERNET_TI_CPSW_PRIV_H_ #define DRIVERS_NET_ETHERNET_TI_CPSW_PRIV_H_ +#include "davinci_cpdma.h" + #define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \ NETIF_MSG_DRV | NETIF_MSG_LINK | \ NETIF_MSG_IFUP | NETIF_MSG_INTR | \ @@ -269,44 +271,6 @@ struct cpsw_host_regs { u32 cpdma_rx_chan_map; }; -struct cpsw_hw_stats { - u32 rxgoodframes; - u32 rxbroadcastframes; - u32 rxmulticastframes; - u32 rxpauseframes; - u32 rxcrcerrors; - u32 rxaligncodeerrors; - u32 rxoversizedframes; - u32 rxjabberframes; - u32 rxundersizedframes; - u32 rxfragments; - u32 __pad_0[2]; - u32 rxoctets; - u32 txgoodframes; - u32 txbroadcastframes; - u32 txmulticastframes; - u32 txpauseframes; - u32 txdeferredframes; - u32 txcollisionframes; - u32 txsinglecollframes; - u32 txmultcollframes; - u32 txexcessivecollisions; - u32 txlatecollisions; - u32 txunderrun; - u32 txcarriersenseerrors; - u32 txoctets; - u32 octetframes64; - u32 octetframes65t127; - u32 octetframes128t255; - u32 octetframes256t511; - u32 octetframes512t1023; - u32 octetframes1024tup; - u32 netoctets; - u32 rxsofoverruns; - u32 rxmofoverruns; - u32 rxdmaoverruns; -}; - struct cpsw_slave_data { struct device_node *phy_node; char phy_id[MII_BUS_ID_SIZE]; @@ -368,6 +332,7 @@ struct cpsw_common { u32 coal_intvl; u32 bus_freq_mhz; int rx_packet_max; + int descs_pool_size; struct cpsw_slave *slaves; struct cpdma_ctlr *dma; struct cpsw_vector txv[CPSW_MAX_QUEUES]; @@ -399,9 +364,6 @@ struct cpsw_priv { struct cpsw_common *cpsw; }; -#define CPSW_STATS_COMMON_LEN ARRAY_SIZE(cpsw_gstrings_stats) -#define CPSW_STATS_CH_LEN ARRAY_SIZE(cpsw_gstrings_ch_stats) - #define ndev_to_cpsw(ndev) (((struct cpsw_priv *)netdev_priv(ndev))->cpsw) #define napi_to_cpsw(napi) container_of(napi, struct cpsw_common, napi) #define for_each_slave(priv, func, arg...) \ @@ -436,5 +398,44 @@ struct addr_sync_ctx { int cpsw_init_common(struct cpsw_common *cpsw, void __iomem *ss_regs, int ale_ageout, u32 desc_mem_phys, int descs_pool_size); +void cpsw_split_res(struct cpsw_common *cpsw); +int cpsw_fill_rx_channels(struct cpsw_priv *priv); +void cpsw_intr_enable(struct cpsw_common *cpsw); +void cpsw_intr_disable(struct cpsw_common *cpsw); +void cpsw_tx_handler(void *token, int len, int status); + +/* ethtool */ +u32 cpsw_get_msglevel(struct net_device *ndev); +void cpsw_set_msglevel(struct net_device *ndev, u32 value); +int cpsw_get_coalesce(struct net_device *ndev, struct ethtool_coalesce *coal); +int cpsw_set_coalesce(struct net_device *ndev, struct ethtool_coalesce *coal); +int cpsw_get_sset_count(struct net_device *ndev, int sset); +void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data); +void cpsw_get_ethtool_stats(struct net_device *ndev, + struct ethtool_stats *stats, u64 *data); +void cpsw_get_pauseparam(struct net_device *ndev, + struct ethtool_pauseparam *pause); +void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol); +int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol); +int cpsw_get_regs_len(struct net_device *ndev); +void cpsw_get_regs(struct net_device *ndev, struct ethtool_regs *regs, void *p); +int cpsw_ethtool_op_begin(struct net_device *ndev); +void cpsw_ethtool_op_complete(struct net_device *ndev); +void cpsw_get_channels(struct net_device *ndev, struct ethtool_channels *ch); +int cpsw_get_link_ksettings(struct net_device *ndev, + struct ethtool_link_ksettings *ecmd); +int cpsw_set_link_ksettings(struct net_device *ndev, + const struct ethtool_link_ksettings *ecmd); +int cpsw_get_eee(struct net_device *ndev, struct ethtool_eee *edata); +int cpsw_set_eee(struct net_device *ndev, struct ethtool_eee *edata); +int cpsw_nway_reset(struct net_device *ndev); +void cpsw_get_ringparam(struct net_device *ndev, + struct ethtool_ringparam *ering); +int cpsw_set_ringparam(struct net_device *ndev, + struct ethtool_ringparam *ering); +int cpsw_set_channels_common(struct net_device *ndev, + struct ethtool_channels *chs, + cpdma_handler_fn rx_handler); +int cpsw_get_ts_info(struct net_device *ndev, struct ethtool_ts_info *info); #endif /* DRIVERS_NET_ETHERNET_TI_CPSW_PRIV_H_ */