From patchwork Thu Apr 25 10:20:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 162839 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp1741876jan; Thu, 25 Apr 2019 03:20:27 -0700 (PDT) X-Google-Smtp-Source: APXvYqweOW39CrqHvsdmdYhp/z7RlIVQzfRHdH0AiX0wZZlT9dUzh+JloEmFkefTJUT81AZ1CvpM X-Received: by 2002:aa7:8b83:: with SMTP id r3mr8289449pfd.248.1556187627345; Thu, 25 Apr 2019 03:20:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556187627; cv=none; d=google.com; s=arc-20160816; b=MH5xpcO0rDeavzqFNCa64Io7qs6rUc1ONPgLRR1Wj6YgbraDizGlTU9bJrhfonxzwV lpmffto3QNwSqQF71YginJDG0f7WsSF68JvkycEuIk1g/xCqTwqfc9IyCRUp1G8WPc4D 5UC/iZnGnBSy7foPuICDicUI7YajtuXuwBgkFq0Y9hFeK8VcZPBsFemqcsdzS1xdQ1dZ VdzzJFqCi8mgLPq7EtR3k7+Gju5hYhefyWJtY300+WDO9Yj8RKe9noyzi+MBeCyZ0SIY SzSjhDg00b5XYU4CaQqaHY+QUjYNOrfJaeN2kKqzxoK7ErL+3HrBGcLrNFa6qLJ+N8tV JH3A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=dwxUX4ZrYJxHMDOfE3iUSJEsHb3GI7l9s+2/3rnu8fQ=; b=y/XPSSI7G/itaEmxjWp5zAII7h6g3E9BY5Lqn8oxw5MtkSevg+g8P2Xq1skRVDZ3el W1LRGoZ2Esi2krRCvlWAC6omzEXB3GfJ/Z70wMAOvtIJjEXYjD7RXpF/atUooOsFF5h0 o7vZj3JbAy5Dgf1JMeAEmNWSh/GDwEIVIAyQZvIBIe7RHSHSMBhaWIuu6ZNXjtRyqHU7 WrmShgjHCdhWrngdKGTvx7s6xbNuTN5TLA7EMNUbSQUn6CW5x33cQzqZ8V77SEUOCYC7 03Giv4Xzxa3PlW34evkPgV8o/GkzFuAfhU7tLU2RHsX4KPpGVQY7YMFxXbGU50kTgA55 3JmA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ApAtigqE; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id w3si22229688plp.260.2019.04.25.03.20.27; Thu, 25 Apr 2019 03:20:27 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ApAtigqE; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726811AbfDYKU0 (ORCPT + 5 others); Thu, 25 Apr 2019 06:20:26 -0400 Received: from mail-wr1-f65.google.com ([209.85.221.65]:41481 "EHLO mail-wr1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726328AbfDYKU0 (ORCPT ); Thu, 25 Apr 2019 06:20:26 -0400 Received: by mail-wr1-f65.google.com with SMTP id c12so23341565wrt.8 for ; Thu, 25 Apr 2019 03:20:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dwxUX4ZrYJxHMDOfE3iUSJEsHb3GI7l9s+2/3rnu8fQ=; b=ApAtigqEc5FJzQDBggGDh4RZWVp7mPonV6ELb9WhOv/RfOXH4daHVpOF9Cf7213nmN sYgvlPjFfB077E198Qppx22/8v8oPV+bSNF0UMalrUK7oKg6i1V3V+q7rPJsMiBXMBHg zDaSLtXPnYP/5mhZZY/SUP+iT+iSDFlxpAW8E9RCSCvdIzL/2hSALvFIG9f4i62pq4Fv iL5eVD8SLoEyfm8+BMD6z0h1mOhGIuQb60nRzbihsrCmBSidjP95dt47mel29VtEgcFP TIJDRRtSrGfSh8w2Xq4NGleFDk2RR0h9XvCb9f+3KqFLPbQmPYavmHwlqjhTqUeCxff5 mCcA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dwxUX4ZrYJxHMDOfE3iUSJEsHb3GI7l9s+2/3rnu8fQ=; b=ePfIHV7qWrVEhai7DbiHTttDuzP4coN87LEBkbMz6/SrihVNQkHkKW3hKB70tzk43o 8CRtjuycaSitFnBedX8q0QZEGOaG8hYzg5lHk9Sa8xsSagtLGfJtkeduatmeyRbeNDHj k4gatk8XHG1H6dZznEWbjWA5JMtRWDGfJmZ7orKY+kFOfEO6FQC3oOSlIhmzAlXEAQpI w1+4xlDqGXKSuhDfGqvXUrDV3pJPo6vm867568f0jnxhrJHEET8XfAzVyU2HEnfLSBkI E+aN3Mgyz7velPyjVw7ublReGUHSzPsZHHyabBXzS26XAI8sOwm9YhC2+KSTMuY4z6Dg KGFw== X-Gm-Message-State: APjAAAXVnsPK2iCMh6whrMXiweZKyqmx5KBvRLS3gTfjn0ibRb5+d7rn yzioJ2WKuHbcuCMDZzaWyXelTUok7ReMEw== X-Received: by 2002:a5d:4087:: with SMTP id o7mr26597083wrp.9.1556187624228; Thu, 25 Apr 2019 03:20:24 -0700 (PDT) Received: from sudo.home ([2a01:cb1d:112:6f00:95f:9014:5be9:5288]) by smtp.gmail.com with ESMTPSA id p18sm5611364wrp.38.2019.04.25.03.20.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Apr 2019 03:20:23 -0700 (PDT) From: Ard Biesheuvel To: linux-arm-kernel@lists.infradead.org Cc: linux-gpio@vger.kernel.org, Ard Biesheuvel , Masahisa Kojima , Linus Walleij , Marc Zyngier , Graeme Gregory Subject: [RFC PATCH 1/3] irqchip/exiu: preparatory refactor for ACPI support Date: Thu, 25 Apr 2019 12:20:18 +0200 Message-Id: <20190425102020.21533-2-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190425102020.21533-1-ard.biesheuvel@linaro.org> References: <20190425102020.21533-1-ard.biesheuvel@linaro.org> MIME-Version: 1.0 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org In preparation of exposing the EXIU controller as the irqchip part of the GPIO controller, split the DT init function in a DT specific and a generic part, where the latter will be reused for ACPI support later. Signed-off-by: Ard Biesheuvel --- drivers/irqchip/irq-sni-exiu.c | 77 ++++++++++++-------- 1 file changed, 48 insertions(+), 29 deletions(-) -- 2.20.1 diff --git a/drivers/irqchip/irq-sni-exiu.c b/drivers/irqchip/irq-sni-exiu.c index 1927b2f36ff6..52ce662334d4 100644 --- a/drivers/irqchip/irq-sni-exiu.c +++ b/drivers/irqchip/irq-sni-exiu.c @@ -1,7 +1,7 @@ /* * Driver for Socionext External Interrupt Unit (EXIU) * - * Copyright (c) 2017 Linaro, Ltd. + * Copyright (c) 2017-2019 Linaro, Ltd. * * Based on irq-tegra.c: * Copyright (C) 2011 Google, Inc. @@ -167,35 +167,25 @@ static const struct irq_domain_ops exiu_domain_ops = { .free = irq_domain_free_irqs_common, }; -static int __init exiu_init(struct device_node *node, - struct device_node *parent) +static struct irq_domain *exiu_init(struct irq_domain *parent_domain, + struct fwnode_handle *fwnode, + struct resource *res) { - struct irq_domain *parent_domain, *domain; + struct irq_domain *domain; struct exiu_irq_data *data; int err; - if (!parent) { - pr_err("%pOF: no parent, giving up\n", node); - return -ENODEV; - } - - parent_domain = irq_find_host(parent); - if (!parent_domain) { - pr_err("%pOF: unable to obtain parent domain\n", node); - return -ENXIO; - } - data = kzalloc(sizeof(*data), GFP_KERNEL); if (!data) - return -ENOMEM; + return ERR_PTR(-ENOMEM); - if (of_property_read_u32(node, "socionext,spi-base", &data->spi_base)) { - pr_err("%pOF: failed to parse 'spi-base' property\n", node); + if (fwnode_property_read_u32_array(fwnode, "socionext,spi-base", + &data->spi_base, 1)) { err = -ENODEV; goto out_free; } - data->base = of_iomap(node, 0); + data->base = ioremap(res->start, resource_size(res)); if (!data->base) { err = -ENODEV; goto out_free; @@ -205,23 +195,52 @@ static int __init exiu_init(struct device_node *node, writel_relaxed(0xFFFFFFFF, data->base + EIREQCLR); writel_relaxed(0xFFFFFFFF, data->base + EIMASK); - domain = irq_domain_add_hierarchy(parent_domain, 0, NUM_IRQS, node, - &exiu_domain_ops, data); + domain = irq_domain_create_hierarchy(parent_domain, 0, NUM_IRQS, + fwnode, &exiu_domain_ops, data); if (!domain) { - pr_err("%pOF: failed to allocate domain\n", node); err = -ENOMEM; goto out_unmap; } + return domain; +out_unmap: + iounmap(data->base); +out_free: + kfree(data); + return ERR_PTR(err); +} + +static int __init exiu_dt_init(struct device_node *node, + struct device_node *parent) +{ + struct irq_domain *parent_domain, *domain; + struct resource res; + + if (!parent) { + pr_err("%pOF: no parent, giving up\n", node); + return -ENODEV; + } + + parent_domain = irq_find_host(parent); + if (!parent_domain) { + pr_err("%pOF: unable to obtain parent domain\n", node); + return -ENXIO; + } + + if (of_address_to_resource(node, 0, &res)) { + pr_err("%pOF: failed to parse memory resource\n", node); + return -ENXIO; + } + + domain = exiu_init(parent_domain, of_node_to_fwnode(node), &res); + if (IS_ERR(domain)) { + pr_err("%pOF: failed to create IRQ domain (%ld)\n", node, + PTR_ERR(domain)); + return PTR_ERR(domain); + } pr_info("%pOF: %d interrupts forwarded to %pOF\n", node, NUM_IRQS, parent); return 0; - -out_unmap: - iounmap(data->base); -out_free: - kfree(data); - return err; } -IRQCHIP_DECLARE(exiu, "socionext,synquacer-exiu", exiu_init); +IRQCHIP_DECLARE(exiu, "socionext,synquacer-exiu", exiu_dt_init); From patchwork Thu Apr 25 10:20:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 162840 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp1741914jan; Thu, 25 Apr 2019 03:20:28 -0700 (PDT) X-Google-Smtp-Source: APXvYqynVOvDkCgJt4myq55ihLgziVwZU1Bf2ZCIaIBEQovpE5Ngv45qL0ozl2B2LtF45ZXSXjgI X-Received: by 2002:a63:7141:: with SMTP id b1mr36077710pgn.331.1556187628913; Thu, 25 Apr 2019 03:20:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556187628; cv=none; d=google.com; s=arc-20160816; b=PdJbJG/m23zvtyibKIlG2cWbx7IF0vXpm0tumUmPzGCUQYoJVVBU1ISqZkHrrEAY4d SoALLVwzDPBK6WzdXkt8fsrCQDqC2FV5VbubPD736njsW3CfSedq3Bm1I/TALs1p5yyW cF2AVR7TY/4bsaj8894tRjT3IqaJTyI5oZiMkodqZNF8tgwnz/43I23Tr1SjjK/NLzkk TpiMJf8d+NaqeCzlg/Nwv5dp69gc0B5JBPNkAuKvKtIiq7B8DfInqoxXaz8BVmQZ4I7d 0Bp+JWtNpF3OfrtZCJ//hQbIwh7ZDJRWU1av551FynyQ44vAByEuvMaIFUi85frvvBEa kjPA== ARC-Message-Signature: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id w3si22229688plp.260.2019.04.25.03.20.28; Thu, 25 Apr 2019 03:20:28 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=rSPNLktu; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726855AbfDYKU2 (ORCPT + 5 others); Thu, 25 Apr 2019 06:20:28 -0400 Received: from mail-wr1-f65.google.com ([209.85.221.65]:35946 "EHLO mail-wr1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726328AbfDYKU2 (ORCPT ); Thu, 25 Apr 2019 06:20:28 -0400 Received: by mail-wr1-f65.google.com with SMTP id b1so18183698wru.3 for ; Thu, 25 Apr 2019 03:20:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/iI7nJ73SLpzt1a6DM6iMbKuntjQ5I6wTyzYnyQXX5c=; b=rSPNLktuJUWLr5ogZiBx00ruj9atfIW58tOa2byzuHAiY5SeG8rphCoi0i4uOG6UFP 694PwquuI9UCQRjzomAS4j6fbICBc9rskc8sdbG4NpXke8v3opzQfOu85VVebTyAOxz9 kPHlH+l6jYaBlBA0YTEyjvv3ya1RlvVxTPXapT8BKbseqbG2oiglJIGy87ZT2qhDr0M/ XF61Uz6d6rl13ObhK4cgrCz7ttjNFA+4TvFIBy34teVW0Vl/oL5QmjgBS/Co5aJXz42S Ysv60Ad2wxfB9v40d4LvoUMKvHvCqBvH6XJI/Hc53N8IEXo+0Po2P8VGfjmCKinZp/0K wUBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/iI7nJ73SLpzt1a6DM6iMbKuntjQ5I6wTyzYnyQXX5c=; b=qTG3cQUN9G3KeYg18+CKGp0LGNPa6wFizuge2QT3oupCO8V4vyjKgomWGa9MEIKvu/ HTUusN+0WDidkm1me5/bCKQ/OxAzpXLQtn9QbOai6rDHj7yFmdqjyUfZZGEQE65WKwRp /4QauRJnh039KJhmISmCcNW2/C/8xy0Uxo1sUg4o5pEl9A1ItBJrMg5MfaBmIn+cj41b C7xQpUjM3IBp30RId+SroknKjnHrw6QZ+A3asD9xed65gEDD9Xhf4wEM0yjBmc1hHdPG axWMVI+GvXCbeKNVEj2HHYKiT/XA1XNdOp1f5q/nbWF7wpef9TdadBYYxqptjSIonAIr esNw== X-Gm-Message-State: APjAAAU+z2uXH3Y0D9h0ycHFhIO4SVCsLqzxLnxocpZyRV12dU+U+VYS B035FfIXaIwTrOQntpuf53A1hg== X-Received: by 2002:adf:fb0d:: with SMTP id c13mr6697537wrr.214.1556187625771; Thu, 25 Apr 2019 03:20:25 -0700 (PDT) Received: from sudo.home ([2a01:cb1d:112:6f00:95f:9014:5be9:5288]) by smtp.gmail.com with ESMTPSA id p18sm5611364wrp.38.2019.04.25.03.20.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Apr 2019 03:20:24 -0700 (PDT) From: Ard Biesheuvel To: linux-arm-kernel@lists.infradead.org Cc: linux-gpio@vger.kernel.org, Ard Biesheuvel , Masahisa Kojima , Linus Walleij , Marc Zyngier , Graeme Gregory Subject: [RFC PATCH 2/3] irqchip/exiu: implement ACPI gpiolib/irqchip support Date: Thu, 25 Apr 2019 12:20:19 +0200 Message-Id: <20190425102020.21533-3-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190425102020.21533-1-ard.biesheuvel@linaro.org> References: <20190425102020.21533-1-ard.biesheuvel@linaro.org> MIME-Version: 1.0 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Expose the existing EXIU hierarchical irqchip domain code to permit the interrupt controller to be used as the irqchip component of a GPIO controller on ACPI systems. Signed-off-by: Ard Biesheuvel --- drivers/irqchip/irq-sni-exiu.c | 82 +++++++++++++++++--- 1 file changed, 73 insertions(+), 9 deletions(-) -- 2.20.1 diff --git a/drivers/irqchip/irq-sni-exiu.c b/drivers/irqchip/irq-sni-exiu.c index 52ce662334d4..99351cf997d9 100644 --- a/drivers/irqchip/irq-sni-exiu.c +++ b/drivers/irqchip/irq-sni-exiu.c @@ -12,6 +12,7 @@ * published by the Free Software Foundation. */ +#include #include #include #include @@ -20,6 +21,7 @@ #include #include #include +#include #include @@ -134,9 +136,13 @@ static int exiu_domain_translate(struct irq_domain *domain, *hwirq = fwspec->param[1] - info->spi_base; *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; - return 0; + } else { + if (fwspec->param_count != 2) + return -EINVAL; + *hwirq = fwspec->param[0]; + *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; } - return -EINVAL; + return 0; } static int exiu_domain_alloc(struct irq_domain *dom, unsigned int virq, @@ -147,16 +153,23 @@ static int exiu_domain_alloc(struct irq_domain *dom, unsigned int virq, struct exiu_irq_data *info = dom->host_data; irq_hw_number_t hwirq; - if (fwspec->param_count != 3) - return -EINVAL; /* Not GIC compliant */ - if (fwspec->param[0] != GIC_SPI) - return -EINVAL; /* No PPI should point to this domain */ - + parent_fwspec = *fwspec; + if (is_of_node(dom->parent->fwnode)) { + if (fwspec->param_count != 3) + return -EINVAL; /* Not GIC compliant */ + if (fwspec->param[0] != GIC_SPI) + return -EINVAL; /* No PPI should point to this domain */ + + hwirq = fwspec->param[1] - info->spi_base; + } else if (is_fwnode_irqchip(dom->parent->fwnode)) { + hwirq = fwspec->param[0]; + parent_fwspec.param[0] = hwirq + info->spi_base + 32; + } else { + return -EINVAL; + } WARN_ON(nr_irqs != 1); - hwirq = fwspec->param[1] - info->spi_base; irq_domain_set_hwirq_and_chip(dom, virq, hwirq, &exiu_irq_chip, info); - parent_fwspec = *fwspec; parent_fwspec.fwnode = dom->parent->fwnode; return irq_domain_alloc_irqs_parent(dom, virq, nr_irqs, &parent_fwspec); } @@ -244,3 +257,54 @@ static int __init exiu_dt_init(struct device_node *node, return 0; } IRQCHIP_DECLARE(exiu, "socionext,synquacer-exiu", exiu_dt_init); + +#ifdef CONFIG_ACPI +static int exiu_acpi_gpio_to_irq(struct gpio_chip *gc, u32 gpio) +{ + struct irq_fwspec fwspec; + + fwspec.fwnode = gc->parent->fwnode; + fwspec.param_count = 2; + fwspec.param[0] = gpio; + fwspec.param[1] = IRQ_TYPE_LEVEL_HIGH; + + return irq_create_fwspec_mapping(&fwspec); +} + +int exiu_acpi_init(struct platform_device *pdev, struct gpio_chip *gc) +{ + struct irq_domain *parent_domain = NULL, *domain; + struct resource *res; + int irq; + + irq = platform_get_irq(pdev, 0); + if (irq > 0) + parent_domain = irq_get_irq_data(irq)->domain; + + if (!parent_domain) { + dev_err(&pdev->dev, "unable to obtain parent domain\n"); + return -ENODEV; + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (!res) { + dev_err(&pdev->dev, "failed to parse memory resource\n"); + return -ENXIO; + } + + domain = exiu_init(parent_domain, dev_fwnode(&pdev->dev), res); + if (IS_ERR(domain)) { + dev_err(&pdev->dev, "failed to create IRQ domain (%ld)\n", + PTR_ERR(domain)); + return PTR_ERR(domain); + } + + gc->irq.domain = domain; + gc->to_irq = exiu_acpi_gpio_to_irq; + + dev_info(&pdev->dev, "%d interrupts forwarded\n", NUM_IRQS); + + return 0; +} +EXPORT_SYMBOL(exiu_acpi_init); +#endif From patchwork Thu Apr 25 10:20:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 162841 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp1741976jan; Thu, 25 Apr 2019 03:20:31 -0700 (PDT) X-Google-Smtp-Source: APXvYqwvXvRFu2Eir/GbFnt9S2k/lGa2RFHrvItj1UMVevq6YT1ju/2W+cyeF34k0cMJvBDQktqF X-Received: by 2002:a17:902:6b03:: with SMTP id o3mr37408753plk.226.1556187630990; Thu, 25 Apr 2019 03:20:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556187630; cv=none; d=google.com; s=arc-20160816; b=CkWE9rJD5BXGb0ym2F0Of+hbtC7wXzMRAQtpRJF75xOWEI7CuScoxOvEzr8ATbtraq H2dHMAVdyXJmBFlVcjFGrLI8MHSCp9ojZ4sI1C0qmSrxXOJbZD4N/gulpq1JVzttXwpV Kr8G200COd89yRmKQrzuqQnlRppNQTBFkc8zL3B8o1QFBoFwEQTCDVozxGWznyEMbLUa BDaSuaeFYLEpxPNsZUeeaZTXUNDkvBw3ZRUHldu8iYvXgaZp8iBQHnMHO5ttLCvPf64i CvPOD/bOZlMDz543jKsyge8cTZmTPXrXjlaqa/FP9xgjoz2JJZryKYB6fL7OXyMpgt6a voCQ== ARC-Message-Signature: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id w3si22229688plp.260.2019.04.25.03.20.30; Thu, 25 Apr 2019 03:20:30 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="mk/R0U3R"; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727282AbfDYKUa (ORCPT + 5 others); Thu, 25 Apr 2019 06:20:30 -0400 Received: from mail-wr1-f67.google.com ([209.85.221.67]:33136 "EHLO mail-wr1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726328AbfDYKUa (ORCPT ); Thu, 25 Apr 2019 06:20:30 -0400 Received: by mail-wr1-f67.google.com with SMTP id s18so4693180wrp.0 for ; Thu, 25 Apr 2019 03:20:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+kDc3li6azRdBVeqSH107MAL3Z+IDS2Va16tVwCqx8k=; b=mk/R0U3R6hu9WlJ1qRU44gKZ8Tj7/3pU6xKmnMjtWxj5BLTYYB4g9bFbUzDBoUz9XM EX6pcFXj/CRhO3glYhUdGflRYsIuN/RBUYKB3nH+SgxJeuvVXqg3sTnBHNGoJ9t9r3TH lKUtdlREEOudPcffAs6gAf7a7IfnUlrxv1IPachgHXT7iVLTTSz6RkhFKkbTYSrWXDv3 QCC9szsbqluHQv6QxN0rsxhT0Waf2YcZLK8M45jRkbYiAB1TBR+Kq5dxC5hwyTv8/Kwv l1OOTOD1oATSUMqhtvMEsoIxIaXeI/HN/Dw30d+GmT5vF27wV2c+zg0guiwWl2l8YiSo CHCw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+kDc3li6azRdBVeqSH107MAL3Z+IDS2Va16tVwCqx8k=; b=sVb7FpZObLgfvjdm98Cou6ATqSH5tFLTDN0VwwdWHtSVPtFFZNpBR9WqoxKbLUDOI4 K9qY0fdLukZ8E79Z+RveBB8hvtFroXI7850mGex3WHgpK7uKplUnMBmO+3cJLB8+SQIh mGVZg4JSXN2c/ry8fnSxRokZMOHRJsbqFTwXgExtSHFIsZzqt7EAD+PyHdvGX7kJgUCi NNI2GYqnv3IH8qLUbPBTDcsEDEmRkJZHdhJwtlIqTfIj3o9XW3sY/ME+oiMDS3DvEUTn tDteL3/TzCIuoYXDSUWLjCrnF/EckWV2rbelvGInof2EHXXXAQIWRSq9SN7k7acjcG7U LN4Q== X-Gm-Message-State: APjAAAXA0V5WW9FU0WSB6j6aiss+Zco8/1Ety7cee2foCpOT5vpY7zhJ CXaERh8jeEn7NX2LnQrj7VC/qg== X-Received: by 2002:adf:ec4e:: with SMTP id w14mr2079300wrn.53.1556187627816; Thu, 25 Apr 2019 03:20:27 -0700 (PDT) Received: from sudo.home ([2a01:cb1d:112:6f00:95f:9014:5be9:5288]) by smtp.gmail.com with ESMTPSA id p18sm5611364wrp.38.2019.04.25.03.20.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Apr 2019 03:20:26 -0700 (PDT) From: Ard Biesheuvel To: linux-arm-kernel@lists.infradead.org Cc: linux-gpio@vger.kernel.org, Ard Biesheuvel , Masahisa Kojima , Linus Walleij , Marc Zyngier , Graeme Gregory Subject: [RFC PATCH 3/3] gpio: mb86s70: enable ACPI and irqchip support Date: Thu, 25 Apr 2019 12:20:20 +0200 Message-Id: <20190425102020.21533-4-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190425102020.21533-1-ard.biesheuvel@linaro.org> References: <20190425102020.21533-1-ard.biesheuvel@linaro.org> MIME-Version: 1.0 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org In order to support this GPIO block in combination with an EXIU interrupt controller on ACPI systems such as Socionext SynQuacer, add the enumeration boilerplate, and add the EXIU irqchip handling to the probe path. Also, make the clock handling conditonal on non-ACPI enumeration, since ACPI handles this internally. Signed-off-by: Ard Biesheuvel --- drivers/gpio/Kconfig | 4 ++ drivers/gpio/gpio-mb86s7x.c | 58 +++++++++++++++++--- 2 files changed, 53 insertions(+), 9 deletions(-) -- 2.20.1 diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 3f50526a771f..2c2773ea9627 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -315,6 +315,10 @@ config GPIO_MB86S7X help Say yes here to support the GPIO controller in Fujitsu MB86S70 SoCs. +config GPIO_MB86S7X_ACPI + def_bool y + depends on ACPI && ARCH_SYNQUACER + config GPIO_MENZ127 tristate "MEN 16Z127 GPIO support" depends on MCB diff --git a/drivers/gpio/gpio-mb86s7x.c b/drivers/gpio/gpio-mb86s7x.c index 3134c0d2bfe4..d254783f7e71 100644 --- a/drivers/gpio/gpio-mb86s7x.c +++ b/drivers/gpio/gpio-mb86s7x.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -27,6 +28,8 @@ #include #include +#include "gpiolib.h" + /* * Only first 8bits of a register correspond to each pin, * so there are 4 registers for 32 pins. @@ -44,6 +47,8 @@ struct mb86s70_gpio_chip { spinlock_t lock; }; +int exiu_acpi_init(struct platform_device *pdev, struct gpio_chip *gc); + static int mb86s70_gpio_request(struct gpio_chip *gc, unsigned gpio) { struct mb86s70_gpio_chip *gchip = gpiochip_get_data(gc); @@ -143,6 +148,12 @@ static void mb86s70_gpio_set(struct gpio_chip *gc, unsigned gpio, int value) spin_unlock_irqrestore(&gchip->lock, flags); } +static bool mb86s70_gpio_have_acpi(struct platform_device *pdev) +{ + return IS_ENABLED(CONFIG_GPIO_MB86S7X_ACPI) && + ACPI_COMPANION(&pdev->dev); +} + static int mb86s70_gpio_probe(struct platform_device *pdev) { struct mb86s70_gpio_chip *gchip; @@ -160,13 +171,15 @@ static int mb86s70_gpio_probe(struct platform_device *pdev) if (IS_ERR(gchip->base)) return PTR_ERR(gchip->base); - gchip->clk = devm_clk_get(&pdev->dev, NULL); - if (IS_ERR(gchip->clk)) - return PTR_ERR(gchip->clk); + if (!mb86s70_gpio_have_acpi(pdev)) { + gchip->clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(gchip->clk)) + return PTR_ERR(gchip->clk); - ret = clk_prepare_enable(gchip->clk); - if (ret) - return ret; + ret = clk_prepare_enable(gchip->clk); + if (ret) + return ret; + } spin_lock_init(&gchip->lock); @@ -182,21 +195,39 @@ static int mb86s70_gpio_probe(struct platform_device *pdev) gchip->gc.parent = &pdev->dev; gchip->gc.base = -1; + if (mb86s70_gpio_have_acpi(pdev)) { + ret = exiu_acpi_init(pdev, &gchip->gc); + if (ret) { + dev_err(&pdev->dev, "couldn't register gpio irqchip\n"); + return ret; + } + } + ret = gpiochip_add_data(&gchip->gc, gchip); if (ret) { dev_err(&pdev->dev, "couldn't register gpio driver\n"); - clk_disable_unprepare(gchip->clk); + if (gchip->clk) + clk_disable_unprepare(gchip->clk); + return ret; } - return ret; + if (mb86s70_gpio_have_acpi(pdev)) + acpi_gpiochip_request_interrupts(&gchip->gc); + + return 0; } static int mb86s70_gpio_remove(struct platform_device *pdev) { struct mb86s70_gpio_chip *gchip = platform_get_drvdata(pdev); + if (gchip->gc.irq.domain) { + acpi_gpiochip_free_interrupts(&gchip->gc); + irq_domain_remove(gchip->gc.irq.domain); + } gpiochip_remove(&gchip->gc); - clk_disable_unprepare(gchip->clk); + if (gchip->clk) + clk_disable_unprepare(gchip->clk); return 0; } @@ -207,10 +238,19 @@ static const struct of_device_id mb86s70_gpio_dt_ids[] = { }; MODULE_DEVICE_TABLE(of, mb86s70_gpio_dt_ids); +#ifdef CONFIG_ACPI +static const struct acpi_device_id mb86s70_gpio_acpi_ids[] = { + { "SCX0007" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(acpi, mb86s70_gpio_acpi_ids); +#endif + static struct platform_driver mb86s70_gpio_driver = { .driver = { .name = "mb86s70-gpio", .of_match_table = mb86s70_gpio_dt_ids, + .acpi_match_table = ACPI_PTR(mb86s70_gpio_acpi_ids), }, .probe = mb86s70_gpio_probe, .remove = mb86s70_gpio_remove,