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Wed, 8 Feb 2023 03:17:23 -0800 Received: from rnnvmail205.nvidia.com (10.129.68.10) by rnnvmail205.nvidia.com (10.129.68.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Wed, 8 Feb 2023 03:17:22 -0800 Received: from mmaddireddy-ubuntu.nvidia.com (10.127.8.10) by mail.nvidia.com (10.129.68.10) with Microsoft SMTP Server id 15.2.986.36 via Frontend Transport; Wed, 8 Feb 2023 03:17:15 -0800 From: Manikanta Maddireddy To: , , , , , , CC: , , , , , , , , , , , , , Manikanta Maddireddy Subject: [RFC,v14 2/5] of/irq: Adjust of_pci_irq parsing for multiple interrupts Date: Wed, 8 Feb 2023 16:46:42 +0530 Message-ID: <20230208111645.3863534-3-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230208111645.3863534-1-mmaddireddy@nvidia.com> References: <20230208111645.3863534-1-mmaddireddy@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT102:EE_|DM4PR12MB5962:EE_ X-MS-Office365-Filtering-Correlation-Id: e99e9885-9c41-4aec-3964-08db09c611bb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Feb 2023 11:17:30.7776 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e99e9885-9c41-4aec-3964-08db09c611bb X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT102.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5962 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Jeffy Chen Currently we are considering the first irq as the PCI interrupt pin, but a PCI device may have multiple interrupts(e.g. PCIe WAKE# pin). Only parse the PCI interrupt pin when the irq is unnamed or named as "pci". Signed-off-by: Jeffy Chen Signed-off-by: Manikanta Maddireddy --- Changes in v14: Address Rob's comment on using of_property_match_string(). Changes in v13: None Changes in v12: None Changes in v11: Address Brian's comments. Changes in v10: None Changes in v9: None Changes in v8: None Changes in v7: None Changes in v6: None Changes in v5: None Changes in v3: None Changes in v2: None drivers/pci/of.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/pci/of.c b/drivers/pci/of.c index 196834ed44fe..ff897c40ed71 100644 --- a/drivers/pci/of.c +++ b/drivers/pci/of.c @@ -429,9 +429,17 @@ static int of_irq_parse_pci(const struct pci_dev *pdev, struct of_phandle_args * */ dn = pci_device_to_OF_node(pdev); if (dn) { - rc = of_irq_parse_one(dn, 0, out_irq); - if (!rc) - return rc; + int index = 0; + + index = of_property_match_string(dn, "interrupt-names", "pci"); + if (index == -EINVAL) /* Property doesn't exist */ + index = 0; + + if (index >= 0) { + rc = of_irq_parse_one(dn, index, out_irq); + if (!rc) + return rc; + } } /* From patchwork Wed Feb 8 11:16:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Maddireddy X-Patchwork-Id: 652050 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AEA76C636D7 for ; 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Wed, 8 Feb 2023 03:17:37 -0800 From: Manikanta Maddireddy To: , , , , , , CC: , , , , , , , , , , , , , Manikanta Maddireddy Subject: [RFC,v14 5/5] soc/tegra: pmc: Add Tegra234 PCIe wake event Date: Wed, 8 Feb 2023 16:46:45 +0530 Message-ID: <20230208111645.3863534-6-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230208111645.3863534-1-mmaddireddy@nvidia.com> References: <20230208111645.3863534-1-mmaddireddy@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT068:EE_|SJ2PR12MB7942:EE_ X-MS-Office365-Filtering-Correlation-Id: 2a1fb2df-3a00-4386-98ea-08db09c620d4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: FPklJNVKITaQVJc/91Oee5OnaVMnBY1AvrHmXGPF6xkfx/+J8Fa04t2qc8/AGmv/ktq1WnaVznLcWMDbvYqDXkSRwKnDTdwJkO+17Ye7w4jSAoRZO38kKvAVDeWGI8IiebO/FAw/xZWF1ttS64Y8ZBlLjRiZxLAlzV8Iphqsjj9Q5w13Fz6H+I4zqEkhtDyngEPvkTqLpQtQgOLT+46amz7lyvYwfn4fCdiGlO2dQJh5Z7jkx0Os6bnqITcnrqrCGWTie0wUgp+YxNTqiW3M+MrWAqZdvHW0Odby2rahGtmd59JEWkLyDV3cZKpNtkMnxGlRtGNBTyuTYLllEiMKpDaZX98KZZMDTcyRfgNFX5AzdaXjExeGDv8GY7U3vu1frVOJpk8RowelXckZfejvEkq4xHT9/UQXBLlWWQO+uNPAanc3EnVjcDeNTXEjBMggIbqOQAtpMIpgzjhnEutPlFQbPuxrR0F8KUW5JpUe9DvI5fiNpPAVYlcTSpfMDEJpketMO6bZCPc6QuQHZNZVqjiankneIkNxGOonXt8pGUHztvyzu95M06tcbU+3H8M073dRTvJRrtNAQVQmzIFUU6Z1oFOauL7up39A/VkwEFfYXdRkSvJcc+fwdLQWcNOoxUQV7/NA1K8+gkV1udDeZ3LnmGNIQdE7cXFFtmT16AARPTsdKx0ueKN7jVyZpyLIJ2T7NO4Kemk8N7+7BhL3GA== X-Forefront-Antispam-Report: CIP:216.228.117.161; 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Signed-off-by: Manikanta Maddireddy --- Changes in v14: New patch in the series to support PCIe WAKE# in NVIDIA Jetson AGX Orin. drivers/soc/tegra/pmc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index cf4cfbf9f7c5..139ee853c32b 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -4225,6 +4225,7 @@ static const char * const tegra234_reset_sources[] = { }; static const struct tegra_wake_event tegra234_wake_events[] = { + TEGRA_WAKE_GPIO("pcie", 1, 0, TEGRA234_MAIN_GPIO(L, 2)), TEGRA_WAKE_GPIO("power", 29, 1, TEGRA234_AON_GPIO(EE, 4)), TEGRA_WAKE_IRQ("rtc", 73, 10), };