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Fri, 10 Feb 2023 07:39:48 -0800 Received: from drhqmail203.nvidia.com (10.126.190.182) by drhqmail202.nvidia.com (10.126.190.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Fri, 10 Feb 2023 07:39:47 -0800 Received: from vdi.nvidia.com (10.127.8.14) by mail.nvidia.com (10.126.190.182) with Microsoft SMTP Server id 15.2.986.36 via Frontend Transport; Fri, 10 Feb 2023 07:39:47 -0800 From: Asmaa Mnebhi To: , , CC: Asmaa Mnebhi Subject: [PATCH v3 1/2] Support NVIDIA BlueField-3 GPIO controller Date: Fri, 10 Feb 2023 10:39:40 -0500 Message-ID: X-Mailer: git-send-email 2.30.1 In-Reply-To: References: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT050:EE_|BL1PR12MB5110:EE_ X-MS-Office365-Filtering-Correlation-Id: 541a6598-8ff0-481f-76ce-08db0b7d0c85 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: q/vZAzS9jq4U3gdZjVbik669Bf8qYH79wta82TlXNk1gwFNEA/CnyT5pDv0tprgG6eUHvTXDkK5jo86p8qR/RCfpwP3tHIl4CU/euyO9FTyOVR4ychOgV/XZ7zQ8gZvMQY1hEXHvu/DMGkX+QIzleNGFhJ9GPQ8K/15IoJHwWixXvKWKWMTMuRt14m4TL7oGUnMg4yQPDgNIHn+B154j18yxV+/PwgofjoqvFqUreDBvjaRDpZ+LBiQLR8179hPNZOGOC0t/KLFvBKJs/3yxm3G5tkBd045HUjteUsVNM80NpnrhlfjRKuO0DGUGTBJHsyDel8U3w6y4/ARcXr78v/FvzHowDfD+h8KkLu/eJDcX24emAqI8qozK2O0+Jt0X0ByL1wR3fjat542B27r/3HLcEo0ptPqgR11Wmh7TtVrV/t7Pg3dkk+Cb2YD+mgy9/nC9BGXxJaii7i6Lt/Q9Lwip3VgI3uB2Az9ex41aE/Mz4FDz3XjUlXK75r68GjS8JIUEV+v5bBB8XbtDpy0n5ULtLI7S1MGtWsRA18r6Wo4E72Ol6PPiJxz8V0dESWB7K2gJEyjZ8jaNN7KBispJfkWeDkrS2MB1MGh1ajT4tZPbtkKvVlCfCp8FW8s/okZLJ2x6GTJomFtv9n9FDOi4wXQu1t/N5YBRbCzgoFlm+6oiCoshFc3WHWQvjd3RO89Ss0LqBIe+gN3sd742+XBu9Q== X-Forefront-Antispam-Report: CIP:216.228.118.233; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge2.nvidia.com; CAT:NONE; SFS:(13230025)(4636009)(396003)(136003)(346002)(39860400002)(376002)(451199018)(36840700001)(40470700004)(46966006)(5660300002)(36756003)(82740400003)(356005)(41300700001)(36860700001)(7636003)(82310400005)(107886003)(86362001)(2616005)(2906002)(83380400001)(47076005)(40460700003)(336012)(426003)(186003)(8936002)(26005)(6666004)(110136005)(40480700001)(450100002)(316002)(478600001)(8676002)(4326008)(70586007)(7696005)(70206006); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Feb 2023 15:39:51.0073 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 541a6598-8ff0-481f-76ce-08db0b7d0c85 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.233]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT050.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5110 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This patch adds support for the BlueField-3 SoC GPIO driver which allows: - setting certain GPIOs as interrupts from other dependent drivers - ability to manipulate certain GPIO pins via libgpiod tools BlueField-3 has 56 GPIOs but the user is only allowed to change some of them into GPIO mode. Use valid_mask to make it impossible to alter the rest of the GPIOs. Signed-off-by: Asmaa Mnebhi --- drivers/gpio/Kconfig | 7 + drivers/gpio/Makefile | 1 + drivers/gpio/gpio-mlxbf3.c | 262 +++++++++++++++++++++++++++++++++++++ 3 files changed, 270 insertions(+) create mode 100644 drivers/gpio/gpio-mlxbf3.c diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index ec7cfd4f52b1..3d56a83db284 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -1534,6 +1534,13 @@ config GPIO_MLXBF2 help Say Y here if you want GPIO support on Mellanox BlueField 2 SoC. +config GPIO_MLXBF3 + tristate "Mellanox BlueField 3 SoC GPIO" + depends on (MELLANOX_PLATFORM && ARM64 && ACPI) || (64BIT && COMPILE_TEST) + select GPIO_GENERIC + help + Say Y here if you want GPIO support on Mellanox BlueField 3 SoC. + config GPIO_ML_IOH tristate "OKI SEMICONDUCTOR ML7213 IOH GPIO support" depends on X86 || COMPILE_TEST diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 010587025fc8..76545ca31457 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -101,6 +101,7 @@ obj-$(CONFIG_GPIO_MERRIFIELD) += gpio-merrifield.o obj-$(CONFIG_GPIO_ML_IOH) += gpio-ml-ioh.o obj-$(CONFIG_GPIO_MLXBF) += gpio-mlxbf.o obj-$(CONFIG_GPIO_MLXBF2) += gpio-mlxbf2.o +obj-$(CONFIG_GPIO_MLXBF3) += gpio-mlxbf3.o obj-$(CONFIG_GPIO_MM_LANTIQ) += gpio-mm-lantiq.o obj-$(CONFIG_GPIO_MOCKUP) += gpio-mockup.o obj-$(CONFIG_GPIO_MOXTET) += gpio-moxtet.o diff --git a/drivers/gpio/gpio-mlxbf3.c b/drivers/gpio/gpio-mlxbf3.c new file mode 100644 index 000000000000..ddd27c316035 --- /dev/null +++ b/drivers/gpio/gpio-mlxbf3.c @@ -0,0 +1,262 @@ +// SPDX-License-Identifier: GPL-2.0-only or BSD-3-Clause + +/* + * Copyright (C) 2022 NVIDIA CORPORATION & AFFILIATES + */ + +#include +#include +#include + +/* + * There are 2 YU GPIO blocks: + * gpio[0]: HOST_GPIO0->HOST_GPIO31 + * gpio[1]: HOST_GPIO32->HOST_GPIO55 + */ +#define MLXBF3_GPIO_MAX_PINS_PER_BLOCK 32 + +/* + * fw_gpio[x] block registers and their offset + */ +#define MLXBF_GPIO_FW_OUTPUT_ENABLE_SET 0x04 +#define MLXBF_GPIO_FW_DATA_OUT_SET 0x08 +#define MLXBF_GPIO_FW_OUTPUT_ENABLE_CLEAR 0x18 +#define MLXBF_GPIO_FW_DATA_OUT_CLEAR 0x1c +#define MLXBF_GPIO_CAUSE_RISE_EN 0x28 +#define MLXBF_GPIO_CAUSE_FALL_EN 0x2c +#define MLXBF_GPIO_READ_DATA_IN 0x30 + +#define MLXBF_GPIO_CAUSE_OR_CAUSE_EVTEN0 0x00 +#define MLXBF_GPIO_CAUSE_OR_EVTEN0 0x14 +#define MLXBF_GPIO_CAUSE_OR_CLRCAUSE 0x18 + +struct mlxbf3_gpio_context { + struct gpio_chip gc; + struct irq_chip irq_chip; + + /* YU GPIO block address */ + void __iomem *gpio_io; + + /* YU GPIO cause block address */ + void __iomem *gpio_cause_io; + + /* Mask of valid gpios that can be accessed by software */ + unsigned int valid_mask; +}; + +static void mlxbf3_gpio_irq_enable(struct irq_data *irqd) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); + struct mlxbf3_gpio_context *gs = gpiochip_get_data(gc); + int offset = irqd_to_hwirq(irqd); + unsigned long flags; + u32 val; + + raw_spin_lock_irqsave(&gs->gc.bgpio_lock, flags); + writel(BIT(offset), gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_CLRCAUSE); + + val = readl(gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_EVTEN0); + val |= BIT(offset); + writel(val, gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_EVTEN0); + raw_spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags); +} + +static void mlxbf3_gpio_irq_disable(struct irq_data *irqd) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); + struct mlxbf3_gpio_context *gs = gpiochip_get_data(gc); + int offset = irqd_to_hwirq(irqd); + unsigned long flags; + u32 val; + + raw_spin_lock_irqsave(&gs->gc.bgpio_lock, flags); + val = readl(gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_EVTEN0); + val &= ~BIT(offset); + writel(val, gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_EVTEN0); + raw_spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags); +} + +static irqreturn_t mlxbf3_gpio_irq_handler(int irq, void *ptr) +{ + struct mlxbf3_gpio_context *gs = ptr; + struct gpio_chip *gc = &gs->gc; + unsigned long pending; + u32 level; + + pending = readl(gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_CAUSE_EVTEN0); + writel(pending, gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_CLRCAUSE); + + for_each_set_bit(level, &pending, gc->ngpio) + generic_handle_irq(irq_find_mapping(gc->irq.domain, level)); + + return IRQ_RETVAL(pending); +} + +static int +mlxbf3_gpio_irq_set_type(struct irq_data *irqd, unsigned int type) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); + struct mlxbf3_gpio_context *gs = gpiochip_get_data(gc); + int offset = irqd_to_hwirq(irqd); + unsigned long flags; + bool fall = false; + bool rise = false; + u32 val; + + switch (type & IRQ_TYPE_SENSE_MASK) { + case IRQ_TYPE_EDGE_BOTH: + fall = true; + rise = true; + break; + case IRQ_TYPE_EDGE_RISING: + rise = true; + break; + case IRQ_TYPE_EDGE_FALLING: + fall = true; + break; + default: + return -EINVAL; + } + + raw_spin_lock_irqsave(&gs->gc.bgpio_lock, flags); + if (fall) { + val = readl(gs->gpio_io + MLXBF_GPIO_CAUSE_FALL_EN); + val |= BIT(offset); + writel(val, gs->gpio_io + MLXBF_GPIO_CAUSE_FALL_EN); + } + + if (rise) { + val = readl(gs->gpio_io + MLXBF_GPIO_CAUSE_RISE_EN); + val |= BIT(offset); + writel(val, gs->gpio_io + MLXBF_GPIO_CAUSE_RISE_EN); + } + raw_spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags); + + return 0; +} + +static int mlxbf3_gpio_init_valid_mask(struct gpio_chip *gc, + unsigned long *valid_mask, + unsigned int ngpios) +{ + struct mlxbf3_gpio_context *gs = gpiochip_get_data(gc); + + *valid_mask = gs->valid_mask; + + return 0; +} + +static int +mlxbf3_gpio_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct mlxbf3_gpio_context *gs; + unsigned int npins, valid_mask; + struct gpio_irq_chip *girq; + struct gpio_chip *gc; + struct resource *res; + const char *name; + int ret, irq; + + name = dev_name(dev); + + gs = devm_kzalloc(dev, sizeof(*gs), GFP_KERNEL); + if (!gs) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -ENODEV; + + /* Resource shared with pinctrl driver */ + gs->gpio_io = devm_ioremap(dev, res->start, resource_size(res)); + if (!gs->gpio_io) + return -ENOMEM; + + /* YU GPIO block address */ + gs->gpio_cause_io = devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(gs->gpio_cause_io)) + return PTR_ERR(gs->gpio_cause_io); + + if (device_property_read_u32(dev, "npins", &npins)) + npins = MLXBF3_GPIO_MAX_PINS_PER_BLOCK; + + if (device_property_read_u32(dev, "valid_mask", &valid_mask)) + valid_mask = 0x0; + + gs->valid_mask = valid_mask; + + gc = &gs->gc; + + ret = bgpio_init(gc, dev, 4, + gs->gpio_io + MLXBF_GPIO_READ_DATA_IN, + gs->gpio_io + MLXBF_GPIO_FW_DATA_OUT_SET, + gs->gpio_io + MLXBF_GPIO_FW_DATA_OUT_CLEAR, + gs->gpio_io + MLXBF_GPIO_FW_OUTPUT_ENABLE_SET, + gs->gpio_io + MLXBF_GPIO_FW_OUTPUT_ENABLE_CLEAR, 0); + + gc->request = gpiochip_generic_request; + gc->free = gpiochip_generic_free; + gc->init_valid_mask = mlxbf3_gpio_init_valid_mask; + + gc->ngpio = npins; + gc->owner = THIS_MODULE; + + irq = platform_get_irq(pdev, 0); + if (irq >= 0) { + gs->irq_chip.name = name; + gs->irq_chip.irq_set_type = mlxbf3_gpio_irq_set_type; + gs->irq_chip.irq_enable = mlxbf3_gpio_irq_enable; + gs->irq_chip.irq_disable = mlxbf3_gpio_irq_disable; + + girq = &gs->gc.irq; + girq->chip = &gs->irq_chip; + girq->handler = handle_simple_irq; + girq->default_type = IRQ_TYPE_NONE; + /* This will let us handle the parent IRQ in the driver */ + girq->num_parents = 0; + girq->parents = NULL; + girq->parent_handler = NULL; + + /* + * Directly request the irq here instead of passing + * a flow-handler because the irq is shared. + */ + ret = devm_request_irq(dev, irq, mlxbf3_gpio_irq_handler, + IRQF_SHARED, name, gs); + if (ret) { + dev_err(dev, "failed to request IRQ"); + return ret; + } + } + + platform_set_drvdata(pdev, gs); + + ret = devm_gpiochip_add_data(dev, &gs->gc, gs); + if (ret) { + dev_err(dev, "Failed adding memory mapped gpiochip\n"); + return ret; + } + + return 0; +} + +static const struct acpi_device_id __maybe_unused mlxbf3_gpio_acpi_match[] = { + { "MLNXBF33", 0 }, + {}, +}; +MODULE_DEVICE_TABLE(acpi, mlxbf3_gpio_acpi_match); + +static struct platform_driver mlxbf3_gpio_driver = { + .driver = { + .name = "mlxbf3_gpio", + .acpi_match_table = mlxbf3_gpio_acpi_match, + }, + .probe = mlxbf3_gpio_probe, +}; + +module_platform_driver(mlxbf3_gpio_driver); + +MODULE_DESCRIPTION("NVIDIA BlueField-3 GPIO Driver"); +MODULE_AUTHOR("Asmaa Mnebhi "); +MODULE_LICENSE("Dual BSD/GPL"); From patchwork Fri Feb 10 15:39:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Asmaa Mnebhi X-Patchwork-Id: 652542 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ED4B2C636CD for ; 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Fri, 10 Feb 2023 07:39:49 -0800 From: Asmaa Mnebhi To: , , CC: Asmaa Mnebhi Subject: [PATCH v3 2/2] Support NVIDIA BlueField-3 pinctrl driver Date: Fri, 10 Feb 2023 10:39:41 -0500 Message-ID: X-Mailer: git-send-email 2.30.1 In-Reply-To: References: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT043:EE_|PH7PR12MB5854:EE_ X-MS-Office365-Filtering-Correlation-Id: 3c5eb5dd-2ceb-42ae-f775-08db0b7d1030 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: I4J5k4MiFXG0hom1blZkbrgnR2lWztsDJOgc3fRUFom9mZsSSHECZO61tQJZYzpgPkVSg4h6ydk4HG+gTgKf6aDHifw/pnmmBnY6QKDGKQaXYzCnMDizeBFOhZv5JYx9sQLRm5xRqYvyVhJwwpG439oxPqYWKkWbGAPAdHOlx5eeS7GjMAPpSFv2ibrHnq075tbeRKMnMfW+ZnrrNRPHMLgUDEOzX8zQGMVcHtKJ6npa3sAMtLkVw3P+UUPlJslFmzzWY8TpSoeirIL1vMUM4jBZ7auczDPlc713TO8uQNnDkmT66E1uQMLH+xzKgGgeyJ3P5zyNSiz1qe93lvKoifnFDjE/KWB4AdSbHyBacd4PLnZbXA8tdNdlgQ/YM9kxr8l5lcc0H42Vnc5JWBn43XfxRxIZ2zeZdH+hB0u15wKKCod5SBKZaDn1WiqTxZycuy/W+dKl0PBNaZedM0mkTvdjk3+eLO7BGuytvMZGbsGbJ1R1w+r7Cux5k0CkY+A5zN8rVUvAl8c/TVF4HPYMqXLj6zdPZ3iM+03EXovh9x47ppzK/1oiEfJ8SUaC7H2o3ElkM7FTwxc7eozw7xBFuLFZ6CuOsl+THP9jyMcCHMKgsZvLEKc8g3ZI/HzH17p3Mb+kbgqarCn7A+ZwzQVYK0SvHgy1LdSYuhM72bIMpWMBdFadTmX2vX7GueBSjPKCPSmRf8VSR0OWFy2+XHslkw== X-Forefront-Antispam-Report: CIP:216.228.118.233; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge2.nvidia.com; CAT:NONE; SFS:(13230025)(4636009)(39860400002)(346002)(136003)(376002)(396003)(451199018)(40470700004)(46966006)(36840700001)(336012)(2616005)(450100002)(70586007)(70206006)(41300700001)(4326008)(186003)(26005)(8676002)(8936002)(107886003)(6666004)(316002)(86362001)(478600001)(2906002)(83380400001)(7696005)(110136005)(36756003)(47076005)(5660300002)(82310400005)(40460700003)(356005)(40480700001)(426003)(30864003)(82740400003)(7636003)(36860700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Feb 2023 15:39:57.1644 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3c5eb5dd-2ceb-42ae-f775-08db0b7d1030 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.233]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT043.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB5854 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This patch adds support to the BlueField-3 SoC pin controller. It allows muxing individual GPIOs to switch from the default hardware mode to software controlled mode. Signed-off-by: Asmaa Mnebhi --- drivers/pinctrl/Kconfig | 10 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-mlxbf.c | 341 ++++++++++++++++++++++++++++++++ 3 files changed, 352 insertions(+) create mode 100644 drivers/pinctrl/pinctrl-mlxbf.c diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 7d5f5458c72e..7040d79a757a 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -523,6 +523,16 @@ config PINCTRL_ZYNQMP This driver can also be built as a module. If so, the module will be called pinctrl-zynqmp. +config PINCTRL_MLXBF + tristate "NVIDIA BlueField-3 SoC Pinctrl driver" + depends on (MELLANOX_PLATFORM && ARM64 && ACPI) + select PINMUX + select GPIOLIB + select GPIOLIB_IRQCHIP + select GPIO_MLXBF3 + help + This selects the pinctrl driver for BlueField-3 SoCs. + source "drivers/pinctrl/actions/Kconfig" source "drivers/pinctrl/aspeed/Kconfig" source "drivers/pinctrl/bcm/Kconfig" diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index d5939840bb2a..67252469e76b 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -36,6 +36,7 @@ obj-$(CONFIG_PINCTRL_MCP23S08_I2C) += pinctrl-mcp23s08_i2c.o obj-$(CONFIG_PINCTRL_MCP23S08_SPI) += pinctrl-mcp23s08_spi.o obj-$(CONFIG_PINCTRL_MCP23S08) += pinctrl-mcp23s08.o obj-$(CONFIG_PINCTRL_MICROCHIP_SGPIO) += pinctrl-microchip-sgpio.o +obj-$(CONFIG_PINCTRL_MLXBF) += pinctrl-mlxbf.o obj-$(CONFIG_PINCTRL_OCELOT) += pinctrl-ocelot.o obj-$(CONFIG_PINCTRL_OXNAS) += pinctrl-oxnas.o obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o diff --git a/drivers/pinctrl/pinctrl-mlxbf.c b/drivers/pinctrl/pinctrl-mlxbf.c new file mode 100644 index 000000000000..405e5a906ee4 --- /dev/null +++ b/drivers/pinctrl/pinctrl-mlxbf.c @@ -0,0 +1,341 @@ +// SPDX-License-Identifier: GPL-2.0-only or BSD-3-Clause + +/* + * Copyright (C) 2022 NVIDIA CORPORATION & AFFILIATES + */ + +#include +#include + +#include +#include + +#define MLXBF_GPIO0_FW_CONTROL_SET 0 +#define MLXBF_GPIO0_FW_CONTROL_CLEAR 0x14 +#define MLXBF_GPIO1_FW_CONTROL_SET 0x80 +#define MLXBF_GPIO1_FW_CONTROL_CLEAR 0x94 + +#define MLXBF_NGPIOS_GPIO0 32 + +enum { + MLXBF_GPIO_HW_MODE, + MLXBF_GPIO_SW_MODE +}; + +struct mlxbf_pinctrl { + void __iomem *base; + struct device *dev; + struct pinctrl_dev *pctl; + struct pinctrl_gpio_range gpio_range; +}; + +#define MLXBF_GPIO_RANGE(_id, _pinbase, _gpiobase, _npins) \ + { \ + .name = "mlxbf_gpio_range", \ + .id = _id, \ + .base = _gpiobase, \ + .pin_base = _pinbase, \ + .npins = _npins, \ + } + +static struct pinctrl_gpio_range mlxbf_pinctrl_gpio_ranges[] = { + MLXBF_GPIO_RANGE(0, 0, 480, 32), + MLXBF_GPIO_RANGE(1, 32, 456, 24), +}; + +static const struct pinctrl_pin_desc mlxbf_pins[] = { + PINCTRL_PIN(0, "gpio0"), + PINCTRL_PIN(1, "gpio1"), + PINCTRL_PIN(2, "gpio2"), + PINCTRL_PIN(3, "gpio3"), + PINCTRL_PIN(4, "gpio4"), + PINCTRL_PIN(5, "gpio5"), + PINCTRL_PIN(6, "gpio6"), + PINCTRL_PIN(7, "gpio7"), + PINCTRL_PIN(8, "gpio8"), + PINCTRL_PIN(9, "gpio9"), + PINCTRL_PIN(10, "gpio10"), + PINCTRL_PIN(11, "gpio11"), + PINCTRL_PIN(12, "gpio12"), + PINCTRL_PIN(13, "gpio13"), + PINCTRL_PIN(14, "gpio14"), + PINCTRL_PIN(15, "gpio15"), + PINCTRL_PIN(16, "gpio16"), + PINCTRL_PIN(17, "gpio17"), + PINCTRL_PIN(18, "gpio18"), + PINCTRL_PIN(19, "gpio19"), + PINCTRL_PIN(20, "gpio20"), + PINCTRL_PIN(21, "gpio21"), + PINCTRL_PIN(22, "gpio22"), + PINCTRL_PIN(23, "gpio23"), + PINCTRL_PIN(24, "gpio24"), + PINCTRL_PIN(25, "gpio25"), + PINCTRL_PIN(26, "gpio26"), + PINCTRL_PIN(27, "gpio27"), + PINCTRL_PIN(28, "gpio28"), + PINCTRL_PIN(29, "gpio29"), + PINCTRL_PIN(30, "gpio30"), + PINCTRL_PIN(31, "gpio31"), + PINCTRL_PIN(32, "gpio32"), + PINCTRL_PIN(33, "gpio33"), + PINCTRL_PIN(34, "gpio34"), + PINCTRL_PIN(35, "gpio35"), + PINCTRL_PIN(36, "gpio36"), + PINCTRL_PIN(37, "gpio37"), + PINCTRL_PIN(38, "gpio38"), + PINCTRL_PIN(39, "gpio39"), + PINCTRL_PIN(40, "gpio40"), + PINCTRL_PIN(41, "gpio41"), + PINCTRL_PIN(42, "gpio42"), + PINCTRL_PIN(43, "gpio43"), + PINCTRL_PIN(44, "gpio44"), + PINCTRL_PIN(45, "gpio45"), + PINCTRL_PIN(46, "gpio46"), + PINCTRL_PIN(47, "gpio47"), + PINCTRL_PIN(48, "gpio48"), + PINCTRL_PIN(49, "gpio49"), + PINCTRL_PIN(50, "gpio50"), + PINCTRL_PIN(51, "gpio51"), + PINCTRL_PIN(52, "gpio52"), + PINCTRL_PIN(53, "gpio53"), + PINCTRL_PIN(54, "gpio54"), + PINCTRL_PIN(55, "gpio55"), +}; + +/* + * All single-pin functions can be mapped to any GPIO, however pinmux applies + * functions to pin groups and only those groups declared as supporting that + * function. To make this work we must put each pin in its own dummy group so + * that the functions can be described as applying to all pins. + * We use the same name as in the datasheet. + */ +static const char * const mlxbf_pinctrl_single_group_names[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", + "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", + "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", + "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", + "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", + "gpio35", "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", + "gpio42", "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", + "gpio49", "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55" +}; + +/* Set of pin numbers for single-pin groups */ +static const unsigned int mlxbf_pinctrl_single_group_pins[] = { + 0, 1, 2, 3, 4, 5, 6, + 7, 8, 9, 10, 11, 12, 13, + 14, 15, 16, 17, 18, 19, 20, + 21, 22, 23, 24, 25, 26, 27, + 28, 29, 30, 31, 32, 33, 34, + 35, 36, 37, 38, 39, 40, 41, + 42, 43, 44, 45, 46, 47, 48, + 49, 50, 51, 52, 53, 54, 55, +}; + +static int mlxbf_get_groups_count(struct pinctrl_dev *pctldev) +{ + /* Number single-pin groups */ + return ARRAY_SIZE(mlxbf_pinctrl_single_group_pins); +} + +static const char *mlxbf_get_group_name(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + return mlxbf_pinctrl_single_group_names[selector]; +} + +static int mlxbf_get_group_pins(struct pinctrl_dev *pctldev, + unsigned int selector, + const unsigned int **pins, + unsigned int *num_pins) +{ + /* return the dummy group for a single pin */ + *pins = &mlxbf_pinctrl_single_group_pins[selector]; + *num_pins = 1; + + return 0; +} + +static const struct pinctrl_ops mlxbf_pinctrl_group_ops = { + .get_groups_count = mlxbf_get_groups_count, + .get_group_name = mlxbf_get_group_name, + .get_group_pins = mlxbf_get_group_pins, +}; + +static const char * const mlxbf_gpiofunc_group_names[] = { "swctrl" }; +static const char * const mlxbf_hwfunc_group_names[] = { "hwctrl" }; + +/* + * Only 2 functions are supported and they apply to all pins: + * 1) Default hardware functionality + * 2) Software controlled GPIO + */ +static const struct { + const char *name; + const char * const *group_names; +} mlxbf_pmx_funcs[] = { + { + .name = "hwfunc", + .group_names = mlxbf_hwfunc_group_names + }, + { + .name = "gpiofunc", + .group_names = mlxbf_gpiofunc_group_names + }, +}; + +static int mlxbf_pmx_get_funcs_count(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(mlxbf_pmx_funcs); +} + +static const char *mlxbf_pmx_get_func_name(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + return mlxbf_pmx_funcs[selector].name; +} + +static int mlxbf_pmx_get_groups(struct pinctrl_dev *pctldev, + unsigned int selector, + const char * const **groups, + unsigned int * const num_groups) +{ + *groups = mlxbf_pmx_funcs[selector].group_names; + *num_groups = ARRAY_SIZE(mlxbf_pinctrl_single_group_pins); + + return 0; +} + +static int mlxbf_pmx_set(struct pinctrl_dev *pctldev, + unsigned int selector, + unsigned int group) +{ + struct mlxbf_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev); + + if (selector == MLXBF_GPIO_HW_MODE) { + if (group < MLXBF_NGPIOS_GPIO0) + writel(BIT(group), priv->base + MLXBF_GPIO0_FW_CONTROL_CLEAR); + else + writel(BIT(group % MLXBF_NGPIOS_GPIO0), priv->base + MLXBF_GPIO1_FW_CONTROL_CLEAR); + } + + if (selector == MLXBF_GPIO_SW_MODE) { + if (group < MLXBF_NGPIOS_GPIO0) + writel(BIT(group), priv->base + MLXBF_GPIO0_FW_CONTROL_SET); + else + writel(BIT(group % MLXBF_NGPIOS_GPIO0), priv->base + MLXBF_GPIO1_FW_CONTROL_SET); + } + + return 0; +} + +static int mlxbf_gpio_request_enable(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int offset) +{ + struct mlxbf_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev); + + if (offset < MLXBF_NGPIOS_GPIO0) + writel(BIT(offset), priv->base + MLXBF_GPIO0_FW_CONTROL_SET); + else + writel(BIT(offset % MLXBF_NGPIOS_GPIO0), priv->base + MLXBF_GPIO1_FW_CONTROL_SET); + + return 0; +} + +static void mlxbf_gpio_disable_free(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int offset) +{ + struct mlxbf_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev); + + /* disable GPIO functionality by giving control back to hardware */ + if (offset < MLXBF_NGPIOS_GPIO0) + writel(BIT(offset), priv->base + MLXBF_GPIO0_FW_CONTROL_CLEAR); + else + writel(BIT(offset % MLXBF_NGPIOS_GPIO0), priv->base + MLXBF_GPIO1_FW_CONTROL_CLEAR); + +} + +static const struct pinmux_ops mlxbf_pmx_ops = { + .get_functions_count = mlxbf_pmx_get_funcs_count, + .get_function_name = mlxbf_pmx_get_func_name, + .get_function_groups = mlxbf_pmx_get_groups, + .set_mux = mlxbf_pmx_set, + .gpio_request_enable = mlxbf_gpio_request_enable, + .gpio_disable_free = mlxbf_gpio_disable_free, +}; + +static struct pinctrl_desc mlxbf_pin_desc = { + .name = "pinctrl-mlxbf", + .pins = mlxbf_pins, + .npins = ARRAY_SIZE(mlxbf_pins), + .pctlops = &mlxbf_pinctrl_group_ops, + .pmxops = &mlxbf_pmx_ops, + .owner = THIS_MODULE, +}; + +static int mlxbf_pinctrl_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct mlxbf_pinctrl *priv; + struct resource *res; + int ret; + + BUILD_BUG_ON(ARRAY_SIZE(mlxbf_pinctrl_single_group_names) != + ARRAY_SIZE(mlxbf_pinctrl_single_group_pins)); + + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->dev = &pdev->dev; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -ENODEV; + + priv->base = devm_ioremap(dev, res->start, resource_size(res)); + if (!priv->base) + return -ENOMEM; + + ret = devm_pinctrl_register_and_init(priv->dev, + &mlxbf_pin_desc, + priv, + &priv->pctl); + if (ret) { + dev_err(priv->dev, "Failed pinctrl register (%d)\n", ret); + return ret; + } + + ret = pinctrl_enable(priv->pctl); + if (ret) { + dev_err(priv->dev, "Failed to enable pinctrl (%d)\n", ret); + return ret; + } + + pinctrl_add_gpio_range(priv->pctl, &mlxbf_pinctrl_gpio_ranges[0]); + pinctrl_add_gpio_range(priv->pctl, &mlxbf_pinctrl_gpio_ranges[1]); + + return 0; +} + +static const struct acpi_device_id mlxbf_pinctrl_acpi_ids[] = { + { "MLNXBF34", 0 }, + {}, +}; +MODULE_DEVICE_TABLE(acpi, mlxbf_pinctrl_acpi_ids); + +static struct platform_driver mlxbf_pinctrl_driver = { + .driver = { + .name = "pinctrl-mlxbf", + .acpi_match_table = mlxbf_pinctrl_acpi_ids, + }, + .probe = mlxbf_pinctrl_probe, +}; + +module_platform_driver(mlxbf_pinctrl_driver); + +MODULE_DESCRIPTION("NVIDIA pinctrl driver"); +MODULE_AUTHOR("Asmaa Mnebhi "); +MODULE_LICENSE("Dual BSD/GPL");