From patchwork Mon Feb 20 20:18:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Clark X-Patchwork-Id: 655161 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 43706C678D5 for ; Mon, 20 Feb 2023 20:19:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229885AbjBTUTz (ORCPT ); Mon, 20 Feb 2023 15:19:55 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37310 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232721AbjBTUTr (ORCPT ); Mon, 20 Feb 2023 15:19:47 -0500 Received: from mail-pj1-x1034.google.com (mail-pj1-x1034.google.com [IPv6:2607:f8b0:4864:20::1034]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9EA1020547; Mon, 20 Feb 2023 12:19:36 -0800 (PST) Received: by mail-pj1-x1034.google.com with SMTP id cp9so3603991pjb.0; Mon, 20 Feb 2023 12:19:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=uqyHMdEv/I4h+kB4S5EmXwyYyPXw9FA0QD7a4XeiZZ4=; b=qWxbi7cysynJlROyYqpT1W5K38P/2KBzlq1IDmM8LAsxKTEBy+yKtthSfCwkwQpTch bJssSD7Jm1bOfNrHo2EZ8pl9i75VI9BkwXKX6wx2OWcwSiqz+LFI4ESOB9eMaeaU+Hra UEawNS4Axf9WfdwkAE0wURqqKZ/MzmKm4VHNtQV7Fp0HSwit+2A811AMVbq/tDLcB3tG 0UYa2Z2WB3lgmlP4y39XuJ3tAdT4EzjY/f2FJHue0XlasQa8LkPliR47zFrwyAT1it7j 6zzbs6m7tGkhnFCdkXE42R75YTq2J1CFMceXM51jdtDfP9oSRPYD2AJjWKwMbz8ZDaQz HW5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uqyHMdEv/I4h+kB4S5EmXwyYyPXw9FA0QD7a4XeiZZ4=; b=CL10t5W6wiNcGehm1/zSyDDwy0fjVL5QVFB+XBzdPISwkmHuCuxZHaIJTfamuiLVy3 jg4CMfu60bS8loMymoL3wNpQYr+TWjGsYtCD+eJolvlyt4Evx998v1N+os5ophW00WKL c6Xgw4RwyTtLezcYE6Xr64Vj1d0SaePyR3q1Trh6pmOLjGP4/QYHzcK8ZFyQPJ+D0YhT b+cshl3pOr+a6GzJObJ4JNrb3mxesne2PsCtsslxVerAGDRbSbePwBGnN5g4qP1OLFbz mb1FSUBlTH5HvjTQGpI/8hWvVNdBZWeOy7uabEB82YJJOAXy+ahUBFc5mPCnGGyNIJUu pQHg== X-Gm-Message-State: AO0yUKWa+2p16YpgtDT0IwyzzoSHnIJv0nDbt5QeoY+I39S8cUI/B+ax 9npRlHXHDgFo9A9lA7RcMZE= X-Google-Smtp-Source: AK7set9MW9Ae7MZ9KibrDVZ+SbelSx7YqcKLkt2u5xbEXakFPUpi+tzyphq21rOe4G4OT1nqIYfOeA== X-Received: by 2002:a17:90b:4f4d:b0:233:e1e6:33dc with SMTP id pj13-20020a17090b4f4d00b00233e1e633dcmr1373625pjb.48.1676924375715; Mon, 20 Feb 2023 12:19:35 -0800 (PST) Received: from localhost (c-73-67-135-195.hsd1.or.comcast.net. [73.67.135.195]) by smtp.gmail.com with ESMTPSA id go6-20020a17090b03c600b00233afe09177sm1872773pjb.8.2023.02.20.12.19.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Feb 2023 12:19:34 -0800 (PST) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: freedreno@lists.freedesktop.org, Daniel Vetter , =?utf-8?q?Christian_K=C3=B6nig?= , =?utf-8?q?Michel_D=C3=A4nzer?= , Tvrtko Ursulin , Rodrigo Vivi , Alex Deucher , Pekka Paalanen , Simon Ser , Rob Clark , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Sumit Semwal , =?utf-8?q?Christian_K=C3=B6nig?= , linux-arm-msm@vger.kernel.org (open list:DRM DRIVER FOR MSM ADRENO GPU), linux-kernel@vger.kernel.org (open list), linux-media@vger.kernel.org (open list:DMA BUFFER SHARING FRAMEWORK), linaro-mm-sig@lists.linaro.org (moderated list:DMA BUFFER SHARING FRAMEWORK) Subject: [PATCH v5 12/14] drm/msm: Add deadline based boost support Date: Mon, 20 Feb 2023 12:18:59 -0800 Message-Id: <20230220201916.1822214-13-robdclark@gmail.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230220201916.1822214-1-robdclark@gmail.com> References: <20230220201916.1822214-1-robdclark@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Rob Clark Track the nearest deadline on a fence timeline and set a timer to expire shortly before to trigger boost if the fence has not yet been signaled. v2: rebase Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/msm_fence.c | 74 +++++++++++++++++++++++++++++++++ drivers/gpu/drm/msm/msm_fence.h | 20 +++++++++ 2 files changed, 94 insertions(+) diff --git a/drivers/gpu/drm/msm/msm_fence.c b/drivers/gpu/drm/msm/msm_fence.c index 56641408ea74..51b461f32103 100644 --- a/drivers/gpu/drm/msm/msm_fence.c +++ b/drivers/gpu/drm/msm/msm_fence.c @@ -8,6 +8,35 @@ #include "msm_drv.h" #include "msm_fence.h" +#include "msm_gpu.h" + +static struct msm_gpu *fctx2gpu(struct msm_fence_context *fctx) +{ + struct msm_drm_private *priv = fctx->dev->dev_private; + return priv->gpu; +} + +static enum hrtimer_restart deadline_timer(struct hrtimer *t) +{ + struct msm_fence_context *fctx = container_of(t, + struct msm_fence_context, deadline_timer); + + kthread_queue_work(fctx2gpu(fctx)->worker, &fctx->deadline_work); + + return HRTIMER_NORESTART; +} + +static void deadline_work(struct kthread_work *work) +{ + struct msm_fence_context *fctx = container_of(work, + struct msm_fence_context, deadline_work); + + /* If deadline fence has already passed, nothing to do: */ + if (msm_fence_completed(fctx, fctx->next_deadline_fence)) + return; + + msm_devfreq_boost(fctx2gpu(fctx), 2); +} struct msm_fence_context * @@ -36,6 +65,13 @@ msm_fence_context_alloc(struct drm_device *dev, volatile uint32_t *fenceptr, fctx->completed_fence = fctx->last_fence; *fctx->fenceptr = fctx->last_fence; + hrtimer_init(&fctx->deadline_timer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS); + fctx->deadline_timer.function = deadline_timer; + + kthread_init_work(&fctx->deadline_work, deadline_work); + + fctx->next_deadline = ktime_get(); + return fctx; } @@ -62,6 +98,8 @@ void msm_update_fence(struct msm_fence_context *fctx, uint32_t fence) spin_lock_irqsave(&fctx->spinlock, flags); if (fence_after(fence, fctx->completed_fence)) fctx->completed_fence = fence; + if (msm_fence_completed(fctx, fctx->next_deadline_fence)) + hrtimer_cancel(&fctx->deadline_timer); spin_unlock_irqrestore(&fctx->spinlock, flags); } @@ -92,10 +130,46 @@ static bool msm_fence_signaled(struct dma_fence *fence) return msm_fence_completed(f->fctx, f->base.seqno); } +static void msm_fence_set_deadline(struct dma_fence *fence, ktime_t deadline) +{ + struct msm_fence *f = to_msm_fence(fence); + struct msm_fence_context *fctx = f->fctx; + unsigned long flags; + ktime_t now; + + spin_lock_irqsave(&fctx->spinlock, flags); + now = ktime_get(); + + if (ktime_after(now, fctx->next_deadline) || + ktime_before(deadline, fctx->next_deadline)) { + fctx->next_deadline = deadline; + fctx->next_deadline_fence = + max(fctx->next_deadline_fence, (uint32_t)fence->seqno); + + /* + * Set timer to trigger boost 3ms before deadline, or + * if we are already less than 3ms before the deadline + * schedule boost work immediately. + */ + deadline = ktime_sub(deadline, ms_to_ktime(3)); + + if (ktime_after(now, deadline)) { + kthread_queue_work(fctx2gpu(fctx)->worker, + &fctx->deadline_work); + } else { + hrtimer_start(&fctx->deadline_timer, deadline, + HRTIMER_MODE_ABS); + } + } + + spin_unlock_irqrestore(&fctx->spinlock, flags); +} + static const struct dma_fence_ops msm_fence_ops = { .get_driver_name = msm_fence_get_driver_name, .get_timeline_name = msm_fence_get_timeline_name, .signaled = msm_fence_signaled, + .set_deadline = msm_fence_set_deadline, }; struct dma_fence * diff --git a/drivers/gpu/drm/msm/msm_fence.h b/drivers/gpu/drm/msm/msm_fence.h index 7f1798c54cd1..cdaebfb94f5c 100644 --- a/drivers/gpu/drm/msm/msm_fence.h +++ b/drivers/gpu/drm/msm/msm_fence.h @@ -52,6 +52,26 @@ struct msm_fence_context { volatile uint32_t *fenceptr; spinlock_t spinlock; + + /* + * TODO this doesn't really deal with multiple deadlines, like + * if userspace got multiple frames ahead.. OTOH atomic updates + * don't queue, so maybe that is ok + */ + + /** next_deadline: Time of next deadline */ + ktime_t next_deadline; + + /** + * next_deadline_fence: + * + * Fence value for next pending deadline. The deadline timer is + * canceled when this fence is signaled. + */ + uint32_t next_deadline_fence; + + struct hrtimer deadline_timer; + struct kthread_work deadline_work; }; struct msm_fence_context * msm_fence_context_alloc(struct drm_device *dev, From patchwork Mon Feb 20 20:19:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Clark X-Patchwork-Id: 655455 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3AEAAC6379F for ; Mon, 20 Feb 2023 20:20:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232789AbjBTUUQ (ORCPT ); Mon, 20 Feb 2023 15:20:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37380 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232837AbjBTUTv (ORCPT ); Mon, 20 Feb 2023 15:19:51 -0500 Received: from mail-pg1-x536.google.com (mail-pg1-x536.google.com [IPv6:2607:f8b0:4864:20::536]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A738A1ABC2; Mon, 20 Feb 2023 12:19:37 -0800 (PST) Received: by mail-pg1-x536.google.com with SMTP id 132so1154979pgh.13; Mon, 20 Feb 2023 12:19:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0EqwRq/t+KHhVrbIAD1sooBDZlG3nzxQWus7/my7j0s=; b=TG1L6nn0mxBlkKBusgwF9MyUCLhHqNTRGOpIiG1+g3+2tbfhq1+DgZUgf4V2KgyNra ENmsUIrjwSSr/A4fn2O9l0F3MUhpCSjJtle6DdruoB8wDezXrbM/gFxXxsBj+dKQf7wl t58P0IMFe+/PCrMmuzStSrS2BkDx3+ndckjxibW/670yzJO914kwBw1L36j4S6OBCdFX LMghJVaa4OPP2iw1qmcJ/x2VEoL4CshIZq34uHqcHASQqYllJCpFEUIWmu/aWIf191bB sXM4DUz8HMGVQHyxzvIsP3fnLQ6VDkpu2myvqfAULLrqWH82Ig+GhmOU3J7uGsCS1mde qLtA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0EqwRq/t+KHhVrbIAD1sooBDZlG3nzxQWus7/my7j0s=; b=5SUfvQGUK9cyUL5jOxtv2W08Ho7kHgvwNxDsTqxOiXQzN0p2VC6oqHqV5Obl424oSq XGvFGqzVBdi2C2JZqz/OWZOlqb4H1rEqu864kZ3bx6n5thWCtYT3R1MO20kcW1WRieg7 nDSvWYoLj+hJalDCffa/zDglgm6M45ZRCUy1UXFWWtuONS5gV72h9Oo5YWcluA1n8y35 QmPkb3E59tkYaxaawoKSYqUzbgMhI4IV/+zQgvPbH5id2vjw7st5rv+ym9A+8zPDPAsw HDbS8cMwQ5G7xrw26MtEjJb8wqkli78wrY44W/0FvSKLvbPAGUTvQnpAQHOkQWHrhu3v f4NA== X-Gm-Message-State: AO0yUKXgGg/eNz95B0WXtVt6HguU9d761DF4jDlltuxoFJ4cG25u6/qU EHlHZTeRtRD+oaCzy9CW1zM= X-Google-Smtp-Source: AK7set+G+O+g8nCJJ/07wSAUrOEukE3ArmuOtJLackiUQfQRUGS/wMiklYbmz15njHhVBhjw7Qo33g== X-Received: by 2002:a05:6a00:9b:b0:5a8:a263:7f4d with SMTP id c27-20020a056a00009b00b005a8a2637f4dmr2306138pfj.15.1676924376984; Mon, 20 Feb 2023 12:19:36 -0800 (PST) Received: from localhost (c-73-67-135-195.hsd1.or.comcast.net. [73.67.135.195]) by smtp.gmail.com with ESMTPSA id c11-20020aa781cb000000b005a8bc154bf4sm2440630pfn.39.2023.02.20.12.19.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Feb 2023 12:19:36 -0800 (PST) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: freedreno@lists.freedesktop.org, Daniel Vetter , =?utf-8?q?Christian_K=C3=B6nig?= , =?utf-8?q?Michel_D=C3=A4nzer?= , Tvrtko Ursulin , Rodrigo Vivi , Alex Deucher , Pekka Paalanen , Simon Ser , Rob Clark , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , linux-arm-msm@vger.kernel.org (open list:DRM DRIVER FOR MSM ADRENO GPU), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v5 13/14] drm/msm: Add wait-boost support Date: Mon, 20 Feb 2023 12:19:00 -0800 Message-Id: <20230220201916.1822214-14-robdclark@gmail.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230220201916.1822214-1-robdclark@gmail.com> References: <20230220201916.1822214-1-robdclark@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Rob Clark Add a way for various userspace waits to signal urgency. Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/msm_drv.c | 12 ++++++++---- drivers/gpu/drm/msm/msm_gem.c | 5 +++++ include/uapi/drm/msm_drm.h | 14 ++++++++++++-- 3 files changed, 25 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index aca48c868c14..f6764a86b2da 100644 --- a/drivers/gpu/drm/msm/msm_drv.c +++ b/drivers/gpu/drm/msm/msm_drv.c @@ -46,6 +46,7 @@ * - 1.8.0 - Add MSM_BO_CACHED_COHERENT for supported GPUs (a6xx) * - 1.9.0 - Add MSM_SUBMIT_FENCE_SN_IN * - 1.10.0 - Add MSM_SUBMIT_BO_NO_IMPLICIT + * - 1.11.0 - Add wait boost (MSM_WAIT_FENCE_BOOST, MSM_PREP_BOOST) */ #define MSM_VERSION_MAJOR 1 #define MSM_VERSION_MINOR 10 @@ -899,7 +900,7 @@ static int msm_ioctl_gem_info(struct drm_device *dev, void *data, } static int wait_fence(struct msm_gpu_submitqueue *queue, uint32_t fence_id, - ktime_t timeout) + ktime_t timeout, uint32_t flags) { struct dma_fence *fence; int ret; @@ -929,6 +930,9 @@ static int wait_fence(struct msm_gpu_submitqueue *queue, uint32_t fence_id, if (!fence) return 0; + if (flags & MSM_WAIT_FENCE_BOOST) + dma_fence_set_deadline(fence, ktime_get()); + ret = dma_fence_wait_timeout(fence, true, timeout_to_jiffies(&timeout)); if (ret == 0) { ret = -ETIMEDOUT; @@ -949,8 +953,8 @@ static int msm_ioctl_wait_fence(struct drm_device *dev, void *data, struct msm_gpu_submitqueue *queue; int ret; - if (args->pad) { - DRM_ERROR("invalid pad: %08x\n", args->pad); + if (args->flags & ~MSM_WAIT_FENCE_FLAGS) { + DRM_ERROR("invalid flags: %08x\n", args->flags); return -EINVAL; } @@ -961,7 +965,7 @@ static int msm_ioctl_wait_fence(struct drm_device *dev, void *data, if (!queue) return -ENOENT; - ret = wait_fence(queue, args->fence, to_ktime(args->timeout)); + ret = wait_fence(queue, args->fence, to_ktime(args->timeout), args->flags); msm_submitqueue_put(queue); diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/msm/msm_gem.c index 1dee0d18abbb..dd4a0d773f6e 100644 --- a/drivers/gpu/drm/msm/msm_gem.c +++ b/drivers/gpu/drm/msm/msm_gem.c @@ -846,6 +846,11 @@ int msm_gem_cpu_prep(struct drm_gem_object *obj, uint32_t op, ktime_t *timeout) op & MSM_PREP_NOSYNC ? 0 : timeout_to_jiffies(timeout); long ret; + if (op & MSM_PREP_BOOST) { + dma_resv_set_deadline(obj->resv, dma_resv_usage_rw(write), + ktime_get()); + } + ret = dma_resv_wait_timeout(obj->resv, dma_resv_usage_rw(write), true, remain); if (ret == 0) diff --git a/include/uapi/drm/msm_drm.h b/include/uapi/drm/msm_drm.h index 329100016e7c..dbf0d6f43fa9 100644 --- a/include/uapi/drm/msm_drm.h +++ b/include/uapi/drm/msm_drm.h @@ -151,8 +151,13 @@ struct drm_msm_gem_info { #define MSM_PREP_READ 0x01 #define MSM_PREP_WRITE 0x02 #define MSM_PREP_NOSYNC 0x04 +#define MSM_PREP_BOOST 0x08 -#define MSM_PREP_FLAGS (MSM_PREP_READ | MSM_PREP_WRITE | MSM_PREP_NOSYNC) +#define MSM_PREP_FLAGS (MSM_PREP_READ | \ + MSM_PREP_WRITE | \ + MSM_PREP_NOSYNC | \ + MSM_PREP_BOOST | \ + 0) struct drm_msm_gem_cpu_prep { __u32 handle; /* in */ @@ -286,6 +291,11 @@ struct drm_msm_gem_submit { }; +#define MSM_WAIT_FENCE_BOOST 0x00000001 +#define MSM_WAIT_FENCE_FLAGS ( \ + MSM_WAIT_FENCE_BOOST | \ + 0) + /* The normal way to synchronize with the GPU is just to CPU_PREP on * a buffer if you need to access it from the CPU (other cmdstream * submission from same or other contexts, PAGE_FLIP ioctl, etc, all @@ -295,7 +305,7 @@ struct drm_msm_gem_submit { */ struct drm_msm_wait_fence { __u32 fence; /* in */ - __u32 pad; + __u32 flags; /* in, bitmask of MSM_WAIT_FENCE_x */ struct drm_msm_timespec timeout; /* in */ __u32 queueid; /* in, submitqueue id */ };