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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id f3-20020a170902e98300b0019141c79b1dsm8559328plb.254.2023.02.20.18.19.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Feb 2023 18:19:56 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Fabiano Rosas Subject: [PATCH v2 01/14] target/arm: Normalize aarch64 gdbstub get/set function names Date: Mon, 20 Feb 2023 16:19:38 -1000 Message-Id: <20230221021951.453601-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230221021951.453601-1-richard.henderson@linaro.org> References: <20230221021951.453601-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Make the form of the function names between fp and sve the same: - arm_gdb_*_svereg -> aarch64_gdb_*_sve_reg. - aarch64_fpu_gdb_*_reg -> aarch64_gdb_*_fpu_reg. Reviewed-by: Fabiano Rosas Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- target/arm/internals.h | 8 ++++---- target/arm/gdbstub.c | 9 +++++---- target/arm/gdbstub64.c | 8 ++++---- 3 files changed, 13 insertions(+), 12 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 759b70c646..121ecd420b 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1326,10 +1326,10 @@ static inline uint64_t pmu_counter_mask(CPUARMState *env) } #ifdef TARGET_AARCH64 -int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg); -int arm_gdb_set_svereg(CPUARMState *env, uint8_t *buf, int reg); -int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg); -int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg); +int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg); +int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg); +int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg); +int aarch64_gdb_set_fpu_reg(CPUARMState *env, uint8_t *buf, int reg); void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp); void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp); void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp); diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index 2f806512d0..cf1c01e3cf 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -466,12 +466,13 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) */ #ifdef TARGET_AARCH64 if (isar_feature_aa64_sve(&cpu->isar)) { - gdb_register_coprocessor(cs, arm_gdb_get_svereg, arm_gdb_set_svereg, - arm_gen_dynamic_svereg_xml(cs, cs->gdb_num_regs), + int nreg = arm_gen_dynamic_svereg_xml(cs, cs->gdb_num_regs); + gdb_register_coprocessor(cs, aarch64_gdb_get_sve_reg, + aarch64_gdb_set_sve_reg, nreg, "sve-registers.xml", 0); } else { - gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg, - aarch64_fpu_gdb_set_reg, + gdb_register_coprocessor(cs, aarch64_gdb_get_fpu_reg, + aarch64_gdb_set_fpu_reg, 34, "aarch64-fpu.xml", 0); } #endif diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index 07a6746944..c598cb0375 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -72,7 +72,7 @@ int aarch64_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) return 0; } -int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg) +int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg) { switch (reg) { case 0 ... 31: @@ -92,7 +92,7 @@ int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg) } } -int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) +int aarch64_gdb_set_fpu_reg(CPUARMState *env, uint8_t *buf, int reg) { switch (reg) { case 0 ... 31: @@ -116,7 +116,7 @@ int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) } } -int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg) +int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg) { ARMCPU *cpu = env_archcpu(env); @@ -164,7 +164,7 @@ int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg) return 0; } -int arm_gdb_set_svereg(CPUARMState *env, uint8_t *buf, int reg) +int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg) { ARMCPU *cpu = env_archcpu(env); From patchwork Tue Feb 21 02:19:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 655341 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcd:0:0:0:0:0 with SMTP id e13csp1724940wrc; Mon, 20 Feb 2023 18:21:39 -0800 (PST) X-Google-Smtp-Source: AK7set9no9V59PE6bFt4IQtmzRe1NydbJnHGPVVrPk77b0uwHEaR0jVPk+HjVfjGNen4lzfKoB11 X-Received: by 2002:a05:622a:5cb:b0:3ba:18c2:99e7 with SMTP id d11-20020a05622a05cb00b003ba18c299e7mr20831972qtb.45.1676946098940; Mon, 20 Feb 2023 18:21:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676946098; cv=none; d=google.com; s=arc-20160816; b=QhBS+whFijT31FRdhFpG9jOTnwUaNtgL3kRAJbxhlLh3dLjen9OpxTbfFcpWXfT9XV jp0o63Sxf0IsW8DdRwJoTk6lAdVxzN5cN90FIrQwzGVnfsvViJD2m/0/oWSmzYxViA8T 1rQvzLj87tGQdNMlbTy7lQt92BdkLvmUzRxKIGjiaD0WklNvPsleTf1E6AB/siyf0+ew 6ACJreMYGWaX12FIUIazFRCOZfhctxrSMRXua0+vwhrRJLtYBHoo2Eh7Qsz5IFsyZ9DG ASMTikuaRXO3w0eK03rlJaI2hM8pWATxYr6Xz15sE3BZ6Xk/MUD2znL7GZUpqOj1clGm 5Ang== ARC-Message-Signature: i=1; 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id f3-20020a170902e98300b0019141c79b1dsm8559328plb.254.2023.02.20.18.19.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Feb 2023 18:19:57 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Fabiano Rosas Subject: [PATCH v2 02/14] target/arm: Unexport arm_gen_dynamic_sysreg_xml Date: Mon, 20 Feb 2023 16:19:39 -1000 Message-Id: <20230221021951.453601-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230221021951.453601-1-richard.henderson@linaro.org> References: <20230221021951.453601-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This function is not used outside gdbstub.c. Reviewed-by: Fabiano Rosas Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- target/arm/cpu.h | 1 - target/arm/gdbstub.c | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 12b1082537..32ca6c9a0d 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1116,7 +1116,6 @@ int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); * Helpers to dynamically generates XML descriptions of the sysregs * and SVE registers. Returns the number of registers in each set. */ -int arm_gen_dynamic_sysreg_xml(CPUState *cpu, int base_reg); int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg); /* Returns the dynamically generated XML for the gdb stub. diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index cf1c01e3cf..52581e9784 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -305,7 +305,7 @@ static void arm_register_sysreg_for_xml(gpointer key, gpointer value, } } -int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg) +static int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg) { ARMCPU *cpu = ARM_CPU(cs); GString *s = g_string_new(NULL); From patchwork Tue Feb 21 02:19:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 655344 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcd:0:0:0:0:0 with SMTP id e13csp1725056wrc; Mon, 20 Feb 2023 18:21:57 -0800 (PST) X-Google-Smtp-Source: AK7set+ks5aPLCV7nQbgxOQ5n7cuv3sB4b+jJC6XD7wqyj1rIGlU2iMd1rW6okend6nErKVSa44/ X-Received: by 2002:ac8:5dc9:0:b0:3a8:20fd:7111 with SMTP id e9-20020ac85dc9000000b003a820fd7111mr17626875qtx.39.1676946116926; Mon, 20 Feb 2023 18:21:56 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676946116; cv=none; d=google.com; s=arc-20160816; b=t7viPbi2QcLlEpahjh19SscI1wYB9YAXAMGh7ljNusrjFc6piFpDW/7cJBYzIXD4vL sbI07MOTEqPn/UUkFNC7xDnmznDaUx7F+96vsOwKWY3Evg0KJaclOozQCYKqVKVm1F+c he9esY/2ry4rvUCXFAxGmKt6Ndx3byAIgkg0CbZgN9l+/tDXMDvK4I9tDuEduWS+IsIV p1ZCtVSsCeueFOreJVx2+qvhnIHpJf2VKfZUJ+dm7IP2NHJYYoYNsX2rTszlETJzpNIv fPSWdV0sFy2xdjgnNMP7hBq6Z3KECgDEAWjpp4AGpGzngX2Cmc6yGTI4866yblhV0t0y bfjA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=ggdqj3TP81zF9AJLhqzoDLwtgovOZJuMr88Ei9wR7CM=; b=Y0fNJgrJZMpZEmU+i520sK42IJyhcpXOVqEAC30M3n12x24Ngiz1ak+sp+tt/yY19/ 1hzZxgrNEtYFS+Ht87dqUiJa8KK9Gu9y1p05G5oslueLv9+WzMc2WFQepWQ42YKjkmxy NiI7RxRVakycPsQMAy4bhU1WyqKl06fF00Wd6cbPv1IR3Xcv2/teNS/G532v36CvI7oX AVEnG1IuvIK1qIW9KNsq/RY5AGe/Nh5Lzt88IWWsR/3tRONokFnSqeZeV7jZm6YOhgei ZIoUfBYadJW9dojF8kExgCfSde+Rplbgsdok+6X4dgbc9sf3RohDGF6WVU+krD2iVScy KQ3g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=bgWpgiDx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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(rrcs-173-198-77-218.west.biz.rr.com. [173.198.77.218]) by smtp.gmail.com with ESMTPSA id f3-20020a170902e98300b0019141c79b1dsm8559328plb.254.2023.02.20.18.19.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Feb 2023 18:19:59 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Fabiano Rosas Subject: [PATCH v2 03/14] target/arm: Move arm_gen_dynamic_svereg_xml to gdbstub64.c Date: Mon, 20 Feb 2023 16:19:40 -1000 Message-Id: <20230221021951.453601-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230221021951.453601-1-richard.henderson@linaro.org> References: <20230221021951.453601-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The function is only used for aarch64, so move it to the file that has the other aarch64 gdbstub stuff. Move the declaration to internals.h. Reviewed-by: Fabiano Rosas Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- target/arm/cpu.h | 6 --- target/arm/internals.h | 1 + target/arm/gdbstub.c | 120 ----------------------------------------- target/arm/gdbstub64.c | 118 ++++++++++++++++++++++++++++++++++++++++ 4 files changed, 119 insertions(+), 126 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 32ca6c9a0d..059fe62eaa 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1112,12 +1112,6 @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); -/* - * Helpers to dynamically generates XML descriptions of the sysregs - * and SVE registers. Returns the number of registers in each set. - */ -int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg); - /* Returns the dynamically generated XML for the gdb stub. * Returns a pointer to the XML contents for the specified XML file or NULL * if the XML name doesn't match the predefined one. diff --git a/target/arm/internals.h b/target/arm/internals.h index 121ecd420b..32b8562cbf 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1326,6 +1326,7 @@ static inline uint64_t pmu_counter_mask(CPUARMState *env) } #ifdef TARGET_AARCH64 +int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg); int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg); int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg); int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg); diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index 52581e9784..bf8aff7824 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -322,126 +322,6 @@ static int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg) return cpu->dyn_sysreg_xml.num; } -struct TypeSize { - const char *gdb_type; - int size; - const char sz, suffix; -}; - -static const struct TypeSize vec_lanes[] = { - /* quads */ - { "uint128", 128, 'q', 'u' }, - { "int128", 128, 'q', 's' }, - /* 64 bit */ - { "ieee_double", 64, 'd', 'f' }, - { "uint64", 64, 'd', 'u' }, - { "int64", 64, 'd', 's' }, - /* 32 bit */ - { "ieee_single", 32, 's', 'f' }, - { "uint32", 32, 's', 'u' }, - { "int32", 32, 's', 's' }, - /* 16 bit */ - { "ieee_half", 16, 'h', 'f' }, - { "uint16", 16, 'h', 'u' }, - { "int16", 16, 'h', 's' }, - /* bytes */ - { "uint8", 8, 'b', 'u' }, - { "int8", 8, 'b', 's' }, -}; - - -int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg) -{ - ARMCPU *cpu = ARM_CPU(cs); - GString *s = g_string_new(NULL); - DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml; - g_autoptr(GString) ts = g_string_new(""); - int i, j, bits, reg_width = (cpu->sve_max_vq * 128); - info->num = 0; - g_string_printf(s, ""); - g_string_append_printf(s, ""); - g_string_append_printf(s, ""); - - /* First define types and totals in a whole VL */ - for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) { - int count = reg_width / vec_lanes[i].size; - g_string_printf(ts, "svev%c%c", vec_lanes[i].sz, vec_lanes[i].suffix); - g_string_append_printf(s, - "", - ts->str, vec_lanes[i].gdb_type, count); - } - /* - * Now define a union for each size group containing unsigned and - * signed and potentially float versions of each size from 128 to - * 8 bits. - */ - for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) { - const char suf[] = { 'q', 'd', 's', 'h', 'b' }; - g_string_append_printf(s, "", suf[i]); - for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) { - if (vec_lanes[j].size == bits) { - g_string_append_printf(s, "", - vec_lanes[j].suffix, - vec_lanes[j].sz, vec_lanes[j].suffix); - } - } - g_string_append(s, ""); - } - /* And now the final union of unions */ - g_string_append(s, ""); - for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) { - const char suf[] = { 'q', 'd', 's', 'h', 'b' }; - g_string_append_printf(s, "", - suf[i], suf[i]); - } - g_string_append(s, ""); - - /* Finally the sve prefix type */ - g_string_append_printf(s, - "", - reg_width / 8); - - /* Then define each register in parts for each vq */ - for (i = 0; i < 32; i++) { - g_string_append_printf(s, - "", - i, reg_width, base_reg++); - info->num++; - } - /* fpscr & status registers */ - g_string_append_printf(s, "", base_reg++); - g_string_append_printf(s, "", base_reg++); - info->num += 2; - - for (i = 0; i < 16; i++) { - g_string_append_printf(s, - "", - i, cpu->sve_max_vq * 16, base_reg++); - info->num++; - } - g_string_append_printf(s, - "", - cpu->sve_max_vq * 16, base_reg++); - g_string_append_printf(s, - "", - base_reg++); - info->num += 2; - g_string_append_printf(s, ""); - cpu->dyn_svereg_xml.desc = g_string_free(s, false); - - return cpu->dyn_svereg_xml.num; -} - - const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) { ARMCPU *cpu = ARM_CPU(cs); diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index c598cb0375..59fb5465d5 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -209,3 +209,121 @@ int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg) return 0; } + +struct TypeSize { + const char *gdb_type; + short size; + char sz, suffix; +}; + +static const struct TypeSize vec_lanes[] = { + /* quads */ + { "uint128", 128, 'q', 'u' }, + { "int128", 128, 'q', 's' }, + /* 64 bit */ + { "ieee_double", 64, 'd', 'f' }, + { "uint64", 64, 'd', 'u' }, + { "int64", 64, 'd', 's' }, + /* 32 bit */ + { "ieee_single", 32, 's', 'f' }, + { "uint32", 32, 's', 'u' }, + { "int32", 32, 's', 's' }, + /* 16 bit */ + { "ieee_half", 16, 'h', 'f' }, + { "uint16", 16, 'h', 'u' }, + { "int16", 16, 'h', 's' }, + /* bytes */ + { "uint8", 8, 'b', 'u' }, + { "int8", 8, 'b', 's' }, +}; + +int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg) +{ + ARMCPU *cpu = ARM_CPU(cs); + GString *s = g_string_new(NULL); + DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml; + g_autoptr(GString) ts = g_string_new(""); + int i, j, bits, reg_width = (cpu->sve_max_vq * 128); + info->num = 0; + g_string_printf(s, ""); + g_string_append_printf(s, ""); + g_string_append_printf(s, ""); + + /* First define types and totals in a whole VL */ + for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) { + int count = reg_width / vec_lanes[i].size; + g_string_printf(ts, "svev%c%c", vec_lanes[i].sz, vec_lanes[i].suffix); + g_string_append_printf(s, + "", + ts->str, vec_lanes[i].gdb_type, count); + } + /* + * Now define a union for each size group containing unsigned and + * signed and potentially float versions of each size from 128 to + * 8 bits. + */ + for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) { + const char suf[] = { 'q', 'd', 's', 'h', 'b' }; + g_string_append_printf(s, "", suf[i]); + for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) { + if (vec_lanes[j].size == bits) { + g_string_append_printf(s, "", + vec_lanes[j].suffix, + vec_lanes[j].sz, vec_lanes[j].suffix); + } + } + g_string_append(s, ""); + } + /* And now the final union of unions */ + g_string_append(s, ""); + for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) { + const char suf[] = { 'q', 'd', 's', 'h', 'b' }; + g_string_append_printf(s, "", + suf[i], suf[i]); + } + g_string_append(s, ""); + + /* Finally the sve prefix type */ + g_string_append_printf(s, + "", + reg_width / 8); + + /* Then define each register in parts for each vq */ + for (i = 0; i < 32; i++) { + g_string_append_printf(s, + "", + i, reg_width, base_reg++); + info->num++; + } + /* fpscr & status registers */ + g_string_append_printf(s, "", base_reg++); + g_string_append_printf(s, "", base_reg++); + info->num += 2; + + for (i = 0; i < 16; i++) { + g_string_append_printf(s, + "", + i, cpu->sve_max_vq * 16, base_reg++); + info->num++; + } + g_string_append_printf(s, + "", + cpu->sve_max_vq * 16, base_reg++); + g_string_append_printf(s, + "", + base_reg++); + info->num += 2; + g_string_append_printf(s, ""); + info->desc = g_string_free(s, false); + + return info->num; +} From patchwork Tue Feb 21 02:19:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 655342 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcd:0:0:0:0:0 with SMTP id e13csp1724944wrc; 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id f3-20020a170902e98300b0019141c79b1dsm8559328plb.254.2023.02.20.18.19.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Feb 2023 18:20:00 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Fabiano Rosas , Peter Maydell Subject: [PATCH v2 04/14] target/arm: Split out output_vector_union_type Date: Mon, 20 Feb 2023 16:19:41 -1000 Message-Id: <20230221021951.453601-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230221021951.453601-1-richard.henderson@linaro.org> References: <20230221021951.453601-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Create a subroutine for creating the union of unions of the various type sizes that a vector may contain. Reviewed-by: Fabiano Rosas Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/gdbstub64.c | 83 +++++++++++++++++++++++------------------- 1 file changed, 45 insertions(+), 38 deletions(-) diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index 59fb5465d5..811833d8de 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -210,44 +210,39 @@ int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg) return 0; } -struct TypeSize { - const char *gdb_type; - short size; - char sz, suffix; -}; - -static const struct TypeSize vec_lanes[] = { - /* quads */ - { "uint128", 128, 'q', 'u' }, - { "int128", 128, 'q', 's' }, - /* 64 bit */ - { "ieee_double", 64, 'd', 'f' }, - { "uint64", 64, 'd', 'u' }, - { "int64", 64, 'd', 's' }, - /* 32 bit */ - { "ieee_single", 32, 's', 'f' }, - { "uint32", 32, 's', 'u' }, - { "int32", 32, 's', 's' }, - /* 16 bit */ - { "ieee_half", 16, 'h', 'f' }, - { "uint16", 16, 'h', 'u' }, - { "int16", 16, 'h', 's' }, - /* bytes */ - { "uint8", 8, 'b', 'u' }, - { "int8", 8, 'b', 's' }, -}; - -int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg) +static void output_vector_union_type(GString *s, int reg_width) { - ARMCPU *cpu = ARM_CPU(cs); - GString *s = g_string_new(NULL); - DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml; + struct TypeSize { + const char *gdb_type; + short size; + char sz, suffix; + }; + + static const struct TypeSize vec_lanes[] = { + /* quads */ + { "uint128", 128, 'q', 'u' }, + { "int128", 128, 'q', 's' }, + /* 64 bit */ + { "ieee_double", 64, 'd', 'f' }, + { "uint64", 64, 'd', 'u' }, + { "int64", 64, 'd', 's' }, + /* 32 bit */ + { "ieee_single", 32, 's', 'f' }, + { "uint32", 32, 's', 'u' }, + { "int32", 32, 's', 's' }, + /* 16 bit */ + { "ieee_half", 16, 'h', 'f' }, + { "uint16", 16, 'h', 'u' }, + { "int16", 16, 'h', 's' }, + /* bytes */ + { "uint8", 8, 'b', 'u' }, + { "int8", 8, 'b', 's' }, + }; + + static const char suf[] = { 'q', 'd', 's', 'h', 'b' }; + g_autoptr(GString) ts = g_string_new(""); - int i, j, bits, reg_width = (cpu->sve_max_vq * 128); - info->num = 0; - g_string_printf(s, ""); - g_string_append_printf(s, ""); - g_string_append_printf(s, ""); + int i, j, bits; /* First define types and totals in a whole VL */ for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) { @@ -263,7 +258,6 @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg) * 8 bits. */ for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) { - const char suf[] = { 'q', 'd', 's', 'h', 'b' }; g_string_append_printf(s, "", suf[i]); for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) { if (vec_lanes[j].size == bits) { @@ -277,11 +271,24 @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg) /* And now the final union of unions */ g_string_append(s, ""); for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) { - const char suf[] = { 'q', 'd', 's', 'h', 'b' }; g_string_append_printf(s, "", suf[i], suf[i]); } g_string_append(s, ""); +} + +int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg) +{ + ARMCPU *cpu = ARM_CPU(cs); + GString *s = g_string_new(NULL); + DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml; + int i, reg_width = (cpu->sve_max_vq * 128); + info->num = 0; + g_string_printf(s, ""); + g_string_append_printf(s, ""); + g_string_append_printf(s, ""); + + output_vector_union_type(s, reg_width); /* Finally the sve prefix type */ g_string_append_printf(s, From patchwork Tue Feb 21 02:19:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 655338 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcd:0:0:0:0:0 with SMTP id e13csp1724758wrc; Mon, 20 Feb 2023 18:21:09 -0800 (PST) X-Google-Smtp-Source: AK7set+xNPuGirms/oIe3MZBXfF1EKOV8yr0CeG2fz2dOsPVTJvK9i3GPT9fRsvMUaUTM0ZQXNtZ X-Received: by 2002:a05:622a:14cc:b0:3bf:a01f:6f50 with SMTP id u12-20020a05622a14cc00b003bfa01f6f50mr1857105qtx.52.1676946068866; Mon, 20 Feb 2023 18:21:08 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676946068; cv=none; d=google.com; s=arc-20160816; b=tBYam3D648jSOeo5REwuub2LzqBOYBUPmvTS44ritBxGLyDY5rkK2FBMgEJtLGoAKG 5TB5B7Eb+UrSN2SPVj3DqL13IfK37139gGK8ZGYLU/0ARH56vKY1KtSNM8aLuxTqZ4gJ 4WMZypIRHz+kKqGnegvSHmNUsxaz4j2Lyl4mP5bp2MFTzRUZILZA/FlEmYPKaceIFe6K 73RpNHc9lPGBQ8mJVd7wbPT2vSI8lGcQqhgazLKR39DbElZvd/wD3A6MyyU9Nd4BGol7 K6VMcZXf7V9wZB4wosgIIdeeKepGNILV/EqJVyWugXT46iOX20ddHY64A7HivgcdoMJc lrbg== ARC-Message-Signature: i=1; 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id f3-20020a170902e98300b0019141c79b1dsm8559328plb.254.2023.02.20.18.20.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Feb 2023 18:20:02 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 05/14] target/arm: Simplify register counting in arm_gen_dynamic_svereg_xml Date: Mon, 20 Feb 2023 16:19:42 -1000 Message-Id: <20230221021951.453601-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230221021951.453601-1-richard.henderson@linaro.org> References: <20230221021951.453601-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Rather than increment base_reg and num, compute num from the change to base_reg at the end. Clean up some nearby comments. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- target/arm/gdbstub64.c | 27 ++++++++++++++++----------- 1 file changed, 16 insertions(+), 11 deletions(-) diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index 811833d8de..070ba20d99 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -277,32 +277,35 @@ static void output_vector_union_type(GString *s, int reg_width) g_string_append(s, ""); } -int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg) +int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg) { ARMCPU *cpu = ARM_CPU(cs); GString *s = g_string_new(NULL); DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml; - int i, reg_width = (cpu->sve_max_vq * 128); - info->num = 0; + int reg_width = cpu->sve_max_vq * 128; + int base_reg = orig_base_reg; + int i; + g_string_printf(s, ""); g_string_append_printf(s, ""); g_string_append_printf(s, ""); + /* Create the vector union type. */ output_vector_union_type(s, reg_width); - /* Finally the sve prefix type */ + /* Create the predicate vector type. */ g_string_append_printf(s, "", reg_width / 8); - /* Then define each register in parts for each vq */ + /* Define the vector registers. */ for (i = 0; i < 32; i++) { g_string_append_printf(s, "", i, reg_width, base_reg++); - info->num++; } + /* fpscr & status registers */ g_string_append_printf(s, "", base_reg++); - info->num += 2; + /* Define the predicate registers. */ for (i = 0; i < 16; i++) { g_string_append_printf(s, "", i, cpu->sve_max_vq * 16, base_reg++); - info->num++; } g_string_append_printf(s, "", cpu->sve_max_vq * 16, base_reg++); + + /* Define the vector length pseudo-register. */ g_string_append_printf(s, "", base_reg++); - info->num += 2; - g_string_append_printf(s, ""); - info->desc = g_string_free(s, false); + g_string_append_printf(s, ""); + + info->desc = g_string_free(s, false); + info->num = base_reg - orig_base_reg; return info->num; } From patchwork Tue Feb 21 02:19:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 655349 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcd:0:0:0:0:0 with SMTP id e13csp1725303wrc; Mon, 20 Feb 2023 18:22:40 -0800 (PST) X-Google-Smtp-Source: AK7set8+3ofrC4wiBGj/QtftnGl0mWloy57ZfxTe2lED3nstU34uJUqBmDHuXRvFTFfnlkw7MuHZ X-Received: by 2002:ac8:5c02:0:b0:3b8:4cba:e26e with SMTP id i2-20020ac85c02000000b003b84cbae26emr18484792qti.51.1676946160773; Mon, 20 Feb 2023 18:22:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676946160; cv=none; d=google.com; s=arc-20160816; b=xN5/Tc31Pz1ex0padefGfWBWorbQTdcFPAiWuk+yIkfSB1fDG2nJ7ebIBj1ioMMC7l 7sbtNnscmYo5DuIkgeJ+8Ui3QcUnd7uyqJ8OMfyKuN1rG84wc9uvIrL0wNglykY7QLDA vR2O26Rkh0vjB+nYYJnrhJSkwC9bUSOo2d3QiykHNfdYTq4wlVyY3leYeAgGVY+zS98K 64qrk7CNRB6NWXeLpc9uhtrnFnniW4iQzRMyXCjq/RxM+F4K1ol8o15Bw+r5vWW46y2M /cDRd1DW5pzk6UfMPk0XSw94yvS0I9iuXPEOaSzkkBY/oExoT+iUnROvYAgB0PktDHql y1wA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=KtfS729W8SNygqiwUg2I8CHVdzajfLrBoTMYCRIqeSU=; b=YBMg3OztuAhqInHEiPcXCRczRfB3t8i0x9W0wF9t/boCS2QPLWqzqoaxQDw8oAKq/H iRrnqq05rV+oJ8wb4RI88DyOA8jGIb3QW/ygT2FjhRsMLkryLcx+lvz2hnPoDkvPiKFL 4PhgL1PY7QpKAwNm4NrtS26lev9ri6vGHikF1365IqEQIUWGMbk2n9Um+u9EKWMt8yIA ieMq7WtlY/gkv5rVQV1SHoGUTUIllSy2+eh2Iunj1d3NaSqDkoJvB+fu8wPCSW0Eq0RH oRFq2xlkDHPj8g0NbPyk9E+r5yTVojug3ZqBhEOmOTd2LbtVNvHH+hc/3vvSAEGnUcOR IzJg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GgcWGFyF; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id f3-20020a170902e98300b0019141c79b1dsm8559328plb.254.2023.02.20.18.20.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Feb 2023 18:20:03 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Fabiano Rosas Subject: [PATCH v2 06/14] target/arm: Hoist pred_width in arm_gen_dynamic_svereg_xml Date: Mon, 20 Feb 2023 16:19:43 -1000 Message-Id: <20230221021951.453601-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230221021951.453601-1-richard.henderson@linaro.org> References: <20230221021951.453601-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Reviewed-by: Fabiano Rosas Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- target/arm/gdbstub64.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index 070ba20d99..895e19f084 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -283,6 +283,7 @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg) GString *s = g_string_new(NULL); DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml; int reg_width = cpu->sve_max_vq * 128; + int pred_width = cpu->sve_max_vq * 16; int base_reg = orig_base_reg; int i; @@ -319,13 +320,13 @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg) g_string_append_printf(s, "", - i, cpu->sve_max_vq * 16, base_reg++); + i, pred_width, base_reg++); } g_string_append_printf(s, "", - cpu->sve_max_vq * 16, base_reg++); + pred_width, base_reg++); /* Define the vector length pseudo-register. */ g_string_append_printf(s, From patchwork Tue Feb 21 02:19:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 655352 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcd:0:0:0:0:0 with SMTP id e13csp1725383wrc; Mon, 20 Feb 2023 18:22:55 -0800 (PST) X-Google-Smtp-Source: AK7set9YHnrDP05PpC2Dq52aL2D5hZuEJBY/k4kbs6Jr8LmsIEATdj0sjshZgLirnZY3f2jcKh7T X-Received: by 2002:a05:6214:c87:b0:56e:a832:928 with SMTP id r7-20020a0562140c8700b0056ea8320928mr3976189qvr.24.1676946174907; Mon, 20 Feb 2023 18:22:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676946174; cv=none; d=google.com; s=arc-20160816; b=hywwtojdGTDPHKVF7/CsOYldzfKpPKesj7WYpuJcg+ZRKlrxBuzdBE+XdUdsQ9/CKo UlfMf8FunByRBnDgVlm0zw69YH08MtTDQOYXRBLdENHcMfyFqm7ZpFL0c2j8wpXGHjzA YY0RhbMQpj3+PiZkR59isIGu3tBF6xdjRBi9Zir58Un8/p8saGHchuZ4F+s33ZUHaL/9 NGke3J1K+r/tgAOpzCyonIMTULIc+HrfaNHRExkbHqOqgeC44Ev4KgH63W60NPl7MFdH 3oxM/GJN69rDXpQWw3olqlBkQyafxyycyOIJqQt0cBaUg6XUEkvqmMWNCLPh02ggj9oQ savQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=atup5JzD1u28pHb0Z+S8hkpRI38cVehaAA91hoO5SKs=; b=vUl7rpWy9ItmvFG4NRwcLrxw4HFW3iNz4Kf/6pQICPcJpxy2jyvniPHPze6RoXQ9sU 2/aTUN8XGSYw4YeUvffwEkCLNseJgDbfz3LdZB+YLSiCkoF7yucSx1OOA8PoHSU7dTlR EvAafm4+jzg5hKgY6kovRsfwfJCMNSCiLViOlL0+1AI3my3uCicEZg0vzANSIO6r4kZ7 iadNcOCxkCEEK30awX3Og10VWSnonZU+y+598fVqMpp4tWffWt5ZinmOkDMRK8Uukb+D S2Ahf6mLK8PaxN4s25eEL87dbZK7LJ0M6KKHa74IxIyrnoBcYUjBFEsa/qBW5CxRgK2N 39cA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Knk1M/Jd"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id f3-20020a170902e98300b0019141c79b1dsm8559328plb.254.2023.02.20.18.20.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Feb 2023 18:20:05 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v2 07/14] target/arm: Fix svep width in arm_gen_dynamic_svereg_xml Date: Mon, 20 Feb 2023 16:19:44 -1000 Message-Id: <20230221021951.453601-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230221021951.453601-1-richard.henderson@linaro.org> References: <20230221021951.453601-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Define svep based on the size of the predicates, not the primary vector registers. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/gdbstub64.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index 895e19f084..d0e1305f6f 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -297,7 +297,7 @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg) /* Create the predicate vector type. */ g_string_append_printf(s, "", - reg_width / 8); + pred_width / 8); /* Define the vector registers. */ for (i = 0; i < 32; i++) { From patchwork Tue Feb 21 02:19:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 655339 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcd:0:0:0:0:0 with SMTP id e13csp1724761wrc; Mon, 20 Feb 2023 18:21:09 -0800 (PST) X-Google-Smtp-Source: AK7set8w9MVZRN0e7I1Z9dec1fr8Q/LLFLRnY4GW78qoRbYtVKJe+PNnG51BiqMESa5zLJD0ANEl X-Received: by 2002:ad4:5bef:0:b0:570:ae8a:f34 with SMTP id k15-20020ad45bef000000b00570ae8a0f34mr3217664qvc.21.1676946069026; Mon, 20 Feb 2023 18:21:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676946069; cv=none; d=google.com; s=arc-20160816; b=zOK6N+tL9ijXyQMP+makhnz2PUkjnAnQChvcdHFar+P4fRM1enDjupzKARE1/6ujNV fqzJS5enmX/19uMK1iAqDCbagBNK1zZIi5KFkDZF6uAhLSHsA0m11WG5c4yz277Gs1+y qobbCR1i262xw8omlWN5DcWXR/em6PCnp88fL6vTNotYL5RuclRqyYKfYXo9mYwQeEKO JoKeS5JpL54PEj1nrisGt1hvV4AvfbEHFJQRnlPvETjeH1PelqUe59Hxf8J9HBP7BG0c Q7J84N06a4RZpm91I0xBROmRULSik09/mA1WdwqZtTmiZUkGS23P2nzYPCC7jNdlfJW0 6zKQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=cGmftzbsAcVY0beQah1Rt/jBjqLnvx4GYi9E+DOFsUs=; b=0gVIrgziBa9w7tzvNmWfKLKwd+vbVbrZ5ZCgoznF9bSJNKR3qSRe4wpJneVMKxLUlJ RPad+L9bBmMeDiEEnKz1xi9VbLe/hqh166CnnMvm5rhf2SmL3DzWPmXuLJ0K6RGOe7wJ xJPYfiktjbZ4PkINw+w8rzLlDGJNTlzkVTo8lMiHThN44rRfo8qozPDWdMfrmlpZgbbT HzRzpTN7c41HNbqmzBxAeVHa4wE0VT0dMY7whqsPq/bp17pSo+dN25RIDq9ABfryKaz2 CPJaZfqrcrzbtRdoxdZ3Yel9EvSZtqrB/FXxt2mBW4rpIz6Az9boaztS+EgVnHr8NsWp n8tQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=fORRrxiz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id f3-20020a170902e98300b0019141c79b1dsm8559328plb.254.2023.02.20.18.20.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Feb 2023 18:20:06 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v2 08/14] target/arm: Add name argument to output_vector_union_type Date: Mon, 20 Feb 2023 16:19:45 -1000 Message-Id: <20230221021951.453601-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230221021951.453601-1-richard.henderson@linaro.org> References: <20230221021951.453601-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This will make the function usable between SVE and SME. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- target/arm/gdbstub64.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index d0e1305f6f..36166bf81e 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -210,7 +210,8 @@ int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg) return 0; } -static void output_vector_union_type(GString *s, int reg_width) +static void output_vector_union_type(GString *s, int reg_width, + const char *name) { struct TypeSize { const char *gdb_type; @@ -240,39 +241,38 @@ static void output_vector_union_type(GString *s, int reg_width) }; static const char suf[] = { 'q', 'd', 's', 'h', 'b' }; - - g_autoptr(GString) ts = g_string_new(""); int i, j, bits; /* First define types and totals in a whole VL */ for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) { - int count = reg_width / vec_lanes[i].size; - g_string_printf(ts, "svev%c%c", vec_lanes[i].sz, vec_lanes[i].suffix); g_string_append_printf(s, - "", - ts->str, vec_lanes[i].gdb_type, count); + "", + name, vec_lanes[i].sz, vec_lanes[i].suffix, + vec_lanes[i].gdb_type, reg_width / vec_lanes[i].size); } + /* * Now define a union for each size group containing unsigned and * signed and potentially float versions of each size from 128 to * 8 bits. */ for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) { - g_string_append_printf(s, "", suf[i]); + g_string_append_printf(s, "", name, suf[i]); for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) { if (vec_lanes[j].size == bits) { - g_string_append_printf(s, "", - vec_lanes[j].suffix, + g_string_append_printf(s, "", + vec_lanes[j].suffix, name, vec_lanes[j].sz, vec_lanes[j].suffix); } } g_string_append(s, ""); } + /* And now the final union of unions */ - g_string_append(s, ""); + g_string_append_printf(s, "", name); for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) { - g_string_append_printf(s, "", - suf[i], suf[i]); + g_string_append_printf(s, "", + suf[i], name, suf[i]); } g_string_append(s, ""); } @@ -292,7 +292,7 @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg) g_string_append_printf(s, ""); /* Create the vector union type. */ - output_vector_union_type(s, reg_width); + output_vector_union_type(s, reg_width, "svev"); /* Create the predicate vector type. */ g_string_append_printf(s, From patchwork Tue Feb 21 02:19:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 655347 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcd:0:0:0:0:0 with SMTP id e13csp1725152wrc; Mon, 20 Feb 2023 18:22:13 -0800 (PST) X-Google-Smtp-Source: AK7set/cLRtMnVv93pA5qdnPd9J+aaNxe3fvc7E7IItNAVo/2/S/l1CiAROSRsnI6wFXelzeYmZk X-Received: by 2002:ac8:5f49:0:b0:3bd:1647:15cd with SMTP id y9-20020ac85f49000000b003bd164715cdmr22319147qta.2.1676946133546; Mon, 20 Feb 2023 18:22:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676946133; cv=none; d=google.com; s=arc-20160816; b=xtneQEFVOzofsbwkVSlCcbLJRQHpSPz8LAICb3Ud3PFCck1M/R7fsnNyLSnvO+/ULz 0DOtVTrkSDLm89+6/XRroB3nXexOcpX5/UHHuQMT3DcQBdcspGDyNZb6gTzuxb6e9uMB jInjR5Yc5BSoiUPhzVq3RItlbCzCMH0lKGpFB+kNGl1Zj0y+C2uZ+jXPvxbATM0fU1Oo X3G5a0FnqKlJKbpZ08zIXUtlhd9vSQ/rDz/3+R7ILMTnCpsFadzHEMVeoLGBtxPQDXWK uN6cVsk1l7KB7wvu6PU697X5XU4ET+1LBowXKiFOo2+pPRlbZ4aHIz/KPzTosau5Mr0i Z7ng== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=ktLcLczpC5J61u+Wz7S4IYVLAaoqvKihU89wRw7bX20=; b=VH4tseFMMOlKNrq3dX8rfOQjaXyySZu2sjFJYUC50hvcnHBinIFt1uoQZQ/yYYGLYX xmcz4f8oJN5nuSQsUKz+6gx41xBc74es7ZIhX2taGzC9GQ1l/xZwF+DlYFXi+ZERXEsa qMu+JO1s7LlNdJmGbm/MlB7J2AIEUDdY/Nz95mvIDseUSPkLJcBNh2MsWMxEW/utRd+0 NGeDJdnSLSnJuZTmI0+6x4pawCBz6L60zZgdVMgoOv8/6FbLYA9yV5d8VTspY4R+OObL qT/Jdlt6KrSLGLsd0NECNHbJ5ElpL9TjPdn/H6zWVDlUzzE4sHTv6DYux1aspp1K+p1p n9vQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZUrhFly4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id f3-20020a170902e98300b0019141c79b1dsm8559328plb.254.2023.02.20.18.20.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Feb 2023 18:20:08 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v2 09/14] target/arm: Simplify iteration over bit widths Date: Mon, 20 Feb 2023 16:19:46 -1000 Message-Id: <20230221021951.453601-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230221021951.453601-1-richard.henderson@linaro.org> References: <20230221021951.453601-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Order suf[] by the log8 of the width. Use ARRAY_SIZE instead of hard-coding 128. This changes the order of the union definitions, but retains the order of the union-of-union members. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/gdbstub64.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index 36166bf81e..3d9e9e97c8 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -240,8 +240,8 @@ static void output_vector_union_type(GString *s, int reg_width, { "int8", 8, 'b', 's' }, }; - static const char suf[] = { 'q', 'd', 's', 'h', 'b' }; - int i, j, bits; + static const char suf[] = { 'b', 'h', 's', 'd', 'q' }; + int i, j; /* First define types and totals in a whole VL */ for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) { @@ -256,7 +256,9 @@ static void output_vector_union_type(GString *s, int reg_width, * signed and potentially float versions of each size from 128 to * 8 bits. */ - for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) { + for (i = 0; i < ARRAY_SIZE(suf); i++) { + int bits = 8 << i; + g_string_append_printf(s, "", name, suf[i]); for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) { if (vec_lanes[j].size == bits) { @@ -270,7 +272,7 @@ static void output_vector_union_type(GString *s, int reg_width, /* And now the final union of unions */ g_string_append_printf(s, "", name); - for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) { + for (i = ARRAY_SIZE(suf) - 1; i >= 0; i--) { g_string_append_printf(s, "", suf[i], name, suf[i]); } From patchwork Tue Feb 21 02:19:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 655340 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcd:0:0:0:0:0 with SMTP id e13csp1724762wrc; Mon, 20 Feb 2023 18:21:09 -0800 (PST) X-Google-Smtp-Source: AK7set/FspQr4Z/QjC4hIrpvcV/Ib5cmT0up/DPMc416M28kHbCG9QWczZmzXsuPCo/JaFu11CUz X-Received: by 2002:a05:622a:1109:b0:3b8:6a5f:9918 with SMTP id e9-20020a05622a110900b003b86a5f9918mr5752620qty.63.1676946069059; Mon, 20 Feb 2023 18:21:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676946069; cv=none; d=google.com; s=arc-20160816; b=tp22UDrMH1MTvEdEOeYEMODY9/S7O7PKvex1RpZE/1eQX1g82QML2Dl5zwRDy5sa7p Pp4F20yYuintvdnErMQ/9PzmSeVYYSCpGEIvrf2PAt/YQEUNdpDc4ogiQPHW4hf9r5hK DY09xtmP/yvkC286H0DstEEdxweiIqEYfqmOa0FwZ3l9IwvRWhhLXWr9GBsD02TtuQFv UYjaGztYWtxo7MpcseA950+cowSwAejeTS0IB8wiaQO9azC6+MOMoLwcHE2HqkjQoGNQ tHbhETFz/NrZiosNx+CrWC45X0vYQIArWx+Z0DSAEFfZOViesKa6q/I/aGvWgMV6i4nE r0FQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Tb7eak0fnXBbpHkQ6RD7c94PCh+h4m119aRi0NXAmMg=; b=UAzY4GtW+RYSaPNT0WK7RKg8ceZ0gU8l8cK53OZFYLvtDKeSjwbga1V4Z5lIposojN 4Oxc3wi8rcBWt+YuI0r867+/TbwjNOPK80oy2uoq3iLyoN33wmgmrL4V+LpynYkaOTm+ 7h6/50EBgX0y6daJROEz8pVKPiolYL3CjmmZx5TJkH0OlJuMsjIQcoYFhxKXwIbR7chv l2cBXbfyB7sJnWOYGRzu+1HO6rzCavKkJIdDRtiZvSkVj+joADJ0hAwz2jVBMJhYonkZ z6z2y+ymJMw/9YJ7gc5syFn0835aZJrNm6BVGgd//24I12WDleOytw5xbe2Myov8BvNU YxBQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=KIJ4RUa4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id f3-20020a170902e98300b0019141c79b1dsm8559328plb.254.2023.02.20.18.20.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Feb 2023 18:20:09 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v2 10/14] target/arm: Create pauth_ptr_mask Date: Mon, 20 Feb 2023 16:19:47 -1000 Message-Id: <20230221021951.453601-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230221021951.453601-1-richard.henderson@linaro.org> References: <20230221021951.453601-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Keep the logic for pauth within pauth_helper.c, and expose a helper function for use with the gdbstub pac extension. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/internals.h | 10 ++++++++++ target/arm/pauth_helper.c | 26 ++++++++++++++++++++++---- 2 files changed, 32 insertions(+), 4 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 32b8562cbf..370655061e 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1350,6 +1350,16 @@ int exception_target_el(CPUARMState *env); bool arm_singlestep_active(CPUARMState *env); bool arm_generate_debug_exceptions(CPUARMState *env); +/** + * pauth_ptr_mask: + * @env: cpu context + * @ptr: selects between TTBR0 and TTBR1 + * @data: selects between TBI and TBID + * + * Return a mask of the bits of @ptr that contain the authentication code. + */ +uint64_t pauth_ptr_mask(CPUARMState *env, uint64_t ptr, bool data); + /* Add the cpreg definitions for debug related system registers */ void define_debug_regs(ARMCPU *cpu); diff --git a/target/arm/pauth_helper.c b/target/arm/pauth_helper.c index d0483bf051..20f347332d 100644 --- a/target/arm/pauth_helper.c +++ b/target/arm/pauth_helper.c @@ -339,14 +339,32 @@ static uint64_t pauth_addpac(CPUARMState *env, uint64_t ptr, uint64_t modifier, return pac | ext | ptr; } -static uint64_t pauth_original_ptr(uint64_t ptr, ARMVAParameters param) +static uint64_t pauth_ptr_mask_internal(ARMVAParameters param) { - /* Note that bit 55 is used whether or not the regime has 2 ranges. */ - uint64_t extfield = sextract64(ptr, 55, 1); int bot_pac_bit = 64 - param.tsz; int top_pac_bit = 64 - 8 * param.tbi; - return deposit64(ptr, bot_pac_bit, top_pac_bit - bot_pac_bit, extfield); + return MAKE_64BIT_MASK(bot_pac_bit, top_pac_bit - bot_pac_bit); +} + +static uint64_t pauth_original_ptr(uint64_t ptr, ARMVAParameters param) +{ + uint64_t mask = pauth_ptr_mask_internal(param); + + /* Note that bit 55 is used whether or not the regime has 2 ranges. */ + if (extract64(ptr, 55, 1)) { + return ptr | mask; + } else { + return ptr & ~mask; + } +} + +uint64_t pauth_ptr_mask(CPUARMState *env, uint64_t ptr, bool data) +{ + ARMMMUIdx mmu_idx = arm_stage1_mmu_idx(env); + ARMVAParameters param = aa64_va_parameters(env, ptr, mmu_idx, data); + + return pauth_ptr_mask_internal(param); } static uint64_t pauth_auth(CPUARMState *env, uint64_t ptr, uint64_t modifier, From patchwork Tue Feb 21 02:19:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 655351 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcd:0:0:0:0:0 with SMTP id e13csp1725324wrc; Mon, 20 Feb 2023 18:22:44 -0800 (PST) X-Google-Smtp-Source: AK7set9V9snWAw+YTWNwVrv5bBkht4sx/mFfoVaIsNKbOfOtATQcSiRXuWA0pQgHVcSkMBmlggfC X-Received: by 2002:ad4:5d61:0:b0:557:a5c5:7e01 with SMTP id fn1-20020ad45d61000000b00557a5c57e01mr8135441qvb.25.1676946164504; Mon, 20 Feb 2023 18:22:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676946164; cv=none; d=google.com; s=arc-20160816; b=ZeGj4RnA09vQb+vrG+mkdXkSIg9as/I5YTiixlNF1OlaWzqyxj7drOmZKEygHmILrL Iu2MtqYrONXN6T9IRcAsHg79g7FRIOnkyjrNjx8WRm5EMHNFv+aFcXnqk00j/kCXiKDG XwYlpCxgOuYI7dJH99A/yWIxnBQp2lm2Mozr8frZgKfbzKQS51984bIN8ayoeDGdKymf uRmek6pWnPKfb7x0sthPAWwh6WUhAcBDtawAAXclgti9/Nrh8cy1fAy/QWF6rW3EIsIk 8I+fDVtvlmf838bNS/DEh+QaPonrLmXmVXWhcZVo8aJYWgIqhLV+jQteeWbiezzt5dBR stAQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=5ppe2Qcjf7oc9HJYN5MySDHbITJCBzPtX1IDnG3TMP0=; b=pow1SG+tMLUNM7jZefc2JniFc/GQRHyMb65m8fJlFRuwBrxmg3yvZHDDbnbNn6jOH6 jstmTV4v3Rn3nTK5mAynX3Hd+DeNIEcTkIPOPSDC3GOtsy2/Kdtvo+vLCdXijMdxrOuz OnY1Us4Lk8mTcLvulZFrAdZ/+36vxKnibP/AUEP52pueW8l2XfpLrRUrkMoKgDIAz0d5 zZzbg79YQf+F5MT1VUI3+30lWxodYzYDWhjT5WnfCd6uSJkgJ1J+MNmlUYhr5Fjo20an RoFju6rs3gbJo02PfBUhrFG9n5olOUNCziRERAd2xooIHke134BBOwAEOZiFkBcUENxL s20g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SkOM92ii; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id f3-20020a170902e98300b0019141c79b1dsm8559328plb.254.2023.02.20.18.20.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Feb 2023 18:20:11 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Luis Machado , Thiago Jung Bauermann Subject: [PATCH v2 11/14] target/arm: Implement gdbstub pauth extension Date: Mon, 20 Feb 2023 16:19:48 -1000 Message-Id: <20230221021951.453601-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230221021951.453601-1-richard.henderson@linaro.org> References: <20230221021951.453601-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1044; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1044.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The extension is primarily defined by the Linux kernel NT_ARM_PAC_MASK ptrace register set. The original gdb feature consists of two masks, data and code, which are used to mask out the authentication code within a pointer. Following discussion with Luis Machado, add two more masks in order to support pointers within the high half of the address space (i.e. TTBR1 vs TTBR0). Cc: Luis Machado Cc: Thiago Jung Bauermann Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1105 Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- configs/targets/aarch64-linux-user.mak | 2 +- configs/targets/aarch64-softmmu.mak | 2 +- configs/targets/aarch64_be-linux-user.mak | 2 +- target/arm/internals.h | 2 ++ target/arm/gdbstub.c | 5 ++++ target/arm/gdbstub64.c | 34 +++++++++++++++++++++++ gdb-xml/aarch64-pauth.xml | 15 ++++++++++ 7 files changed, 59 insertions(+), 3 deletions(-) create mode 100644 gdb-xml/aarch64-pauth.xml diff --git a/configs/targets/aarch64-linux-user.mak b/configs/targets/aarch64-linux-user.mak index db552f1839..ba8bc5fe3f 100644 --- a/configs/targets/aarch64-linux-user.mak +++ b/configs/targets/aarch64-linux-user.mak @@ -1,6 +1,6 @@ TARGET_ARCH=aarch64 TARGET_BASE_ARCH=arm -TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml +TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/aarch64-pauth.xml TARGET_HAS_BFLT=y CONFIG_SEMIHOSTING=y CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y diff --git a/configs/targets/aarch64-softmmu.mak b/configs/targets/aarch64-softmmu.mak index d489e6da83..b4338e9568 100644 --- a/configs/targets/aarch64-softmmu.mak +++ b/configs/targets/aarch64-softmmu.mak @@ -1,5 +1,5 @@ TARGET_ARCH=aarch64 TARGET_BASE_ARCH=arm TARGET_SUPPORTS_MTTCG=y -TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml gdb-xml/arm-m-profile-mve.xml +TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml gdb-xml/arm-m-profile-mve.xml gdb-xml/aarch64-pauth.xml TARGET_NEED_FDT=y diff --git a/configs/targets/aarch64_be-linux-user.mak b/configs/targets/aarch64_be-linux-user.mak index dc78044fb1..acb5620cdb 100644 --- a/configs/targets/aarch64_be-linux-user.mak +++ b/configs/targets/aarch64_be-linux-user.mak @@ -1,7 +1,7 @@ TARGET_ARCH=aarch64 TARGET_BASE_ARCH=arm TARGET_BIG_ENDIAN=y -TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml +TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/aarch64-pauth.xml TARGET_HAS_BFLT=y CONFIG_SEMIHOSTING=y CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y diff --git a/target/arm/internals.h b/target/arm/internals.h index 370655061e..fb88b16579 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1331,6 +1331,8 @@ int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg); int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg); int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg); int aarch64_gdb_set_fpu_reg(CPUARMState *env, uint8_t *buf, int reg); +int aarch64_gdb_get_pauth_reg(CPUARMState *env, GByteArray *buf, int reg); +int aarch64_gdb_set_pauth_reg(CPUARMState *env, uint8_t *buf, int reg); void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp); void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp); void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp); diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index bf8aff7824..062c8d447a 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -355,6 +355,11 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) aarch64_gdb_set_fpu_reg, 34, "aarch64-fpu.xml", 0); } + if (isar_feature_aa64_pauth(&cpu->isar)) { + gdb_register_coprocessor(cs, aarch64_gdb_get_pauth_reg, + aarch64_gdb_set_pauth_reg, + 4, "aarch64-pauth.xml", 0); + } #endif } else { if (arm_feature(env, ARM_FEATURE_NEON)) { diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index 3d9e9e97c8..3bee892fb7 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -210,6 +210,40 @@ int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg) return 0; } +int aarch64_gdb_get_pauth_reg(CPUARMState *env, GByteArray *buf, int reg) +{ + switch (reg) { + case 0: /* pauth_dmask */ + case 1: /* pauth_cmask */ + case 2: /* pauth_dmask_high */ + case 3: /* pauth_cmask_high */ + /* + * Note that older versions of this feature only contained + * pauth_{d,c}mask, for use with Linux user processes, and + * thus exclusively in the low half of the address space. + * + * To support system mode, and to debug kernels, two new regs + * were added to cover the high half of the address space. + * For the purpose of pauth_ptr_mask, we can use any well-formed + * address within the address space half -- here, 0 and -1. + */ + { + bool is_data = !(reg & 1); + bool is_high = reg & 2; + uint64_t mask = pauth_ptr_mask(env, -is_high, is_data); + return gdb_get_reg64(buf, mask); + } + default: + return 0; + } +} + +int aarch64_gdb_set_pauth_reg(CPUARMState *env, uint8_t *buf, int reg) +{ + /* All pseudo registers are read-only. */ + return 0; +} + static void output_vector_union_type(GString *s, int reg_width, const char *name) { diff --git a/gdb-xml/aarch64-pauth.xml b/gdb-xml/aarch64-pauth.xml new file mode 100644 index 0000000000..24af5f903c --- /dev/null +++ b/gdb-xml/aarch64-pauth.xml @@ -0,0 +1,15 @@ + + + + + + + + + + + From patchwork Tue Feb 21 02:19:49 2023 Content-Type: text/plain; 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id f3-20020a170902e98300b0019141c79b1dsm8559328plb.254.2023.02.20.18.20.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Feb 2023 18:20:12 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, David Reiss , Peter Maydell Subject: [PATCH v2 12/14] target/arm: Export arm_v7m_mrs_control Date: Mon, 20 Feb 2023 16:19:49 -1000 Message-Id: <20230221021951.453601-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230221021951.453601-1-richard.henderson@linaro.org> References: <20230221021951.453601-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: David Reiss Allow the function to be used outside of m_helper.c. Rename with an "arm_" prefix. Reviewed-by: Peter Maydell Signed-off-by: David Reiss [rth: Split out of a larger patch] Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- target/arm/internals.h | 3 +++ target/arm/m_helper.c | 6 +++--- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index fb88b16579..89052b1c94 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1339,6 +1339,9 @@ void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp); void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp); #endif +/* Read the CONTROL register as the MRS instruction would. */ +uint32_t arm_v7m_mrs_control(CPUARMState *env, uint32_t secure); + #ifdef CONFIG_USER_ONLY static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { } #else diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index f94e87e728..03be79e7bf 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -56,7 +56,7 @@ static uint32_t v7m_mrs_xpsr(CPUARMState *env, uint32_t reg, unsigned el) return xpsr_read(env) & mask; } -static uint32_t v7m_mrs_control(CPUARMState *env, uint32_t secure) +uint32_t arm_v7m_mrs_control(CPUARMState *env, uint32_t secure) { uint32_t value = env->v7m.control[secure]; @@ -93,7 +93,7 @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) case 0 ... 7: /* xPSR sub-fields */ return v7m_mrs_xpsr(env, reg, 0); case 20: /* CONTROL */ - return v7m_mrs_control(env, 0); + return arm_v7m_mrs_control(env, 0); default: /* Unprivileged reads others as zero. */ return 0; @@ -2465,7 +2465,7 @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) case 0 ... 7: /* xPSR sub-fields */ return v7m_mrs_xpsr(env, reg, el); case 20: /* CONTROL */ - return v7m_mrs_control(env, env->v7m.secure); + return arm_v7m_mrs_control(env, env->v7m.secure); case 0x94: /* CONTROL_NS */ /* * We have to handle this here because unprivileged Secure code From patchwork Tue Feb 21 02:19:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 655345 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcd:0:0:0:0:0 with SMTP id e13csp1725062wrc; Mon, 20 Feb 2023 18:21:58 -0800 (PST) X-Google-Smtp-Source: AK7set+qhtAjSZ+WssbVrif2ZL7WyqNs/WUIWkIbV2l4Ekg9CI5nynopYSQ4PiFJRvT+VtL0qQDO X-Received: by 2002:a05:6214:d89:b0:56e:a7d1:4d65 with SMTP id e9-20020a0562140d8900b0056ea7d14d65mr6328354qve.52.1676946117888; Mon, 20 Feb 2023 18:21:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676946117; cv=none; d=google.com; s=arc-20160816; b=VX9th8aBgQ7x9oD6iycpUP5oD8UR2bADuQUspNEqO8yOEZQslshFxwlkgsQQtWa+/O n2hlU2QUENfWdnS81ww1hWRhZKp1bMX2GvRAfrISpFsfVmvPWjcUZSafFifj0G0NNbVX 6tp5/cTWabRBJLHzvvfT25gmByWjkvTK+ZB58bOSX9CVtEHv7w3guX0Rkv+mA+f7KzVF P6OcjLvyRY7s8Z9lnFuHtSORfljsB0C57zAU6TqO3MTB0QhQJxpJGCUDniT61Vh7zx5F IIfyLT+/mySBKKdHdTEpU6lmE/JCdowvQZNBO/AGejsuVv0KSSbIfDZGUQVtzJz8gShE bXaA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=IdlPIsbyU63QTH8OjgZ/6X4x7sICRqYPKrZtVtFUFwM=; b=vd5lU0BuJNeL2wAz4z/55BJWVvxrMiCPAbCHdaIRJPezFht7+kYc7Gwlp/eZQBnwPY hNbtfvDdKfuZuz54ExCuT3LDiD0a02nERhJZCMo6tWZb1RrBPtaG3w/dgCUihbZU2cP1 EnoueF7fhN89O09sgAwyK2VqbPvECH6IuGfEg1mqQGFpkEvZL4J+nHiylHMpQSyO/nj9 NjS72VvZm7yRunt1cm4k1ekY2bXrVla5edWN9tRPf21pjwMdCc+UtA2EgVrXDIyiRQdc lz0kjOKeMwy/sbciipD4VjwsTlze5J2n68b+XOZRf33PAQjxJ7xsIxUUf56v3jlQutcC rkPg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ygWv7Ror; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id f3-20020a170902e98300b0019141c79b1dsm8559328plb.254.2023.02.20.18.20.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Feb 2023 18:20:14 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, David Reiss , Peter Maydell Subject: [PATCH v2 13/14] target/arm: Export arm_v7m_get_sp_ptr Date: Mon, 20 Feb 2023 16:19:50 -1000 Message-Id: <20230221021951.453601-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230221021951.453601-1-richard.henderson@linaro.org> References: <20230221021951.453601-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: David Reiss Allow the function to be used outside of m_helper.c. Move to be outside of ifndef CONFIG_USER_ONLY block. Rename from get_v7m_sp_ptr. Reviewed-by: Peter Maydell Signed-off-by: David Reiss [rth: Split out of a larger patch] Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- target/arm/internals.h | 10 +++++ target/arm/m_helper.c | 84 +++++++++++++++++++++--------------------- 2 files changed, 51 insertions(+), 43 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 89052b1c94..523822ac87 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1342,6 +1342,16 @@ void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp); /* Read the CONTROL register as the MRS instruction would. */ uint32_t arm_v7m_mrs_control(CPUARMState *env, uint32_t secure); +/* + * Return a pointer to the location where we currently store the + * stack pointer for the requested security state and thread mode. + * This pointer will become invalid if the CPU state is updated + * such that the stack pointers are switched around (eg changing + * the SPSEL control bit). + */ +uint32_t *arm_v7m_get_sp_ptr(CPUARMState *env, bool secure, + bool threadmode, bool spsel); + #ifdef CONFIG_USER_ONLY static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { } #else diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 03be79e7bf..081fc3f5f7 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -650,42 +650,6 @@ void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest) arm_rebuild_hflags(env); } -static uint32_t *get_v7m_sp_ptr(CPUARMState *env, bool secure, bool threadmode, - bool spsel) -{ - /* - * Return a pointer to the location where we currently store the - * stack pointer for the requested security state and thread mode. - * This pointer will become invalid if the CPU state is updated - * such that the stack pointers are switched around (eg changing - * the SPSEL control bit). - * Compare the v8M ARM ARM pseudocode LookUpSP_with_security_mode(). - * Unlike that pseudocode, we require the caller to pass us in the - * SPSEL control bit value; this is because we also use this - * function in handling of pushing of the callee-saves registers - * part of the v8M stack frame (pseudocode PushCalleeStack()), - * and in the tailchain codepath the SPSEL bit comes from the exception - * return magic LR value from the previous exception. The pseudocode - * opencodes the stack-selection in PushCalleeStack(), but we prefer - * to make this utility function generic enough to do the job. - */ - bool want_psp = threadmode && spsel; - - if (secure == env->v7m.secure) { - if (want_psp == v7m_using_psp(env)) { - return &env->regs[13]; - } else { - return &env->v7m.other_sp; - } - } else { - if (want_psp) { - return &env->v7m.other_ss_psp; - } else { - return &env->v7m.other_ss_msp; - } - } -} - static bool arm_v7m_load_vector(ARMCPU *cpu, int exc, bool targets_secure, uint32_t *pvec) { @@ -810,8 +774,8 @@ static bool v7m_push_callee_stack(ARMCPU *cpu, uint32_t lr, bool dotailchain, !mode; mmu_idx = arm_v7m_mmu_idx_for_secstate_and_priv(env, M_REG_S, priv); - frame_sp_p = get_v7m_sp_ptr(env, M_REG_S, mode, - lr & R_V7M_EXCRET_SPSEL_MASK); + frame_sp_p = arm_v7m_get_sp_ptr(env, M_REG_S, mode, + lr & R_V7M_EXCRET_SPSEL_MASK); want_psp = mode && (lr & R_V7M_EXCRET_SPSEL_MASK); if (want_psp) { limit = env->v7m.psplim[M_REG_S]; @@ -1656,10 +1620,8 @@ static void do_v7m_exception_exit(ARMCPU *cpu) * use 'frame_sp_p' after we do something that makes it invalid. */ bool spsel = env->v7m.control[return_to_secure] & R_V7M_CONTROL_SPSEL_MASK; - uint32_t *frame_sp_p = get_v7m_sp_ptr(env, - return_to_secure, - !return_to_handler, - spsel); + uint32_t *frame_sp_p = arm_v7m_get_sp_ptr(env, return_to_secure, + !return_to_handler, spsel); uint32_t frameptr = *frame_sp_p; bool pop_ok = true; ARMMMUIdx mmu_idx; @@ -1965,7 +1927,7 @@ static bool do_v7m_function_return(ARMCPU *cpu) threadmode = !arm_v7m_is_handler_mode(env); spsel = env->v7m.control[M_REG_S] & R_V7M_CONTROL_SPSEL_MASK; - frame_sp_p = get_v7m_sp_ptr(env, true, threadmode, spsel); + frame_sp_p = arm_v7m_get_sp_ptr(env, true, threadmode, spsel); frameptr = *frame_sp_p; /* @@ -2900,3 +2862,39 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op) } #endif /* !CONFIG_USER_ONLY */ + +uint32_t *arm_v7m_get_sp_ptr(CPUARMState *env, bool secure, bool threadmode, + bool spsel) +{ + /* + * Return a pointer to the location where we currently store the + * stack pointer for the requested security state and thread mode. + * This pointer will become invalid if the CPU state is updated + * such that the stack pointers are switched around (eg changing + * the SPSEL control bit). + * Compare the v8M ARM ARM pseudocode LookUpSP_with_security_mode(). + * Unlike that pseudocode, we require the caller to pass us in the + * SPSEL control bit value; this is because we also use this + * function in handling of pushing of the callee-saves registers + * part of the v8M stack frame (pseudocode PushCalleeStack()), + * and in the tailchain codepath the SPSEL bit comes from the exception + * return magic LR value from the previous exception. The pseudocode + * opencodes the stack-selection in PushCalleeStack(), but we prefer + * to make this utility function generic enough to do the job. + */ + bool want_psp = threadmode && spsel; + + if (secure == env->v7m.secure) { + if (want_psp == v7m_using_psp(env)) { + return &env->regs[13]; + } else { + return &env->v7m.other_sp; + } + } else { + if (want_psp) { + return &env->v7m.other_ss_psp; + } else { + return &env->v7m.other_ss_msp; + } + } +} From patchwork Tue Feb 21 02:19:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 655348 Delivered-To: patch@linaro.org Received: by 2002:adf:9bcd:0:0:0:0:0 with SMTP id e13csp1725295wrc; Mon, 20 Feb 2023 18:22:38 -0800 (PST) X-Google-Smtp-Source: AK7set8g4PZBggMbsBOwiahRXwUJcUnj1HvQMML664KHWTnXrsigIH3d8QKo6alwEbbphS7PYW0s X-Received: by 2002:a05:622a:1210:b0:3bd:190e:64bd with SMTP id y16-20020a05622a121000b003bd190e64bdmr3596802qtx.59.1676946158645; Mon, 20 Feb 2023 18:22:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676946158; cv=none; d=google.com; s=arc-20160816; b=vemcbQw2fbcoQoyL6RJQzNT3HzaFh1S4QmCTVDc17ZhRUlhWSRN7nBfPvxaEKwP4Me QDbvUPXKecmnMTL4XQ9M48YVlV1pT1DRCvD+uAN0zL6pyJ9eBRLHKx2xqHtao3pIJTCg ENEEBKJnlmsp4IwiFzL7jtWyx1gWQ1SVJSTU0OrjFlfjvDlNVtmkiN+//PlRyuQeASeI FOoOn0PAiBQRPpgXv6UyHyoBDugQqFPpJk3FCphGHNNwR42q0KjoTA3gpOeL5j/rQlTy pMEwpY0IJWHHOx+TOzNQ2lxldStfD5qEF4cx9pfY0sV5U82EvxkcBcIwT49GwwJ6qvPw tH+Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=C4PEKitcWEtZp1SVejXeRjs9KFolSy/o7SWCuKGHUqY=; b=tDR5Od5938ao7yY5MYDVC5MkpMZvV8W0hr/T3qK0ukDOpxKhJboxlgazH1NbI41m85 6wfb7hywnTCY3+Lr4IWC2RlZw25kwyCCcXHr4uqGbIxVaXfqqLi99tuS4FPJ+E6m7rFb iZiuOELaTnKJrxpe1hzdQrZaPoeYLSy26VCWeqnuy4xLQrChtGvX6Di5mxqJF9EfqztK CRJoHRerKL90aqzYdbqKHfGJtAAz2Iju2U1D5CSxO77Png7DlVJP/H/DSAcVGGs+olyi H0OM2bhxbdzSLYjBSdxQEVdih1nPFimLHrAWPOZm8uG98ek/zSkk6MkKV4SBmTiACwS7 Hx+g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="N3NJ6KF/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id f3-20020a170902e98300b0019141c79b1dsm8559328plb.254.2023.02.20.18.20.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Feb 2023 18:20:15 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, David Reiss Subject: [PATCH v2 14/14] target/arm: Implement gdbstub m-profile systemreg and secext Date: Mon, 20 Feb 2023 16:19:51 -1000 Message-Id: <20230221021951.453601-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230221021951.453601-1-richard.henderson@linaro.org> References: <20230221021951.453601-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The upstream gdb xml only implements {MSP,PSP}{,_NS,S}, but go ahead and implement the other system registers as well. Since there is significant overlap between the two, implement them with common code. The only exception is the systemreg view of CONTROL, which merges the banked bits as per MRS. Signed-off-by: David Reiss [rth: Substatial rewrite using enumerator and shared code.] Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- target/arm/cpu.h | 2 + target/arm/gdbstub.c | 194 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 196 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 059fe62eaa..6e97a256fb 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -869,6 +869,8 @@ struct ArchCPU { DynamicGDBXMLInfo dyn_sysreg_xml; DynamicGDBXMLInfo dyn_svereg_xml; + DynamicGDBXMLInfo dyn_m_systemreg_xml; + DynamicGDBXMLInfo dyn_m_secextreg_xml; /* Timers used by the generic (architected) timer */ QEMUTimer *gt_timer[NUM_GTIMERS]; diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index 062c8d447a..fef53e4ef5 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -322,6 +322,180 @@ static int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg) return cpu->dyn_sysreg_xml.num; } +typedef enum { + M_SYSREG_MSP, + M_SYSREG_PSP, + M_SYSREG_PRIMASK, + M_SYSREG_CONTROL, + M_SYSREG_BASEPRI, + M_SYSREG_FAULTMASK, + M_SYSREG_MSPLIM, + M_SYSREG_PSPLIM, +} MProfileSysreg; + +static const struct { + const char *name; + int feature; +} m_sysreg_def[] = { + [M_SYSREG_MSP] = { "msp", ARM_FEATURE_M }, + [M_SYSREG_PSP] = { "psp", ARM_FEATURE_M }, + [M_SYSREG_PRIMASK] = { "primask", ARM_FEATURE_M }, + [M_SYSREG_CONTROL] = { "control", ARM_FEATURE_M }, + [M_SYSREG_BASEPRI] = { "basepri", ARM_FEATURE_M_MAIN }, + [M_SYSREG_FAULTMASK] = { "faultmask", ARM_FEATURE_M_MAIN }, + [M_SYSREG_MSPLIM] = { "msplim", ARM_FEATURE_V8 }, + [M_SYSREG_PSPLIM] = { "psplim", ARM_FEATURE_V8 }, +}; + +static uint32_t *m_sysreg_ptr(CPUARMState *env, MProfileSysreg reg, bool sec) +{ + uint32_t *ptr; + + switch (reg) { + case M_SYSREG_MSP: + ptr = arm_v7m_get_sp_ptr(env, sec, false, true); + break; + case M_SYSREG_PSP: + ptr = arm_v7m_get_sp_ptr(env, sec, true, true); + break; + case M_SYSREG_MSPLIM: + ptr = &env->v7m.msplim[sec]; + break; + case M_SYSREG_PSPLIM: + ptr = &env->v7m.psplim[sec]; + break; + case M_SYSREG_PRIMASK: + ptr = &env->v7m.primask[sec]; + break; + case M_SYSREG_BASEPRI: + ptr = &env->v7m.basepri[sec]; + break; + case M_SYSREG_FAULTMASK: + ptr = &env->v7m.faultmask[sec]; + break; + case M_SYSREG_CONTROL: + ptr = &env->v7m.control[sec]; + break; + default: + return NULL; + } + return arm_feature(env, m_sysreg_def[reg].feature) ? ptr : NULL; +} + +static int m_sysreg_get(CPUARMState *env, GByteArray *buf, + MProfileSysreg reg, bool secure) +{ + uint32_t *ptr = m_sysreg_ptr(env, reg, secure); + + if (ptr == NULL) { + return 0; + } + return gdb_get_reg32(buf, *ptr); +} + +static int m_sysreg_set(CPUARMState *env, uint8_t *buf, + MProfileSysreg reg, bool secure) +{ + uint32_t *ptr = m_sysreg_ptr(env, reg, secure); + + if (ptr == NULL) { + return 0; + } + *ptr = ldl_p(buf); + return 4; +} + +static int arm_gdb_get_m_systemreg(CPUARMState *env, GByteArray *buf, int reg) +{ + /* + * Here, we emulate MRS instruction, where CONTROL has a mix of + * banked and non-banked bits. + */ + if (reg == M_SYSREG_CONTROL) { + return gdb_get_reg32(buf, arm_v7m_mrs_control(env, env->v7m.secure)); + } + return m_sysreg_get(env, buf, reg, env->v7m.secure); +} + +static int arm_gdb_set_m_systemreg(CPUARMState *env, uint8_t *buf, int reg) +{ + /* Control is a mix of banked and non-banked bits -- disallow write. */ + if (reg == M_SYSREG_CONTROL) { + return 0; + } + return m_sysreg_set(env, buf, reg, env->v7m.secure); +} + +static int arm_gen_dynamic_m_systemreg_xml(CPUState *cs, int orig_base_reg) +{ + ARMCPU *cpu = ARM_CPU(cs); + CPUARMState *env = &cpu->env; + GString *s = g_string_new(NULL); + int base_reg = orig_base_reg; + int i; + + g_string_printf(s, ""); + g_string_append_printf(s, ""); + g_string_append_printf(s, "\n"); + + for (i = 0; i < ARRAY_SIZE(m_sysreg_def); i++) { + if (arm_feature(env, m_sysreg_def[i].feature)) { + g_string_append_printf(s, + "\n", + m_sysreg_def[i].name, base_reg++); + } + } + + g_string_append_printf(s, ""); + cpu->dyn_m_systemreg_xml.desc = g_string_free(s, false); + cpu->dyn_m_systemreg_xml.num = base_reg - orig_base_reg; + + return cpu->dyn_m_systemreg_xml.num; +} + +#ifndef CONFIG_USER_ONLY +/* + * For user-only, we see the non-secure registers via m_systemreg above. + * For secext, encode the non-secure view as even and secure view as odd. + */ +static int arm_gdb_get_m_secextreg(CPUARMState *env, GByteArray *buf, int reg) +{ + return m_sysreg_get(env, buf, reg >> 1, reg & 1); +} + +static int arm_gdb_set_m_secextreg(CPUARMState *env, uint8_t *buf, int reg) +{ + return m_sysreg_set(env, buf, reg >> 1, reg & 1); +} + +static int arm_gen_dynamic_m_secextreg_xml(CPUState *cs, int orig_base_reg) +{ + ARMCPU *cpu = ARM_CPU(cs); + GString *s = g_string_new(NULL); + int base_reg = orig_base_reg; + int i; + + g_string_printf(s, ""); + g_string_append_printf(s, ""); + g_string_append_printf(s, "\n"); + + for (i = 0; i < ARRAY_SIZE(m_sysreg_def); i++) { + g_string_append_printf(s, + "\n", + m_sysreg_def[i].name, base_reg++); + g_string_append_printf(s, + "\n", + m_sysreg_def[i].name, base_reg++); + } + + g_string_append_printf(s, ""); + cpu->dyn_m_secextreg_xml.desc = g_string_free(s, false); + cpu->dyn_m_secextreg_xml.num = base_reg - orig_base_reg; + + return cpu->dyn_m_secextreg_xml.num; +} +#endif + const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) { ARMCPU *cpu = ARM_CPU(cs); @@ -330,6 +504,12 @@ const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) return cpu->dyn_sysreg_xml.desc; } else if (strcmp(xmlname, "sve-registers.xml") == 0) { return cpu->dyn_svereg_xml.desc; + } else if (strcmp(xmlname, "arm-m-system.xml") == 0) { + return cpu->dyn_m_systemreg_xml.desc; +#ifndef CONFIG_USER_ONLY + } else if (strcmp(xmlname, "arm-m-secext.xml") == 0) { + return cpu->dyn_m_secextreg_xml.desc; +#endif } return NULL; } @@ -389,4 +569,18 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) arm_gen_dynamic_sysreg_xml(cs, cs->gdb_num_regs), "system-registers.xml", 0); + if (arm_feature(env, ARM_FEATURE_M)) { + gdb_register_coprocessor(cs, + arm_gdb_get_m_systemreg, arm_gdb_set_m_systemreg, + arm_gen_dynamic_m_systemreg_xml(cs, cs->gdb_num_regs), + "arm-m-system.xml", 0); +#ifndef CONFIG_USER_ONLY + if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { + gdb_register_coprocessor(cs, + arm_gdb_get_m_secextreg, arm_gdb_set_m_secextreg, + arm_gen_dynamic_m_secextreg_xml(cs, cs->gdb_num_regs), + "arm-m-secext.xml", 0); + } +#endif + } }