From patchwork Thu May 9 11:10:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 163700 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:142:0:0:0:0 with SMTP id j2csp818309ilr; Thu, 9 May 2019 04:11:32 -0700 (PDT) X-Google-Smtp-Source: APXvYqzzu9hcGynJ5zBCsg8bsPqD6Oh6FXjGaA5x1Mv7shM8UYqOVOauz/Km8wf6Q8xH4dTfkI3o X-Received: by 2002:a63:f707:: with SMTP id x7mr4490800pgh.343.1557400292202; Thu, 09 May 2019 04:11:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1557400292; cv=none; d=google.com; s=arc-20160816; b=aqaFIBzw+dVh0IMsQDjKgp8lsUqhHUFbfilK5dRjZ7PLMgcfZqSmb0aAoWsA5aPlcm YaD3QG3nQZL+at4hltA9tJDm4MpnAzrBcetnwuAYOsdb6SxnVkLFa9PSwau9FtjwOUMg P73PFDDQp4t/iD++Cw59wcysuxEdoLyvV77CA3NC1jV1hp9eWdelre0mxXfalmGrNdB5 qRZvAefzJL+q4YulVB/E+eZMXkX6cW5VIFNLLNCu4DFqZrLSdaVsVjY0wSnDotQGq/7E KE+khOftWENwMP5pyKYAimswRHbOHyAhMqu0wqQ+aa7kiieOxv1t7PQEMdHSJnYDjWWi 9CoA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=btyjrIBgvEiFaw+UeR2po3KmpV02gWF8Za6NMh5yZW4=; b=R35hfB1CFBDN9TWtEHaR0I9M8SXH12WnT0off+Zp718hU4pbh6rqyDa2BLQO06hEWy 5DH2B0fjjmUjblSywl9M3BeF6QOpzTbss3NvO65hdvQXnlpZonVxwojDoGYj0qjJPFS2 jdX8YhdLyT4GoLF3qUp2ULXTSqdpinnlh+HohFl7dpO8+oIaYb0mxfsrpasrWxyMEryJ mcKjHZhEnQZeIAXPWGVJ1ley29i++MKVy201IO9lH7n0g4UWh3MykHi6vElzZqkyZ9ff gYLjZDeB9fLSOZ2Ty+Jvj1dU/+DEqMN89kmHXeqG8Z2q1ZdGLN14pr1PA3ufqQhHSG4T DuiQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PWBiTlpp; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r3si2370980pfn.139.2019.05.09.04.11.31; Thu, 09 May 2019 04:11:32 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PWBiTlpp; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726491AbfEILLa (ORCPT + 30 others); Thu, 9 May 2019 07:11:30 -0400 Received: from mail-wr1-f67.google.com ([209.85.221.67]:43372 "EHLO mail-wr1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725869AbfEILL3 (ORCPT ); Thu, 9 May 2019 07:11:29 -0400 Received: by mail-wr1-f67.google.com with SMTP id r4so2439269wro.10 for ; Thu, 09 May 2019 04:11:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=btyjrIBgvEiFaw+UeR2po3KmpV02gWF8Za6NMh5yZW4=; b=PWBiTlppp3qNKNSeeS/VbeyXHbeoNzIgZOkqg0QoiRFGQ/PoyWUhxKj3BLPDmz8W6Y JzXPTH5kOri0av4o3+l7pnSkszbh2LqCnIXf4oU7wWhWtha3iWEYL7mQP6CFGfFbTFGr KOuc7K4lgMulVZGUEawzuC5yZkFF4RwYXvm9sF2F08eXrBZgq9NOsUh0frqjNdNgmn9X OYWoNik+J4XJ2wimnmZN/CyFgZHo3ggmQHf9szz/AttkvE0AwkumSzIT5DMZ9lacacVu AGRDb0WGfRrkeIcK07euzHhF1/GjcTl/yHabhuTGJRx+PkjlxWuUAdoFN7KiZeFFph6z W3CQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=btyjrIBgvEiFaw+UeR2po3KmpV02gWF8Za6NMh5yZW4=; b=GPUE8hu3VAzVblW4CVTuOdYBeB3E5x1mvgT2er7cVBsUdU0V4PzB+yaE6dczDSLZcN iEX61+ToF9n/GmoHNMhBD5xrkxoZtJqDOTrrhjvwSf4HoTqVEGHYj3eMhAuYGOboZZ6x OhIBC2GDWinG3/CKjHq4vaQ2HmWUdProbUqrpEcoWOQRcVB/ukQu1rBr7pDH0ym8yTHu 7iY905cikIuJBIebwmV/kh19yWWXfpH7Ckrh5QmoBGDDIkQbDhzK4ovfAWBLoMxT+Q1B O3bUaQhzWdYANlFhK601jlx7dqPdw/h3mnQpxZALT6dxUdt9oWRKxu8mqDPn2v7rQXwr M8Ig== X-Gm-Message-State: APjAAAU4hXR7zSqY8rdhkQJtzOSdwS7jxjukv3DQ6YOSmOpHd7lNXI05 wS3keGsygLlWsRiPnbFJba3wZQ== X-Received: by 2002:a5d:4648:: with SMTP id j8mr2745726wrs.53.1557400287888; Thu, 09 May 2019 04:11:27 -0700 (PDT) Received: from mai.irit.fr ([141.115.39.235]) by smtp.gmail.com with ESMTPSA id z7sm2299778wme.26.2019.05.09.04.11.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 09 May 2019 04:11:26 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Mesih Kilinc , Maxime Ripard , Chen-Yu Tsai , linux-arm-kernel@lists.infradead.org (moderated list:ARM/Allwinner sunXi SoC support) Subject: [PATCH 01/15] clocksource/drivers/sun4i: Add a compatible for suniv Date: Thu, 9 May 2019 13:10:34 +0200 Message-Id: <20190509111048.11151-1-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <7e786ba3-a664-8fd9-dd17-6a5be996a712@linaro.org> References: <7e786ba3-a664-8fd9-dd17-6a5be996a712@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Mesih Kilinc The suniv (new F-series) chip has a timer with less functionality than the A10 timer, e.g. it has only 3 channels. Add a new compatible for it. As we didn't use the extra channels on A10 either now, the code needn't to be changed. The suniv chip is based on ARM926EJ-S CPU, thus it has no architecture timer. Register sun4i_timer as sched_clock on it. Signed-off-by: Mesih Kilinc Acked-by: Maxime Ripard Acked-by: Daniel Lezcano Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-sun4i.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/drivers/clocksource/timer-sun4i.c b/drivers/clocksource/timer-sun4i.c index 6e0180aaf784..65f38f6ca714 100644 --- a/drivers/clocksource/timer-sun4i.c +++ b/drivers/clocksource/timer-sun4i.c @@ -186,7 +186,8 @@ static int __init sun4i_timer_init(struct device_node *node) */ if (of_machine_is_compatible("allwinner,sun4i-a10") || of_machine_is_compatible("allwinner,sun5i-a13") || - of_machine_is_compatible("allwinner,sun5i-a10s")) + of_machine_is_compatible("allwinner,sun5i-a10s") || + of_machine_is_compatible("allwinner,suniv-f1c100s")) sched_clock_register(sun4i_timer_sched_read, 32, timer_of_rate(&to)); @@ -218,3 +219,5 @@ static int __init sun4i_timer_init(struct device_node *node) } TIMER_OF_DECLARE(sun4i, "allwinner,sun4i-a10-timer", sun4i_timer_init); +TIMER_OF_DECLARE(suniv, "allwinner,suniv-f1c100s-timer", + sun4i_timer_init); From patchwork Thu May 9 11:10:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 163701 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:142:0:0:0:0 with SMTP id j2csp818397ilr; Thu, 9 May 2019 04:11:37 -0700 (PDT) X-Google-Smtp-Source: APXvYqyWa1fv97q9lsBGt0dit0PkkSLyOel3f3nvz/6WxSUhJrVIHL3yB3pu8rGpmHO7D6jAYYeM X-Received: by 2002:a17:902:2862:: with SMTP id e89mr4188756plb.203.1557400296987; Thu, 09 May 2019 04:11:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1557400296; cv=none; d=google.com; s=arc-20160816; b=OaPIwbwSu4Ec8RrPw9Z2QGJx9nqmpHvSIUKSRYQFmRS54+BvSeUM97YNbSRZ36viQh kwqwrSUVj7QW1+mpQyWQRFEem5YkuxUhkOLxMqjZd9odpQEWzqDMpOYKUXtwiKS798qV obBchJBlufDVRLohg+JDR7A16tOdCYRX6FQ1URQa2DbXwyXuCdSgJ1aE2tq/ywhEq1kI X+4QrgFS8B/Lbyq0nnZQTJYYzswohXUHj3dxI116HmTkl7iefy2HiKaLhGDATUhn/FRs fNCsDSSIfOOMbbuYFNmqgI2/P7ZtaH868rLvKxqeMsQ9LPwlwCHCz1R9qekUNt+BKkPw vcgA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=b6Iva+4zZfXyJB7DwiHORWnnmSZxQ4pOGmjZY+dIVDQ=; b=Kts527QquA10beri3Tz22aiRHhiqJkYz20xbLM8OcbZqZdkvK/7rSeUmWF3UjACm+X v4gWT2Ec6ksWMYH7ZHXbg0v7HwsPOHkBFezF/l3PRImNRXFtbQZHlZDOI/loYRzBq99u 6kpckwyECsgXY6P9lR6QKmU/KtRJUosonjzkkcW1h+9B0/KHZEtjoZGI9vtSKaYFJEmR dG+8DZIUBywqAy0fh8q9wYICPmdfh5IQzKRc3j1gRHj4CMTQ8wLZPFdD0FY7/FGk64Uv +HQG+5jXD7Tpqz/4XSQ05rHN2Wr7Q3nmTDjM2OQgpRfUlaMJq/w/5uGbMQCiqxQTE2Ue XWOA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PEP2HOwr; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Add COMPILE_TEST option. Tested with 5.1-rc3+ on Fedora/RISCV. CONFIG_ARM_TIMER_SP804 no more shows up in riscv config. Signed-off-by: David Abdurachmanov Signed-off-by: Daniel Lezcano --- drivers/clocksource/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.17.1 diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 171502a356aa..ede5d20299b9 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -379,7 +379,7 @@ config ARM_GLOBAL_TIMER This options enables support for the ARM global timer unit config ARM_TIMER_SP804 - bool "Support for Dual Timer SP804 module" + bool "Support for Dual Timer SP804 module" if COMPILE_TEST depends on GENERIC_SCHED_CLOCK && CLKDEV_LOOKUP select CLKSRC_MMIO select TIMER_OF if OF From patchwork Thu May 9 11:10:36 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 163714 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:142:0:0:0:0 with SMTP id j2csp819695ilr; Thu, 9 May 2019 04:12:38 -0700 (PDT) X-Google-Smtp-Source: APXvYqwnETXw79US0SP5U8JR+717GRIrGwaaMlyy/KoEdsAapSJvrTlAokZHM312zC9HwTYRqFD6 X-Received: by 2002:aa7:8096:: with SMTP id v22mr4171006pff.94.1557400358595; Thu, 09 May 2019 04:12:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1557400358; cv=none; d=google.com; s=arc-20160816; b=jHffLUrBnn8WCdIutUARFu7ElzZFWIzr4+aWKmXhNf1I2VZGTLz+cpGqwildr1SadU ysekR3r95a7Sbpr3yeS8/h2UDm+quLFypR+/whFlEP2VQ5xF/IatdeI5Uopnkgoe3Oj5 4IB1eO82xpw6GfJmq+4ZM373bErHDGXjvN3bcoBB+5mZGoOMrPCJdEgp8hfX6kG7nBda B99DRHLq9Xmse/45X4YQovQ17ArTsVCaXw+LtvvxZQbC9qh3d0cwTbmSmocTys8PkIKa Yj4GaRwIUprBbfaKdmV4CqghOv84UKVXn7Uv+CWYVxumYKM/x0SOmNS/eVnuUsm3kv7C 2QXQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=7LulJJ0S3g9c4ZB5zK2P4vbeSt5R6AzVP5XZMwFs7gY=; b=jPDWdfOQQcFMtlG0vpeK7OLAc5m7WGZ102PLVkxkBovc00mrRVTPkbtfP1AQgBeUOo /cnogCGi9xGx6a412wSQGWBXRm+pZjEif4Q7am/ErJwwg2UHb85JBjIPDqr/jwY9MOu5 O4SrZcn81qGCh8WpMRszQ81TMv0TlBBhwnIZlw7Ga9BctkMer8huTXfLEANHW1kd3A1Y 1DLx7VbyZz0jTQP3lcB3hncvJOZBAp7ZHliZeH4RU+FA+N3hv+QKopYgDNdR2ryI89sO z7PCqSdPNRVTxcCu7rzJJ/efSR9qDw+HlUfCWsux7uKqqgHnDlWsigDK13yJs6Y6naBM Sf6w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Uu08UAic; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e8si2457152pgs.308.2019.05.09.04.12.38; Thu, 09 May 2019 04:12:38 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Uu08UAic; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726909AbfEILMh (ORCPT + 30 others); Thu, 9 May 2019 07:12:37 -0400 Received: from mail-wm1-f65.google.com ([209.85.128.65]:33321 "EHLO mail-wm1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726495AbfEILLc (ORCPT ); Thu, 9 May 2019 07:11:32 -0400 Received: by mail-wm1-f65.google.com with SMTP id s18so3955001wmh.0 for ; Thu, 09 May 2019 04:11:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=7LulJJ0S3g9c4ZB5zK2P4vbeSt5R6AzVP5XZMwFs7gY=; b=Uu08UAicY4C7RZWDJG4+i1ZKr/KJka5pFaopy+U1CxXs+Eh+KBy4qT6U4w7Kc7OOk5 ulsUhtabXTtR7s/lYGW8y3/4rSR21pquhpMtK+QZhXql286TgroEn7+li7k+haz/0EEs VqKFLLHDFHm2FDVTD71ND4frC3twwgmHuYdc3+1m1rPL5MnWMHmX+T5+IiBSeuroQnuq UZbVvBK+Gk/8luLs8JwUHpd8xAQ3RYTRCWOkhyZlXVipzEUfoGvcwMMEciM99q3K0yCz RuDsrWbJ3TkhUwVIKsDNp5FKT0iRydBTauCLixOhSHXRx6wiYDbkGOdcEJSjiPioeqHM PtoQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=7LulJJ0S3g9c4ZB5zK2P4vbeSt5R6AzVP5XZMwFs7gY=; b=CaExORAEUpaRCGZsOetFiWK/TzoKGy1dEBGHuAVyxN86wKP+SoCc026HRj84KpzqYM VzfokNL3eBT/s4qnqMmeW2vldTKI7/6Q8TBJBgebdvV8NOyLNJrcKPjFXWnXbzg6P+Yp PQCpnR4T26Pgo+dJJjt2WT1N1x0N+to24VOHmdQ+8cLzf1yOYS9xMjUsmgSW5aBlMAhY IBpRAyc1vNOZwCYVleqFawEh3XVWa1YETjFl60ehTv6zcSbT6lfuRHPtQtkQ7UyqoJLM zrfevAT3WnjvOX4qn0oiSzBPRh3BFJ/REFAT9HjDDtFOo6W0apxdUL3ku89B4tKS2VK0 kE4A== X-Gm-Message-State: APjAAAXdaVwyDQxLGxseTL6rfEM93UByA0HJQVbX9FClGzHXIKAv7lnd 0N5b/RHll9+7fyTnBfxHBmfDHg== X-Received: by 2002:a1c:ed12:: with SMTP id l18mr2616089wmh.13.1557400290437; Thu, 09 May 2019 04:11:30 -0700 (PDT) Received: from mai.irit.fr ([141.115.39.235]) by smtp.gmail.com with ESMTPSA id z7sm2299778wme.26.2019.05.09.04.11.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 09 May 2019 04:11:29 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Joseph Lo , Thierry Reding , Thierry Reding , Jonathan Hunter , linux-tegra@vger.kernel.org (open list:TEGRA ARCHITECTURE SUPPORT) Subject: [PATCH 03/15] clocksource/drivers/tegra: Rework for compensation of suspend time Date: Thu, 9 May 2019 13:10:36 +0200 Message-Id: <20190509111048.11151-3-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190509111048.11151-1-daniel.lezcano@linaro.org> References: <7e786ba3-a664-8fd9-dd17-6a5be996a712@linaro.org> <20190509111048.11151-1-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Joseph Lo Since the clocksource framework has the support for suspend time compensation. Re-work the driver to use that, so we can reduce the duplicate code. Suggested-by: Daniel Lezcano Signed-off-by: Joseph Lo Acked-by: Thierry Reding Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-tegra20.c | 63 +++++++++-------------------- 1 file changed, 20 insertions(+), 43 deletions(-) -- 2.17.1 diff --git a/drivers/clocksource/timer-tegra20.c b/drivers/clocksource/timer-tegra20.c index fdb3d795a409..919b3568c495 100644 --- a/drivers/clocksource/timer-tegra20.c +++ b/drivers/clocksource/timer-tegra20.c @@ -60,9 +60,6 @@ static u32 usec_config; static void __iomem *timer_reg_base; #ifdef CONFIG_ARM -static void __iomem *rtc_base; -static struct timespec64 persistent_ts; -static u64 persistent_ms, last_persistent_ms; static struct delay_timer tegra_delay_timer; #endif @@ -199,40 +196,30 @@ static unsigned long tegra_delay_timer_read_counter_long(void) return readl(timer_reg_base + TIMERUS_CNTR_1US); } +static struct timer_of suspend_rtc_to = { + .flags = TIMER_OF_BASE | TIMER_OF_CLOCK, +}; + /* * tegra_rtc_read - Reads the Tegra RTC registers * Care must be taken that this funciton is not called while the * tegra_rtc driver could be executing to avoid race conditions * on the RTC shadow register */ -static u64 tegra_rtc_read_ms(void) +static u64 tegra_rtc_read_ms(struct clocksource *cs) { - u32 ms = readl(rtc_base + RTC_MILLISECONDS); - u32 s = readl(rtc_base + RTC_SHADOW_SECONDS); + u32 ms = readl(timer_of_base(&suspend_rtc_to) + RTC_MILLISECONDS); + u32 s = readl(timer_of_base(&suspend_rtc_to) + RTC_SHADOW_SECONDS); return (u64)s * MSEC_PER_SEC + ms; } -/* - * tegra_read_persistent_clock64 - Return time from a persistent clock. - * - * Reads the time from a source which isn't disabled during PM, the - * 32k sync timer. Convert the cycles elapsed since last read into - * nsecs and adds to a monotonically increasing timespec64. - * Care must be taken that this funciton is not called while the - * tegra_rtc driver could be executing to avoid race conditions - * on the RTC shadow register - */ -static void tegra_read_persistent_clock64(struct timespec64 *ts) -{ - u64 delta; - - last_persistent_ms = persistent_ms; - persistent_ms = tegra_rtc_read_ms(); - delta = persistent_ms - last_persistent_ms; - - timespec64_add_ns(&persistent_ts, delta * NSEC_PER_MSEC); - *ts = persistent_ts; -} +static struct clocksource suspend_rtc_clocksource = { + .name = "tegra_suspend_timer", + .rating = 200, + .read = tegra_rtc_read_ms, + .mask = CLOCKSOURCE_MASK(32), + .flags = CLOCK_SOURCE_IS_CONTINUOUS | CLOCK_SOURCE_SUSPEND_NONSTOP, +}; #endif static int tegra_timer_common_init(struct device_node *np, struct timer_of *to) @@ -385,25 +372,15 @@ static int __init tegra_init_timer(struct device_node *np) static int __init tegra20_init_rtc(struct device_node *np) { - struct clk *clk; + int ret; - rtc_base = of_iomap(np, 0); - if (!rtc_base) { - pr_err("Can't map RTC registers\n"); - return -ENXIO; - } + ret = timer_of_init(np, &suspend_rtc_to); + if (ret) + return ret; - /* - * rtc registers are used by read_persistent_clock, keep the rtc clock - * enabled - */ - clk = of_clk_get(np, 0); - if (IS_ERR(clk)) - pr_warn("Unable to get rtc-tegra clock\n"); - else - clk_prepare_enable(clk); + clocksource_register_hz(&suspend_rtc_clocksource, 1000); - return register_persistent_clock(tegra_read_persistent_clock64); + return 0; } TIMER_OF_DECLARE(tegra20_rtc, "nvidia,tegra20-rtc", tegra20_init_rtc); #endif From patchwork Thu May 9 11:10:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 163713 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:142:0:0:0:0 with SMTP id j2csp819594ilr; Thu, 9 May 2019 04:12:33 -0700 (PDT) X-Google-Smtp-Source: APXvYqxnH9YWBg0mBr9SDXz5JZeA5dgO8bh5fLu70w6x9SrjgJuhQyV4I6E2rHyppz9BWI4d1/Ro X-Received: by 2002:a17:902:4643:: with SMTP id o61mr4085082pld.95.1557400352917; Thu, 09 May 2019 04:12:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1557400352; cv=none; d=google.com; s=arc-20160816; b=Yk6XTcF/xJUgViLPqUmyVvUeji7eIFlKcydVyB2dZFLruCl+LuAaMXkT4wvnm9+i2X oH1xf16GD3d2etk7hAdiFVwLduNbiy+xpuUmEms2LvtrvQ/DkwpErjqHaWRLCoKzYNCB B9+MpNboXXUjo0awFT0e6y5WQl66CH2IldO0WwzhoOtGMUGLTJ0COQBrqq5Eu7Oxrmjh DFsIKE4foVA22oSzgJ52knqYjyuGYKHNv7ME4H0gLiLFJxNcM3Jkv6xWZzUMoZh3mDx4 miduai5Wq6tYy0COJ3F7Zev80BFq3By6+VjlLA8miXnzvt6b/8tYT5cEi5a6Rlp1gPFK E4SQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=kv9Gg7wOfmL+wc19PLSZwbSNlh1m7pR6gGXghMqKj+Q=; b=DN9aGt1Aa3YssMfOdpSJgK3WuGll8BhufX7QVl7jtgc6TgXQPOfjOoCiXO7NN2Mim7 55dJ1gF+A8HlAi2b6WwTz/nuqy4LkBVQo9I7jRsoU0sd2pjGYlxCw2W7fljjli5Tf9rX M4Hxm4sRV3azTFCtIJGfzKiC3XSQJamEfCruoVnS0UeJnDSYAnYr8IYSyavLYHNyp/hL u2thtJV8M5WKPXUdKDPW17we5srlNoNxbHNZYPbx4Q4zl7Wj4swP/KoqU9wU5nWUISjZ rpIbF2LcjFp4CnYaTOvYAscyPdEVOTScvZEsvhHsjEzaB+CqBKpHWQgVueefFRlN75b5 9wGw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZSOSTbeL; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e8si2457152pgs.308.2019.05.09.04.12.32; Thu, 09 May 2019 04:12:32 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZSOSTbeL; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726894AbfEILMb (ORCPT + 30 others); Thu, 9 May 2019 07:12:31 -0400 Received: from mail-wm1-f65.google.com ([209.85.128.65]:40333 "EHLO mail-wm1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726452AbfEILLd (ORCPT ); Thu, 9 May 2019 07:11:33 -0400 Received: by mail-wm1-f65.google.com with SMTP id h11so2625783wmb.5 for ; Thu, 09 May 2019 04:11:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=kv9Gg7wOfmL+wc19PLSZwbSNlh1m7pR6gGXghMqKj+Q=; b=ZSOSTbeLUM+WduaH5DIUMhdAUFskp10W/dVpZKJcgy5jCLvb5X//1FQXBf4kqQn41s gNi17ihaAJ8vshdbXN1DiFXQmPvEUuGS/7EJe3P2Mo6R5q3E99PmsntDrhSE0olQHw+s lF7T9lgxVat/P8ULcY1irobhb1DFegGLMKGRh18kh68gLXzRcdANccvn4TOVQ9eb2AiT Gmc/QjCNi2NVn3zYJZZvERQa14Wh4j4tMaHzmiU36t0/IMQ9Jtu6MjojDDc8sd17Cqkz gpWUIiSY+WTEDAP5YLbieswGyjp/fcqnK6GIZGxWr3jfl0I9KApye7laXduQryxGpvZn cHEA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=kv9Gg7wOfmL+wc19PLSZwbSNlh1m7pR6gGXghMqKj+Q=; b=i6Yf9GefoNCXbhsHaKCxE8oZf7xVbSamEKBcFsDnSrioQeoWwoWKntmn380wNAeb5L pmsIM0dq/P+EKdMgwjMAX3cTLNwj/zgCA4/ZK8HBvwByCyQ/bidVeFpCWDyOSMZQSwJy 54kOCZmDoFAurqmApY/xvvVyIiZTKSv1z5ZUE8O5n+C2wNZFQcT3E6jrNyOLPV3ZW6fG 0aW2Zg+KjxxqqTshAPpAw4p1mHxyNLQ7YiuMBUNAlcL4Q9H0D0csCNKhnShlKEFMeGq5 O1MZ3YqqxCDQuEYIak+rGsyppQ+PNqWGi0KJIgd4lxyokJzVfcVVrsXGX4Av5jA47NF4 ifvg== X-Gm-Message-State: APjAAAWgYaFyx/UTGlRD8V75CUCTpJKAiBvE35IJ5XWMQg2U5Qu4fKer eI9CZe9qzoeWf2Ffu6C9wcRpDQ== X-Received: by 2002:a1c:9a14:: with SMTP id c20mr2585565wme.104.1557400291553; Thu, 09 May 2019 04:11:31 -0700 (PDT) Received: from mai.irit.fr ([141.115.39.235]) by smtp.gmail.com with ESMTPSA id z7sm2299778wme.26.2019.05.09.04.11.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 09 May 2019 04:11:30 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Sugaya Taichi Subject: [PATCH 04/15] clocksource/drivers/timer-milbeaut: Fix to enable one-shot timer Date: Thu, 9 May 2019 13:10:37 +0200 Message-Id: <20190509111048.11151-4-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190509111048.11151-1-daniel.lezcano@linaro.org> References: <7e786ba3-a664-8fd9-dd17-6a5be996a712@linaro.org> <20190509111048.11151-1-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Sugaya Taichi Fix mlb_set_oneshot_state() to enable one-shot timer. The function should stop and start a timer, but "start" statement was dropped. Kick the register to start one-shot timer. Fixes: b58f28f306db ("clocksource/drivers/timer-milbeaut: Introduce timer for Milbeaut SoCs") Signed-off-by: Sugaya Taichi Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-milbeaut.c | 2 ++ 1 file changed, 2 insertions(+) -- 2.17.1 diff --git a/drivers/clocksource/timer-milbeaut.c b/drivers/clocksource/timer-milbeaut.c index f2019a88e3ee..9fd5d081fac4 100644 --- a/drivers/clocksource/timer-milbeaut.c +++ b/drivers/clocksource/timer-milbeaut.c @@ -79,6 +79,8 @@ static int mlb_set_state_oneshot(struct clock_event_device *clk) struct timer_of *to = to_timer_of(clk); u32 val = MLB_TMR_TMCSR_CSL_DIV2; + writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS); + val |= MLB_TMR_TMCSR_CNTE | MLB_TMR_TMCSR_TRG | MLB_TMR_TMCSR_INTE; writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS); return 0; } From patchwork Thu May 9 11:10:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 163711 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:142:0:0:0:0 with SMTP id j2csp819293ilr; Thu, 9 May 2019 04:12:19 -0700 (PDT) X-Google-Smtp-Source: APXvYqzdSB3YYzsPg7C85q8Rah/ZVKGUNVlk2fVtuSl5VRDzX67+WN8wGRhs7CNqTbj+yU9pYDZq X-Received: by 2002:a63:2b03:: with SMTP id r3mr4466383pgr.105.1557400339620; Thu, 09 May 2019 04:12:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1557400339; cv=none; d=google.com; s=arc-20160816; b=VrKjuFW4CVZx54xTatU0zA7XQlF7g1dDDbAm0Ki9UrxGZcSahigI1EE3ZHIuz/RKrg 412LtVkXLFU35lqVlvO+0YmBrzrzT7loydL2UfrlbmiYleSb2t8lLTvzd2n5Ty3I6Xv0 gd24FzCp0wmsx6bUvwl1CbTxdOmwaoNBw0zuTmzX6pP2LRVyudSOHXZwa9ggCw4Gv4Pk YDR59v1KMp6IxpvHRa9OF0JApzcl1HVyjiCBzXbteYuKlP4fCSz2RcDrkMXR0jPA90w5 RK+CMOQz7pRTcw3EZiQyHpEYneYJrzlLYZnyEV+H+62hHPRscKNbi8HTu1jeUMlm8XjQ ULzw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=/WmgvSfXfoUbACWV/y6fHRyMAz3Q73nCkH7XU2xCVsg=; b=lLKz2Grw6oZt87C0Zvr67ZpzIMJb+NNGrLMVWk2Ypt/GqM9MJowxLgsLz+Z4FflWKU Jk6S2EF0z7OuBX1Xzdcq1T+yIjTQZE8/umjjnA49c7EmhusBPH4sxcmGfAZvRk2XIqrK +aMuVNtIGKAsGWqngSyNavbxLlSg3oFRexRQmpkCuhPDLKuBkpWsjzAUmkyM8tLyBHrF bZiV9MI+fHYnc7QqQooQcJpPMl41v6xsLUGJ/bkmrYhssi4x0HbhnyaRzE9BH45QSKWd 3tmuo3UhY150F3R9oDm21+QHUsdl40HN3OMfi1Scz+ocnn8a086EgkEjJ+MI5M0cOO0M niDA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="JseNp/50"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id l34si2407668pgb.574.2019.05.09.04.12.19; Thu, 09 May 2019 04:12:19 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="JseNp/50"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726678AbfEILLi (ORCPT + 30 others); Thu, 9 May 2019 07:11:38 -0400 Received: from mail-wm1-f66.google.com ([209.85.128.66]:51125 "EHLO mail-wm1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726573AbfEILLf (ORCPT ); Thu, 9 May 2019 07:11:35 -0400 Received: by mail-wm1-f66.google.com with SMTP id y17so1799208wmj.0 for ; Thu, 09 May 2019 04:11:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=/WmgvSfXfoUbACWV/y6fHRyMAz3Q73nCkH7XU2xCVsg=; b=JseNp/50Kl6x0zRxnuIBNt6ZENsiT1YNUMbrHDI44juGeU4+0J+iOKLLbHuoCGaus+ 5VViG2X7dR05UBYpYMdYXdw/RqVhZyYDHGKYbS6uL/tcxJQzPTI+gb0rpe+5gmTxxroe 4MJqt52DjlrdkeLlRFqaw9ml50vZ47f9RoeeRcnaqDB9OgJwpxM0TEeZ4a7TkexRrHZ1 8WLO5KmaxdIm3sdVlh3Thuc6FOBveKoO7nhMvHXIaWhjNtW9mCDCoqrlie6OOJFUFzKT rAY2wx/WhyRovOurRqRrDuKTue2BxagZZLeEzX2xz9KLkmT52z/BH5/5t194OZzHQoui BYyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=/WmgvSfXfoUbACWV/y6fHRyMAz3Q73nCkH7XU2xCVsg=; b=uOxOQMoAC9/8ikAEi5uWdmCLOWJJluSWrUuyMfl2JoBGLRdcbMXCsaRXnsp20jB8bD PwHJHZZkgxOUHpUu/LEHKVvVVobqJXHQX+eZy0NfU/Hq4zQL3X6de0sPIAugWYIM0FMf Vc6avpw5/4nBA8EhnXfu7q2e+tfnEYYG3MlQ+zJ1a3VsD/Vd5vcSPhIJ7wqDXBhjo0ww 9jbBezSBGce+D+IWJ+cIi3dHE0hmzr7iDW622TV6gZWt8clR+xQy80wFLup7kKANuCU5 R5S2CTpxxl+tE3e8oB9YHAAA6abgUKZ9STumuwu8Su6DblVodwHPRlsSt8intdaaCu8q boDA== X-Gm-Message-State: APjAAAVwrMbGkWVRNj9H8IjGN6Rzi2TV9wh9oRgwT/rtN6yMjxzFRg0+ UycKWZ8Fx+VLMDviH0TupKQiFA== X-Received: by 2002:a7b:c04b:: with SMTP id u11mr2341301wmc.95.1557400292983; Thu, 09 May 2019 04:11:32 -0700 (PDT) Received: from mai.irit.fr ([141.115.39.235]) by smtp.gmail.com with ESMTPSA id z7sm2299778wme.26.2019.05.09.04.11.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 09 May 2019 04:11:32 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Sugaya Taichi Subject: [PATCH 05/15] clocksource/drivers/timer-milbeaut: Add shutdown function Date: Thu, 9 May 2019 13:10:38 +0200 Message-Id: <20190509111048.11151-5-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190509111048.11151-1-daniel.lezcano@linaro.org> References: <7e786ba3-a664-8fd9-dd17-6a5be996a712@linaro.org> <20190509111048.11151-1-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Sugaya Taichi Add a shutdown operation to support shutdown timer. Signed-off-by: Sugaya Taichi Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-milbeaut.c | 10 ++++++++++ 1 file changed, 10 insertions(+) -- 2.17.1 diff --git a/drivers/clocksource/timer-milbeaut.c b/drivers/clocksource/timer-milbeaut.c index 9fd5d081fac4..f4780619dbaf 100644 --- a/drivers/clocksource/timer-milbeaut.c +++ b/drivers/clocksource/timer-milbeaut.c @@ -85,6 +85,15 @@ static int mlb_set_state_oneshot(struct clock_event_device *clk) return 0; } +static int mlb_set_state_shutdown(struct clock_event_device *clk) +{ + struct timer_of *to = to_timer_of(clk); + u32 val = MLB_TMR_TMCSR_CSL_DIV2; + + writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS); + return 0; +} + static int mlb_clkevt_next_event(unsigned long event, struct clock_event_device *clk) { @@ -125,6 +134,7 @@ static struct timer_of to = { .features = CLOCK_EVT_FEAT_DYNIRQ | CLOCK_EVT_FEAT_ONESHOT, .set_state_oneshot = mlb_set_state_oneshot, .set_state_periodic = mlb_set_state_periodic, + .set_state_shutdown = mlb_set_state_shutdown, .set_next_event = mlb_clkevt_next_event, }, From patchwork Thu May 9 11:10:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 163712 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:142:0:0:0:0 with SMTP id j2csp819481ilr; Thu, 9 May 2019 04:12:26 -0700 (PDT) X-Google-Smtp-Source: APXvYqwt2Wbzly4U8DcC36vlPy+4smHQw1xZ+Pn0/V80dtJEe6mH0RnahGFjPCickRLACurcw/xF X-Received: by 2002:a63:5110:: with SMTP id f16mr4629704pgb.107.1557400346866; Thu, 09 May 2019 04:12:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1557400346; cv=none; d=google.com; s=arc-20160816; b=ZsSMO4oKFKxLnCmKJ6/AmpDSiqGA21vvd8kxI0y0wW49AfHAUc7JyHWx4dg3kupGNV I4WVcwDavx1HSCC4NdxnyYckUA5Jx/O9vPb6fIyx8T4EVaIy4aG+8dLBQIEp7HBPn7YJ 44wtVYQkSWF37OH5dYeqpUKANIaC/31nxiyjWKXWVjbPn/hyqK9ed9XVwe/dBvlx6kmp J7p48O9Q7xyW9YOT7rOJEsojV6hS9kQrKmNThLlc+eHFiKaVY4By/+VwpeRk9GQTnc9T h1Ez20PHIDVFvPFAuVRHmfuWnIOlscu7g9PETSFJXO808XUGzw8VauYPsC1G/UuWX35H vSxQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=P3ip9Z1kPiurKcUpueirhLQ3VIip1Pisqdmbkd91afc=; b=pKcH9qnqFwOO72Y4cMlYlYAGKYFPOXeziTAQBHaq07AQK1KLKQl1kLxFzLk9SyKAOb 4zOQwEiL0+Z7q3W/JjKIF2YjmooKYOiHXa/lL2nWCX2EARk5xTZ5CRK4GL9MJj18mdu5 41muYKpFqctSnYwHvKWiGke80GHtScRO8zNE+2k67zfBtOmfwoDPf1lXXw16ZSq6ezLX 6+uCtEG7Z5CH3sfC/hBIrv9fAuKlBN45qEcFNB+10P1WZrpOvdgmGjrjjAi+GxgzbGOB jhXXXkavZuX/N8x4cDGLepg+/zaHDYfJjp6nXMvnTONHDueX0Azqn2z/Q+7/QGfjB/Vu vqhg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tk0VK6es; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Sugaya Taichi Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-milbeaut.c | 62 +++++++++++++++++----------- 1 file changed, 39 insertions(+), 23 deletions(-) -- 2.17.1 diff --git a/drivers/clocksource/timer-milbeaut.c b/drivers/clocksource/timer-milbeaut.c index f4780619dbaf..fa9fb4eacade 100644 --- a/drivers/clocksource/timer-milbeaut.c +++ b/drivers/clocksource/timer-milbeaut.c @@ -26,8 +26,8 @@ #define MLB_TMR_TMCSR_CSL_DIV2 0 #define MLB_TMR_DIV_CNT 2 -#define MLB_TMR_SRC_CH (1) -#define MLB_TMR_EVT_CH (0) +#define MLB_TMR_SRC_CH 1 +#define MLB_TMR_EVT_CH 0 #define MLB_TMR_SRC_CH_OFS (MLB_TMR_REGSZPCH * MLB_TMR_SRC_CH) #define MLB_TMR_EVT_CH_OFS (MLB_TMR_REGSZPCH * MLB_TMR_EVT_CH) @@ -43,6 +43,8 @@ #define MLB_TMR_EVT_TMRLR2_OFS (MLB_TMR_EVT_CH_OFS + MLB_TMR_TMRLR2_OFS) #define MLB_TIMER_RATING 500 +#define MLB_TIMER_ONESHOT 0 +#define MLB_TIMER_PERIODIC 1 static irqreturn_t mlb_timer_interrupt(int irq, void *dev_id) { @@ -59,38 +61,53 @@ static irqreturn_t mlb_timer_interrupt(int irq, void *dev_id) return IRQ_HANDLED; } -static int mlb_set_state_periodic(struct clock_event_device *clk) +static void mlb_evt_timer_start(struct timer_of *to, bool periodic) { - struct timer_of *to = to_timer_of(clk); u32 val = MLB_TMR_TMCSR_CSL_DIV2; + val |= MLB_TMR_TMCSR_CNTE | MLB_TMR_TMCSR_TRG | MLB_TMR_TMCSR_INTE; + if (periodic) + val |= MLB_TMR_TMCSR_RELD; writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS); +} + +static void mlb_evt_timer_stop(struct timer_of *to) +{ + u32 val = readl_relaxed(timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS); - writel_relaxed(to->of_clk.period, timer_of_base(to) + - MLB_TMR_EVT_TMRLR1_OFS); - val |= MLB_TMR_TMCSR_RELD | MLB_TMR_TMCSR_CNTE | - MLB_TMR_TMCSR_TRG | MLB_TMR_TMCSR_INTE; + val &= ~MLB_TMR_TMCSR_CNTE; writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS); +} + +static void mlb_evt_timer_register_count(struct timer_of *to, unsigned long cnt) +{ + writel_relaxed(cnt, timer_of_base(to) + MLB_TMR_EVT_TMRLR1_OFS); +} + +static int mlb_set_state_periodic(struct clock_event_device *clk) +{ + struct timer_of *to = to_timer_of(clk); + + mlb_evt_timer_stop(to); + mlb_evt_timer_register_count(to, to->of_clk.period); + mlb_evt_timer_start(to, MLB_TIMER_PERIODIC); return 0; } static int mlb_set_state_oneshot(struct clock_event_device *clk) { struct timer_of *to = to_timer_of(clk); - u32 val = MLB_TMR_TMCSR_CSL_DIV2; - writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS); - val |= MLB_TMR_TMCSR_CNTE | MLB_TMR_TMCSR_TRG | MLB_TMR_TMCSR_INTE; - writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS); + mlb_evt_timer_stop(to); + mlb_evt_timer_start(to, MLB_TIMER_ONESHOT); return 0; } static int mlb_set_state_shutdown(struct clock_event_device *clk) { struct timer_of *to = to_timer_of(clk); - u32 val = MLB_TMR_TMCSR_CSL_DIV2; - writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS); + mlb_evt_timer_stop(to); return 0; } @@ -99,22 +116,21 @@ static int mlb_clkevt_next_event(unsigned long event, { struct timer_of *to = to_timer_of(clk); - writel_relaxed(event, timer_of_base(to) + MLB_TMR_EVT_TMRLR1_OFS); - writel_relaxed(MLB_TMR_TMCSR_CSL_DIV2 | - MLB_TMR_TMCSR_CNTE | MLB_TMR_TMCSR_INTE | - MLB_TMR_TMCSR_TRG, timer_of_base(to) + - MLB_TMR_EVT_TMCSR_OFS); + mlb_evt_timer_stop(to); + mlb_evt_timer_register_count(to, event); + mlb_evt_timer_start(to, MLB_TIMER_ONESHOT); return 0; } static int mlb_config_clock_source(struct timer_of *to) { - writel_relaxed(0, timer_of_base(to) + MLB_TMR_SRC_TMCSR_OFS); - writel_relaxed(~0, timer_of_base(to) + MLB_TMR_SRC_TMR_OFS); + u32 val = MLB_TMR_TMCSR_CSL_DIV2; + + writel_relaxed(val, timer_of_base(to) + MLB_TMR_SRC_TMCSR_OFS); writel_relaxed(~0, timer_of_base(to) + MLB_TMR_SRC_TMRLR1_OFS); writel_relaxed(~0, timer_of_base(to) + MLB_TMR_SRC_TMRLR2_OFS); - writel_relaxed(BIT(4) | BIT(1) | BIT(0), timer_of_base(to) + - MLB_TMR_SRC_TMCSR_OFS); + val |= MLB_TMR_TMCSR_RELD | MLB_TMR_TMCSR_CNTE | MLB_TMR_TMCSR_TRG; + writel_relaxed(val, timer_of_base(to) + MLB_TMR_SRC_TMCSR_OFS); return 0; } From patchwork Thu May 9 11:10:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 163702 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:142:0:0:0:0 with SMTP id j2csp818451ilr; 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[209.132.180.67]) by mx.google.com with ESMTP id j65si2539886pfc.220.2019.05.09.04.11.39; Thu, 09 May 2019 04:11:39 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dDaPI9k3; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726705AbfEILLi (ORCPT + 30 others); Thu, 9 May 2019 07:11:38 -0400 Received: from mail-wr1-f67.google.com ([209.85.221.67]:40892 "EHLO mail-wr1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726650AbfEILLh (ORCPT ); Thu, 9 May 2019 07:11:37 -0400 Received: by mail-wr1-f67.google.com with SMTP id h4so2458343wre.7 for ; Thu, 09 May 2019 04:11:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=OrI1DkG8hXh5qOzNYuZ9U1o4Js7uyFKM86UkARAQjFU=; b=dDaPI9k3tcMtll47Djpz/rdtUGEzwzvLyyL0l//cu8cVR2Rt99lGVVkca4bXCWy+bF 6cA0oko1TzN6KJydKoxqLaE6azX6lRuedbrSJPew3NWRjR7BLke3Fqi8giw2uDhne1qD qKVThZQ/j3dwNLYKXGIjM4SUk48jDT86z07FLXGIg3JuxV1uIUCtgXMDgPR09ZZMfZr+ TNHzhK3fyYN/vr3k/3/WP6pHTR+hO1AntaTqGiyZ0TU+Wlnzh8TPRxANcXf0ShFml+vx o70PgJlW2nxCNS2TKkr488HT9y5XauThy5EedX37kOz98RiqhvvRoUuaPW9l7sXT3Nbm Qhkg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=OrI1DkG8hXh5qOzNYuZ9U1o4Js7uyFKM86UkARAQjFU=; b=eWpGnFrnW5nweBXx0TNnNMK3ELKL91Vww5U1vEfG0l0tpWF/Rq2ha7BcQuOddLV2cM SPh+SYCzGV+v4QuoLoF4mVQaCqCCUCB32UOrlqfLa/sQHmL/U23qfCHE01uw5MF7usxX nrBL2n0qXUPE56oKHGhUz5dg6qDNJZw0fsKw3MFEO20gudOOuh37oFUyx2auf6HeBsZR 0p0oN8nKsGsFBh7AIckIfFYCFEqE08JIwE5/PqisGcLYioMSjOUK/AjW408c9GzcKgh/ +k4Ey9HNBW4SN0Pix/dc8YDpTqmv2Gw9ES/s/I2EU6kb7QNR1/5fivG8sQK3/PtLpL61 4Vmg== X-Gm-Message-State: APjAAAX4jDUVOJPMEU5DcvirQ00BXQeMn892wzWL2DMPWIRHwDa75Vx/ HP6TnZbLsjkDCdKV6OyWhSMRng== X-Received: by 2002:adf:9c87:: with SMTP id d7mr2643806wre.68.1557400295729; Thu, 09 May 2019 04:11:35 -0700 (PDT) Received: from mai.irit.fr ([141.115.39.235]) by smtp.gmail.com with ESMTPSA id z7sm2299778wme.26.2019.05.09.04.11.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 09 May 2019 04:11:35 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Alexandre Belloni , Thierry Reding , Arnd Bergmann , Nicolas Ferre , Greg Kroah-Hartman , Ludovic Desroches , Chas Williams <3chas3@gmail.com>, linux-arm-kernel@lists.infradead.org (moderated list:MICROCHIP TIMER COUNTER (TC) AND CLOCKSOURCE DR...), linux-pwm@vger.kernel.org (open list:PWM SUBSYSTEM), linux-atm-general@lists.sourceforge.net (moderated list:ATM), netdev@vger.kernel.org (open list:ATM) Subject: [PATCH 07/15] ARM: at91: move SoC specific definitions to SoC folder Date: Thu, 9 May 2019 13:10:40 +0200 Message-Id: <20190509111048.11151-7-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190509111048.11151-1-daniel.lezcano@linaro.org> References: <7e786ba3-a664-8fd9-dd17-6a5be996a712@linaro.org> <20190509111048.11151-1-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Alexandre Belloni Move linux/atmel_tc.h to the SoC specific folder include/soc/at91. Signed-off-by: Alexandre Belloni Acked-by: Thierry Reding Acked-by: Arnd Bergmann Signed-off-by: Daniel Lezcano --- drivers/clocksource/tcb_clksrc.c | 2 +- drivers/misc/atmel_tclib.c | 2 +- drivers/pwm/pwm-atmel-tcb.c | 2 +- include/{linux/atmel_tc.h => soc/at91/atmel_tcb.h} | 4 ++-- 4 files changed, 5 insertions(+), 5 deletions(-) rename include/{linux/atmel_tc.h => soc/at91/atmel_tcb.h} (99%) -- 2.17.1 diff --git a/drivers/clocksource/tcb_clksrc.c b/drivers/clocksource/tcb_clksrc.c index 43f4d5c4d6fa..138a12090149 100644 --- a/drivers/clocksource/tcb_clksrc.c +++ b/drivers/clocksource/tcb_clksrc.c @@ -11,7 +11,7 @@ #include #include #include -#include +#include /* diff --git a/drivers/misc/atmel_tclib.c b/drivers/misc/atmel_tclib.c index ac24a4bd63f7..194f774ab3a1 100644 --- a/drivers/misc/atmel_tclib.c +++ b/drivers/misc/atmel_tclib.c @@ -1,4 +1,3 @@ -#include #include #include #include @@ -10,6 +9,7 @@ #include #include #include +#include /* * This is a thin library to solve the problem of how to portably allocate diff --git a/drivers/pwm/pwm-atmel-tcb.c b/drivers/pwm/pwm-atmel-tcb.c index 0d0f8376bc35..7da1fdb4d269 100644 --- a/drivers/pwm/pwm-atmel-tcb.c +++ b/drivers/pwm/pwm-atmel-tcb.c @@ -17,10 +17,10 @@ #include #include #include -#include #include #include #include +#include #define NPWM 6 diff --git a/include/linux/atmel_tc.h b/include/soc/at91/atmel_tcb.h similarity index 99% rename from include/linux/atmel_tc.h rename to include/soc/at91/atmel_tcb.h index 468fdfa643f0..c3c7200ce151 100644 --- a/include/linux/atmel_tc.h +++ b/include/soc/at91/atmel_tcb.h @@ -7,8 +7,8 @@ * (at your option) any later version. */ -#ifndef ATMEL_TC_H -#define ATMEL_TC_H +#ifndef __SOC_ATMEL_TCB_H +#define __SOC_ATMEL_TCB_H #include #include From patchwork Thu May 9 11:10:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 163703 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:142:0:0:0:0 with SMTP id j2csp818528ilr; Thu, 9 May 2019 04:11:44 -0700 (PDT) X-Google-Smtp-Source: APXvYqxPmOPUFXRq4AAcYukWFWDkBbJe1gVklwJmxEGy1ch0K6MpOFJhY3CTSbWgipH6ikOVdqhd X-Received: by 2002:a17:902:bc85:: with SMTP id bb5mr4194479plb.310.1557400303970; Thu, 09 May 2019 04:11:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1557400303; cv=none; d=google.com; s=arc-20160816; b=AQLmXRNUSqmOm1m62F+TW6CV3r6QyPciQuf/VHDlTcJCksZWg2j9e/sX0SwqtD9s0V JM1MyHiuaSg4mCZrI8+TrE6WZCC1/bmmdJi4eIYFHlHGmJVEmBjnSm/qf9EojUhpXgJ5 eYuRGvb30XnF9pPsMHFgoS5zSgd8/7JdihCI0A5fMjIwbjMmhayikxFzSci/zy2e011C Cp3zwDK1Sxoqqn6se3YUwNo4WnC1eDaLVOvNoqebj2fpLbtSoJaK9KCXiU1jhaq4Qb+1 MsfXjd2/Jf+7bCWr4tuTNXCc4Q0ftiiIX+1a2A7+Yw4NcOv/heTUiITurDBBYEJXHO9T 6G2A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=bmjB3BHnekjxDNQPFJ4nw5UiA2KYqoVK/B7ROqlZgj4=; b=Y5P0DnvmPLXdDbIj5FNUynAKzFr8/jNSTVG777pQD+iCMDF36Z0XVH5slcAoH8U9CM tst90cA4VdeGc96zsoscx9J8sZaS38Ou0saqo6HX2BfuoHEiI+/G5GtXc1o4N6VnhSdK LlTZN3mmgSG5mZZnkkUfTcqYkwkMT+sp+VO1EhBAgOKA5sIkaKBTcoshWygMqX91DODc kqnAM3AF2q14r7Oap60G+0rwpKwayT+y6qPe6OKAyA4k1azk7qoWjSJdKZYSTFnoAXCm gZLQsO8gnUATi9AVw/+sRwju5Iuvhw/lx9tJcS8cuw1mlDaAq5ZJyJfNkfycRHWirpkI okzw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FIM0wqqC; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Subject: [PATCH 08/15] clocksource/drivers/tcb_clksrc: Stop depending on atmel_tclib Date: Thu, 9 May 2019 13:10:41 +0200 Message-Id: <20190509111048.11151-8-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190509111048.11151-1-daniel.lezcano@linaro.org> References: <7e786ba3-a664-8fd9-dd17-6a5be996a712@linaro.org> <20190509111048.11151-1-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Alexandre Belloni atmel_tclib is probed too late in the boot process to be able to use the TCB as the boot clocksource. This is an issue for SoCs without the PIT (sams70, samv70 and samv71 families) as they simply currently can't boot. Get rid of the atmel_tclib dependency and probe everything on our own using the correct device tree binding. This also allows getting rid of ATMEL_TCB_CLKSRC_BLOCK and makes the driver a bit more flexible as the TCB is not hardcoded in the kernel anymore. Signed-off-by: Alexandre Belloni Signed-off-by: Daniel Lezcano --- drivers/clocksource/tcb_clksrc.c | 108 +++++++++++++++++++------------ drivers/misc/Kconfig | 14 +--- 2 files changed, 70 insertions(+), 52 deletions(-) -- 2.17.1 diff --git a/drivers/clocksource/tcb_clksrc.c b/drivers/clocksource/tcb_clksrc.c index 138a12090149..bf68504da94a 100644 --- a/drivers/clocksource/tcb_clksrc.c +++ b/drivers/clocksource/tcb_clksrc.c @@ -9,7 +9,8 @@ #include #include #include -#include +#include +#include #include #include @@ -28,13 +29,6 @@ * source, used in either periodic or oneshot mode. This runs * at 32 KiHZ, and can handle delays of up to two seconds. * - * A boot clocksource and clockevent source are also currently needed, - * unless the relevant platforms (ARM/AT91, AVR32/AT32) are changed so - * this code can be used when init_timers() is called, well before most - * devices are set up. (Some low end AT91 parts, which can run uClinux, - * have only the timers in one TC block... they currently don't support - * the tclib code, because of that initialization issue.) - * * REVISIT behavior during system suspend states... we should disable * all clocks and save the power. Easily done for clockevent devices, * but clocksources won't necessarily get the needed notifications. @@ -112,7 +106,6 @@ void tc_clksrc_resume(struct clocksource *cs) } static struct clocksource clksrc = { - .name = "tcb_clksrc", .rating = 200, .read = tc_get_cycles, .mask = CLOCKSOURCE_MASK(32), @@ -214,7 +207,6 @@ static int tc_next_event(unsigned long delta, struct clock_event_device *d) static struct tc_clkevt_device clkevt = { .clkevt = { - .name = "tc_clkevt", .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, /* Should be lower than at91rm9200's system timer */ @@ -330,39 +322,73 @@ static void __init tcb_setup_single_chan(struct atmel_tc *tc, int mck_divisor_id writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR); } -static int __init tcb_clksrc_init(void) -{ - static char bootinfo[] __initdata - = KERN_DEBUG "%s: tc%d at %d.%03d MHz\n"; +static const u8 atmel_tcb_divisors[5] = { 2, 8, 32, 128, 0, }; + +static const struct of_device_id atmel_tcb_of_match[] = { + { .compatible = "atmel,at91rm9200-tcb", .data = (void *)16, }, + { .compatible = "atmel,at91sam9x5-tcb", .data = (void *)32, }, + { /* sentinel */ } +}; - struct platform_device *pdev; - struct atmel_tc *tc; +static int __init tcb_clksrc_init(struct device_node *node) +{ + struct atmel_tc tc; struct clk *t0_clk; + const struct of_device_id *match; u32 rate, divided_rate = 0; int best_divisor_idx = -1; int clk32k_divisor_idx = -1; + int bits; int i; int ret; - tc = atmel_tc_alloc(CONFIG_ATMEL_TCB_CLKSRC_BLOCK); - if (!tc) { - pr_debug("can't alloc TC for clocksource\n"); - return -ENODEV; + /* Protect against multiple calls */ + if (tcaddr) + return 0; + + tc.regs = of_iomap(node->parent, 0); + if (!tc.regs) + return -ENXIO; + + t0_clk = of_clk_get_by_name(node->parent, "t0_clk"); + if (IS_ERR(t0_clk)) + return PTR_ERR(t0_clk); + + tc.slow_clk = of_clk_get_by_name(node->parent, "slow_clk"); + if (IS_ERR(tc.slow_clk)) + return PTR_ERR(tc.slow_clk); + + tc.clk[0] = t0_clk; + tc.clk[1] = of_clk_get_by_name(node->parent, "t1_clk"); + if (IS_ERR(tc.clk[1])) + tc.clk[1] = t0_clk; + tc.clk[2] = of_clk_get_by_name(node->parent, "t2_clk"); + if (IS_ERR(tc.clk[2])) + tc.clk[2] = t0_clk; + + tc.irq[2] = of_irq_get(node->parent, 2); + if (tc.irq[2] <= 0) { + tc.irq[2] = of_irq_get(node->parent, 0); + if (tc.irq[2] <= 0) + return -EINVAL; } - tcaddr = tc->regs; - pdev = tc->pdev; - t0_clk = tc->clk[0]; + match = of_match_node(atmel_tcb_of_match, node->parent); + bits = (uintptr_t)match->data; + + for (i = 0; i < ARRAY_SIZE(tc.irq); i++) + writel(ATMEL_TC_ALL_IRQ, tc.regs + ATMEL_TC_REG(i, IDR)); + ret = clk_prepare_enable(t0_clk); if (ret) { pr_debug("can't enable T0 clk\n"); - goto err_free_tc; + return ret; } /* How fast will we be counting? Pick something over 5 MHz. */ rate = (u32) clk_get_rate(t0_clk); - for (i = 0; i < 5; i++) { - unsigned divisor = atmel_tc_divisors[i]; + for (i = 0; i < ARRAY_SIZE(atmel_tcb_divisors); i++) { + unsigned divisor = atmel_tcb_divisors[i]; unsigned tmp; /* remember 32 KiHz clock for later */ @@ -381,27 +407,29 @@ static int __init tcb_clksrc_init(void) best_divisor_idx = i; } - - printk(bootinfo, clksrc.name, CONFIG_ATMEL_TCB_CLKSRC_BLOCK, - divided_rate / 1000000, + clksrc.name = kbasename(node->parent->full_name); + clkevt.clkevt.name = kbasename(node->parent->full_name); + pr_debug("%s at %d.%03d MHz\n", clksrc.name, divided_rate / 1000000, ((divided_rate % 1000000) + 500) / 1000); - if (tc->tcb_config && tc->tcb_config->counter_width == 32) { + tcaddr = tc.regs; + + if (bits == 32) { /* use apropriate function to read 32 bit counter */ clksrc.read = tc_get_cycles32; /* setup ony channel 0 */ - tcb_setup_single_chan(tc, best_divisor_idx); + tcb_setup_single_chan(&tc, best_divisor_idx); } else { - /* tclib will give us three clocks no matter what the + /* we have three clocks no matter what the * underlying platform supports. */ - ret = clk_prepare_enable(tc->clk[1]); + ret = clk_prepare_enable(tc.clk[1]); if (ret) { pr_debug("can't enable T1 clk\n"); goto err_disable_t0; } /* setup both channel 0 & 1 */ - tcb_setup_dual_chan(tc, best_divisor_idx); + tcb_setup_dual_chan(&tc, best_divisor_idx); } /* and away we go! */ @@ -410,7 +438,7 @@ static int __init tcb_clksrc_init(void) goto err_disable_t1; /* channel 2: periodic and oneshot timer support */ - ret = setup_clkevents(tc, clk32k_divisor_idx); + ret = setup_clkevents(&tc, clk32k_divisor_idx); if (ret) goto err_unregister_clksrc; @@ -420,14 +448,14 @@ static int __init tcb_clksrc_init(void) clocksource_unregister(&clksrc); err_disable_t1: - if (!tc->tcb_config || tc->tcb_config->counter_width != 32) - clk_disable_unprepare(tc->clk[1]); + if (bits != 32) + clk_disable_unprepare(tc.clk[1]); err_disable_t0: clk_disable_unprepare(t0_clk); -err_free_tc: - atmel_tc_free(tc); + tcaddr = NULL; + return ret; } -arch_initcall(tcb_clksrc_init); +TIMER_OF_DECLARE(atmel_tcb_clksrc, "atmel,tcb-timer", tcb_clksrc_init); diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 42ab8ec92a04..268a01d3d6f3 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -61,7 +61,8 @@ config ATMEL_TCLIB config ATMEL_TCB_CLKSRC bool "TC Block Clocksource" - depends on ATMEL_TCLIB + depends on ARCH_AT91 + select TIMER_OF if OF default y help Select this to get a high precision clocksource based on a @@ -72,17 +73,6 @@ config ATMEL_TCB_CLKSRC may be used as a clock event device supporting oneshot mode (delays of up to two seconds) based on the 32 KiHz clock. -config ATMEL_TCB_CLKSRC_BLOCK - int - depends on ATMEL_TCB_CLKSRC - default 0 - range 0 1 - help - Some chips provide more than one TC block, so you have the - choice of which one to use for the clock framework. The other - TC can be used for other purposes, such as PWM generation and - interval timing. - config DUMMY_IRQ tristate "Dummy IRQ handler" default n From patchwork Thu May 9 11:10:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 163704 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:142:0:0:0:0 with SMTP id j2csp818575ilr; Thu, 9 May 2019 04:11:46 -0700 (PDT) X-Google-Smtp-Source: APXvYqwwFYevjjZ90Co4t5xwLmVTgmVQvMt2NeTqWSNqR6YkAzChYOuHZxR2cz2ks5CpQGa792Bw X-Received: by 2002:a62:ae05:: with SMTP id q5mr4079688pff.13.1557400306097; Thu, 09 May 2019 04:11:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1557400306; cv=none; d=google.com; s=arc-20160816; b=PpgF9ydfj2KP5UcgVranczKfsR6FXctzslHj173mqZZ9yyoAUEbswBemncrsnrdWCs b9rOz/Ik8bunIwrYRaCnhO/Mcgm4qz9kwEn2rXrmYQm0PKLngogTtlvCRIBkLFTHwGiM MJUJtpyfQo6DURQosHwnuVu3t6ns3gfY/dIHFTT7WizuDHgiW1to7hySjM1wzUeAYw9/ qO0+dkLijx73yjoshCZrtN27AdivBcJhjbDK1vG+7Y1NucDam8Mxqe4FGbn21EZf3hKK H8H26Zz1mPlUf6TEwLr8wR+6L8NX/qGAylQMfQiSbrCB9tUL5mIzpHwX74XW8Ge/m+xj 0hGA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=uXE39cHm/ePcze6cpMzENlQKnSZwc2KOJnys2n77A3I=; b=vwBlBFPOBpzIf+nw5pPur9+8EeWBWYCZsbc5NFuH4UGRdCTrapGSLXNhq5iX/UuItS lzW2hPWEGDlSfYglm1qe/ZCZufssKKjtpFQw25ixPyp5oWJ0aVjYRG4AAgTxbqoDq8qr C4uzI36vDGuUMm4tstfYLib6SdGS7xi1YkcdYygUGqPQey2EtpBaLgswFqOv1Vadafem vYBeq6c4cc8rnc51ypkanPUU4WmZnNLZpQDTbLe+eJeIn6lBNqCvbKJkGx3qG+ilokEY WfTSJhMD/NdxSVacaHGXbbIvmhUzxtd/bRNLSEJ+ngbJDj4r9r6V3+OD4O3niD4oS47T 7+Xw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=fBGeZQwy; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Subject: [PATCH 09/15] clocksource/drivers/tcb_clksrc: Use tcb as sched_clock Date: Thu, 9 May 2019 13:10:42 +0200 Message-Id: <20190509111048.11151-9-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190509111048.11151-1-daniel.lezcano@linaro.org> References: <7e786ba3-a664-8fd9-dd17-6a5be996a712@linaro.org> <20190509111048.11151-1-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Alexandre Belloni Now that the driver is registered early enough, use the TCB as the sched_clock which is much more accurate than the jiffies implementation. Signed-off-by: Alexandre Belloni Signed-off-by: Daniel Lezcano --- drivers/clocksource/tcb_clksrc.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) -- 2.17.1 diff --git a/drivers/clocksource/tcb_clksrc.c b/drivers/clocksource/tcb_clksrc.c index bf68504da94a..9de8c10ab546 100644 --- a/drivers/clocksource/tcb_clksrc.c +++ b/drivers/clocksource/tcb_clksrc.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include @@ -114,6 +115,16 @@ static struct clocksource clksrc = { .resume = tc_clksrc_resume, }; +static u64 notrace tc_sched_clock_read(void) +{ + return tc_get_cycles(&clksrc); +} + +static u64 notrace tc_sched_clock_read32(void) +{ + return tc_get_cycles32(&clksrc); +} + #ifdef CONFIG_GENERIC_CLOCKEVENTS struct tc_clkevt_device { @@ -335,6 +346,7 @@ static int __init tcb_clksrc_init(struct device_node *node) struct atmel_tc tc; struct clk *t0_clk; const struct of_device_id *match; + u64 (*tc_sched_clock)(void); u32 rate, divided_rate = 0; int best_divisor_idx = -1; int clk32k_divisor_idx = -1; @@ -419,6 +431,7 @@ static int __init tcb_clksrc_init(struct device_node *node) clksrc.read = tc_get_cycles32; /* setup ony channel 0 */ tcb_setup_single_chan(&tc, best_divisor_idx); + tc_sched_clock = tc_sched_clock_read32; } else { /* we have three clocks no matter what the * underlying platform supports. @@ -430,6 +443,7 @@ static int __init tcb_clksrc_init(struct device_node *node) } /* setup both channel 0 & 1 */ tcb_setup_dual_chan(&tc, best_divisor_idx); + tc_sched_clock = tc_sched_clock_read; } /* and away we go! */ @@ -442,6 +456,8 @@ static int __init tcb_clksrc_init(struct device_node *node) if (ret) goto err_unregister_clksrc; + sched_clock_register(tc_sched_clock, 32, divided_rate); + return 0; err_unregister_clksrc: From patchwork Thu May 9 11:10:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 163710 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:142:0:0:0:0 with SMTP id j2csp819156ilr; Thu, 9 May 2019 04:12:13 -0700 (PDT) X-Google-Smtp-Source: APXvYqzjAYJi+9YrBjVkOpf14xPOTFMqIEkmCJvvupjfVr4NWNJ2p3ZQbYUNQ24EQWgofoDH+Hnp X-Received: by 2002:a17:902:5c5:: with SMTP id f63mr4035913plf.327.1557400333894; Thu, 09 May 2019 04:12:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1557400333; cv=none; d=google.com; s=arc-20160816; b=FUd/IyaK2xEdO/wLLexSDrnXwHdF90ElaumDpPhLIBh7jiLa6ZTIGbOXt8hAop4H4p dCuvOcUgGYaW3TIYXBCoputm/V37G4cTz+BTNYhOFJy+qSxLur9TMyUr1ZMdgKET/oDL TIUkT3xVYJWlmWK+V7Y5B8R5OrrWxadr9brPsuZAGTOM6gahoUokx7h47jLLmwjifyfB gdm83YCwLfnfIcDBw/Vm97kC7j4uqHPFMxUa2IXozL28io4z/9FtZSl+tUYhZtrMXk7H SX9MQeiJ9v+8Lk04e+ZHWtZG776fbqodcZWOfR3JdJQu7sAs7xwi8uiQipYEBuw8mBOS KfeA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=QCYNgLeacHF6Po+7GOvr1beHIPnLrcjXHBlwdHrGCU0=; b=fqxjHZDdr+7gq2vtGilmPjEIm1SAuJ9zKu7LCZPyHWt+f4TkXtbwfqixKrhhfXaLkO D4PMHt1U8uxBIWoxYm2RXgJu3dym3Jo1kLZfcX1qlvuIK6rjdYT2SnCGLenW19FmjeFW NvZy+kZhEWlNv9NwbBKircWvOseous6w0Y3+cssuaRyaf+gdkBqh4fJKf4CNbB2TGxpo NZGOwb8aEUlQbcMFD77NUtyzQaaxVqnGSFJo8H+Ru/T+ZynvudLVK2cXJ/jnhQFMOj3s XjwgqXWkKVrkRjyT67OnBFAfRL1WFnQTH8tWhPu7mFab133jJZ3fVMjwhq91N4T05Tnk jFsg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xrKRJ01F; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Alexandre Belloni Signed-off-by: Daniel Lezcano --- arch/arm/mach-at91/Kconfig | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) -- 2.17.1 diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 903f23c309df..da1d97a06c53 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -107,6 +107,29 @@ config SOC_AT91SAM9 AT91SAM9X35 AT91SAM9XE +comment "Clocksource driver selection" + +config ATMEL_CLOCKSOURCE_PIT + bool "Periodic Interval Timer (PIT) support" + depends on SOC_AT91SAM9 || SOC_SAMA5 + default SOC_AT91SAM9 || SOC_SAMA5 + select ATMEL_PIT + help + Select this to get a clocksource based on the Atmel Periodic Interval + Timer. It has a relatively low resolution and the TC Block clocksource + should be preferred. + +config ATMEL_CLOCKSOURCE_TCB + bool "Timer Counter Blocks (TCB) support" + default SOC_AT91RM9200 || SOC_AT91SAM9 || SOC_SAMA5 + select ATMEL_TCB_CLKSRC + help + Select this to get a high precision clocksource based on a + TC block with a 5+ MHz base clock rate. + On platforms with 16-bit counters, two timer channels are combined + to make a single 32-bit timer. + It can also be used as a clock event device supporting oneshot mode. + config HAVE_AT91_UTMI bool From patchwork Thu May 9 11:10:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 163705 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:142:0:0:0:0 with SMTP id j2csp818642ilr; Thu, 9 May 2019 04:11:49 -0700 (PDT) X-Google-Smtp-Source: APXvYqy2VnpHdPuALLIk1gvEcTKfoxYU9NBZHOr40PxB52vEsI35y+cCAhEQxTudXUNhWs+KgOp6 X-Received: by 2002:a17:902:567:: with SMTP id 94mr4132774plf.120.1557400309771; Thu, 09 May 2019 04:11:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1557400309; cv=none; d=google.com; s=arc-20160816; b=S59now9KD2Lrt00qnjWyyboYmsMXsBZu9BbbWwANR3lttw1NdfZkIVtIVRlWQWqye6 mPfqhspWCtZ/Ygr0Dc+uJvEIxjNsqi1ZulisQ3Qo0egXwoRZzPPcOEh9K0uqI2+tLyGd 9167fH7fXiu9BFzalh0nxAHoufcJ95v3GhyY2SL0yvd86aa3e5IjBblCLiEdMgV2Qs7G FGOXAlwNKqG7lKllgdNiYLQskIJW2jtANgXtk5LsOjyCA8HOTb8zC20vymJJ3uZraK8K P0be01ftshgmPwkkgzM+3aFiWTWI6vpYsA7gSYMQZ1pTznR32T+GD7s+j1omVZQAwspW Ctzw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=LvXnZafEYce3eQKqHnoNFRM0UdhTjWak2LbszgnoCDw=; b=C/LqGA+45dhFSbNd4CXThNWRStA3h7Sxzbuy7gGcmX8BvpYJuNoEtjqCNIWNaGqqrb 1nWkwoRtzkciqy3X04JzcvVreEeD5ad+g4nRfiDORT0RLgs5/MoEIPAry7USXHf++8Ys zocMUb+GhRaE8Yj7WUrQ/u3TbJD9cLfD8UrZK4ljk6pp9q5IjSAU9I1/GClCLFU55cyH GcriY9xXO5tUkJh1OS5wMpeXHz5E18QQv0WhIpoMx78xd9NzQJ/NooayEiODegSVBpdC PmPwWFhKdeklgGS06LSH4dU1u5jQE0BOh1srBxa4MduhVSMRNluxDgYvxGsh4b2f61X5 0vOA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=nVNkiLZZ; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g90si2243293plb.140.2019.05.09.04.11.49; Thu, 09 May 2019 04:11:49 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=nVNkiLZZ; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726771AbfEILLs (ORCPT + 30 others); Thu, 9 May 2019 07:11:48 -0400 Received: from mail-wr1-f66.google.com ([209.85.221.66]:46200 "EHLO mail-wr1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726715AbfEILLn (ORCPT ); Thu, 9 May 2019 07:11:43 -0400 Received: by mail-wr1-f66.google.com with SMTP id r7so1824236wrr.13 for ; Thu, 09 May 2019 04:11:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=LvXnZafEYce3eQKqHnoNFRM0UdhTjWak2LbszgnoCDw=; b=nVNkiLZZnD0l0mljltaU+TL2K/INQVTmvo6L6LxI4KN1XdK8+rV4sSWsBWCDaI0v2u 4MV/gdQ/dH//yjmesEhgh7co8VVsOg9SGz0aNJi3RMSiZNJN3uhnXNWjqYPg3i+7NE9g P9UG4KP4Wkn+o3i52xoJSa4mp90sh1Cu0F0XUfRXvhkjojFuWq5usvUFwTVVZxktGnz4 m9sdKKS5d9WX3FDpvhMfwERGRJm8Pc8S0w6keRmjiXlVF9SkrEQHLO6oHpBUtHiHzZTU s8pidw8/Xl2K9ntFRohkonecIOKkLuZCK8UKelRWP563YP6k8Qe0pLvW9rMEC6F1mIAb n1mg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=LvXnZafEYce3eQKqHnoNFRM0UdhTjWak2LbszgnoCDw=; b=MT2MTPY7OJaUSUl/pY1abi2zv962TH5VnWqXGw9Fz5rTbTYkLsQ/kF8wwEuKDEJmZ/ r+GIJTroTJMeUAouLq2FadLXnPOP/h5N+sTWXLLmM3iCHb4Ew8IxfHGoyJCm1ScwK+q6 u6frq7+Zgt6SHp/rfY/GBiG90Nt84l4NsoYK13FtPt9YzPvkS6z9f4/SiwMLRlspBDhv SmKKfJqkMdMpwteGFgtcFSPxfUGGk0UDS23PV4PEToqIv7SnmN8acAGClCXEgrcUQ8tc yyW3ddBy2bvHy1dsKhypsrhMrRRLdVzUw0MiQ6MuM9Y8d0dck2R0bbERqJcVRRMMWB0r nVSg== X-Gm-Message-State: APjAAAUsxCq8QXStGan2xzWbemo0up3BRTRDAJup5AApHQxPaZxJP3Nm rBHTc+WSLts8jbEmasHvMi/AQA== X-Received: by 2002:adf:f108:: with SMTP id r8mr814863wro.221.1557400301093; Thu, 09 May 2019 04:11:41 -0700 (PDT) Received: from mai.irit.fr ([141.115.39.235]) by smtp.gmail.com with ESMTPSA id z7sm2299778wme.26.2019.05.09.04.11.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 09 May 2019 04:11:40 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Alexandre Belloni , Arnd Bergmann , Greg Kroah-Hartman Subject: [PATCH 11/15] clocksource/drivers/tcb_clksrc: Move Kconfig option Date: Thu, 9 May 2019 13:10:44 +0200 Message-Id: <20190509111048.11151-11-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190509111048.11151-1-daniel.lezcano@linaro.org> References: <7e786ba3-a664-8fd9-dd17-6a5be996a712@linaro.org> <20190509111048.11151-1-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Alexandre Belloni Move the ATMEL_TCB_CLKSRC option to drivers/clocksource and make it silent if COMPILE_TEST is not selected. Cc: Arnd Bergmann Signed-off-by: Alexandre Belloni Signed-off-by: Daniel Lezcano --- drivers/clocksource/Kconfig | 7 +++++++ drivers/misc/Kconfig | 14 -------------- 2 files changed, 7 insertions(+), 14 deletions(-) -- 2.17.1 diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index ede5d20299b9..eb1560187434 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -410,6 +410,13 @@ config ATMEL_ST help Support for the Atmel ST timer. +config ATMEL_TCB_CLKSRC + bool "Atmel TC Block timer driver" if COMPILE_TEST + depends on HAS_IOMEM + select TIMER_OF if OF + help + Support for Timer Counter Blocks on Atmel SoCs. + config CLKSRC_EXYNOS_MCT bool "Exynos multi core timer driver" if COMPILE_TEST depends on ARM || ARM64 diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 268a01d3d6f3..c84033909395 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -59,20 +59,6 @@ config ATMEL_TCLIB blocks found on many Atmel processors. This facilitates using these blocks by different drivers despite processor differences. -config ATMEL_TCB_CLKSRC - bool "TC Block Clocksource" - depends on ARCH_AT91 - select TIMER_OF if OF - default y - help - Select this to get a high precision clocksource based on a - TC block with a 5+ MHz base clock rate. Two timer channels - are combined to make a single 32-bit timer. - - When GENERIC_CLOCKEVENTS is defined, the third timer channel - may be used as a clock event device supporting oneshot mode - (delays of up to two seconds) based on the 32 KiHz clock. - config DUMMY_IRQ tristate "Dummy IRQ handler" default n From patchwork Thu May 9 11:10:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 163707 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:142:0:0:0:0 with SMTP id j2csp818756ilr; Thu, 9 May 2019 04:11:54 -0700 (PDT) X-Google-Smtp-Source: APXvYqwrCeTEe7fUNfiB3Yraf3Hl/euN8+eGJgxpl9p2CJ5EgcuKRQL0UHQe+EIB/kA6EBaVDvvb X-Received: by 2002:a63:550c:: with SMTP id j12mr4554076pgb.450.1557400314735; Thu, 09 May 2019 04:11:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1557400314; cv=none; d=google.com; s=arc-20160816; b=GkDBgdA5L4TFtoZY7n84gBFjhUn3z4HNYaAPF5/gmm3bmIvymrygOuDYmPFY6b9d1v EmTQxdf6FwtoANU04kdbvHRrOlj/rx9/yFKkGslPe4O83SZ67aJer25yCADp0fi+7A3j sslSRG+8RcMXLVUboQKXDWOT2qdo58nVxO7YlkGGfBRBcDL71PcJS6Ne6MI6xaTHHZKi sD6HWsFwmQEL8K0zaBfXEMebZff47l5KiXqvAU6M6XIDnIbWWJ1+rMbinxvCYSYASUpo ojbpN/Ju7SuyTsR9awQb2dDIVO9fN3uhnAG8Y78x1xm/8xZnOo3gt7XG+c3ysLu4qLgK txKA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=UqB421RDZrmI+ZkHu7BcjtNVEU1ZDEYv3yb1vRTJinE=; b=u6nB8uyuWJKvE1bpznPS1U+pdgw1GiOwNPIJ81AbpyglEDH+Oqs6bcLsDz7plYqTM2 OwZXwIn601QJiVIs5xY/mPR8RLBaeyx2rTOnBXolkoCRoZTsaH3jLhOPzvKNDcHSvHNM khLPYROa9KG+BCIagJEUOKmvYO29gqgmm9Q+fCmdy0+PE62G8iU7JQgdgQxItng1CKXi YwMkRllR8NUhoF8Ge9dz1ucIPqu6Trq+E8c1Kw2/XRpAs1ovAXtujPXsFmhYbULZdkRu zYBKXRq/+V6LlpDxpiRz8W/g3BQLQM/wQBp63i72wntw/0AA4baGNYMmwcrPZmwKG+zW bWzA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FGNyjK32; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Also remove its default value so it can be disabled. Signed-off-by: Alexandre Belloni Signed-off-by: Daniel Lezcano --- drivers/clocksource/Kconfig | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index eb1560187434..2137f672a12f 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -399,8 +399,11 @@ config ARMV7M_SYSTICK This options enables support for the ARMv7M system timer unit config ATMEL_PIT + bool "Atmel PIT support" if COMPILE_TEST + depends on HAS_IOMEM select TIMER_OF if OF - def_bool SOC_AT91SAM9 || SOC_SAMA5 + help + Support for the Periodic Interval Timer found on Atmel SoCs. config ATMEL_ST bool "Atmel ST timer support" if COMPILE_TEST From patchwork Thu May 9 11:10:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 163706 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:142:0:0:0:0 with SMTP id j2csp818720ilr; Thu, 9 May 2019 04:11:53 -0700 (PDT) X-Google-Smtp-Source: APXvYqy67cFunPyD43NzMPGLeNINeW0YpPYvpIL7YI1xFa2b4J/ylAvju0CtAp76KKxzt3+gNtbP X-Received: by 2002:a63:a1a:: with SMTP id 26mr4469976pgk.11.1557400313103; Thu, 09 May 2019 04:11:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1557400313; cv=none; d=google.com; s=arc-20160816; b=fztx68cBpVAfZ5+DtTmgNzDoFgCW8vBFY5T2vXc0M3Ki3068pRTYoMC3GDl64nSb7E wEu9kQYpfunk3ctvCkWLxnDBrmUSy93IjzwOS4cU1RYrrhfTUQRa8T4R6+7NP+sH22br tqFA3ekCXXY9Y57O26YAjuXYP0tsTXGdE22e8UDdSGVHB7stCE1sHjpFRUYNP9ox10b6 0tyaKf+xpt729qI8WKu/vg3xYYuDBVfuG4zT8CZbbrexFp2SJaXWvnQ+WEd31trSXB3M zsM+LBA+nSd788rg89/6WMY6MQAjQBMeH+fxHrJFf1hX0Aqx6XUMrsBPgVPXjdgZnQtn f9gw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=56kLt7cMNMrr+o0ZwgjCRQvJlape+fGAyz5m6qcTE4M=; b=ky6W2IeTnfS2SlRBLJllrIZt0RKSPRKcblLHinDyqLo6zQJWdZP7Ha7SY7p+gG/KKU gZfITdjiioEqOVqAYq4SQE2ngIwja5Gq29F6xSXZA6n96yQ3LOwvQewB2kIEjg/7NBkc UXYCmaAcxCEFYbzq+5Rzmg1MKLex2bTL523h6rjhWHvvceWKoPwE/Hp+/R8+PfTu+R2g gFb5yuvGaDuRSc49V7XiCqfHVoHKvtETrXss8CJeDrBhG0A3blb2LKeO0AdcY6jbZlTL oyrVK2az1fYIj+bagTJa2K77k0eaadWWhPSafsK+aOs5rSkZBx4V/V07YeasDtCloNby F8bw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OUDkSeo5; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Alexandre Belloni Signed-off-by: Daniel Lezcano --- drivers/clocksource/Makefile | 2 +- drivers/clocksource/{tcb_clksrc.c => timer-atmel-tcb.c} | 0 2 files changed, 1 insertion(+), 1 deletion(-) rename drivers/clocksource/{tcb_clksrc.c => timer-atmel-tcb.c} (100%) -- 2.17.1 diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index be6e0fbc7489..923b9b60c909 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -3,7 +3,7 @@ obj-$(CONFIG_TIMER_OF) += timer-of.o obj-$(CONFIG_TIMER_PROBE) += timer-probe.o obj-$(CONFIG_ATMEL_PIT) += timer-atmel-pit.o obj-$(CONFIG_ATMEL_ST) += timer-atmel-st.o -obj-$(CONFIG_ATMEL_TCB_CLKSRC) += tcb_clksrc.o +obj-$(CONFIG_ATMEL_TCB_CLKSRC) += timer-atmel-tcb.o obj-$(CONFIG_X86_PM_TIMER) += acpi_pm.o obj-$(CONFIG_SCx200HR_TIMER) += scx200_hrt.o obj-$(CONFIG_CS5535_CLOCK_EVENT_SRC) += timer-cs5535.o diff --git a/drivers/clocksource/tcb_clksrc.c b/drivers/clocksource/timer-atmel-tcb.c similarity index 100% rename from drivers/clocksource/tcb_clksrc.c rename to drivers/clocksource/timer-atmel-tcb.c From patchwork Thu May 9 11:10:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 163709 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:142:0:0:0:0 with SMTP id j2csp818972ilr; Thu, 9 May 2019 04:12:05 -0700 (PDT) X-Google-Smtp-Source: APXvYqz69SXTNgygRM0YEFpSIMs92pOXyfN4vxLFnecP+GRAL0cI+wX84GapAKGa9dJ8nrqPoVGu X-Received: by 2002:a17:902:e407:: with SMTP id ci7mr4091977plb.219.1557400325105; Thu, 09 May 2019 04:12:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1557400325; cv=none; d=google.com; s=arc-20160816; b=ryoHFapHqwZzxplmWDTwvB5fZI37Ciw4EoRTkstzIwm4Qmf3gt5YjsOo0sQBABZL43 gdBaKoKS2Mi2knvxbJN8zBTL2En2b53MrZ+Kubmr0za5L6UEzGoUdi1ImDha5cDupod/ piW3ydDiLAD5E+yFX8t+vXK+rlPfiYy6tYD/Sypylo6umrRFQmv5qPEFGz2Kpc4qIC0u NKnrXRCfY08AFv9IFtpi/eCn09wNqwPY6lN9nlvcBgmQ4HFrnxDt8ezl3lNs8pxSmcEz AQDJRhb0pa3ucPBJuwt/c+YEBGVYoFf3HhRkVrkyu1ySLIpqvB2REMor3Tes7zmsVquA qaww== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=4vJDMe7+EQ4+NOcbJfE9TymlnXHgYOUGu64vsRLBkac=; b=fcsFIoXj9K9Hhiqlw2pYWFy+BovCvOwVY/av0BTvhJNjPPBIFv455S55cSm0Iew8wO OVpXV3ns8GXYeoE/7cOvwAZj3VNmj1umym7ufz8pZhM7SqHlMx7ecQz5DLo2dPMkxVlY QxQ2V1QhrSVegWG7j4s5fZJsGPCZTnA+elUzZtDqzyYRj+HqU22/RQIBCWDueTxRJz9J smWaicWywuJvAgux+rxKY4gQjz1QoCouLx1JJol0jgce90yxU5va3+fKZpHTvRCqRU4Q PzUitAXAcCoDmzyZtZdbEm7BGqlPOelZoED0eArRUypcNimG7SEzlTmX0Mmdqc29Mrf7 tkRg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=N1bOovgD; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: kbuild test robot Signed-off-by: Alexandre Belloni Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-atmel-tcb.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/drivers/clocksource/timer-atmel-tcb.c b/drivers/clocksource/timer-atmel-tcb.c index 9de8c10ab546..6ed31f9def7e 100644 --- a/drivers/clocksource/timer-atmel-tcb.c +++ b/drivers/clocksource/timer-atmel-tcb.c @@ -66,7 +66,7 @@ static u64 tc_get_cycles32(struct clocksource *cs) return readl_relaxed(tcaddr + ATMEL_TC_REG(0, CV)); } -void tc_clksrc_suspend(struct clocksource *cs) +static void tc_clksrc_suspend(struct clocksource *cs) { int i; @@ -81,7 +81,7 @@ void tc_clksrc_suspend(struct clocksource *cs) bmr_cache = readl(tcaddr + ATMEL_TC_BMR); } -void tc_clksrc_resume(struct clocksource *cs) +static void tc_clksrc_resume(struct clocksource *cs) { int i; From patchwork Thu May 9 11:10:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 163708 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:142:0:0:0:0 with SMTP id j2csp818795ilr; Thu, 9 May 2019 04:11:56 -0700 (PDT) X-Google-Smtp-Source: APXvYqyLyCaStTQLUOL0/IPVkA4M12EFVscf6F1Re3sZXg4ikzkzPHon8BkgeZkjK9UL+Jv1EGLS X-Received: by 2002:a17:902:bd0c:: with SMTP id p12mr4262037pls.50.1557400316514; Thu, 09 May 2019 04:11:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1557400316; cv=none; d=google.com; s=arc-20160816; b=saL35yUkDmcRpQSMRWP1Z4NrXgOezuGm6PWbEy1FEdsyFdDlfQWPoT97ayEexCffDM n0qsCgcUqUM3t8HqLdYRBSrP7Kqjs9ktevKuVUjUWQo6rQsfjSVzP9wvYhXUmfHl/kTV 2bmm6joajQqHoJn4yt2DaOoKl1KBFtLcn/UZkhLkC2uDa1yMawdT48yNeLBfSKRxJTZW T1XtupC7HbDSV7Hkmo0Vwx8mkpL6aKJf5GdrXGbQo0sazAWLIAMLMkzngnhSn96gUEeX hQkNr5wqvEU8Qv3pxL9V5ecHulB0AmA8kp/2XpLZBzcYwFV6bl6otyV0gQppj9N0o/an IPqg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=qVGkTtEbJGXMDq9yfYbvGEhm0nTx4/Q5KKy9E6G6Uls=; b=Y68FXtmB01Ab5XTIN6dVF/xVRNdQGEKG723Ko26OPmOwg1gHTbGP1IYr8kyqCkyBK7 rYqSfI1kY19FQUvOchp6MUSQtGf/ZUxjUvWFEzKLiLX6w0x+1dKnAWeivGnqA9SXwZuq RTnUaMBWmQF/Wp7kW448VeGzHhWG+MeWMkVkxSk+dQr599r/GZVYCEG/BOt3oRYSGS6A 5FNI0R7UDCDQ6BHwIvp0AAsQZolccQCnpapFEX1j+hQ2bQRQ9ptMqzn2wyH4l9f2uOoW O1G+Cnfg8KBDNNMAhiefsP6e/V33/rIVSJakCY/KZ/k+JOKb0e/TAK3v+RXNNGsopBD9 d6Bg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Q14zEwAV; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Subject: [PATCH 15/15] misc: atmel_tclib: Do not probe already used TCBs Date: Thu, 9 May 2019 13:10:48 +0200 Message-Id: <20190509111048.11151-15-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190509111048.11151-1-daniel.lezcano@linaro.org> References: <7e786ba3-a664-8fd9-dd17-6a5be996a712@linaro.org> <20190509111048.11151-1-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Alexandre Belloni The TCBs that have children are using the proper DT bindings and don't need to be handled by tclib. Acked-by: Greg Kroah-Hartman Signed-off-by: Alexandre Belloni Signed-off-by: Daniel Lezcano --- drivers/misc/atmel_tclib.c | 3 +++ 1 file changed, 3 insertions(+) -- 2.17.1 diff --git a/drivers/misc/atmel_tclib.c b/drivers/misc/atmel_tclib.c index 194f774ab3a1..2c6850ef0e9c 100644 --- a/drivers/misc/atmel_tclib.c +++ b/drivers/misc/atmel_tclib.c @@ -111,6 +111,9 @@ static int __init tc_probe(struct platform_device *pdev) struct resource *r; unsigned int i; + if (of_get_child_count(pdev->dev.of_node)) + return -EBUSY; + irq = platform_get_irq(pdev, 0); if (irq < 0) return -EINVAL;