From patchwork Wed Mar 8 23:38:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 660737 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 67270C74A44 for ; Wed, 8 Mar 2023 23:38:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229911AbjCHXie (ORCPT ); Wed, 8 Mar 2023 18:38:34 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37300 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229991AbjCHXic (ORCPT ); Wed, 8 Mar 2023 18:38:32 -0500 Received: from mail-oa1-x2a.google.com (mail-oa1-x2a.google.com [IPv6:2001:4860:4864:20::2a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 736F95DEEE for ; Wed, 8 Mar 2023 15:38:29 -0800 (PST) Received: by mail-oa1-x2a.google.com with SMTP id 586e51a60fabf-176e43eb199so544440fac.7 for ; Wed, 08 Mar 2023 15:38:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678318709; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xIF+TzoNCpNgaaPFRZQkOEM2aIrfReHqLZ5t062NKS8=; b=Ltdx//bI8+EcfFFzVD0xzgZ4Q9JkiCo8HulKF9GyblSCbeO0M/DRcxuu8WKR+GRUt9 6rkQSewqo20alox3EQ+oRwG64/ER6XRoEI5koKP+nd5pPV78gPeSp4lGf2DN5/bCpSVY UJXMb/luPG/27tbLPKu93kXMaa/V/kRtyHs6FCuQFYAfe6z9WSTqiELHdh+jywdC3Xi9 /SmYl5EyeUI02L1KMc8YjRjPQ9DJ6vAPhbRAiNAsR6cVUPZA/4Ge9azkkf0yoRDl7gAX HjzXlRtiCn4bzKRnerkvp3AwZTvxIHWPNfegjOTCQvix4WHDgZkfqcl1OftcgReOrEQX aCKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678318709; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xIF+TzoNCpNgaaPFRZQkOEM2aIrfReHqLZ5t062NKS8=; b=N7Y9TKXhbYxHPS1qQn2vOQxf0/D7U4tZ+aFwe70UVbbdBxSWPFLMpMVdm7rPb240my FxD7rKHh786VJVObk/PuqknUDwiWb9Mol26VUyHoVWb5TaXSColaXG3/UlP37nD2ssyE pz80IQOnT9Ao4pGF0XGCsTyYH7Rkg3KmddEqFFDdwGTl64/nEioXsPjUxtxXDwpYuY6Y 7L/Sm8lwhyWrLmpP75gZBebn1H3VUcFsMEBC/Ev2Pdvz28JT7gvn1TBTkQEbj4taI1YI BzQbH6Mv2N4tPqZtV3uz/FCyXWQLGPrBs31zPOkXU0skR2I4ndM5FatxEy68zit7DqeZ EJMQ== X-Gm-Message-State: AO0yUKV9aTfmTtMRQ27GmDGzMf3C3xCB/vodQAT/PePjNQghO9cw/do9 TalkSBmDjSXXLA656seh1oKnVA== X-Google-Smtp-Source: AK7set9VYwr+T8z+k6L0BS4GEK0pru9L4q1IR9HnAm4ODTR2MOgjxtRbVtTujQn6EOwctOvNq02Lpg== X-Received: by 2002:a05:6870:5703:b0:16e:9056:4a03 with SMTP id k3-20020a056870570300b0016e90564a03mr1788575oap.47.1678318709176; Wed, 08 Mar 2023 15:38:29 -0800 (PST) Received: from localhost ([136.49.140.41]) by smtp.gmail.com with ESMTPSA id m41-20020a4a952c000000b0051ff746e2b2sm6714646ooi.8.2023.03.08.15.38.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Mar 2023 15:38:28 -0800 (PST) From: Sam Protsenko To: Krzysztof Kozlowski , Rob Herring , Sylwester Nawrocki Cc: Marek Szyprowski , Tomasz Figa , Chanwoo Choi , Chanho Park , David Virag , Alim Akhtar , Michael Turquette , Stephen Boyd , linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/7] clk: samsung: exynos850: Make PMU_ALIVE_PCLK critical Date: Wed, 8 Mar 2023 17:38:19 -0600 Message-Id: <20230308233822.31180-5-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230308233822.31180-1-semen.protsenko@linaro.org> References: <20230308233822.31180-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org PMU_ALIVE_PCLK is needed for PMU registers access, and it must be always running, as not only the kernel accesses PMU registers. Make it critical to ensure that. Signed-off-by: Sam Protsenko --- drivers/clk/samsung/clk-exynos850.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk-exynos850.c b/drivers/clk/samsung/clk-exynos850.c index 6ab5fa8c2ef3..98b23af7324d 100644 --- a/drivers/clk/samsung/clk-exynos850.c +++ b/drivers/clk/samsung/clk-exynos850.c @@ -612,7 +612,7 @@ static const struct samsung_gate_clock apm_gate_clks[] __initconst = { CLK_CON_GAT_GOUT_APM_APBIF_GPIO_ALIVE_PCLK, 21, CLK_IGNORE_UNUSED, 0), GATE(CLK_GOUT_PMU_ALIVE_PCLK, "gout_pmu_alive_pclk", "dout_apm_bus", - CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK, 21, 0, 0), + CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK, 21, CLK_IS_CRITICAL, 0), GATE(CLK_GOUT_SYSREG_APM_PCLK, "gout_sysreg_apm_pclk", "dout_apm_bus", CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK, 21, 0, 0), }; From patchwork Wed Mar 8 23:38:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 660736 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E4A19C6FD19 for ; Wed, 8 Mar 2023 23:38:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230147AbjCHXis (ORCPT ); Wed, 8 Mar 2023 18:38:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37646 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230242AbjCHXie (ORCPT ); Wed, 8 Mar 2023 18:38:34 -0500 Received: from mail-oi1-x22c.google.com (mail-oi1-x22c.google.com [IPv6:2607:f8b0:4864:20::22c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 463845FE94 for ; Wed, 8 Mar 2023 15:38:31 -0800 (PST) Received: by mail-oi1-x22c.google.com with SMTP id bh20so356662oib.9 for ; Wed, 08 Mar 2023 15:38:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678318710; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=OhdSRqJaGfztHCYkWeNpp02lhvYbsG6+3kQCkkXc7Pc=; b=myK0jC+/mCPv7bj4QZjfKujIW7s5qz4C4CX+hrTsKV0Ed2EcuIjpHKLR2ZVa2Q0lKT 1WDrcUgQmd+9rr7lZg1UzoTZmzQcwMIxwVhjJBlWSkAz5YDruoqRks2ox9oJfMkZ2AR/ x0xYrt0Al4un/UhGeMGmiYZsHgSW9N1rCq75w7c6ENYcw4ldbAfM2HQCHzp7aSGKKiST jXDhQF+NMIxHO7JbBkl48Q42o5abcxJd6C2TGlUPdirgIJTZgQw5RxmdwLR+pv9TkQah 3O/NFu1H/IH2BpSFtvvc2RLQfV7gXiE0mHh3nlgSFKVEgTqPul36zZvyYEBsPEX+uvKX XQFw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678318710; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OhdSRqJaGfztHCYkWeNpp02lhvYbsG6+3kQCkkXc7Pc=; b=gqOgONqYZO1PuJBGvAbB09SQydHcIbW5B0aaLyiC0IKlKR/yWcEIJvRv0QqfSRuwrF cGX36nQHdBE0JKQqQ4m1JfK0+ztGdaRabSlHQrrn6G8hELsTn8/M8NkiLlFyykS56/U6 cZjguCWETfKwHL4y+MKIeoFw5CYkg2G5k7oxjYFhkGZBrC79Rxlhfuqke+fdtWJtjBvv PRCpZYaLi4T21VeueWN5rLW0soGQz8tU1ZROKLVRdP88qrwFZkfnlED5Hy2ke44qUQEx C2L5qA3kPzGog3mo5AVP7LdrfwSthbSbfTsOFEI4f/MeQTitpdEqwjbDF3q6OlLL8jLR nCBA== X-Gm-Message-State: AO0yUKX5KzoIdyCMaAwXsOiAtNw5loOv6fdUD5qxXiDgcoVLgbcjyfkx htC4PcqL8+bm4uQRTmiHnJcKqA== X-Google-Smtp-Source: AK7set/5z392BFVptFZBGokctJdIkZ9WCLRF4yHopeCLA19ESHC4RJaazlSVqK2iAy92qLm8tsbZXA== X-Received: by 2002:a05:6808:188:b0:384:232:2a4f with SMTP id w8-20020a056808018800b0038402322a4fmr7731504oic.4.1678318710527; Wed, 08 Mar 2023 15:38:30 -0800 (PST) Received: from localhost ([136.49.140.41]) by smtp.gmail.com with ESMTPSA id f8-20020a9d2c08000000b00690dc5d9b9esm7021525otb.6.2023.03.08.15.38.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Mar 2023 15:38:30 -0800 (PST) From: Sam Protsenko To: Krzysztof Kozlowski , Rob Herring , Sylwester Nawrocki Cc: Marek Szyprowski , Tomasz Figa , Chanwoo Choi , Chanho Park , David Virag , Alim Akhtar , Michael Turquette , Stephen Boyd , linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 5/7] clk: samsung: exynos850: Add suspend state for all CMUs Date: Wed, 8 Mar 2023 17:38:20 -0600 Message-Id: <20230308233822.31180-6-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230308233822.31180-1-semen.protsenko@linaro.org> References: <20230308233822.31180-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Before entering suspend, some clocks must be set to some specific configuration. For example, top-level MUX clocks in each CMU should be switched to OSCCLK input, etc. This is needed by the firmware to properly perform system suspend operation. Provide the suspend state for mentioned clocks using 'suspend_regs' feature. This patch was inspired by commit a766065279e2 ("clk: samsung: exynos5433: Add suspend state for TOP, CPIF & PERIC CMUs"). Signed-off-by: Sam Protsenko --- drivers/clk/samsung/clk-exynos850.c | 92 +++++++++++++++++++++++++++++ 1 file changed, 92 insertions(+) diff --git a/drivers/clk/samsung/clk-exynos850.c b/drivers/clk/samsung/clk-exynos850.c index 98b23af7324d..5664d17bae83 100644 --- a/drivers/clk/samsung/clk-exynos850.c +++ b/drivers/clk/samsung/clk-exynos850.c @@ -186,6 +186,12 @@ static const unsigned long top_clk_regs[] __initconst = { CLK_CON_GAT_GATE_CLKCMU_PERI_UART, }; +static const struct samsung_clk_reg_dump top_suspend_regs[] = { + { PLL_CON0_PLL_MMC, 0 }, + { PLL_CON0_PLL_SHARED0, 0 }, + { PLL_CON0_PLL_SHARED1, 0 }, +}; + /* * Do not provide PLL tables to core PLLs, as MANUAL_PLL_CTRL bit is not set * for those PLLs by default, so set_rate operation would fail. @@ -489,6 +495,8 @@ static const struct samsung_cmu_info top_cmu_info __initconst = { .nr_clk_ids = TOP_NR_CLK, .clk_regs = top_clk_regs, .nr_clk_regs = ARRAY_SIZE(top_clk_regs), + .suspend_regs = top_suspend_regs, + .nr_suspend_regs = ARRAY_SIZE(top_suspend_regs), }; static void __init exynos850_cmu_top_init(struct device_node *np) @@ -547,6 +555,13 @@ static const unsigned long apm_clk_regs[] __initconst = { CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK, }; +static const struct samsung_clk_reg_dump apm_suspend_regs[] = { + { PLL_CON0_MUX_CLKCMU_APM_BUS_USER, 0 }, + { PLL_CON0_MUX_CLK_RCO_APM_I3C_USER, 0 }, + { PLL_CON0_MUX_CLK_RCO_APM_USER, 0 }, + { PLL_CON0_MUX_DLL_USER, 0 }, +}; + /* List of parent clocks for Muxes in CMU_APM */ PNAME(mout_apm_bus_user_p) = { "oscclk_rco_apm", "dout_clkcmu_apm_bus" }; PNAME(mout_rco_apm_i3c_user_p) = { "oscclk_rco_apm", "clk_rco_i3c_pmic" }; @@ -629,6 +644,8 @@ static const struct samsung_cmu_info apm_cmu_info __initconst = { .nr_clk_ids = APM_NR_CLK, .clk_regs = apm_clk_regs, .nr_clk_regs = ARRAY_SIZE(apm_clk_regs), + .suspend_regs = apm_suspend_regs, + .nr_suspend_regs = ARRAY_SIZE(apm_suspend_regs), .clk_name = "dout_clkcmu_apm_bus", }; @@ -746,6 +763,12 @@ static const unsigned long aud_clk_regs[] __initconst = { CLK_CON_GAT_GOUT_AUD_WDT_PCLK, }; +static const struct samsung_clk_reg_dump aud_suspend_regs[] = { + { PLL_CON0_PLL_AUD, 0 }, + { PLL_CON0_MUX_CLKCMU_AUD_CPU_USER, 0 }, + { PLL_CON0_MUX_TICK_USB_USER, 0 }, +}; + /* List of parent clocks for Muxes in CMU_AUD */ PNAME(mout_aud_pll_p) = { "oscclk", "fout_aud_pll" }; PNAME(mout_aud_cpu_user_p) = { "oscclk", "dout_aud" }; @@ -912,6 +935,8 @@ static const struct samsung_cmu_info aud_cmu_info __initconst = { .nr_clk_ids = AUD_NR_CLK, .clk_regs = aud_clk_regs, .nr_clk_regs = ARRAY_SIZE(aud_clk_regs), + .suspend_regs = aud_suspend_regs, + .nr_suspend_regs = ARRAY_SIZE(aud_suspend_regs), .clk_name = "dout_aud", }; @@ -950,6 +975,12 @@ static const unsigned long cmgp_clk_regs[] __initconst = { CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK, }; +static const struct samsung_clk_reg_dump cmgp_suspend_regs[] = { + { CLK_CON_MUX_CLK_CMGP_ADC, 0 }, + { CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0, 0 }, + { CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1, 0 }, +}; + /* List of parent clocks for Muxes in CMU_CMGP */ PNAME(mout_cmgp_usi0_p) = { "clk_rco_cmgp", "gout_clkcmu_cmgp_bus" }; PNAME(mout_cmgp_usi1_p) = { "clk_rco_cmgp", "gout_clkcmu_cmgp_bus" }; @@ -1015,6 +1046,8 @@ static const struct samsung_cmu_info cmgp_cmu_info __initconst = { .nr_clk_ids = CMGP_NR_CLK, .clk_regs = cmgp_clk_regs, .nr_clk_regs = ARRAY_SIZE(cmgp_clk_regs), + .suspend_regs = cmgp_suspend_regs, + .nr_suspend_regs = ARRAY_SIZE(cmgp_suspend_regs), .clk_name = "gout_clkcmu_cmgp_bus", }; @@ -1051,6 +1084,11 @@ static const unsigned long g3d_clk_regs[] __initconst = { CLK_CON_GAT_GOUT_G3D_SYSREG_PCLK, }; +static const struct samsung_clk_reg_dump g3d_suspend_regs[] = { + { PLL_CON0_PLL_G3D, 0 }, + { PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER, 0 }, +}; + /* List of parent clocks for Muxes in CMU_G3D */ PNAME(mout_g3d_pll_p) = { "oscclk", "fout_g3d_pll" }; PNAME(mout_g3d_switch_user_p) = { "oscclk", "dout_g3d_switch" }; @@ -1111,6 +1149,8 @@ static const struct samsung_cmu_info g3d_cmu_info __initconst = { .nr_clk_ids = G3D_NR_CLK, .clk_regs = g3d_clk_regs, .nr_clk_regs = ARRAY_SIZE(g3d_clk_regs), + .suspend_regs = g3d_suspend_regs, + .nr_suspend_regs = ARRAY_SIZE(g3d_suspend_regs), .clk_name = "dout_g3d_switch", }; @@ -1153,6 +1193,13 @@ static const unsigned long hsi_clk_regs[] __initconst = { CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY, }; +static const struct samsung_clk_reg_dump hsi_suspend_regs[] = { + { PLL_CON0_MUX_CLKCMU_HSI_BUS_USER, 0 }, + { PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER, 0 }, + { PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER, 0 }, + { CLK_CON_MUX_MUX_CLK_HSI_RTC, 0 }, +}; + /* List of parent clocks for Muxes in CMU_HSI */ PNAME(mout_hsi_bus_user_p) = { "oscclk", "dout_hsi_bus" }; PNAME(mout_hsi_mmc_card_user_p) = { "oscclk", "dout_hsi_mmc_card" }; @@ -1213,6 +1260,8 @@ static const struct samsung_cmu_info hsi_cmu_info __initconst = { .nr_clk_ids = HSI_NR_CLK, .clk_regs = hsi_clk_regs, .nr_clk_regs = ARRAY_SIZE(hsi_clk_regs), + .suspend_regs = hsi_suspend_regs, + .nr_suspend_regs = ARRAY_SIZE(hsi_suspend_regs), .clk_name = "dout_hsi_bus", }; @@ -1268,6 +1317,13 @@ static const unsigned long is_clk_regs[] __initconst = { CLK_CON_GAT_GOUT_IS_SYSREG_PCLK, }; +static const struct samsung_clk_reg_dump is_suspend_regs[] = { + { PLL_CON0_MUX_CLKCMU_IS_BUS_USER, 0 }, + { PLL_CON0_MUX_CLKCMU_IS_GDC_USER, 0 }, + { PLL_CON0_MUX_CLKCMU_IS_ITP_USER, 0 }, + { PLL_CON0_MUX_CLKCMU_IS_VRA_USER, 0 }, +}; + /* List of parent clocks for Muxes in CMU_IS */ PNAME(mout_is_bus_user_p) = { "oscclk", "dout_is_bus" }; PNAME(mout_is_itp_user_p) = { "oscclk", "dout_is_itp" }; @@ -1345,6 +1401,8 @@ static const struct samsung_cmu_info is_cmu_info __initconst = { .nr_clk_ids = IS_NR_CLK, .clk_regs = is_clk_regs, .nr_clk_regs = ARRAY_SIZE(is_clk_regs), + .suspend_regs = is_suspend_regs, + .nr_suspend_regs = ARRAY_SIZE(is_suspend_regs), .clk_name = "dout_is_bus", }; @@ -1384,6 +1442,13 @@ static const unsigned long mfcmscl_clk_regs[] __initconst = { CLK_CON_GAT_GOUT_MFCMSCL_SYSREG_PCLK, }; +static const struct samsung_clk_reg_dump mfcmscl_suspend_regs[] = { + { PLL_CON0_MUX_CLKCMU_MFCMSCL_JPEG_USER, 0 }, + { PLL_CON0_MUX_CLKCMU_MFCMSCL_M2M_USER, 0 }, + { PLL_CON0_MUX_CLKCMU_MFCMSCL_MCSC_USER, 0 }, + { PLL_CON0_MUX_CLKCMU_MFCMSCL_MFC_USER, 0 }, +}; + /* List of parent clocks for Muxes in CMU_MFCMSCL */ PNAME(mout_mfcmscl_mfc_user_p) = { "oscclk", "dout_mfcmscl_mfc" }; PNAME(mout_mfcmscl_m2m_user_p) = { "oscclk", "dout_mfcmscl_m2m" }; @@ -1454,6 +1519,8 @@ static const struct samsung_cmu_info mfcmscl_cmu_info __initconst = { .nr_clk_ids = MFCMSCL_NR_CLK, .clk_regs = mfcmscl_clk_regs, .nr_clk_regs = ARRAY_SIZE(mfcmscl_clk_regs), + .suspend_regs = mfcmscl_suspend_regs, + .nr_suspend_regs = ARRAY_SIZE(mfcmscl_suspend_regs), .clk_name = "dout_mfcmscl_mfc", }; @@ -1532,6 +1599,13 @@ static const unsigned long peri_clk_regs[] __initconst = { CLK_CON_GAT_GOUT_PERI_WDT_1_PCLK, }; +static const struct samsung_clk_reg_dump peri_suspend_regs[] = { + { PLL_CON0_MUX_CLKCMU_PERI_BUS_USER, 0 }, + { PLL_CON0_MUX_CLKCMU_PERI_HSI2C_USER, 0 }, + { PLL_CON0_MUX_CLKCMU_PERI_SPI_USER, 0 }, + { PLL_CON0_MUX_CLKCMU_PERI_UART_USER, 0 }, +}; + /* List of parent clocks for Muxes in CMU_PERI */ PNAME(mout_peri_bus_user_p) = { "oscclk", "dout_peri_bus" }; PNAME(mout_peri_uart_user_p) = { "oscclk", "dout_peri_uart" }; @@ -1629,6 +1703,8 @@ static const struct samsung_cmu_info peri_cmu_info __initconst = { .nr_clk_ids = PERI_NR_CLK, .clk_regs = peri_clk_regs, .nr_clk_regs = ARRAY_SIZE(peri_clk_regs), + .suspend_regs = peri_suspend_regs, + .nr_suspend_regs = ARRAY_SIZE(peri_suspend_regs), .clk_name = "dout_peri_bus", }; @@ -1676,6 +1752,14 @@ static const unsigned long core_clk_regs[] __initconst = { CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK, }; +static const struct samsung_clk_reg_dump core_suspend_regs[] = { + { PLL_CON0_MUX_CLKCMU_CORE_BUS_USER, 0 }, + { PLL_CON0_MUX_CLKCMU_CORE_CCI_USER, 0 }, + { PLL_CON0_MUX_CLKCMU_CORE_MMC_EMBD_USER, 0 }, + { PLL_CON0_MUX_CLKCMU_CORE_SSS_USER, 0 }, + { CLK_CON_MUX_MUX_CLK_CORE_GIC, 0x1 }, +}; + /* List of parent clocks for Muxes in CMU_CORE */ PNAME(mout_core_bus_user_p) = { "oscclk", "dout_core_bus" }; PNAME(mout_core_cci_user_p) = { "oscclk", "dout_core_cci" }; @@ -1736,6 +1820,8 @@ static const struct samsung_cmu_info core_cmu_info __initconst = { .nr_clk_ids = CORE_NR_CLK, .clk_regs = core_clk_regs, .nr_clk_regs = ARRAY_SIZE(core_clk_regs), + .suspend_regs = core_suspend_regs, + .nr_suspend_regs = ARRAY_SIZE(core_suspend_regs), .clk_name = "dout_core_bus", }; @@ -1766,6 +1852,10 @@ static const unsigned long dpu_clk_regs[] __initconst = { CLK_CON_GAT_GOUT_DPU_SYSREG_PCLK, }; +static const struct samsung_clk_reg_dump dpu_suspend_regs[] = { + { PLL_CON0_MUX_CLKCMU_DPU_USER, 0 }, +}; + /* List of parent clocks for Muxes in CMU_DPU */ PNAME(mout_dpu_user_p) = { "oscclk", "dout_dpu" }; @@ -1810,6 +1900,8 @@ static const struct samsung_cmu_info dpu_cmu_info __initconst = { .nr_clk_ids = DPU_NR_CLK, .clk_regs = dpu_clk_regs, .nr_clk_regs = ARRAY_SIZE(dpu_clk_regs), + .suspend_regs = dpu_suspend_regs, + .nr_suspend_regs = ARRAY_SIZE(dpu_suspend_regs), .clk_name = "dout_dpu", }; From patchwork Wed Mar 8 23:38:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 660735 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CF777C64EC4 for ; Wed, 8 Mar 2023 23:39:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230323AbjCHXjL (ORCPT ); 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Wed, 08 Mar 2023 15:38:32 -0800 (PST) From: Sam Protsenko To: Krzysztof Kozlowski , Rob Herring , Sylwester Nawrocki Cc: Marek Szyprowski , Tomasz Figa , Chanwoo Choi , Chanho Park , David Virag , Alim Akhtar , Michael Turquette , Stephen Boyd , linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 7/7] arm64: dts: exynos: Remove clock from Exynos850 pmu_system_controller Date: Wed, 8 Mar 2023 17:38:22 -0600 Message-Id: <20230308233822.31180-8-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230308233822.31180-1-semen.protsenko@linaro.org> References: <20230308233822.31180-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org As described in the corresponding binding documentation for "samsung,exynos850-pmu", the "clocks" property should be used for specifying CLKOUT mux inputs. Therefore, the clock provided to exynos850 pmu_system_controller is incorrect and should be removed. Instead of making syscon regmap keep that clock running for PMU accesses, it should be made always running in the clock driver, because the kernel is not the only software accessing PMU registers on Exynos850 platform. Signed-off-by: Sam Protsenko --- arch/arm64/boot/dts/exynos/exynos850.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/exynos/exynos850.dtsi b/arch/arm64/boot/dts/exynos/exynos850.dtsi index d67e98120313..aa077008b3be 100644 --- a/arch/arm64/boot/dts/exynos/exynos850.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos850.dtsi @@ -200,7 +200,6 @@ gic: interrupt-controller@12a01000 { pmu_system_controller: system-controller@11860000 { compatible = "samsung,exynos850-pmu", "syscon"; reg = <0x11860000 0x10000>; - clocks = <&cmu_apm CLK_GOUT_PMU_ALIVE_PCLK>; reboot: syscon-reboot { compatible = "syscon-reboot";