From patchwork Tue May 14 12:21:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 164154 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp2552239ili; Tue, 14 May 2019 05:23:16 -0700 (PDT) X-Google-Smtp-Source: APXvYqzXRZhQjH56JaPmA3xFpgOiBkTBB7VT3LFrjHu3JAIQF2qV267gVRVRNRxQEllYeZBzj7TZ X-Received: by 2002:a6b:b988:: with SMTP id j130mr7053370iof.255.1557836596132; Tue, 14 May 2019 05:23:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1557836596; cv=none; d=google.com; s=arc-20160816; b=vg53JYxsIzAHi9lgUGZ65hPV+qaRREtsFp5W5VbM6Qpi8l6h/zuiKC6y483/edCamG m+kel/h11IQa7+fosnOVR57X6nRIMJ16uyB5OjQT1MCJ68kN4VMdyHUjI76L3RPcVUwo jM0smAS22MgTL86XChCHBuDK4kutUQTEInKjsAtqsb+BDoqfRad3Rx1OqrHt+5k0hotI 6Ez++92olbPKYuUvgI8oWeGOY+kGk1CosKuenn/ovlG2SPFpPlWp4KZkG2Jek9MLIDhM iBp5cmfHYtG+v0tU5fdDmhlAnrNM5tuSkq02VLpUcL0P63+gVwyFNScANMehmZ5vQUVf FmgA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=l7IMz6SmFkbIDcRqmOwsxEm6qLyqX/4jEzjnX1BC1qQ=; b=M8WjbGSgLEJXIG5ZciQtE+LXxhd4hMFmuDinJOtYCT+0jbp9KSFg4Zk7MHXl80GLIo BXXY8cEEE5jogf7BB8vhVltYBs4Qn+0lQdRPy1u8tgOg0hfmyYoVGCEnT4LgPg+qX5A3 G/vDVQ6rYwOQMHCw2ogtgBG7M9mnc2ztOJvmrlLAf7q20jSY6k3HJ5aVl6Lce0J15w59 plDbCC4gQFTTqp9y/GsLpPMFUr6ZpXdQO93++ZtDExMXUpPw0P8AbkORcKHLpg9Zomt2 mM33SlnXBEZao2y+R6fQz83wdYOL5oYjqLIzorWY3j73yvM8kspbVuf0FXkzly+pRjA7 sJ+Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id 7si1428799itv.107.2019.05.14.05.23.16 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 14 May 2019 05:23:16 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hQWRH-00086W-Py; Tue, 14 May 2019 12:21:47 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hQWRG-00086L-Az for xen-devel@lists.xenproject.org; Tue, 14 May 2019 12:21:46 +0000 X-Inumbo-ID: d6900b1c-7642-11e9-bdcd-e7faff90497c Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTP id d6900b1c-7642-11e9-bdcd-e7faff90497c; Tue, 14 May 2019 12:21:45 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D936615AB; Tue, 14 May 2019 05:21:44 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C98B43F71E; Tue, 14 May 2019 05:21:43 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Tue, 14 May 2019 13:21:10 +0100 Message-Id: <20190514122136.28215-2-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190514122136.28215-1-julien.grall@arm.com> References: <20190514122136.28215-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH MM-PART1 v3 1/8] xen/arm: Don't boot Xen on platform using AIVIVT instruction caches X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Oleksandr_Tyshchenko@epam.com, Julien Grall , Stefano Stabellini , Andrii_Anisov@epam.com MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The AIVIVT is a type of instruction cache available on Armv7. This is the only cache not implementing the IVIPT extension and therefore requiring specific care. To simplify maintenance requirements, Xen will not boot on platform using AIVIVT cache. This should not be an issue because Xen Arm32 can only boot on a small number of processors (see arch/arm/arm32/proc-v7.S). All of them are not using AIVIVT cache. Signed-off-by: Julien Grall --- Changes in v3: - Patch added --- xen/arch/arm/setup.c | 5 +++++ xen/include/asm-arm/processor.h | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/xen/arch/arm/setup.c b/xen/arch/arm/setup.c index ccb0f181ea..faaf029b99 100644 --- a/xen/arch/arm/setup.c +++ b/xen/arch/arm/setup.c @@ -526,10 +526,15 @@ static void __init setup_mm(unsigned long dtb_paddr, size_t dtb_size) unsigned long boot_mfn_start, boot_mfn_end; int i; void *fdt; + const uint32_t ctr = READ_CP32(CTR); if ( !bootinfo.mem.nr_banks ) panic("No memory bank\n"); + /* We only supports instruction caches implementing the IVIPT extension. */ + if ( ((ctr >> CTR_L1Ip_SHIFT) & CTR_L1Ip_MASK) == CTR_L1Ip_AIVIVT ) + panic("AIVIVT instruction cache not supported\n"); + init_pdx(); ram_start = bootinfo.mem.bank[0].start; diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h index b5f515805d..04b05b3f39 100644 --- a/xen/include/asm-arm/processor.h +++ b/xen/include/asm-arm/processor.h @@ -6,6 +6,11 @@ #endif #include +/* CTR Cache Type Register */ +#define CTR_L1Ip_MASK 0x3 +#define CTR_L1Ip_SHIFT 14 +#define CTR_L1Ip_AIVIVT 0x1 + /* MIDR Main ID Register */ #define MIDR_REVISION_MASK 0xf #define MIDR_RESIVION(midr) ((midr) & MIDR_REVISION_MASK) From patchwork Tue May 14 12:21:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 164157 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp2552261ili; Tue, 14 May 2019 05:23:17 -0700 (PDT) X-Google-Smtp-Source: APXvYqyjEfZZbTGbfQcybQwxw1lKENh3CavOKNL+f0lAxT790PddO9fO1jot92wHJaGW7XacopQr X-Received: by 2002:a24:4d1:: with SMTP id 200mr3224257itb.92.1557836596986; Tue, 14 May 2019 05:23:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1557836596; cv=none; d=google.com; s=arc-20160816; b=hR+LO/y05D/mSGct2TqkJ/0oEF502T/nnjcds5E3DkGFB60OakgvPLq0urZ/yKURaH Elm3PUnkkAwpWgm+YIsv2WUe8PWTzxXTkU199EFPE7TVH/tPJ/Zpt83TiGYitm8R+7V1 +NsFa/ykWYPnBf5MubIxEGN6iSB0GQpk3FBZJY8kWoahlpeS9yaCglKnC+tS5oZOjAF5 Ur8H8mfCglhiT07FaBPCpkxCrogH6ldQJurbnIm3ey1PogWGzxM2qw9gMMuXQCjDFbg+ v+NNECj248yn1XHZN2s/bC5bVZ09qE3RzmEyHzODw0nlds5+swwQwX6X26ScJDERaEM7 /mOA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=BhTZ+0klaTehJOtVb+DOx1H9QOZvkNN7IXM574DSmRw=; b=Omfw8tEy0YZFS4i/zHWbagKUBhbdUh1kaBJgNpN3QxFAqSPf3XrzRcNaSsE+2CMUvb H6xpy68BeuIHsofTz2JrToImTSs6k++YSH9PlP8hBENgP6KcGEv3KDK6Pd/LAeWS6C0i 3vDjllOgwIvTeS0YxdV0nKeDk8jOP0eBV5XngiXLy3NbXkgolo0vy4zIRwbpI4FZz8L7 ozghjfllJ10aSXgpUqrY7YPsmN8k6IToWWJFFWX2UP1Wx/tFxv9QnePSa1H6M4y+B9RR 53MxoW4iKsH+LY4Qxm1yq8CACRie5wgVGwLQsRg1xQV/nrZR++tvEzmtBn2Z2OmoP+7G 6PPQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id o21si8199350ioa.123.2019.05.14.05.23.16 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 14 May 2019 05:23:16 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hQWRM-00088E-Kw; Tue, 14 May 2019 12:21:52 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hQWRK-000878-Q8 for xen-devel@lists.xenproject.org; Tue, 14 May 2019 12:21:50 +0000 X-Inumbo-ID: d8e5a58f-7642-11e9-8980-bc764e045a96 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id d8e5a58f-7642-11e9-8980-bc764e045a96; Tue, 14 May 2019 12:21:49 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CDBC515AB; Tue, 14 May 2019 05:21:48 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 9A8B83F71E; Tue, 14 May 2019 05:21:47 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Tue, 14 May 2019 13:21:12 +0100 Message-Id: <20190514122136.28215-4-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190514122136.28215-1-julien.grall@arm.com> References: <20190514122136.28215-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH MM-PART1 v3 2/8] xen/arm: mm: Consolidate setting SCTLR_EL2.WXN in a single place X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Oleksandr_Tyshchenko@epam.com, Julien Grall , Stefano Stabellini , Andrii Anisov MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The logic to set SCTLR_EL2.WXN is the same for the boot CPU and non-boot CPU. So introduce a function to set the bit and clear TLBs. This new function will help us to document and update the logic in a single place. Signed-off-by: Julien Grall Reviewed-by: Andrii Anisov Reviewed-by: Stefano Stabellini --- Changes in v3: - Add Stefano's reviewed-by Changes in v2: - Fix typo in the commit message - Add Andrii's reviewed-by --- xen/arch/arm/mm.c | 22 +++++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c index 01ae2cccc0..93ad118183 100644 --- a/xen/arch/arm/mm.c +++ b/xen/arch/arm/mm.c @@ -601,6 +601,19 @@ void __init remove_early_mappings(void) flush_xen_data_tlb_range_va(BOOT_FDT_VIRT_START, BOOT_FDT_SLOT_SIZE); } +/* + * After boot, Xen page-tables should not contain mapping that are both + * Writable and eXecutables. + * + * This should be called on each CPU to enforce the policy. + */ +static void xen_pt_enforce_wnx(void) +{ + WRITE_SYSREG32(READ_SYSREG32(SCTLR_EL2) | SCTLR_WXN, SCTLR_EL2); + /* Flush everything after setting WXN bit. */ + flush_xen_text_tlb_local(); +} + extern void switch_ttbr(uint64_t ttbr); /* Clear a translation table and clean & invalidate the cache */ @@ -702,10 +715,7 @@ void __init setup_pagetables(unsigned long boot_phys_offset) clear_table(boot_second); clear_table(boot_third); - /* From now on, no mapping may be both writable and executable. */ - WRITE_SYSREG32(READ_SYSREG32(SCTLR_EL2) | SCTLR_WXN, SCTLR_EL2); - /* Flush everything after setting WXN bit. */ - flush_xen_text_tlb_local(); + xen_pt_enforce_wnx(); #ifdef CONFIG_ARM_32 per_cpu(xen_pgtable, 0) = cpu0_pgtable; @@ -777,9 +787,7 @@ int init_secondary_pagetables(int cpu) /* MMU setup for secondary CPUS (which already have paging enabled) */ void mmu_init_secondary_cpu(void) { - /* From now on, no mapping may be both writable and executable. */ - WRITE_SYSREG32(READ_SYSREG32(SCTLR_EL2) | SCTLR_WXN, SCTLR_EL2); - flush_xen_text_tlb_local(); + xen_pt_enforce_wnx(); } #ifdef CONFIG_ARM_32 From patchwork Tue May 14 12:21:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 164162 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp2552316ili; Tue, 14 May 2019 05:23:19 -0700 (PDT) X-Google-Smtp-Source: APXvYqwnKBkeSLFFeFXgbZKwgKg8m/pXb54zaf7d+IIUIvR0NKjDRJ2W81ZYui+4hR2bKlg882PE X-Received: by 2002:a24:93c2:: with SMTP id y185mr3111081itd.95.1557836599757; Tue, 14 May 2019 05:23:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1557836599; cv=none; d=google.com; s=arc-20160816; b=ddPxEIseuLWb9cRWHIW8UFpfxCm4vOTFHfPmus2df+LZw42UJYSDaSW7fJ2S4y83GP GnhN8HRbQMZYmeN86Ny0Ozv/HO7+DBEsFXzwtyciYr7zKGmyzMlVbRoA9p+5vgh1tcFE YSZrCeJex5NGEyFPc77y0kaax9kgl8K7oxzG5d3kHsOK/7MbwObN9880y3oJK78twbFz eb1zIWaHLhh4xJfTB7KAxAbJO0XWQ3M41DIXlhBfNEH2GLi1Ac/kTytSyX6MTflpU0JT Sg/dB9Kq3XbRr+43OtzO3I+Efifz/tz+mybrk31oxvKiT7x7yjeJhHxTvbii42ZZWONM JzVQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=iclZddht+DWiNIUSx4flRMaUt3yS0rXYIKQgnnxlCZk=; b=UZym3JB2dgg/oNbv7SocvbFSdRSnxO8+3IyRNSq2heb4u+JVILH15sbRdsY6qNwSEb M9GVd1+sTz7B5GLv0yccEqt1WiE84XX1VFUnOXM8PVMZkInYu4r+sdB5tHhvqE3OCBXW G4holoeeniNWQ3W6SQcxuyci5JAEQEuWqp4BH12Wp08Q0QUYPJ90HwaRhDzaZrnG1hGy zWuFYjmvcamAKFHe+z0Pc7p+pUgLR2FI6x4OiSABDoG3rZ5ZXu+nfJwgmq08tz4cDX6b QENmCvk1vTjktO2fyuj8KActPJcxDF4klzNQHDS+Zb2Z/r4mOPpnZt6mZVZJ9wPfz2si IaVA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id b200si9226854iof.70.2019.05.14.05.23.19 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 14 May 2019 05:23:19 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hQWRP-0008AS-O2; Tue, 14 May 2019 12:21:55 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hQWRO-00089K-Dg for xen-devel@lists.xenproject.org; Tue, 14 May 2019 12:21:54 +0000 X-Inumbo-ID: db5db89e-7642-11e9-8980-bc764e045a96 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id db5db89e-7642-11e9-8980-bc764e045a96; Tue, 14 May 2019 12:21:53 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 15E5D15AB; Tue, 14 May 2019 05:21:53 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D6D0D3F71E; Tue, 14 May 2019 05:21:51 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Tue, 14 May 2019 13:21:15 +0100 Message-Id: <20190514122136.28215-7-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190514122136.28215-1-julien.grall@arm.com> References: <20190514122136.28215-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH MM-PART1 v3 3/8] xen/arm: Remove flush_xen_text_tlb_local() X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Oleksandr_Tyshchenko@epam.com, Julien Grall , Stefano Stabellini , Andrii Anisov MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The function flush_xen_text_tlb_local() has been misused and will result to invalidate the instruction cache more than necessary. For instance, there is no need to invalidate the instruction cache if we are setting SCTLR_EL2.WXN. There is effectively only one caller (i.e free_init_memory() who would need to invalidate the instruction cache. So rather than keeping around the function flush_xen_text_tlb_local() replace it with call to flush_xen_tlb_local() and explicitely flush the cache when necessary. Signed-off-by: Julien Grall Reviewed-by: Andrii Anisov --- Changes in v3: - Fix typoes Changes in v2: - Add Andrii's reviewed-by --- xen/arch/arm/mm.c | 17 ++++++++++++++--- xen/include/asm-arm/arm32/page.h | 23 +++++++++-------------- xen/include/asm-arm/arm64/page.h | 21 +++++---------------- 3 files changed, 28 insertions(+), 33 deletions(-) diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c index 93ad118183..dfbe39c70a 100644 --- a/xen/arch/arm/mm.c +++ b/xen/arch/arm/mm.c @@ -610,8 +610,12 @@ void __init remove_early_mappings(void) static void xen_pt_enforce_wnx(void) { WRITE_SYSREG32(READ_SYSREG32(SCTLR_EL2) | SCTLR_WXN, SCTLR_EL2); - /* Flush everything after setting WXN bit. */ - flush_xen_text_tlb_local(); + /* + * The TLBs may cache SCTLR_EL2.WXN. So ensure it is synchronized + * before flushing the TLBs. + */ + isb(); + flush_xen_data_tlb_local(); } extern void switch_ttbr(uint64_t ttbr); @@ -1123,7 +1127,7 @@ static void set_pte_flags_on_range(const char *p, unsigned long l, enum mg mg) } write_pte(xen_xenmap + i, pte); } - flush_xen_text_tlb_local(); + flush_xen_data_tlb_local(); } /* Release all __init and __initdata ranges to be reused */ @@ -1136,6 +1140,13 @@ void free_init_memory(void) uint32_t *p; set_pte_flags_on_range(__init_begin, len, mg_rw); + + /* + * From now on, init will not be used for execution anymore, + * so nuke the instruction cache to remove entries related to init. + */ + invalidate_icache_local(); + #ifdef CONFIG_ARM_32 /* udf instruction i.e (see A8.8.247 in ARM DDI 0406C.c) */ insn = 0xe7f000f0; diff --git a/xen/include/asm-arm/arm32/page.h b/xen/include/asm-arm/arm32/page.h index ea4b312c70..40a77daa9d 100644 --- a/xen/include/asm-arm/arm32/page.h +++ b/xen/include/asm-arm/arm32/page.h @@ -46,24 +46,19 @@ static inline void invalidate_icache(void) } /* - * Flush all hypervisor mappings from the TLB and branch predictor of - * the local processor. - * - * This is needed after changing Xen code mappings. - * - * The caller needs to issue the necessary DSB and D-cache flushes - * before calling flush_xen_text_tlb. + * Invalidate all instruction caches on the local processor to PoU. + * We also need to flush the branch predictor for ARMv7 as it may be + * architecturally visible to the software (see B2.2.4 in ARM DDI 0406C.b). */ -static inline void flush_xen_text_tlb_local(void) +static inline void invalidate_icache_local(void) { asm volatile ( - "isb;" /* Ensure synchronization with previous changes to text */ - CMD_CP32(TLBIALLH) /* Flush hypervisor TLB */ - CMD_CP32(ICIALLU) /* Flush I-cache */ - CMD_CP32(BPIALL) /* Flush branch predictor */ - "dsb;" /* Ensure completion of TLB+BP flush */ - "isb;" + CMD_CP32(ICIALLU) /* Flush I-cache. */ + CMD_CP32(BPIALL) /* Flush branch predictor. */ : : : "memory"); + + dsb(nsh); /* Ensure completion of the flush I-cache */ + isb(); /* Synchronize fetched instruction stream. */ } /* diff --git a/xen/include/asm-arm/arm64/page.h b/xen/include/asm-arm/arm64/page.h index 23d778154d..6c36d0210f 100644 --- a/xen/include/asm-arm/arm64/page.h +++ b/xen/include/asm-arm/arm64/page.h @@ -37,23 +37,12 @@ static inline void invalidate_icache(void) isb(); } -/* - * Flush all hypervisor mappings from the TLB of the local processor. - * - * This is needed after changing Xen code mappings. - * - * The caller needs to issue the necessary DSB and D-cache flushes - * before calling flush_xen_text_tlb. - */ -static inline void flush_xen_text_tlb_local(void) +/* Invalidate all instruction caches on the local processor to PoU */ +static inline void invalidate_icache_local(void) { - asm volatile ( - "isb;" /* Ensure synchronization with previous changes to text */ - "tlbi alle2;" /* Flush hypervisor TLB */ - "ic iallu;" /* Flush I-cache */ - "dsb sy;" /* Ensure completion of TLB flush */ - "isb;" - : : : "memory"); + asm volatile ("ic iallu"); + dsb(nsh); /* Ensure completion of the I-cache flush */ + isb(); } /* From patchwork Tue May 14 12:21:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 164159 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp2552292ili; Tue, 14 May 2019 05:23:18 -0700 (PDT) X-Google-Smtp-Source: APXvYqyTngVTWfEm/FLplMqsLe4koEcM/mkdtnfGCf2FHTZyOlYR7mAI5J05GoKza07MCJm6uUtW X-Received: by 2002:a24:6e94:: with SMTP id w142mr3147061itc.19.1557836598420; Tue, 14 May 2019 05:23:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1557836598; cv=none; d=google.com; s=arc-20160816; b=MJEaM+W4Mt/uNpXFKNG3V6CId37BVZh/Z9SU5Wd319KHF7wBox5Zec23FlsKH5Bx6N 6VSrQdwsO4/j7eccGRS3FIt87Bct0rwjBWGRpaVKyaG+T0ogNLeDn+Vg/zAHizeGGz8D iaO/Pkp9siytGXdLvEO5e17wAWAa4SRngg/aiqEvia/owrKRACz05d0gah7W3nJe05S0 2pT1Ppe2TGTG23ltlXUCbxp0EOWMF+rYGoKRMJ+JFQ/5GfuBqluEDEFBU7XTX5azMtLs 65NXi5ARqMkMXfFEtZxFPYv7lDEa2hRI7I4xu2yIiRJ36EcZ67e2FDkmuuZXBB/LQQ7y 5zPw== ARC-Message-Signature: i=1; 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[192.237.175.120]) by mx.google.com with ESMTPS id c124si9903642jac.116.2019.05.14.05.23.18 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 14 May 2019 05:23:18 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hQWRR-0008C0-69; Tue, 14 May 2019 12:21:57 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hQWRP-0008AN-Km for xen-devel@lists.xenproject.org; Tue, 14 May 2019 12:21:55 +0000 X-Inumbo-ID: dc3cb1b3-7642-11e9-8980-bc764e045a96 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id dc3cb1b3-7642-11e9-8980-bc764e045a96; Tue, 14 May 2019 12:21:54 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 63FC615AD; Tue, 14 May 2019 05:21:54 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 53C9D3F71E; Tue, 14 May 2019 05:21:53 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Tue, 14 May 2019 13:21:16 +0100 Message-Id: <20190514122136.28215-8-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190514122136.28215-1-julien.grall@arm.com> References: <20190514122136.28215-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH MM-PART2 v2 04/19] xen/arm: Rework HSCTLR_BASE X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Oleksandr_Tyshchenko@epam.com, Julien Grall , Stefano Stabellini , Andrii_Anisov@epam.com MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The current value of HSCTLR_BASE for Arm64 is pretty wrong. It would actually turn on SCTLR_EL2.nAA (bit 6) on hardware implementing ARMv8.4-LSE. Furthermore, the documentation of what is cleared/set in SCTLR_EL2 is also not correct and looks like to be a verbatim copy from Arm32. HSCTLR_BASE is replaced with a bunch of per-architecture new defines helping to understand better what is the initialie value for SCTLR_EL2/HSCTLR. Note the defines *_CLEAR are only used to check the state of each bits are known. Lastly, the documentation is dropped from arm{32,64}/head.S as it would be pretty easy to get out-of-sync with the definitions. Signed-off-by: Julien Grall --- Changes in v2: - Use BIT(..., UL) instead of _BITUL --- xen/arch/arm/arm32/head.S | 12 +-------- xen/arch/arm/arm64/head.S | 10 +------- xen/include/asm-arm/processor.h | 54 ++++++++++++++++++++++++++++++++++++++++- 3 files changed, 55 insertions(+), 21 deletions(-) diff --git a/xen/arch/arm/arm32/head.S b/xen/arch/arm/arm32/head.S index 454d24537c..8a98607459 100644 --- a/xen/arch/arm/arm32/head.S +++ b/xen/arch/arm/arm32/head.S @@ -234,17 +234,7 @@ cpu_init_done: ldr r0, =(TCR_RES1|TCR_SH0_IS|TCR_ORGN0_WBWA|TCR_IRGN0_WBWA|TCR_T0SZ(0)) mcr CP32(r0, HTCR) - /* - * Set up the HSCTLR: - * Exceptions in LE ARM, - * Low-latency IRQs disabled, - * Write-implies-XN disabled (for now), - * D-cache disabled (for now), - * I-cache enabled, - * Alignment checking enabled, - * MMU translation disabled (for now). - */ - ldr r0, =(HSCTLR_BASE|SCTLR_Axx_ELx_A) + ldr r0, =HSCTLR_SET mcr CP32(r0, HSCTLR) /* diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S index 8a6be3352e..4fe904c51d 100644 --- a/xen/arch/arm/arm64/head.S +++ b/xen/arch/arm/arm64/head.S @@ -363,15 +363,7 @@ skip_bss: msr tcr_el2, x0 - /* Set up the SCTLR_EL2: - * Exceptions in LE ARM, - * Low-latency IRQs disabled, - * Write-implies-XN disabled (for now), - * D-cache disabled (for now), - * I-cache enabled, - * Alignment checking disabled, - * MMU translation disabled (for now). */ - ldr x0, =(HSCTLR_BASE) + ldr x0, =SCTLR_EL2_SET msr SCTLR_EL2, x0 /* Ensure that any exceptions encountered at EL2 diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h index bbcba061ca..9afc3786c5 100644 --- a/xen/include/asm-arm/processor.h +++ b/xen/include/asm-arm/processor.h @@ -127,6 +127,9 @@ #define SCTLR_A32_ELx_TE BIT(30, UL) #define SCTLR_A32_ELx_FI BIT(21, UL) +/* Common bits for SCTLR_ELx for Arm64 */ +#define SCTLR_A64_ELx_SA BIT(3, UL) + /* Common bits for SCTLR_ELx on all architectures */ #define SCTLR_Axx_ELx_EE BIT(25, UL) #define SCTLR_Axx_ELx_WXN BIT(19, UL) @@ -135,7 +138,56 @@ #define SCTLR_Axx_ELx_A BIT(1, UL) #define SCTLR_Axx_ELx_M BIT(0, UL) -#define HSCTLR_BASE _AC(0x30c51878,U) +#ifdef CONFIG_ARM_32 + +#define HSCTLR_RES1 (BIT( 3, UL) | BIT( 4, UL) | BIT( 5, UL) |\ + BIT( 6, UL) | BIT(11, UL) | BIT(16, UL) |\ + BIT(18, UL) | BIT(22, UL) | BIT(23, UL) |\ + BIT(28, UL) | BIT(29, UL)) + +#define HSCTLR_RES0 (BIT(7, UL) | BIT(8, UL) | BIT(9, UL) | BIT(10, UL) |\ + BIT(13, UL) | BIT(14, UL) | BIT(15, UL) | BIT(17, UL) |\ + BIT(20, UL) | BIT(24, UL) | BIT(26, UL) | BIT(27, UL) |\ + BIT(31, UL)) + +/* Initial value for HSCTLR */ +#define HSCTLR_SET (HSCTLR_RES1 | SCTLR_Axx_ELx_A | SCTLR_Axx_ELx_I) + +#define HSCTLR_CLEAR (HSCTLR_RES0 | SCTLR_Axx_ELx_M |\ + SCTLR_Axx_ELx_C | SCTLR_Axx_ELx_WXN |\ + SCTLR_A32_ELx_FI | SCTLR_Axx_ELx_EE |\ + SCTLR_A32_ELx_TE) + +#if (HSCTLR_SET ^ HSCTLR_CLEAR) != 0xffffffffU +#error "Inconsistent HSCTLR set/clear bits" +#endif + +#else + +#define SCTLR_EL2_RES1 (BIT( 4, UL) | BIT( 5, UL) | BIT(11, UL) |\ + BIT(16, UL) | BIT(18, UL) | BIT(22, UL) |\ + BIT(23, UL) | BIT(28, UL) | BIT(29, UL)) + +#define SCTLR_EL2_RES0 (BIT( 6, UL) | BIT( 7, UL) | BIT( 8, UL) |\ + BIT( 9, UL) | BIT(10, UL) | BIT(13, UL) |\ + BIT(14, UL) | BIT(15, UL) | BIT(17, UL) |\ + BIT(20, UL) | BIT(21, UL) | BIT(24, UL) |\ + BIT(26, UL) | BIT(27, UL) | BIT(30, UL) |\ + BIT(31, UL) | (0xffffffffULL << 32)) + +/* Initial value for SCTLR_EL2 */ +#define SCTLR_EL2_SET (SCTLR_EL2_RES1 | SCTLR_A64_ELx_SA |\ + SCTLR_Axx_ELx_I) + +#define SCTLR_EL2_CLEAR (SCTLR_EL2_RES0 | SCTLR_Axx_ELx_M |\ + SCTLR_Axx_ELx_A | SCTLR_Axx_ELx_C |\ + SCTLR_Axx_ELx_WXN | SCTLR_Axx_ELx_EE) + +#if (SCTLR_EL2_SET ^ SCTLR_EL2_CLEAR) != 0xffffffffffffffffUL +#error "Inconsistent SCTLR_EL2 set/clear bits" +#endif + +#endif /* HCR Hyp Configuration Register */ #define HCR_RW (_AC(1,UL)<<31) /* Register Width, ARM64 only */ From patchwork Tue May 14 12:21:19 2019 Content-Type: text/plain; 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[192.237.175.120]) by mx.google.com with ESMTPS id o3si9951395jao.16.2019.05.14.05.23.21 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 14 May 2019 05:23:21 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hQWRV-0008HR-My; Tue, 14 May 2019 12:22:01 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hQWRU-0008Fe-A6 for xen-devel@lists.xenproject.org; Tue, 14 May 2019 12:22:00 +0000 X-Inumbo-ID: deae9228-7642-11e9-8980-bc764e045a96 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id deae9228-7642-11e9-8980-bc764e045a96; Tue, 14 May 2019 12:21:58 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9FC8215AD; Tue, 14 May 2019 05:21:58 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 9029C3F71E; Tue, 14 May 2019 05:21:57 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Tue, 14 May 2019 13:21:19 +0100 Message-Id: <20190514122136.28215-11-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190514122136.28215-1-julien.grall@arm.com> References: <20190514122136.28215-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH MM-PART2 v2 05/19] xen/arm: Remove parameter cpuid from start_xen X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Oleksandr_Tyshchenko@epam.com, Julien Grall , Stefano Stabellini , Andrii_Anisov@epam.com MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The parameter cpuid is not used by start_xen. So remove it. Signed-off-by: Julien Grall --- - Re-order the patch with "xen/arm: Rework secondary_start prototype" --- xen/arch/arm/arm32/head.S | 1 - xen/arch/arm/arm64/head.S | 1 - xen/arch/arm/setup.c | 3 +-- 3 files changed, 1 insertion(+), 4 deletions(-) diff --git a/xen/arch/arm/arm32/head.S b/xen/arch/arm/arm32/head.S index 8a98607459..cb8a3bf829 100644 --- a/xen/arch/arm/arm32/head.S +++ b/xen/arch/arm/arm32/head.S @@ -447,7 +447,6 @@ launch: sub sp, #CPUINFO_sizeof /* Make room for CPU save record */ mov r0, r10 /* Marshal args: - phys_offset */ mov r1, r8 /* - DTB address */ - mov r2, r7 /* - CPU ID */ teq r12, #0 beq start_xen /* and disappear into the land of C */ b start_secondary /* (to the appropriate entry point) */ diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S index 4fe904c51d..075013878e 100644 --- a/xen/arch/arm/arm64/head.S +++ b/xen/arch/arm/arm64/head.S @@ -584,7 +584,6 @@ launch: mov x0, x20 /* Marshal args: - phys_offset */ mov x1, x21 /* - FDT */ - mov x2, x24 /* - CPU ID */ cbnz x22, 1f b start_xen /* and disappear into the land of C */ 1: diff --git a/xen/arch/arm/setup.c b/xen/arch/arm/setup.c index faaf029b99..2f714d8b37 100644 --- a/xen/arch/arm/setup.c +++ b/xen/arch/arm/setup.c @@ -733,8 +733,7 @@ size_t __read_mostly dcache_line_bytes; /* C entry point for boot CPU */ void __init start_xen(unsigned long boot_phys_offset, - unsigned long fdt_paddr, - unsigned long cpuid) + unsigned long fdt_paddr) { size_t fdt_size; int cpus, i; From patchwork Tue May 14 12:21:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 164167 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp2552416ili; Tue, 14 May 2019 05:23:26 -0700 (PDT) X-Google-Smtp-Source: APXvYqxdcAArAONQmWhwEvVPz+gxhyelCci/WplqV2fE4VulzOTl7/aUJvSnDwhONrDGOqK8BbFn X-Received: by 2002:a24:2782:: with SMTP id g124mr527651ita.137.1557836606173; Tue, 14 May 2019 05:23:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1557836606; cv=none; d=google.com; s=arc-20160816; b=aLIuCfCPTRjURsJNu21/9+OyjagyCjjNIaQ6hn3qjcul4plFwLgqWt1KqqwUKrLqg7 ABITg+ng7mc/GYh4y6ML4sYpHiPj9fvZwsVxX3J/TZ+iF3G0VzMc34tJ4+jYO0QARBIb 2wiAhVL/pWFJaXUPyhkiOekssoXDGyExVf6a0gxVNy0g6YF8zSYRhK8j4TiOPBKNxVPv qIonCyq7bw9nJyNIAnImX/UvlVG/JcEg3rgYXpFnSdqQmNWvYUo8Csx2DQK/e3hjVcfU C+zeuILlEkOQZBC46jCRBE7UVpJO+holvZdDzUEZtm3afXyWw99AVLJ/ZE+Sj9xNzrb+ gIBg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=296nWOIdD8CG10ZnJrzh6KlRoWEZk/F2RrPHIPTfgf8=; b=xEpSwsoQDEth3CWZpDrjg2pDFNnWS2mMd9X8ZrH5ZvxK81I8QKYGjSbhlGUp+mqzT5 oeKY4I8mJMSaon8hQZ1KoWUMdqwYeyvPnnsQ1eioB+dQ5dENekymAAExDrTu15FYImiU ZOeLpHTq0O3DPz4/erNikaaqj26OjPDmBC/CHSr1yl/L5QULnGUEJTTsiOJjN0Qw/BWl NMOIy14EP9OWxcxgvEWzHERVHROVvDioj0kS2YfmryV461nghiV3909df1eh0IkJvhHS v6BkzYqOqrPIB3bxaCaZiTMHAjQuqMJa++u5uZ7N/fBf6EB4vGQfV+LRpS7NbRcI9JMi L0bQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id w138si1509728ita.21.2019.05.14.05.23.26 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 14 May 2019 05:23:26 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hQWRX-0008JM-4h; Tue, 14 May 2019 12:22:03 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hQWRV-0008H5-EV for xen-devel@lists.xenproject.org; Tue, 14 May 2019 12:22:01 +0000 X-Inumbo-ID: dfa1e180-7642-11e9-963d-47d53be77ade Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTP id dfa1e180-7642-11e9-963d-47d53be77ade; Tue, 14 May 2019 12:22:00 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1CC79341; Tue, 14 May 2019 05:22:00 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id DE0753F71E; Tue, 14 May 2019 05:21:58 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Tue, 14 May 2019 13:21:20 +0100 Message-Id: <20190514122136.28215-12-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190514122136.28215-1-julien.grall@arm.com> References: <20190514122136.28215-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH MM-PART1 v3 6/8] xen/arm: Gather all TLB flush helpers in tlbflush.h X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Oleksandr_Tyshchenko@epam.com, Julien Grall , Stefano Stabellini , Andrii Anisov MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" At the moment, TLB helpers are scattered in 2 headers: page.h (for Xen TLB helpers) and tlbflush.h (for guest TLB helpers). This patch is gathering all of them in tlbflush. This will help to uniformize and update the logic of the helpers in follow-up patches. Signed-off-by: Julien Grall Reviewed-by: Andrii Anisov Acked-by: Stefano Stabellini --- Changes in v3: - Add Stefano's acked-by Changes in v2: - Add Andrii's reviewed-by --- xen/include/asm-arm/arm32/flushtlb.h | 22 +++++++++++++++++++++ xen/include/asm-arm/arm32/page.h | 22 --------------------- xen/include/asm-arm/arm64/flushtlb.h | 23 ++++++++++++++++++++++ xen/include/asm-arm/arm64/page.h | 23 ---------------------- xen/include/asm-arm/flushtlb.h | 38 ++++++++++++++++++++++++++++++++++++ xen/include/asm-arm/page.h | 38 ------------------------------------ 6 files changed, 83 insertions(+), 83 deletions(-) diff --git a/xen/include/asm-arm/arm32/flushtlb.h b/xen/include/asm-arm/arm32/flushtlb.h index 22e100eccf..b629db61cb 100644 --- a/xen/include/asm-arm/arm32/flushtlb.h +++ b/xen/include/asm-arm/arm32/flushtlb.h @@ -45,6 +45,28 @@ static inline void flush_all_guests_tlb(void) isb(); } +/* Flush all hypervisor mappings from the TLB of the local processor. */ +static inline void flush_xen_tlb_local(void) +{ + asm volatile("dsb;" /* Ensure preceding are visible */ + CMD_CP32(TLBIALLH) + "dsb;" /* Ensure completion of the TLB flush */ + "isb;" + : : : "memory"); +} + +/* Flush TLB of local processor for address va. */ +static inline void __flush_xen_tlb_one_local(vaddr_t va) +{ + asm volatile(STORE_CP32(0, TLBIMVAH) : : "r" (va) : "memory"); +} + +/* Flush TLB of all processors in the inner-shareable domain for address va. */ +static inline void __flush_xen_tlb_one(vaddr_t va) +{ + asm volatile(STORE_CP32(0, TLBIMVAHIS) : : "r" (va) : "memory"); +} + #endif /* __ASM_ARM_ARM32_FLUSHTLB_H__ */ /* * Local variables: diff --git a/xen/include/asm-arm/arm32/page.h b/xen/include/asm-arm/arm32/page.h index 0b41b9214b..715a9e4fef 100644 --- a/xen/include/asm-arm/arm32/page.h +++ b/xen/include/asm-arm/arm32/page.h @@ -61,28 +61,6 @@ static inline void invalidate_icache_local(void) isb(); /* Synchronize fetched instruction stream. */ } -/* Flush all hypervisor mappings from the TLB of the local processor. */ -static inline void flush_xen_tlb_local(void) -{ - asm volatile("dsb;" /* Ensure preceding are visible */ - CMD_CP32(TLBIALLH) - "dsb;" /* Ensure completion of the TLB flush */ - "isb;" - : : : "memory"); -} - -/* Flush TLB of local processor for address va. */ -static inline void __flush_xen_tlb_one_local(vaddr_t va) -{ - asm volatile(STORE_CP32(0, TLBIMVAH) : : "r" (va) : "memory"); -} - -/* Flush TLB of all processors in the inner-shareable domain for address va. */ -static inline void __flush_xen_tlb_one(vaddr_t va) -{ - asm volatile(STORE_CP32(0, TLBIMVAHIS) : : "r" (va) : "memory"); -} - /* Ask the MMU to translate a VA for us */ static inline uint64_t __va_to_par(vaddr_t va) { diff --git a/xen/include/asm-arm/arm64/flushtlb.h b/xen/include/asm-arm/arm64/flushtlb.h index adbbd5c522..2fed34b2ec 100644 --- a/xen/include/asm-arm/arm64/flushtlb.h +++ b/xen/include/asm-arm/arm64/flushtlb.h @@ -45,6 +45,29 @@ static inline void flush_all_guests_tlb(void) : : : "memory"); } +/* Flush all hypervisor mappings from the TLB of the local processor. */ +static inline void flush_xen_tlb_local(void) +{ + asm volatile ( + "dsb sy;" /* Ensure visibility of PTE writes */ + "tlbi alle2;" /* Flush hypervisor TLB */ + "dsb sy;" /* Ensure completion of TLB flush */ + "isb;" + : : : "memory"); +} + +/* Flush TLB of local processor for address va. */ +static inline void __flush_xen_tlb_one_local(vaddr_t va) +{ + asm volatile("tlbi vae2, %0;" : : "r" (va>>PAGE_SHIFT) : "memory"); +} + +/* Flush TLB of all processors in the inner-shareable domain for address va. */ +static inline void __flush_xen_tlb_one(vaddr_t va) +{ + asm volatile("tlbi vae2is, %0;" : : "r" (va>>PAGE_SHIFT) : "memory"); +} + #endif /* __ASM_ARM_ARM64_FLUSHTLB_H__ */ /* * Local variables: diff --git a/xen/include/asm-arm/arm64/page.h b/xen/include/asm-arm/arm64/page.h index 31d04ecf76..0cba266373 100644 --- a/xen/include/asm-arm/arm64/page.h +++ b/xen/include/asm-arm/arm64/page.h @@ -45,29 +45,6 @@ static inline void invalidate_icache_local(void) isb(); } -/* Flush all hypervisor mappings from the TLB of the local processor. */ -static inline void flush_xen_tlb_local(void) -{ - asm volatile ( - "dsb sy;" /* Ensure visibility of PTE writes */ - "tlbi alle2;" /* Flush hypervisor TLB */ - "dsb sy;" /* Ensure completion of TLB flush */ - "isb;" - : : : "memory"); -} - -/* Flush TLB of local processor for address va. */ -static inline void __flush_xen_tlb_one_local(vaddr_t va) -{ - asm volatile("tlbi vae2, %0;" : : "r" (va>>PAGE_SHIFT) : "memory"); -} - -/* Flush TLB of all processors in the inner-shareable domain for address va. */ -static inline void __flush_xen_tlb_one(vaddr_t va) -{ - asm volatile("tlbi vae2is, %0;" : : "r" (va>>PAGE_SHIFT) : "memory"); -} - /* Ask the MMU to translate a VA for us */ static inline uint64_t __va_to_par(vaddr_t va) { diff --git a/xen/include/asm-arm/flushtlb.h b/xen/include/asm-arm/flushtlb.h index 83ff9fa8b3..ab1aae5c90 100644 --- a/xen/include/asm-arm/flushtlb.h +++ b/xen/include/asm-arm/flushtlb.h @@ -28,6 +28,44 @@ static inline void page_set_tlbflush_timestamp(struct page_info *page) /* Flush specified CPUs' TLBs */ void flush_tlb_mask(const cpumask_t *mask); +/* + * Flush a range of VA's hypervisor mappings from the TLB of the local + * processor. + */ +static inline void flush_xen_tlb_range_va_local(vaddr_t va, + unsigned long size) +{ + vaddr_t end = va + size; + + dsb(sy); /* Ensure preceding are visible */ + while ( va < end ) + { + __flush_xen_tlb_one_local(va); + va += PAGE_SIZE; + } + dsb(sy); /* Ensure completion of the TLB flush */ + isb(); +} + +/* + * Flush a range of VA's hypervisor mappings from the TLB of all + * processors in the inner-shareable domain. + */ +static inline void flush_xen_tlb_range_va(vaddr_t va, + unsigned long size) +{ + vaddr_t end = va + size; + + dsb(sy); /* Ensure preceding are visible */ + while ( va < end ) + { + __flush_xen_tlb_one(va); + va += PAGE_SIZE; + } + dsb(sy); /* Ensure completion of the TLB flush */ + isb(); +} + #endif /* __ASM_ARM_FLUSHTLB_H__ */ /* * Local variables: diff --git a/xen/include/asm-arm/page.h b/xen/include/asm-arm/page.h index 195345e24a..2bcdb0f1a5 100644 --- a/xen/include/asm-arm/page.h +++ b/xen/include/asm-arm/page.h @@ -233,44 +233,6 @@ static inline int clean_and_invalidate_dcache_va_range : : "r" (_p), "m" (*_p)); \ } while (0) -/* - * Flush a range of VA's hypervisor mappings from the TLB of the local - * processor. - */ -static inline void flush_xen_tlb_range_va_local(vaddr_t va, - unsigned long size) -{ - vaddr_t end = va + size; - - dsb(sy); /* Ensure preceding are visible */ - while ( va < end ) - { - __flush_xen_tlb_one_local(va); - va += PAGE_SIZE; - } - dsb(sy); /* Ensure completion of the TLB flush */ - isb(); -} - -/* - * Flush a range of VA's hypervisor mappings from the TLB of all - * processors in the inner-shareable domain. - */ -static inline void flush_xen_tlb_range_va(vaddr_t va, - unsigned long size) -{ - vaddr_t end = va + size; - - dsb(sy); /* Ensure preceding are visible */ - while ( va < end ) - { - __flush_xen_tlb_one(va); - va += PAGE_SIZE; - } - dsb(sy); /* Ensure completion of the TLB flush */ - isb(); -} - /* Flush the dcache for an entire page. */ void flush_page_to_ram(unsigned long mfn, bool sync_icache); From patchwork Tue May 14 12:21:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 164166 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp2552386ili; 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[192.237.175.120]) by mx.google.com with ESMTPS id m32si135505iti.49.2019.05.14.05.23.23 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 14 May 2019 05:23:23 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hQWRa-0008OL-2Q; Tue, 14 May 2019 12:22:06 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hQWRZ-0008N7-EO for xen-devel@lists.xenproject.org; Tue, 14 May 2019 12:22:05 +0000 X-Inumbo-ID: e21d84dc-7642-11e9-a4fa-6b4a2d3c314f Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTP id e21d84dc-7642-11e9-a4fa-6b4a2d3c314f; Tue, 14 May 2019 12:22:04 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 58B86341; Tue, 14 May 2019 05:22:04 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 257EC3F71E; Tue, 14 May 2019 05:22:03 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Tue, 14 May 2019 13:21:23 +0100 Message-Id: <20190514122136.28215-15-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190514122136.28215-1-julien.grall@arm.com> References: <20190514122136.28215-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH MM-PART1 v3 7/8] xen/arm: tlbflush: Rework TLB helpers X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Oleksandr_Tyshchenko@epam.com, Julien Grall , Stefano Stabellini , Andrii Anisov MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" All the TLBs helpers invalidate all the TLB entries are using the same pattern: DSB SY TLBI ... DSB SY ISB This pattern is following pattern recommended by the Arm Arm to ensure visibility of updates to translation tables (see K11.5.2 in ARM DDI 0487D.b). We have been a bit too eager in Xen and use system-wide DSBs when this can be limited to the inner-shareable domain. Furthermore, the first DSB can be restrict further to only store in the inner-shareable domain. This is because the DSB is here to ensure visibility of the update to translation table walks. Lastly, there are a lack of documentation in most of the TLBs helper. Rather than trying to update the helpers one by one, this patch introduce a per-arch macro to generate the TLB helpers. This will be easier to update the TLBs helper in the future and the documentation. Signed-off-by: Julien Grall Reviewed-by: Andrii Anisov Reviewed-by: Stefano Stabellini --- Changes in v3: - Add Stefano's reviewed-by Changes in v2: - Update the reference to the Arm Arm to the latest spec - Add Andrii's reviewed-by --- xen/include/asm-arm/arm32/flushtlb.h | 73 ++++++++++++++-------------------- xen/include/asm-arm/arm64/flushtlb.h | 76 +++++++++++++++--------------------- 2 files changed, 60 insertions(+), 89 deletions(-) diff --git a/xen/include/asm-arm/arm32/flushtlb.h b/xen/include/asm-arm/arm32/flushtlb.h index b629db61cb..9085e65011 100644 --- a/xen/include/asm-arm/arm32/flushtlb.h +++ b/xen/include/asm-arm/arm32/flushtlb.h @@ -1,59 +1,44 @@ #ifndef __ASM_ARM_ARM32_FLUSHTLB_H__ #define __ASM_ARM_ARM32_FLUSHTLB_H__ -/* Flush local TLBs, current VMID only */ -static inline void flush_guest_tlb_local(void) -{ - dsb(sy); - - WRITE_CP32((uint32_t) 0, TLBIALL); - - dsb(sy); - isb(); +/* + * Every invalidation operation use the following patterns: + * + * DSB ISHST // Ensure prior page-tables updates have completed + * TLBI... // Invalidate the TLB + * DSB ISH // Ensure the TLB invalidation has completed + * ISB // See explanation below + * + * For Xen page-tables the ISB will discard any instructions fetched + * from the old mappings. + * + * For the Stage-2 page-tables the ISB ensures the completion of the DSB + * (and therefore the TLB invalidation) before continuing. So we know + * the TLBs cannot contain an entry for a mapping we may have removed. + */ +#define TLB_HELPER(name, tlbop) \ +static inline void name(void) \ +{ \ + dsb(ishst); \ + WRITE_CP32(0, tlbop); \ + dsb(ish); \ + isb(); \ } -/* Flush inner shareable TLBs, current VMID only */ -static inline void flush_guest_tlb(void) -{ - dsb(sy); - - WRITE_CP32((uint32_t) 0, TLBIALLIS); +/* Flush local TLBs, current VMID only */ +TLB_HELPER(flush_guest_tlb_local, TLBIALL); - dsb(sy); - isb(); -} +/* Flush inner shareable TLBs, current VMID only */ +TLB_HELPER(flush_guest_tlb, TLBIALLIS); /* Flush local TLBs, all VMIDs, non-hypervisor mode */ -static inline void flush_all_guests_tlb_local(void) -{ - dsb(sy); - - WRITE_CP32((uint32_t) 0, TLBIALLNSNH); - - dsb(sy); - isb(); -} +TLB_HELPER(flush_all_guests_tlb_local, TLBIALLNSNH); /* Flush innershareable TLBs, all VMIDs, non-hypervisor mode */ -static inline void flush_all_guests_tlb(void) -{ - dsb(sy); - - WRITE_CP32((uint32_t) 0, TLBIALLNSNHIS); - - dsb(sy); - isb(); -} +TLB_HELPER(flush_all_guests_tlb, TLBIALLNSNHIS); /* Flush all hypervisor mappings from the TLB of the local processor. */ -static inline void flush_xen_tlb_local(void) -{ - asm volatile("dsb;" /* Ensure preceding are visible */ - CMD_CP32(TLBIALLH) - "dsb;" /* Ensure completion of the TLB flush */ - "isb;" - : : : "memory"); -} +TLB_HELPER(flush_xen_tlb_local, TLBIALLH); /* Flush TLB of local processor for address va. */ static inline void __flush_xen_tlb_one_local(vaddr_t va) diff --git a/xen/include/asm-arm/arm64/flushtlb.h b/xen/include/asm-arm/arm64/flushtlb.h index 2fed34b2ec..ceec59542e 100644 --- a/xen/include/asm-arm/arm64/flushtlb.h +++ b/xen/include/asm-arm/arm64/flushtlb.h @@ -1,60 +1,46 @@ #ifndef __ASM_ARM_ARM64_FLUSHTLB_H__ #define __ASM_ARM_ARM64_FLUSHTLB_H__ -/* Flush local TLBs, current VMID only */ -static inline void flush_guest_tlb_local(void) -{ - asm volatile( - "dsb sy;" - "tlbi vmalls12e1;" - "dsb sy;" - "isb;" - : : : "memory"); +/* + * Every invalidation operation use the following patterns: + * + * DSB ISHST // Ensure prior page-tables updates have completed + * TLBI... // Invalidate the TLB + * DSB ISH // Ensure the TLB invalidation has completed + * ISB // See explanation below + * + * For Xen page-tables the ISB will discard any instructions fetched + * from the old mappings. + * + * For the Stage-2 page-tables the ISB ensures the completion of the DSB + * (and therefore the TLB invalidation) before continuing. So we know + * the TLBs cannot contain an entry for a mapping we may have removed. + */ +#define TLB_HELPER(name, tlbop) \ +static inline void name(void) \ +{ \ + asm volatile( \ + "dsb ishst;" \ + "tlbi " # tlbop ";" \ + "dsb ish;" \ + "isb;" \ + : : : "memory"); \ } +/* Flush local TLBs, current VMID only. */ +TLB_HELPER(flush_guest_tlb_local, vmalls12e1); + /* Flush innershareable TLBs, current VMID only */ -static inline void flush_guest_tlb(void) -{ - asm volatile( - "dsb sy;" - "tlbi vmalls12e1is;" - "dsb sy;" - "isb;" - : : : "memory"); -} +TLB_HELPER(flush_guest_tlb, vmalls12e1is); /* Flush local TLBs, all VMIDs, non-hypervisor mode */ -static inline void flush_all_guests_tlb_local(void) -{ - asm volatile( - "dsb sy;" - "tlbi alle1;" - "dsb sy;" - "isb;" - : : : "memory"); -} +TLB_HELPER(flush_all_guests_tlb_local, alle1); /* Flush innershareable TLBs, all VMIDs, non-hypervisor mode */ -static inline void flush_all_guests_tlb(void) -{ - asm volatile( - "dsb sy;" - "tlbi alle1is;" - "dsb sy;" - "isb;" - : : : "memory"); -} +TLB_HELPER(flush_all_guests_tlb, alle1is); /* Flush all hypervisor mappings from the TLB of the local processor. */ -static inline void flush_xen_tlb_local(void) -{ - asm volatile ( - "dsb sy;" /* Ensure visibility of PTE writes */ - "tlbi alle2;" /* Flush hypervisor TLB */ - "dsb sy;" /* Ensure completion of TLB flush */ - "isb;" - : : : "memory"); -} +TLB_HELPER(flush_xen_tlb_local, alle2); /* Flush TLB of local processor for address va. */ static inline void __flush_xen_tlb_one_local(vaddr_t va) From patchwork Tue May 14 12:21:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 164144 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp2551973ili; Tue, 14 May 2019 05:23:03 -0700 (PDT) X-Google-Smtp-Source: APXvYqxc8DCIZmb7PQrybQmUh65nwqB5DNnPZGQ7imEPHnFeogp2xrEs+1ezpg6TkkpUvJ8AIwCU X-Received: by 2002:a5e:9607:: with SMTP id a7mr2483964ioq.151.1557836583395; Tue, 14 May 2019 05:23:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1557836583; cv=none; d=google.com; s=arc-20160816; b=tmdrAbKoKbH08zERcWzKkq/JS125NlxbXa5iDv/5xmgpyVIBhXRVfnxWESP8nJl20g wKtkE/3ZJyjaDFPOxaDjVMvhr5b0/lBqPzqQ6j0i86Y1N6KhT/pEOud+VwkIQC+3d3cK BBL3laJXfLclQ/CpdasDftV09ewi3EFw8auZkB04NKTz5NNYY7tZmo67SUlwFIVOegaM +CwSXg7UEQgo5D5rm38rAa6Rru9CFyrbR4rlS/DU8UTw3b72ZAg64o8NpMiXBmI6FXrW SvftjeIyxJsUvavr6xfoDM5IBO8iCRmwceTvhlM0GfMH/QfEeAHRSsjcCGvS9TXIrXUV rBQw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=g3Z4pVaRU9xc9T/B8NCdJWDiIuJKE3zj4IDLXRCZPkI=; b=TrhXUbpeB6I92cxzmsjGy3P+HnPCmfZ4fKHjihfAAlQ0R509H2+i2l3hKQ2TfCG1mV BTKcgsDpHi+ACiTg0ZbkYuCdcxOTD8PeK/WT1RtryKTAEANw0h7EtjMrIP3Fia6eoHQ3 E4Lx+cXka2ioXM+mRZxh8yHsdjxu+Bmt+Y1RUJOn5GC9X0c7kxSsjLHt3VBQ84EGSgTB Nkpz7VpxsmTiDOJSShR+s6XhkyscAAfg+RFxadOd4ZhNiGRx6saqtWqpyYxuQFbijwIz WAJ/XY2rdXer650IZ6mMA3+KJ2ZuzPL92J22w5aKsffKqn+bka4ClIXuvIfSAskhIecb Oo+w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id q7si4547480iot.11.2019.05.14.05.23.03 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 14 May 2019 05:23:03 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hQWRe-0008UK-4Y; Tue, 14 May 2019 12:22:10 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hQWRc-0008ST-Ug for xen-devel@lists.xenproject.org; Tue, 14 May 2019 12:22:08 +0000 X-Inumbo-ID: e3e6a51e-7642-11e9-8509-abde66b4cdf3 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTP id e3e6a51e-7642-11e9-8509-abde66b4cdf3; Tue, 14 May 2019 12:22:07 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 45F65341; Tue, 14 May 2019 05:22:07 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 12BFF3F71E; Tue, 14 May 2019 05:22:05 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Tue, 14 May 2019 13:21:25 +0100 Message-Id: <20190514122136.28215-17-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190514122136.28215-1-julien.grall@arm.com> References: <20190514122136.28215-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH MM-PART1 v3 8/8] xen/arm: mm: Flush the TLBs even if a mapping failed in create_xen_entries X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Oleksandr_Tyshchenko@epam.com, Julien Grall , Stefano Stabellini , Andrii Anisov MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" At the moment, create_xen_entries will only flush the TLBs if the full range has successfully been updated. This may lead to leave unwanted entries in the TLBs if we fail to update some entries. Signed-off-by: Julien Grall Reviewed-by: Andrii Anisov Reviewed-by: Stefano Stabellini --- Changes in v2: - Add Andrii's reviewed-by - Add Stefano's reviewed-by --- xen/arch/arm/mm.c | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c index 8ee828d445..9d584e4cbf 100644 --- a/xen/arch/arm/mm.c +++ b/xen/arch/arm/mm.c @@ -984,7 +984,7 @@ static int create_xen_entries(enum xenmap_operation op, unsigned long nr_mfns, unsigned int flags) { - int rc; + int rc = 0; unsigned long addr = virt, addr_end = addr + nr_mfns * PAGE_SIZE; lpae_t pte, *entry; lpae_t *third = NULL; @@ -1013,7 +1013,8 @@ static int create_xen_entries(enum xenmap_operation op, { printk("%s: trying to replace an existing mapping addr=%lx mfn=%"PRI_mfn"\n", __func__, addr, mfn_x(mfn)); - return -EINVAL; + rc = -EINVAL; + goto out; } if ( op == RESERVE ) break; @@ -1030,7 +1031,8 @@ static int create_xen_entries(enum xenmap_operation op, { printk("%s: trying to %s a non-existing mapping addr=%lx\n", __func__, op == REMOVE ? "remove" : "modify", addr); - return -EINVAL; + rc = -EINVAL; + goto out; } if ( op == REMOVE ) pte.bits = 0; @@ -1043,7 +1045,8 @@ static int create_xen_entries(enum xenmap_operation op, { printk("%s: Incorrect combination for addr=%lx\n", __func__, addr); - return -EINVAL; + rc = -EINVAL; + goto out; } } write_pte(entry, pte); @@ -1052,11 +1055,14 @@ static int create_xen_entries(enum xenmap_operation op, BUG(); } } +out: + /* + * Flush the TLBs even in case of failure because we may have + * partially modified the PT. This will prevent any unexpected + * behavior afterwards. + */ flush_xen_tlb_range_va(virt, PAGE_SIZE * nr_mfns); - rc = 0; - -out: return rc; } From patchwork Tue May 14 12:21:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 164148 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp2552075ili; Tue, 14 May 2019 05:23:08 -0700 (PDT) X-Google-Smtp-Source: APXvYqxeHTztO8UjlKkfIZBPkTeGYMwLkTaN0WkIeEDxLoj+EMl1epRWSFkc4CyjHpcXmheV/Itn X-Received: by 2002:a24:edc6:: with SMTP id r189mr3315203ith.90.1557836588076; Tue, 14 May 2019 05:23:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1557836588; cv=none; d=google.com; s=arc-20160816; b=OWpC0TDhp0ThJU3hxCnXH4lXYwH1gPsVXp0wMjMGmBOh4EfNRXBUCJJZghGhpXmY9c OTypcwDoDs0dyYTPUFHYg7HVOzirlWxP6CxasB9pYTA05r9izEFUDBhh3RWqmUjIWNPF awIwlAZaMzxHJxbaJjoQQQS0jVI7xNbUGHaFDzuZelhlekyTQ0uW7cFedAevByZuT0z6 S31lRr1BXqgVQPEK7lWf431zo9GKEkiF2WqUxJ0X6TSjI7hAKizCjtcqR7rtbkKZU7ji JOgXQxhhgjr2OAMrvWdkuJoU83Y2RuczTZe3xrzwPL8M9gpxXdMl2JUjUW8zN6kFrw2e ovjg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=SVvnDDvkXOt9PhNeVd6Neu09c6WdnWwLFDcQjDC5oBw=; b=BNM59O3eBbxhqs7CrQ0gESeI7xqQTQIHKfwm5vqE/+GqltGLAEuwMh/Zsb3EuM7DeX uahE016srtmEK9Cm4w52OYez8rlkRedFf6BOdyMfshuYM98bGZ/pgGEgQ/y88YJOVUDy yaZqqCx5D2SyWzmw+09u7nb3PIpWmSDBVFbVpb6Kvn8HVjzurmzzdPXcYOVMqNZhO/OE sWw1sVGncFbrpxBzMWLqaBmxKGVoXPQdQ5yjtouHNoZHdLWX4g/zjMk3AvV8vUL1Km+v QN7SJEt/NiAj4BcfX+F1I7IMkeUlv42RANSfNRQ+WNwhVUwnQRQZi9jE8LeD8hyXD+ZU 1Paw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id a7si10618676jah.23.2019.05.14.05.23.08 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 14 May 2019 05:23:08 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hQWRf-000055-LE; Tue, 14 May 2019 12:22:11 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hQWRe-0008UP-76 for xen-devel@lists.xenproject.org; Tue, 14 May 2019 12:22:10 +0000 X-Inumbo-ID: e4c40576-7642-11e9-8a9e-0b59dbad4b84 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTP id e4c40576-7642-11e9-8a9e-0b59dbad4b84; Tue, 14 May 2019 12:22:09 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B6F6C15AD; Tue, 14 May 2019 05:22:08 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 83ED03F71E; Tue, 14 May 2019 05:22:07 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Tue, 14 May 2019 13:21:26 +0100 Message-Id: <20190514122136.28215-18-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190514122136.28215-1-julien.grall@arm.com> References: <20190514122136.28215-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH MM-PART2 v2 09/19] xen/arm64: head: Correctly report the HW CPU ID X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Oleksandr_Tyshchenko@epam.com, Julien Grall , Stefano Stabellini , Andrii Anisov MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" There are no reason to consider the HW CPU ID will be 0 when the processor is part of a uniprocessor system. At best, this will result to conflicting output as the rest of Xen use the value directly read from MPIDR_EL1. So remove the zeroing and logic to check if the CPU is part of a uniprocessor system. Signed-off-by: Julien Grall Reviewed-by: Andrii Anisov --- Changes in v2: - Add Andrii's reviewed-by --- xen/arch/arm/arm64/head.S | 6 ------ 1 file changed, 6 deletions(-) diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S index b957eb90fb..08094a273e 100644 --- a/xen/arch/arm/arm64/head.S +++ b/xen/arch/arm/arm64/head.S @@ -277,15 +277,9 @@ GLOBAL(init_secondary) mov x26, #1 /* X26 := skip_zero_bss */ common_start: - mov x24, #0 /* x24 := CPU ID. Initialy zero until we - * find that multiprocessor extensions are - * present and the system is SMP */ mrs x0, mpidr_el1 - tbnz x0, _MPIDR_UP, 1f /* Uniprocessor system? */ - ldr x13, =(~MPIDR_HWID_MASK) bic x24, x0, x13 /* Mask out flags to get CPU ID */ -1: /* Non-boot CPUs wait here until __cpu_up is ready for them */ cbz x22, 1f From patchwork Tue May 14 12:21:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 164145 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp2551992ili; Tue, 14 May 2019 05:23:04 -0700 (PDT) X-Google-Smtp-Source: APXvYqxdU79LU+6fcJHlRvBtgJTJt3U3XqpoPuOyWLYTH0KDQhUC0OZFb/EwUc9ZLZgVi9S3RhuG X-Received: by 2002:a05:660c:404:: with SMTP id c4mr3360895itk.60.1557836584032; Tue, 14 May 2019 05:23:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1557836584; cv=none; d=google.com; s=arc-20160816; b=pyfFn+Uz15xo7JvRyHUYeZlVkCeq8eMc5oWjw/FRUTWxT9XZTg/r2scJLspN2L0IRC BjBP0asiKEqYgOAQ39rfompj/cKFiFNk3brNEvFfQzDrrD27D8J+TvSeFi9pEbHkkdyQ AbTy5ZYtCH8q7MZJa2ua29b/FEdFWbilEibLZaUiDflYtOAC9nRO6EPPrKwXepVj0n9q 8fv4ApyTRwdxFpFEJcrvSlFU/98JRH0JjdbqzjqcTxNy2NwDdArvCxMD1BSLDnF4NfK1 7Owfg+WQHTY742q40X6xpjWg62/C6LE7BqAE2Ya38xXoGgbHlp0qZxiKGNcqjIidGU6o g5VQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=gWiIjnb7FKVA+rv1YIQ9lWA/2IPZtXuIP6zSBI8grJU=; b=Zz0BcLt4AfVfVJppCbznZqSO2xi3TihBwKuf3wAL61Skzqymu3YqddKVENJBLAlTYe UCZCdc/c2OHdkLJ7ju4uRnXg9hG3tcAK7MxuBZXTQpazHlPQpwgtZ3lDNukDgMkXagHW XOVYWk2rlNMPDdUsK3awHIuPiQzL+WFq9/4xoHPPfPjmwLGY8FH+sMVKSTTuy3jD6orL DJJUIIVMz0UsGpLENfHC8fXdBJxkRPl4kpglz8qj1GrgT5g0Zm1TaqDw414tubxrdahu RGr5H5hvPqjTYzpBwF0i4yOxw+hFmadZQ6XWOeiCQYCPYNOBADOZ9S4KqclSPyc7p8LQ Y3rA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id n186si9014243iof.2.2019.05.14.05.23.03 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 14 May 2019 05:23:04 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hQWRi-00009R-7q; Tue, 14 May 2019 12:22:14 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hQWRf-00005W-Rd for xen-devel@lists.xenproject.org; Tue, 14 May 2019 12:22:11 +0000 X-Inumbo-ID: e591c939-7642-11e9-8980-bc764e045a96 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id e591c939-7642-11e9-8980-bc764e045a96; Tue, 14 May 2019 12:22:10 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 338F2341; Tue, 14 May 2019 05:22:10 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 009753F71E; Tue, 14 May 2019 05:22:08 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Tue, 14 May 2019 13:21:27 +0100 Message-Id: <20190514122136.28215-19-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190514122136.28215-1-julien.grall@arm.com> References: <20190514122136.28215-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH MM-PART2 v2 10/19] xen/arm32: head: Correctly report the HW CPU ID X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Oleksandr_Tyshchenko@epam.com, Julien Grall , Stefano Stabellini , Andrii Anisov MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" There are no reason to consider the HW CPU ID will be 0 when the processor is part of a uniprocessor system. At best, this will result to conflicting output as the rest of Xen use the value directly read from MPIDR. So remove the zeroing and logic to check if the CPU is part of a uniprocessor system. Signed-off-by: Julien Grall Reviewed-by: Andrii Anisov --- Changes in v2: - Add Andrii's reviewed-by --- xen/arch/arm/arm32/head.S | 8 -------- 1 file changed, 8 deletions(-) diff --git a/xen/arch/arm/arm32/head.S b/xen/arch/arm/arm32/head.S index 9f40face98..d42a13556c 100644 --- a/xen/arch/arm/arm32/head.S +++ b/xen/arch/arm/arm32/head.S @@ -124,16 +124,8 @@ GLOBAL(init_secondary) mov r12, #1 /* r12 := is_secondary_cpu */ common_start: - mov r7, #0 /* r7 := CPU ID. Initialy zero until we - * find that multiprocessor extensions are - * present and the system is SMP */ mrc CP32(r1, MPIDR) - tst r1, #MPIDR_SMP /* Multiprocessor extension supported? */ - beq 1f - tst r1, #MPIDR_UP /* Uniprocessor system? */ - bne 1f bic r7, r1, #(~MPIDR_HWID_MASK) /* Mask out flags to get CPU ID */ -1: /* Non-boot CPUs wait here until __cpu_up is ready for them */ teq r12, #0 From patchwork Tue May 14 12:21:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 164149 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp2552090ili; Tue, 14 May 2019 05:23:08 -0700 (PDT) X-Google-Smtp-Source: APXvYqxzSjhCfrZmmInJ4Q5iNPc/yAF72ibEWBUjl5zcsKD7KI4q340ccNWjgvrO9N9QWHN1SJI8 X-Received: by 2002:a24:6292:: with SMTP id d140mr3084575itc.12.1557836588415; Tue, 14 May 2019 05:23:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1557836588; cv=none; d=google.com; s=arc-20160816; b=VgsIV8ZoTJkoAm+Le3svzkpLnOdnuVgaOByCG+N4K0yTd2C2Eay5TzpsGK1HXTTfi9 jqvDMm9QcVoVbYp6ICUdjkEyiJSIw/9vl9+82Q3hfJF5iGoKm2YjeOlY9cCVpwrbTGPu ESG7Yk73Rtf1mFZBj1O5xXB0VFNIQm+6r6yCdaiZVZROWzUJzdn66VYcKQX7tbza4Syu nE1xqe7eBmL5RoAUAX5aBAzR0Az10jW3Dju+R5LINilbTLIbh2YqVRA8rY/A3Bn6RS+k kHsLu3xiq6CD6cffm8+liOCl3sqlkd/TpXsksNVT6Xe4Kc7UrU3uHO9w+/64i0p9Mw1N 1ozw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=rKH6b2vJKj4RaNahOIvZ5cHDJ9vsSUsddb3fOXvecRA=; b=I9fygiQMf2Hlk5yQT4oS5PK13XzPo4fWN5FhWiE9mcU2rj+3QTiwFVKujjAxB/mPvb 3IZE20AxMvm/RVmBKdoVJQEPSUeerkL3AcTKNIjXxVJW4EwDTdogyrhT8wTPwJIMcbO/ Mc+tn7hs4ddFsa9qKf/THbRjqHC8HyTNGOsAbvwdvliWbCfDIHFPpEKdeyLUrfIRhKCk tRMoOO8tx1qgM4fLEDQzVNDO5nq0G1EukQ+ds7xU2/pH/5E/maXc0Sq9QfEW/RdUqlel ckbVRPYQtvf5p0Ql+WSXmp8MW5Np8r6h9eE3oLVIR5YtvqQeWSZlWwvUEapYycfPiW7x GQTQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id d43si9922817jaf.100.2019.05.14.05.23.08 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 14 May 2019 05:23:08 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hQWRj-0000BL-4S; Tue, 14 May 2019 12:22:15 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hQWRh-00007X-3N for xen-devel@lists.xenproject.org; Tue, 14 May 2019 12:22:13 +0000 X-Inumbo-ID: e6741eb8-7642-11e9-8980-bc764e045a96 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id e6741eb8-7642-11e9-8980-bc764e045a96; Tue, 14 May 2019 12:22:11 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A4EE315AB; Tue, 14 May 2019 05:22:11 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 71D213F71E; Tue, 14 May 2019 05:22:10 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Tue, 14 May 2019 13:21:28 +0100 Message-Id: <20190514122136.28215-20-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190514122136.28215-1-julien.grall@arm.com> References: <20190514122136.28215-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH MM-PART2 v2 11/19] xen/arm32: head: Don't set MAIR0 and MAIR1 X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Oleksandr_Tyshchenko@epam.com, Julien Grall , Stefano Stabellini , Andrii Anisov MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The co-processor registers MAIR0 and MAIR1 are managed by EL1. So there are no need to initialize them during Xen boot. Signed-off-by: Julien Grall Reviewed-by: Andrii Anisov --- Changes in v2 - Add Andrii's reviewed-by --- xen/arch/arm/arm32/head.S | 2 -- 1 file changed, 2 deletions(-) diff --git a/xen/arch/arm/arm32/head.S b/xen/arch/arm/arm32/head.S index d42a13556c..3448817aab 100644 --- a/xen/arch/arm/arm32/head.S +++ b/xen/arch/arm/arm32/head.S @@ -212,8 +212,6 @@ cpu_init_done: /* Set up memory attribute type tables */ ldr r0, =MAIR0VAL ldr r1, =MAIR1VAL - mcr CP32(r0, MAIR0) - mcr CP32(r1, MAIR1) mcr CP32(r0, HMAIR0) mcr CP32(r1, HMAIR1) From patchwork Tue May 14 12:21:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 164146 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp2552008ili; Tue, 14 May 2019 05:23:04 -0700 (PDT) X-Google-Smtp-Source: APXvYqyA1J8XP9dM3ZNBCUQIs40tFzNBC2MAMGxFadYPPYujCzKmcTdQLxGqXF+yjGFSO3zmFfVV X-Received: by 2002:a6b:5116:: with SMTP id f22mr12498104iob.185.1557836584605; Tue, 14 May 2019 05:23:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1557836584; cv=none; d=google.com; s=arc-20160816; b=ZzEWBYIPFL9CtI61wHyAZ82pN8WkOplgDEOO5OfgYtaMpfPfCrTVqBZ/oWRQ9g74cX +imzcvi188HRi6ncphcMY6gFbNqyzgG0qZRYrV1Mnkt75En7BVRVbHVP1vI1Sqlwk+1j VnGwiSnQHitdZbigrA/RF6utCd+W/6BSnoKFXg4WIj3GXe07YY1LP6ZoNBk6e38X3oHv QI+nvENN4QzqRRezRq7l/8Sb34HnJxfSOuM9f8rN4t28HPB/KNqe8/BnfQZotJK0vewT iJ2gZoj18Kxy+hZ2yUyTz8fj4ACOj12/UfY6ufr857rGOKzMxm9o8E9iKlO7qQPhgIcM Z4jg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=kumSZGcY2u14dTnJuAA7tUfD8yb4Jj5VGtOy5uAhNTg=; b=nmtgWm6z98eq/1NI49sdIb33YJaiIQqfvOQvh9g4/94PMsgnPTLiraWehcnMsxHkBb 1VhmfDIKDA7E/8F561HanZs1JthJWRpbTk0z1bgSmLoh/wytwTNWCB9B/spfnZHo9Pc5 FqmiPD6CVYKEJ0xSlH2EqXzaLjgXVVP1mw94cP1YKJw9D3/MIR/tuN7w+J7UzqvqhdkA puaoCZvIDjSGG3vSId8lF0tl/liDF/9ojwBVOB0vuMXCSaBNE4hX48LPC+UnhChWm9zF slQO88a/UWymBLrEjJWaUY4sX4/XYWSC3XY0YjHQmW7iTL3vHHwiBYfkWrLDC995M0Ce In8Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id h12si9813500iof.87.2019.05.14.05.23.04 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 14 May 2019 05:23:04 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hQWRj-0000Cg-PO; Tue, 14 May 2019 12:22:15 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hQWRi-00009a-D3 for xen-devel@lists.xenproject.org; Tue, 14 May 2019 12:22:14 +0000 X-Inumbo-ID: e73a3f5b-7642-11e9-8980-bc764e045a96 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id e73a3f5b-7642-11e9-8980-bc764e045a96; Tue, 14 May 2019 12:22:13 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id F28BF15AD; Tue, 14 May 2019 05:22:12 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E2C263F71E; Tue, 14 May 2019 05:22:11 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Tue, 14 May 2019 13:21:29 +0100 Message-Id: <20190514122136.28215-21-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190514122136.28215-1-julien.grall@arm.com> References: <20190514122136.28215-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH MM-PART2 v2 12/19] xen/arm32: head: Always zero r3 before update a page-table entry X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Oleksandr_Tyshchenko@epam.com, Julien Grall , Stefano Stabellini , Andrii_Anisov@epam.com MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The boot code is using r2 and r3 to hold the page-table entry value. While r2 is always updated before storing the value, this is not always the case for r3. Thankfully today, r3 will always be zero when we care. But this is difficult to track and error-prone. So always zero r3 within the few instructions before the write the page-table entry. Signed-off-by: Julien Grall --- Changes in v2: - Use 0x0 instead of 0 - Remove a duplicate mov r3, #0 --- xen/arch/arm/arm32/head.S | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/arm32/head.S b/xen/arch/arm/arm32/head.S index 3448817aab..18ded49a04 100644 --- a/xen/arch/arm/arm32/head.S +++ b/xen/arch/arm/arm32/head.S @@ -270,6 +270,7 @@ cpu_init_done: orr r2, r2, #PT_UPPER(MEM) /* r2:r3 := section map */ orr r2, r2, #PT_LOWER(MEM) lsl r1, r1, #3 /* r1 := Slot offset */ + mov r3, #0x0 strd r2, r3, [r4, r1] /* Mapping of paddr(start) */ mov r6, #1 /* r6 := identity map now in place */ @@ -372,11 +373,11 @@ paging: /* Add UART to the fixmap table */ ldr r1, =xen_fixmap /* r1 := vaddr (xen_fixmap) */ - mov r3, #0 lsr r2, r11, #THIRD_SHIFT lsl r2, r2, #THIRD_SHIFT /* 4K aligned paddr of UART */ orr r2, r2, #PT_UPPER(DEV_L3) orr r2, r2, #PT_LOWER(DEV_L3) /* r2:r3 := 4K dev map including UART */ + mov r3, #0x0 strd r2, r3, [r1, #(FIXMAP_CONSOLE*8)] /* Map it in the first fixmap's slot */ 1: @@ -388,6 +389,7 @@ paging: orr r2, r2, #PT_LOWER(PT) /* r2:r3 := table map of xen_fixmap */ ldr r4, =FIXMAP_ADDR(0) mov r4, r4, lsr #(SECOND_SHIFT - 3) /* r4 := Slot for FIXMAP(0) */ + mov r3, #0x0 strd r2, r3, [r1, r4] /* Map it in the fixmap's slot */ /* Use a virtual address to access the UART. */ From patchwork Tue May 14 12:21:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 164150 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp2552166ili; Tue, 14 May 2019 05:23:12 -0700 (PDT) X-Google-Smtp-Source: APXvYqzWXb/vu5YuXkI2oi/0dL8MfdPbbO7YlG8fHv0RHMNm2LGGmQnIj0nVSnpWzNWbEhix+U08 X-Received: by 2002:a24:4453:: with SMTP id o80mr3174083ita.160.1557836592360; Tue, 14 May 2019 05:23:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1557836592; cv=none; d=google.com; s=arc-20160816; b=oIqtv4Bx8xmGIoTS/jfJgJz8Fl+yGdWhrqiEfMlg2nGjeAkmOO+JrMawFSXuGlm0Y6 PfKlxWkCMfjKRxTpoeFiUY4kdf65b52ZtTEGkTHZa+U76MaFTgjwb/GUJYoyKM/9sTYV jZVYF8+Nh/7LmkkROSOW7zqcFcfpUTLyF4xkmt+iQycZQbsHDw0/jg5epnWro5CXNu8I O03n+fTcBseQN/WNi67DT0q/KP11pQ51n5bPFYBL7aOkNics30GTcXbLYATXaOE2LIXZ 3rdh7LgQfvjOuFCg0LQFmuStw8ySIaSQxoqL+hB1wiERr61Jg2ymiiS+4OwzHVcFvQhl ZcIQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=nPABOQvlQbFcabCCgz8apQE2RJ6pWYm70CDrjaPFSPc=; b=XtdAqtDDn2uRbz0wnO3YJQ3bZA1zvo6O/P5Kebk/oeaxhxSZMdADJHASOaYpD/EWqM /m6qfu6L5D/PZP7Olyi7C4h+vKSQGEGHmbhrNIWE8ycNU5HRp9bqB16j/Mn23BNbl+yh OrIP5ot1J9a6tXgL6BGPXTFhMOZarO3SV9Mq/PItg49PNG3EJfGQDdTpYDg7GfRKTb9k FZR1bW4oIKSAM7mS0fuPQm2yKiO8M9JABB2nC+Md/9rzr0IjNJ83sogam7BrcWlpWttA fuEXPnLHUS+5O46ECYvS2aBHF5rIEAYjhtlanxreeNJpFkfkp3M9WwVJeUnocQd97g8C g0dA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id i12si10227368jak.18.2019.05.14.05.23.12 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 14 May 2019 05:23:12 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hQWRk-0000Eo-L6; Tue, 14 May 2019 12:22:16 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hQWRj-0000CN-Li for xen-devel@lists.xenproject.org; Tue, 14 May 2019 12:22:15 +0000 X-Inumbo-ID: e81f2f19-7642-11e9-8980-bc764e045a96 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id e81f2f19-7642-11e9-8980-bc764e045a96; Tue, 14 May 2019 12:22:14 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6FB7C341; Tue, 14 May 2019 05:22:14 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 3CBD03F71E; Tue, 14 May 2019 05:22:13 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Tue, 14 May 2019 13:21:30 +0100 Message-Id: <20190514122136.28215-22-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190514122136.28215-1-julien.grall@arm.com> References: <20190514122136.28215-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH MM-PART2 v2 13/19] xen/arm32: mm: Avoid to zero and clean cache for CPU0 domheap X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Oleksandr_Tyshchenko@epam.com, Julien Grall , Stefano Stabellini , Andrii Anisov MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The page-table walker is configured to use the same shareability and cacheability as the access performed when updating the page-tables. This means cleaning the cache for CPU0 domheap is unnecessary. Furthermore, CPU0 page-tables are part of Xen binary and will already be zeroed before been used. So it is pointless to zero the domheap again. Signed-off-by: Julien Grall Reviewed-by: Andrii Anisov --- Changes in v2: - Tweak a bit the commit message - Add Andrii's reviewed-by --- xen/arch/arm/mm.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c index e090afb976..cda2847d00 100644 --- a/xen/arch/arm/mm.c +++ b/xen/arch/arm/mm.c @@ -724,11 +724,6 @@ void __init setup_pagetables(unsigned long boot_phys_offset) #ifdef CONFIG_ARM_32 per_cpu(xen_pgtable, 0) = cpu0_pgtable; per_cpu(xen_dommap, 0) = cpu0_dommap; - - /* Make sure it is clear */ - memset(this_cpu(xen_dommap), 0, DOMHEAP_SECOND_PAGES*PAGE_SIZE); - clean_dcache_va_range(this_cpu(xen_dommap), - DOMHEAP_SECOND_PAGES*PAGE_SIZE); #endif } From patchwork Tue May 14 12:21:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 164153 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp2552218ili; Tue, 14 May 2019 05:23:15 -0700 (PDT) X-Google-Smtp-Source: APXvYqxCOHGwmg83xacrzW17b4oEVy+ZgcV6dgVFmVhhgb8Qr+bk0unYpDAwcP0I4X0IPWAOPR6G X-Received: by 2002:a24:5255:: with SMTP id d82mr3523475itb.104.1557836594969; Tue, 14 May 2019 05:23:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1557836594; cv=none; d=google.com; s=arc-20160816; b=jSYqz8CubTQKnAK0utggb8l2rAFg8fCynO8yTEBQhzYXGk8EPTtEyjd2wxHIoLiGmC bhohRaDpnVnzSXanwiojodrttyq8bQTiMZ3SM8NQT0Dm2wuolM7HS27IHn4VKgpV32VE S6Y60BJwTV8/qd0Xc8Z7P8ExQKb5I+Pgj4xBH5MknCB7R37jDA/so1j3gXzOcKKoyrSF imab0GsOJ1muaTJm2oXolaoQg/zoJSyvV8Izy3+d6FDjr8Lmorud61KrOKGppLr2knp2 nB4O/lL/F/Fvgokq/rah1TutZqZaMt1sBEFzTQSEt7WyfO+Yxq9ct9V2TCnUg0Ys9Mw1 rDjw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=0IYOeOo+2lNCD8Y0PLPTB6wZUjE3dFZyctv6YK1o+8g=; b=fnJLlM5J+8aDGEYRYNBlGvmk9oK0Kdrzu0pM+LJFD2H728R/A68pVS6ixdvobclErU YJTPxWUcZe6w//2pju9ODCYDkFTxaqS4pTfKAeCaPcppLi94ydTWy8GVa1WSj20JePxU gFdOlDRLTRzB8q48+SKufeTx3pFGqrCZc/cv/Uw0qHLxOH2+H6SDq79ru0/0+nAXkivl ohD+F+3ORMHT81C6bAqZfA8z/InTOXMdmvlRDRMIFcYj+hCsTkovm38rIeFDw7IDkOW0 JqanPlfAYebf1Onbd2gQ6MnezbwgT6icEe9qF9KgUwKKunxJ10Ym1T0AZto5j03wL81b 9xPA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id v6si2909275ion.63.2019.05.14.05.23.14 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 14 May 2019 05:23:14 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hQWRn-0000Kf-FC; Tue, 14 May 2019 12:22:19 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hQWRl-0000HK-GQ for xen-devel@lists.xenproject.org; Tue, 14 May 2019 12:22:17 +0000 X-Inumbo-ID: e900d312-7642-11e9-9425-ff57c8e298c2 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTP id e900d312-7642-11e9-9425-ff57c8e298c2; Tue, 14 May 2019 12:22:16 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E081F15AB; Tue, 14 May 2019 05:22:15 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id ADA9B3F71E; Tue, 14 May 2019 05:22:14 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Tue, 14 May 2019 13:21:31 +0100 Message-Id: <20190514122136.28215-23-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190514122136.28215-1-julien.grall@arm.com> References: <20190514122136.28215-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH MM-PART2 v2 14/19] xen/arm32: mm: Avoid cleaning the cache for secondary CPUs page-tables X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Oleksandr_Tyshchenko@epam.com, Julien Grall , Stefano Stabellini , Andrii Anisov MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The page-table walker is configured to use the same shareability and cacheability as the access performed when updating the page-tables. This means cleaning the cache for secondary CPUs runtime page-tables is unnecessary. Signed-off-by: Julien Grall Reviewed-by: Andrii Anisov --- Changes in v2: - Add Andrii's reviewed-by --- xen/arch/arm/mm.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c index cda2847d00..6db7dda0da 100644 --- a/xen/arch/arm/mm.c +++ b/xen/arch/arm/mm.c @@ -769,9 +769,6 @@ int init_secondary_pagetables(int cpu) write_pte(&first[first_table_offset(DOMHEAP_VIRT_START+i*FIRST_SIZE)], pte); } - clean_dcache_va_range(first, PAGE_SIZE); - clean_dcache_va_range(domheap, DOMHEAP_SECOND_PAGES*PAGE_SIZE); - per_cpu(xen_pgtable, cpu) = first; per_cpu(xen_dommap, cpu) = domheap; From patchwork Tue May 14 12:21:32 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 164155 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp2552238ili; Tue, 14 May 2019 05:23:16 -0700 (PDT) X-Google-Smtp-Source: APXvYqy+CqEpvzmL7TZBFHWkNFGqKnWFri6DGksWHITlbr/P6MKeqLlEXqmkNwZJ87An0wRiCIq2 X-Received: by 2002:a02:95aa:: with SMTP id b39mr22556546jai.45.1557836595482; Tue, 14 May 2019 05:23:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1557836595; cv=none; d=google.com; s=arc-20160816; b=BB26C2uA8EPSstegx9nwIfb2p4P5nmDbw0JvfwYdvpak4fV3mGEGWEcNuCxhd22QRc yCUyykuT4Iw8FxDQVf+tAlYZgUcnldVIPM/6x3dA6FZu3H7Cr0IOxDuGVNz1PmuqxC2h 0vKkAzSiyxGfsWuyFfKX6vGDhEZ3gUTjvdNPvjPr/yVo2emLUpmqnCpQJ/JBE5K8hhog 9YBst2rw+gjSzRp3UW+JMxhi+4CB8kUZAizEB7bVz8/5SND71cKL+QcBusM5zosBze9x 6bna7wreC79f5n/aLamCu7i2nOsGcE5vY29lBujc7d7cjAtrpm62+5bvNpHkKU4y+TEt 6Ufg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=kIQ8j07N6sGKRipePn8wYBH0jmpLKCu9DJDn+JV6ypU=; b=bVCjo4US8xqeLscBHij4xImZU32TzYaMdMc/QpsM+6uQFmreFTlRpGHv24IPOf49ST i8hatpS9djsEwkEB3b5v+Wimj1hWlIBir0/RWz4Eey6EWLhQkFH03I9Nc01Bm+xrc0Yf MvYiLxWginsP84JfscduKQZlyVNH980jpNS8wyKxGEBeThN/uAQ4XE0S3KaQXy0RvZvj mIS+kTtTL2wilGQT5r2y6rSEdTtLkJ9Be/qJDu4V0Ji1zV9DdFPXPSB4QDAzPfILH1Ze roN2roFRzY7QHFYZ/OvPVuG+qmz2/GQtf1BuNWuzSQRAMqUPxcpBaxXPIfkDQG2Cf5tb 1SEg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id x2si9813666jap.62.2019.05.14.05.23.15 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 14 May 2019 05:23:15 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hQWRo-0000Lw-1I; Tue, 14 May 2019 12:22:20 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hQWRm-0000JW-Py for xen-devel@lists.xenproject.org; Tue, 14 May 2019 12:22:18 +0000 X-Inumbo-ID: e9d0013c-7642-11e9-a9ee-cfe6d1d02b94 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTP id e9d0013c-7642-11e9-a9ee-cfe6d1d02b94; Tue, 14 May 2019 12:22:17 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3A87315AD; Tue, 14 May 2019 05:22:17 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 2AA193F71E; Tue, 14 May 2019 05:22:16 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Tue, 14 May 2019 13:21:32 +0100 Message-Id: <20190514122136.28215-24-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190514122136.28215-1-julien.grall@arm.com> References: <20190514122136.28215-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH MM-PART2 v2 15/19] xen/arm: mm: Introduce DEFINE_PAGE_TABLE{, S} and use it X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Oleksandr_Tyshchenko@epam.com, Julien Grall , Stefano Stabellini , Andrii_Anisov@epam.com MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" We have multiple static page-tables defined in arch/arm/mm.c. The current way to define them is difficult to read and does not help when making modification. Two new helpers DEFINE_PAGE_TABLES (to define multiple page-tables) and DEFINE_PAGE_TABLE (alias of DEFINE_PAGE_TABLES(..., 1)) are introduced and now used to define static page-tables. Note that DEFINE_PAGE_TABLES() alignment differs from what is currently used for allocating page-tables. This is fine because page-tables are only required to be aligned to a page-size. Signed-off-by: Julien Grall --- Changes in v2: - Patch in replacement of "Use the shorter version __aligned(PAGE_SIZE) to align page-tables". --- xen/arch/arm/mm.c | 32 ++++++++++++++++++-------------- 1 file changed, 18 insertions(+), 14 deletions(-) diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c index 6db7dda0da..9a5f2e1c3f 100644 --- a/xen/arch/arm/mm.c +++ b/xen/arch/arm/mm.c @@ -50,6 +50,11 @@ struct domain *dom_xen, *dom_io, *dom_cow; #undef mfn_to_virt #define mfn_to_virt(mfn) __mfn_to_virt(mfn_x(mfn)) +#define DEFINE_PAGE_TABLES(name, nr) \ +lpae_t __aligned(PAGE_SIZE) name[LPAE_ENTRIES * (nr)] + +#define DEFINE_PAGE_TABLE(name) DEFINE_PAGE_TABLES(name, 1) + /* Static start-of-day pagetables that we use before the allocators * are up. These are used by all CPUs during bringup before switching * to the CPUs own pagetables. @@ -73,13 +78,13 @@ struct domain *dom_xen, *dom_io, *dom_cow; * Finally, if EARLY_PRINTK is enabled then xen_fixmap will be mapped * by the CPU once it has moved off the 1:1 mapping. */ -lpae_t boot_pgtable[LPAE_ENTRIES] __attribute__((__aligned__(4096))); +DEFINE_PAGE_TABLE(boot_pgtable); #ifdef CONFIG_ARM_64 -lpae_t boot_first[LPAE_ENTRIES] __attribute__((__aligned__(4096))); -lpae_t boot_first_id[LPAE_ENTRIES] __attribute__((__aligned__(4096))); +DEFINE_PAGE_TABLE(boot_first); +DEFINE_PAGE_TABLE(boot_first_id); #endif -lpae_t boot_second[LPAE_ENTRIES] __attribute__((__aligned__(4096))); -lpae_t boot_third[LPAE_ENTRIES] __attribute__((__aligned__(4096))); +DEFINE_PAGE_TABLE(boot_second); +DEFINE_PAGE_TABLE(boot_third); /* Main runtime page tables */ @@ -93,8 +98,8 @@ lpae_t boot_third[LPAE_ENTRIES] __attribute__((__aligned__(4096))); #ifdef CONFIG_ARM_64 #define HYP_PT_ROOT_LEVEL 0 -lpae_t xen_pgtable[LPAE_ENTRIES] __attribute__((__aligned__(4096))); -lpae_t xen_first[LPAE_ENTRIES] __attribute__((__aligned__(4096))); +static DEFINE_PAGE_TABLE(xen_pgtable); +static DEFINE_PAGE_TABLE(xen_first); #define THIS_CPU_PGTABLE xen_pgtable #else #define HYP_PT_ROOT_LEVEL 1 @@ -107,17 +112,16 @@ static DEFINE_PER_CPU(lpae_t *, xen_pgtable); * DOMHEAP_VIRT_START...DOMHEAP_VIRT_END in 2MB chunks. */ static DEFINE_PER_CPU(lpae_t *, xen_dommap); /* Root of the trie for cpu0, other CPU's PTs are dynamically allocated */ -lpae_t cpu0_pgtable[LPAE_ENTRIES] __attribute__((__aligned__(4096))); +static DEFINE_PAGE_TABLE(cpu0_pgtable); /* cpu0's domheap page tables */ -lpae_t cpu0_dommap[LPAE_ENTRIES*DOMHEAP_SECOND_PAGES] - __attribute__((__aligned__(4096*DOMHEAP_SECOND_PAGES))); +static DEFINE_PAGE_TABLES(cpu0_dommap, DOMHEAP_SECOND_PAGES); #endif #ifdef CONFIG_ARM_64 /* The first page of the first level mapping of the xenheap. The * subsequent xenheap first level pages are dynamically allocated, but * we need this one to bootstrap ourselves. */ -lpae_t xenheap_first_first[LPAE_ENTRIES] __attribute__((__aligned__(4096))); +static DEFINE_PAGE_TABLE(xenheap_first_first); /* The zeroeth level slot which uses xenheap_first_first. Used because * setup_xenheap_mappings otherwise relies on mfn_to_virt which isn't * valid for a non-xenheap mapping. */ @@ -131,12 +135,12 @@ static __initdata int xenheap_first_first_slot = -1; * addresses from 0 to 0x7fffffff. Offsets into it are calculated * with second_linear_offset(), not second_table_offset(). */ -lpae_t xen_second[LPAE_ENTRIES*2] __attribute__((__aligned__(4096*2))); +static DEFINE_PAGE_TABLES(xen_second, 2); /* First level page table used for fixmap */ -lpae_t xen_fixmap[LPAE_ENTRIES] __attribute__((__aligned__(4096))); +DEFINE_PAGE_TABLE(xen_fixmap); /* First level page table used to map Xen itself with the XN bit set * as appropriate. */ -static lpae_t xen_xenmap[LPAE_ENTRIES] __attribute__((__aligned__(4096))); +static DEFINE_PAGE_TABLE(xen_xenmap); /* Non-boot CPUs use this to find the correct pagetables. */ uint64_t init_ttbr; From patchwork Tue May 14 12:21:33 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 164152 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp2552219ili; Tue, 14 May 2019 05:23:15 -0700 (PDT) X-Google-Smtp-Source: APXvYqzyXkTWdaZibwHrPcWC6Zd4ykiuAr666Um/PjlV+dCt4ENK/RsC1z8DblkPlfHN2zwBD1bH X-Received: by 2002:a6b:37c2:: with SMTP id e185mr18345683ioa.143.1557836594996; Tue, 14 May 2019 05:23:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1557836594; cv=none; d=google.com; s=arc-20160816; b=lxXmAzG/2V1LOUwMWNPAc4K5w3nJcfPGHNCXkyomdRG+HAZ5CfQUtgIK9TlrqiY5u/ eKtuY0t39aMcIV1HCdJziqHrE0yXLGeQ+7oTKPxLCoMMkjRXgvS3N7/wEvRbuaMKc4Fs IZCHPSVwuxHSs9/PFQbsD+0U3j+ttOwvjRgxST6YvahlOrajztS9ojf5csNIvzeI/SnA 3kCNSRxNhi4gnxid1NUERBkZpbbRPhlRDeWnM0PZPXe3s1CvYrveTcRJE5iluqxDKqwP /PqtAQYty2hXHrs0P86eguILje/HZD8ukIioiFmGtafHrC9ApuTG+ffHAjUYgXGovRju e2jw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=b8pUgsBkjgmcNr3jm0+cfqB5BNuu57xPBzSveDyZutQ=; b=tN5Yqon0TvcY8L5oulE0OwGKguEuAO/Bhro5wpg1RBrnS0FpPEiAQ7/MY8xW8nmP9V mhNpuvTeavO8v2CmdQ8R2SADF9B6643U/xV7GIIlFJ0LmwPnNjdjWHNfUQ39uGlN3haO LBESMLcT5pR/x0Sv9XYS02C0EROXa6I6XO+2Rax3jGWQMNqjIVg3gXvE9SXd/nouMBWc DjMZrNbvNvIfSzBesqWH68NXI313jxkweSHrWYQCHZM6Fsfa+ZKYFRpI/5zMjrP1bhOk TMiEibTMEdJLBGu14WZTmQ4BoKEnUaoQXkQLs3+63pQAMj1hw1VbaqB3NQlF4MbkUz7G DJyQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id h133si1414047ith.107.2019.05.14.05.23.14 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 14 May 2019 05:23:14 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hQWRp-0000PG-Or; Tue, 14 May 2019 12:22:21 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hQWRo-0000Lt-2L for xen-devel@lists.xenproject.org; Tue, 14 May 2019 12:22:20 +0000 X-Inumbo-ID: ea935614-7642-11e9-bb29-ff42585fbcaf Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTP id ea935614-7642-11e9-bb29-ff42585fbcaf; Tue, 14 May 2019 12:22:18 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 881C4341; Tue, 14 May 2019 05:22:18 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 781CD3F71E; Tue, 14 May 2019 05:22:17 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Tue, 14 May 2019 13:21:33 +0100 Message-Id: <20190514122136.28215-25-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190514122136.28215-1-julien.grall@arm.com> References: <20190514122136.28215-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH MM-PART2 v2 16/19] xen/arm: mm: Protect Xen page-table update with a spinlock X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Oleksandr_Tyshchenko@epam.com, Julien Grall , Stefano Stabellini , Andrii_Anisov@epam.com MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The function create_xen_entries() may be called concurrently. For instance, while the vmap allocation is protected by a spinlock, the mapping is not. The implementation create_xen_entries() contains quite a few TOCTOU races such as when allocating the 3rd-level page-tables. Thankfully, they are pretty hard to reach as page-tables are allocated once and never released. Yet it is possible, so we need to protect with a spinlock to avoid corrupting the page-tables. Signed-off-by: Julien Grall --- Changes in v2: - Rework the commit message --- xen/arch/arm/mm.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c index 9a5f2e1c3f..7502a14760 100644 --- a/xen/arch/arm/mm.c +++ b/xen/arch/arm/mm.c @@ -974,6 +974,8 @@ enum xenmap_operation { RESERVE }; +static DEFINE_SPINLOCK(xen_pt_lock); + static int create_xen_entries(enum xenmap_operation op, unsigned long virt, mfn_t mfn, @@ -985,6 +987,8 @@ static int create_xen_entries(enum xenmap_operation op, lpae_t pte, *entry; lpae_t *third = NULL; + spin_lock(&xen_pt_lock); + for(; addr < addr_end; addr += PAGE_SIZE, mfn = mfn_add(mfn, 1)) { entry = &xen_second[second_linear_offset(addr)]; @@ -1059,6 +1063,8 @@ out: */ flush_xen_tlb_range_va(virt, PAGE_SIZE * nr_mfns); + spin_unlock(&xen_pt_lock); + return rc; } From patchwork Tue May 14 12:21:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 164151 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp2552182ili; Tue, 14 May 2019 05:23:13 -0700 (PDT) X-Google-Smtp-Source: APXvYqwIc7MwiBkyN95wjvD/MZUTFZWfIPTqYgiY9k52tX9phydH/ZUvxyFyEU/BAxVIRlSgYOm1 X-Received: by 2002:a24:6d81:: with SMTP id m123mr3521483itc.128.1557836593075; Tue, 14 May 2019 05:23:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1557836593; cv=none; d=google.com; s=arc-20160816; b=mI0qNNQBg7U1W7XPuIlq9tqi9mnZnQxMKQHFP1WVnscCZ32aGD8q4LYmbLTt0B5Aee 6CjsKHv8n/oe0zR58Yvm4zMcsFGe1Xr/orZb10FtN8t1tYWNa3AxpnnN7yYBuQvQ76XU E8Xi+ixfRR7EDjkEpR2b09hYdb/HShHLmT7aZnTcPcQhezPf2+LOOc3hMa+M93AWfnz1 7c5cPcMLAh+ARF9v2wsjhl66dUMei5Kdpz90f0x07M3tzVLXbksqKVhdaj2Y8uZNf1c1 RqgXGwydVRc+5pPo1jw09F5wlbluhMITggRV1szsFyKO09T4qrXkgP4Frid5jLL7k0HQ oJVA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=3C2F9fXKeXttZXZS1fbz2NQjVcwq3ee+jAJZxVmE/Is=; b=Uwh/ByNh79s6oIaCvbHJX3kKkNUnTTG52vJfY00Xo8zWM0FjVB2unsh9MENONiDuIq CctJ4ROkddU5r47JTwaMTWw3Le8wFF6aJawsOvLtq6SP+4Gc7UqmsFbMy03FD06FEvnP v27xNvyzTc8wpWNGe1RUXZkDk0Bchi/RYtbUrxczb3nq3cPin0UQo5KquU+Eqi/68YMG wffqUWn4BhsK9UYbFXm1YIVr3E6xf/RILjLr8wiJmd9/d5gSYxI0jvmpBkG5QgD8Ql+9 45KP7e2nuIzWwNSMVrgTVvQ6STI29n3v+U216wejUtQu0JsERFS7VKYx5bDihcplWnEj 0raA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id t11si1430574itb.34.2019.05.14.05.23.12 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 14 May 2019 05:23:13 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hQWRq-0000Qj-EL; Tue, 14 May 2019 12:22:22 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hQWRp-0000ON-Ac for xen-devel@lists.xenproject.org; Tue, 14 May 2019 12:22:21 +0000 X-Inumbo-ID: eb70a43d-7642-11e9-8980-bc764e045a96 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id eb70a43d-7642-11e9-8980-bc764e045a96; Tue, 14 May 2019 12:22:20 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 058D315BE; Tue, 14 May 2019 05:22:20 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C61B73F71E; Tue, 14 May 2019 05:22:18 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Tue, 14 May 2019 13:21:34 +0100 Message-Id: <20190514122136.28215-26-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190514122136.28215-1-julien.grall@arm.com> References: <20190514122136.28215-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH MM-PART2 v2 17/19] xen/arm: mm: Initialize page-tables earlier X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Oleksandr_Tyshchenko@epam.com, Julien Grall , Stefano Stabellini , Andrii Anisov MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Since commit f60658c6ae "xen/arm: Stop relocating Xen", the function setup_page_tables() does not require any information from the FDT. So the initialization of the page-tables can be done much earlier in the boot process. The earliest setup_page_tables() can be called is after traps have been initialized, so we can get backtrace if an error occurred. Moving the initialization of the page-tables also avoid the dance to map the FDT again in the new set of page-tables. Signed-off-by: Julien Grall Reviewed-by: Andrii Anisov --- Changes in v2: - Add Andrii's reviewed-by --- xen/arch/arm/mm.c | 12 +++--------- xen/arch/arm/setup.c | 4 ++-- 2 files changed, 5 insertions(+), 11 deletions(-) diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c index 7502a14760..eacc1647e0 100644 --- a/xen/arch/arm/mm.c +++ b/xen/arch/arm/mm.c @@ -550,7 +550,7 @@ static inline lpae_t pte_of_xenaddr(vaddr_t va) return mfn_to_xen_entry(maddr_to_mfn(ma), MT_NORMAL); } -/* Map the FDT in the early boot page table */ +/* Map the FDT in the runtime page table */ void * __init early_fdt_map(paddr_t fdt_paddr) { /* We are using 2MB superpage for mapping the FDT */ @@ -573,7 +573,7 @@ void * __init early_fdt_map(paddr_t fdt_paddr) /* The FDT is mapped using 2MB superpage */ BUILD_BUG_ON(BOOT_FDT_VIRT_START % SZ_2M); - create_mappings(boot_second, BOOT_FDT_VIRT_START, paddr_to_pfn(base_paddr), + create_mappings(xen_second, BOOT_FDT_VIRT_START, paddr_to_pfn(base_paddr), SZ_2M >> PAGE_SHIFT, SZ_2M); offset = fdt_paddr % SECOND_SIZE; @@ -588,7 +588,7 @@ void * __init early_fdt_map(paddr_t fdt_paddr) if ( (offset + size) > SZ_2M ) { - create_mappings(boot_second, BOOT_FDT_VIRT_START + SZ_2M, + create_mappings(xen_second, BOOT_FDT_VIRT_START + SZ_2M, paddr_to_pfn(base_paddr + SZ_2M), SZ_2M >> PAGE_SHIFT, SZ_2M); } @@ -699,12 +699,6 @@ void __init setup_pagetables(unsigned long boot_phys_offset) pte.pt.table = 1; xen_second[second_table_offset(FIXMAP_ADDR(0))] = pte; - /* ... DTB */ - pte = boot_second[second_table_offset(BOOT_FDT_VIRT_START)]; - xen_second[second_table_offset(BOOT_FDT_VIRT_START)] = pte; - pte = boot_second[second_table_offset(BOOT_FDT_VIRT_START + SZ_2M)]; - xen_second[second_table_offset(BOOT_FDT_VIRT_START + SZ_2M)] = pte; - #ifdef CONFIG_ARM_64 ttbr = (uintptr_t) xen_pgtable + phys_offset; #else diff --git a/xen/arch/arm/setup.c b/xen/arch/arm/setup.c index 2f714d8b37..889da40d8d 100644 --- a/xen/arch/arm/setup.c +++ b/xen/arch/arm/setup.c @@ -759,6 +759,8 @@ void __init start_xen(unsigned long boot_phys_offset, /* Initialize traps early allow us to get backtrace when an error occurred */ init_traps(); + setup_pagetables(boot_phys_offset); + smp_clear_cpu_maps(); device_tree_flattened = early_fdt_map(fdt_paddr); @@ -780,8 +782,6 @@ void __init start_xen(unsigned long boot_phys_offset, (paddr_t)(uintptr_t)(_end - _start + 1), false); BUG_ON(!xen_bootmodule); - setup_pagetables(boot_phys_offset); - setup_mm(fdt_paddr, fdt_size); /* Parse the ACPI tables for possible boot-time configuration */ From patchwork Tue May 14 12:21:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 164165 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp2552369ili; Tue, 14 May 2019 05:23:22 -0700 (PDT) X-Google-Smtp-Source: APXvYqz2d6XE04JbP3dymATndl1Rak41fvm/S0x7i9J3I/hfp02kfOAayZ2vsFUeSf1mMwELZb8h X-Received: by 2002:a24:320c:: with SMTP id j12mr2974121ita.131.1557836602419; Tue, 14 May 2019 05:23:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1557836602; cv=none; d=google.com; s=arc-20160816; b=Q9z9UtxdpEyhJV6R9WU66/V6JviXuTN0CY0DRFxxM/L6xFSVMbG9pvRTL2VgZkGz+2 2ox8Hs0SiH6PtzZm8fKEOHWv8a0KjxeSnjHg93a+uoOW6Kck2qth/HGlMblxtxuoUpHk je2A90PJk0dQXTbEywHoZTF83zF8C0M+O1yod59Nd2dzjLJh1lqvrnhXsfgwBUi1iKA3 4AmTzYGfVUX28amiAUvLiRFwpTmfoccYp9na03kodFa2xgXXQ2gZWWWXb3mWFcIUPBe2 Mg4V3N8ZSvBEcXr/fJ69WlwbyP5Y8od4nw/K7sWTwdakDNZ43iSIgpubUeEhAGWSY3Hr kphQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=Py+BjY5hw5qju9cux+1+KLgu52CoNyXrmrwH3H0tjNE=; b=n/IS/Qo/ISoTGoZYABkb5zBMka4K3bpz+PKL5Tq5yoOALPJVDAuYCyRv15ZKZ2+W9E wFafErmKUuajpss4nzhKKAlPmaq00u24NfnkXxi1I9VR5MhqiQOJwnuXJ2cIfPmox/Ma VTGSJb/sL2ADPqWgZQgKCXOG3SwYkiX0J46K7zIf6lRZxwpxLflvQTzj/yoDxmgafeeE XgmUlBSZFmHS+zpIbNjEmzZRBOVhWcop4uzszwYBe3vtv0+cPhdUTw0HsGcSkgy0JLac UoqUvz3Qq7VuPAiX/+oTX5SogNLPc1anG2I5ISglu3mKEoazGP/ZQkn+jE0hM4tNQpLk xkHQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id 72si485307itk.58.2019.05.14.05.23.22 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 14 May 2019 05:23:22 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hQWRs-0000UG-5I; Tue, 14 May 2019 12:22:24 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hQWRr-0000TC-KV for xen-devel@lists.xenproject.org; Tue, 14 May 2019 12:22:23 +0000 X-Inumbo-ID: ec586b83-7642-11e9-8980-bc764e045a96 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id ec586b83-7642-11e9-8980-bc764e045a96; Tue, 14 May 2019 12:22:21 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 771E8341; Tue, 14 May 2019 05:22:21 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 43BD43F71E; Tue, 14 May 2019 05:22:20 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Tue, 14 May 2019 13:21:35 +0100 Message-Id: <20190514122136.28215-27-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190514122136.28215-1-julien.grall@arm.com> References: <20190514122136.28215-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH MM-PART2 v2 18/19] xen/arm: mm: Check start is always before end in {destroy, modify}_xen_mappings X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Oleksandr_Tyshchenko@epam.com, Julien Grall , Stefano Stabellini , Andrii Anisov MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The two helpers {destroy, modify}_xen_mappings don't check that the start is always before the end. This should never happen but if it happens, it will result to unexpected behavior. Catch such issues earlier on by adding an ASSERT in destroy_xen_mappings and modify_xen_mappings. Signed-off-by: Julien Grall Reviewed-by: Andrii Anisov --- Changes in v2: - Add Andrii's reviewed-by --- xen/arch/arm/mm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c index eacc1647e0..b408de7c75 100644 --- a/xen/arch/arm/mm.c +++ b/xen/arch/arm/mm.c @@ -1077,11 +1077,13 @@ int populate_pt_range(unsigned long virt, unsigned long nr_mfns) int destroy_xen_mappings(unsigned long v, unsigned long e) { + ASSERT(v <= e); return create_xen_entries(REMOVE, v, INVALID_MFN, (e - v) >> PAGE_SHIFT, 0); } int modify_xen_mappings(unsigned long s, unsigned long e, unsigned int flags) { + ASSERT(s <= e); return create_xen_entries(MODIFY, s, INVALID_MFN, (e - s) >> PAGE_SHIFT, flags); } From patchwork Tue May 14 12:21:36 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 164163 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp2552327ili; Tue, 14 May 2019 05:23:20 -0700 (PDT) X-Google-Smtp-Source: APXvYqyvFkPbEFE3TZL42XxxG/+XPZFRXPcI9qy/mSAubjSZzNJdDZCLgCnIl6UahRQuEoUAH76j X-Received: by 2002:a24:a943:: with SMTP id x3mr569598iti.64.1557836600243; Tue, 14 May 2019 05:23:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1557836600; cv=none; d=google.com; s=arc-20160816; b=A7k78uHvd7U55HSOa8Bk6LSdfi/7nDkYN+B1vgj0m8wVYwxHkhhYAC9sv6sG1SqCi0 Wra7Eb9mWPExlxzmX1yhW+YRirK005ccJZB6NefT7psyrpqJFihRBP9EDBPst494Jbpa 7JejcKHOE5d4a+VLvqOzfAdN2nkGJaqHHUYKXTAndNe44VH6JMePRmseZS/Qi056jvsr m0oNno8OohWX1d+URSwWH3GO3/DhCuMfwv4vqgCmA+EWZOpOe94A6fphEvtDZ8YAXtKx hWDl5c4HcSMAvS9NRrWqCiYgY6oO9LvGuxrNu9EREO7bxuioFvCn04mUYJ5f+eDz8+uW rjmQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=L8D+cxzqu/amENytuourTm5F3hxNZ5GypY+mx9yb+18=; b=rF9dz8sMNsDtDBrbkwzVQVkiKc36gaS/oMaOKuWEWJ9Sy/tZzGLRH5NN9FaEitSrEK iHpkUb0t6a85am/1cObS6Q0U2U9NhNmrWxYhFGOMCeMdNA09yvfKEAYwnFFWUi3QjI7F F5SJc/EGq/H4gCGSKY7pA85qFCTaLKN8uJAVI9DG6bsOjOeiu8eL1i5W1XEOfwn3/PI9 2DXsvaOyl14TQ8VjsqCcGFyutBBP2IEQZjpQH0VKstkqiIG4z+bd4Fr7MHJvs1aEvUip XgQdJgjzlWq7qxwhfOUAgq3jnMjOY6AJnwkwkKFfy1Wl9EJZWCSTZo4TJ2uj/3ZPbUsM Cy9g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id a188si1422353itc.68.2019.05.14.05.23.20 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 14 May 2019 05:23:20 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hQWRu-0000Yi-9I; Tue, 14 May 2019 12:22:26 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hQWRs-0000UE-65 for xen-devel@lists.xenproject.org; Tue, 14 May 2019 12:22:24 +0000 X-Inumbo-ID: ed3274ae-7642-11e9-9bd8-af6c598e80cf Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTP id ed3274ae-7642-11e9-9bd8-af6c598e80cf; Tue, 14 May 2019 12:22:23 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E887015AB; Tue, 14 May 2019 05:22:22 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B538B3F71E; Tue, 14 May 2019 05:22:21 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Tue, 14 May 2019 13:21:36 +0100 Message-Id: <20190514122136.28215-28-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190514122136.28215-1-julien.grall@arm.com> References: <20190514122136.28215-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH MM-PART2 v2 19/19] xen/arm: Pair call to set_fixmap with call to clear_fixmap in copy_from_paddr X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Oleksandr_Tyshchenko@epam.com, Julien Grall , Stefano Stabellini , Andrii Anisov MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" At the moment, set_fixmap may replace a valid entry without following the break-before-make sequence. This may result to TLB conflict abort. Rather than dealing with Break-Before-Make in set_fixmap, every call to set_fixmap is paired with a call to clear_fixmap. Signed-off-by: Julien Grall Reviewed-by: Andrii Anisov --- Changes in v2: - Add Andrii's reviewed-by --- xen/arch/arm/kernel.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/xen/arch/arm/kernel.c b/xen/arch/arm/kernel.c index e3ffdb2fa1..389bef2afa 100644 --- a/xen/arch/arm/kernel.c +++ b/xen/arch/arm/kernel.c @@ -58,13 +58,12 @@ void __init copy_from_paddr(void *dst, paddr_t paddr, unsigned long len) set_fixmap(FIXMAP_MISC, maddr_to_mfn(paddr), PAGE_HYPERVISOR_WC); memcpy(dst, src + s, l); clean_dcache_va_range(dst, l); + clear_fixmap(FIXMAP_MISC); paddr += l; dst += l; len -= l; } - - clear_fixmap(FIXMAP_MISC); } static void __init place_modules(struct kernel_info *info,