From patchwork Tue May 21 06:16:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 164684 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp1210637ili; Mon, 20 May 2019 23:18:17 -0700 (PDT) X-Google-Smtp-Source: APXvYqy7wPzt4qVGQ59vTaDjpqkhLScynxlXZKewnVANWPCzgVEL+cz+nMD3Ahg7rgD/DkL2fl7o X-Received: by 2002:a17:902:2e81:: with SMTP id r1mr64656812plb.0.1558419497600; Mon, 20 May 2019 23:18:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1558419497; cv=none; d=google.com; s=arc-20160816; b=Kd25FdmAT3OdnHB9obEEcrV9BDtFZDUHKrAIoWa/t7C1V0g+53QL34FTtRYAI55MfR YwDU57LcRLuDAI7sh+jSVE/oPINLpsN7uWSY/972Oy3WKukKSpHFQtf7W9i7UaBR4d3k vhd7JcPP2uD3j3O4PWRu3Yg0ZS2/4kPdBss5IC3iEGB7nPH2Z/f6rsE1CpUtszmfaPyG brjB+RA1r5ksekAJ431wIADCAjql5vL7o3M6803KKCexcyMr0MOtGeiNIo/uUNtWFdzP SotpbbMhilixreq3R7IS3qRjeMzJPmwfq6S2V4foOrWGUKyVg+jgVRT+klffehxQGdA5 qgGA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from :dkim-signature:dkim-filter; bh=XrIYM7aPLD1wF9IwpTW/Z8OCfZUnOmtJFdrupyPx8Jg=; b=ZsW9Zr6ZpyKLHvYSrrWHyCnuReDwnZoTlVlm/kZaPOWCZIcLzxBC6wyBenL2VinF2W 8BkewHJUzldOMLkeoc7zC6pXoZ4nZuFZd17PRQpRT3S2Q/Y2QhQ9nAWni+ZQAIsTZj9K Behd22YBVYSYwChxNphMrQoptqOw70dHC1nWzGYg1mBfviISgss1SXt6SQjJRTzWjRf8 F/NSTYYNRNAV9IdwrNum4n7SAcDrf9J1EB/j7lGR+V7uSnp5P+iN/itfUtdLTGY4jx9S WhIed1StFS1wk+MGXkLZF46lZtRNkNn54HAFMEO7gPdHvn/rvOLaO0Yfzab48RfBLYxg tJvA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=qRhjmuYx; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id v29si13017759pgc.64.2019.05.20.23.18.17; Mon, 20 May 2019 23:18:17 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=qRhjmuYx; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727966AbfEUGSQ (ORCPT + 30 others); Tue, 21 May 2019 02:18:16 -0400 Received: from conuserg-10.nifty.com ([210.131.2.77]:50479 "EHLO conuserg-10.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726344AbfEUGSQ (ORCPT ); Tue, 21 May 2019 02:18:16 -0400 Received: from localhost.localdomain (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-10.nifty.com with ESMTP id x4L6H3Aj032461; Tue, 21 May 2019 15:17:03 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-10.nifty.com x4L6H3Aj032461 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1558419423; bh=XrIYM7aPLD1wF9IwpTW/Z8OCfZUnOmtJFdrupyPx8Jg=; h=From:To:Cc:Subject:Date:From; b=qRhjmuYxD1rELM9hqEW562/6ESLP8dewpyu3CRkbpHWF/HyEsjx4CGe5Z9rn8qLQ+ gboSm5Et1KAj3cRJMaRBFPSH4UA7AkbxWqvj495Ob5JkS8H/a9sJA494+KEZvTfxoh 3INjo03cOlwI6gYC0amArPqePIVHH8CDPPZEYRd8Gt/aS+niGNLLi2HBOly8hnGu9L XquUKHIO435JOzS08erKhaVC/V3+jc5FuO/Tf6AB8rEd15ACMZuObKOyldeDbk4Fas TyuVWDZrd55cnf86Y+vvNrnQ7cM0OsEo9jy9RD4igjtuKvrN/FgYG+TOTMjMz50Hdz /zHMLg0X9EnQA== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: linuxppc-dev@lists.ozlabs.org, Michael Ellerman Cc: Masahiro Yamada , Paul Mackerras , Benjamin Herrenschmidt , linux-kernel@vger.kernel.org Subject: [PATCH] powerpc/mm: mark more tlb functions as __always_inline Date: Tue, 21 May 2019 15:16:59 +0900 Message-Id: <20190521061659.6073-1-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.17.1 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org With CONFIG_OPTIMIZE_INLINING enabled, Laura Abbott reported error with gcc 9.1.1: arch/powerpc/mm/book3s64/radix_tlb.c: In function '_tlbiel_pid': arch/powerpc/mm/book3s64/radix_tlb.c:104:2: warning: asm operand 3 probably doesn't match constraints 104 | asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1) | ^~~ arch/powerpc/mm/book3s64/radix_tlb.c:104:2: error: impossible constraint in 'asm' Fixing _tlbiel_pid() is enough to address the warning above, but I inlined more functions to fix all potential issues. To meet the 'i' (immediate) constraint for the asm operands, functions propagating propagated 'ric' must be always inlined. Fixes: 9012d011660e ("compiler: allow all arches to enable CONFIG_OPTIMIZE_INLINING") Reported-by: Laura Abbott Signed-off-by: Masahiro Yamada --- arch/powerpc/mm/book3s64/hash_native.c | 8 +++-- arch/powerpc/mm/book3s64/radix_tlb.c | 44 +++++++++++++++----------- 2 files changed, 30 insertions(+), 22 deletions(-) -- 2.17.1 diff --git a/arch/powerpc/mm/book3s64/hash_native.c b/arch/powerpc/mm/book3s64/hash_native.c index aaa28fd918fe..bc2c35c0d2b1 100644 --- a/arch/powerpc/mm/book3s64/hash_native.c +++ b/arch/powerpc/mm/book3s64/hash_native.c @@ -60,9 +60,11 @@ static inline void tlbiel_hash_set_isa206(unsigned int set, unsigned int is) * tlbiel instruction for hash, set invalidation * i.e., r=1 and is=01 or is=10 or is=11 */ -static inline void tlbiel_hash_set_isa300(unsigned int set, unsigned int is, - unsigned int pid, - unsigned int ric, unsigned int prs) +static __always_inline void tlbiel_hash_set_isa300(unsigned int set, + unsigned int is, + unsigned int pid, + unsigned int ric, + unsigned int prs) { unsigned long rb; unsigned long rs; diff --git a/arch/powerpc/mm/book3s64/radix_tlb.c b/arch/powerpc/mm/book3s64/radix_tlb.c index 4d841369399f..91c4242c1be3 100644 --- a/arch/powerpc/mm/book3s64/radix_tlb.c +++ b/arch/powerpc/mm/book3s64/radix_tlb.c @@ -29,9 +29,11 @@ * tlbiel instruction for radix, set invalidation * i.e., r=1 and is=01 or is=10 or is=11 */ -static inline void tlbiel_radix_set_isa300(unsigned int set, unsigned int is, - unsigned int pid, - unsigned int ric, unsigned int prs) +static __always_inline void tlbiel_radix_set_isa300(unsigned int set, + unsigned int is, + unsigned int pid, + unsigned int ric, + unsigned int prs) { unsigned long rb; unsigned long rs; @@ -150,8 +152,8 @@ static __always_inline void __tlbie_lpid(unsigned long lpid, unsigned long ric) trace_tlbie(lpid, 0, rb, rs, ric, prs, r); } -static inline void __tlbiel_lpid_guest(unsigned long lpid, int set, - unsigned long ric) +static __always_inline void __tlbiel_lpid_guest(unsigned long lpid, int set, + unsigned long ric) { unsigned long rb,rs,prs,r; @@ -167,8 +169,8 @@ static inline void __tlbiel_lpid_guest(unsigned long lpid, int set, } -static inline void __tlbiel_va(unsigned long va, unsigned long pid, - unsigned long ap, unsigned long ric) +static __always_inline void __tlbiel_va(unsigned long va, unsigned long pid, + unsigned long ap, unsigned long ric) { unsigned long rb,rs,prs,r; @@ -183,8 +185,8 @@ static inline void __tlbiel_va(unsigned long va, unsigned long pid, trace_tlbie(0, 1, rb, rs, ric, prs, r); } -static inline void __tlbie_va(unsigned long va, unsigned long pid, - unsigned long ap, unsigned long ric) +static __always_inline void __tlbie_va(unsigned long va, unsigned long pid, + unsigned long ap, unsigned long ric) { unsigned long rb,rs,prs,r; @@ -199,8 +201,10 @@ static inline void __tlbie_va(unsigned long va, unsigned long pid, trace_tlbie(0, 0, rb, rs, ric, prs, r); } -static inline void __tlbie_lpid_va(unsigned long va, unsigned long lpid, - unsigned long ap, unsigned long ric) +static __always_inline void __tlbie_lpid_va(unsigned long va, + unsigned long lpid, + unsigned long ap, + unsigned long ric) { unsigned long rb,rs,prs,r; @@ -239,7 +243,7 @@ static inline void fixup_tlbie_lpid(unsigned long lpid) /* * We use 128 set in radix mode and 256 set in hpt mode. */ -static inline void _tlbiel_pid(unsigned long pid, unsigned long ric) +static __always_inline void _tlbiel_pid(unsigned long pid, unsigned long ric) { int set; @@ -341,7 +345,8 @@ static inline void _tlbie_lpid(unsigned long lpid, unsigned long ric) asm volatile("eieio; tlbsync; ptesync": : :"memory"); } -static inline void _tlbiel_lpid_guest(unsigned long lpid, unsigned long ric) +static __always_inline void _tlbiel_lpid_guest(unsigned long lpid, + unsigned long ric) { int set; @@ -381,8 +386,8 @@ static inline void __tlbiel_va_range(unsigned long start, unsigned long end, __tlbiel_va(addr, pid, ap, RIC_FLUSH_TLB); } -static inline void _tlbiel_va(unsigned long va, unsigned long pid, - unsigned long psize, unsigned long ric) +static __always_inline void _tlbiel_va(unsigned long va, unsigned long pid, + unsigned long psize, unsigned long ric) { unsigned long ap = mmu_get_ap(psize); @@ -413,8 +418,8 @@ static inline void __tlbie_va_range(unsigned long start, unsigned long end, __tlbie_va(addr, pid, ap, RIC_FLUSH_TLB); } -static inline void _tlbie_va(unsigned long va, unsigned long pid, - unsigned long psize, unsigned long ric) +static __always_inline void _tlbie_va(unsigned long va, unsigned long pid, + unsigned long psize, unsigned long ric) { unsigned long ap = mmu_get_ap(psize); @@ -424,8 +429,9 @@ static inline void _tlbie_va(unsigned long va, unsigned long pid, asm volatile("eieio; tlbsync; ptesync": : :"memory"); } -static inline void _tlbie_lpid_va(unsigned long va, unsigned long lpid, - unsigned long psize, unsigned long ric) +static __always_inline void _tlbie_lpid_va(unsigned long va, unsigned long lpid, + unsigned long psize, + unsigned long ric) { unsigned long ap = mmu_get_ap(psize);