From patchwork Mon Jun 3 07:34:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 165583 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp4124962ili; Mon, 3 Jun 2019 00:35:07 -0700 (PDT) X-Google-Smtp-Source: APXvYqx9KpRXBOBfIsYOHqJjX8QoXucIg5Wq2L2YjcFTrvvxJNyaa0jn1c3J1rBkA5FkZRfiTQv0 X-Received: by 2002:a17:902:e2:: with SMTP id a89mr28382100pla.210.1559547307331; Mon, 03 Jun 2019 00:35:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1559547307; cv=none; d=google.com; s=arc-20160816; b=PjgE21FBT+6IDEgrNDgUN3sq/QuFEZTn9jS7dUvzrbuhvSiNvWGjxO9Fv3SfB8hyEv wUxU702ZnMc0k5K2OeYdU26GZi/sGc9subGKJyOdsqP1n2yn+Sf2clFqbR31g1xCdZYG ZMNoAA6+ZaV8NbsUQ8VHYooScBBKhTVRxxXq+3I5UGmSMkavGYYvEYMS1Ee7iNwKVa4Q OVqfl91WNfR8OcR+w1k9/rgmWJuWTNBH5pAYKHyty18zVhDlBQlMxi5GAF+p4vO8nPan iqpnPgLdkqGojw1isbe9gzX7LtIT4Z59pv0skb7GA4bgCJk22/PlbwYOLRRoI5LwVmLg oydA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from :dkim-signature; bh=WeJByq3I424RHBGjH32sFcsG6B+iqGeZ0ID7b3v4bBs=; b=OqnptjjOdnOcBxhWDfBy47rAR3XeSSTFljAihv28c9//6QBb/iONA3FWIfhK9bYvqH M5J5OJXaEasKqiO5VaXNWfD580LX8WPf3D/rxUDUR53wppe0Dx2r6q7Fmd44hpiJMcf7 BlRE6psH4zt9NZxijDnc9YRZengHpeIZx0Cb7nOG5IYgaktbSYHMEjI7tfeQqMO4SPv2 4o73x0b9dkK0NfnLemILxWETIvntE0pkc2rm4wjv/JBaH+h926wg+2i29G47cNcMSsm3 GoVxV8MTgkDHMpySBpjI/jr7djlc51hpQyY4fRDzX1hOvaXnqPBIRzcD8hr80/9/hK8Z QLlg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=enpEKMCr; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id a69si18376819pla.178.2019.06.03.00.35.06; Mon, 03 Jun 2019 00:35:07 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=enpEKMCr; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726369AbfFCHfG (ORCPT + 5 others); Mon, 3 Jun 2019 03:35:06 -0400 Received: from mail-pl1-f194.google.com ([209.85.214.194]:42635 "EHLO mail-pl1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726270AbfFCHfG (ORCPT ); Mon, 3 Jun 2019 03:35:06 -0400 Received: by mail-pl1-f194.google.com with SMTP id go2so6624088plb.9 for ; Mon, 03 Jun 2019 00:35:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=WeJByq3I424RHBGjH32sFcsG6B+iqGeZ0ID7b3v4bBs=; b=enpEKMCrOjQNrqE7jiuWbbNkwP0ud8MaKH14i8OrVQdQkjM6brJwG40pVUfM0RwkKL 68yUG4qsPrqXI0ArlfjwfzSjkInEtjsdwuEpLzFD7D0MCnIrzjmPf6dgC3zWZaaJmwPv h/NbUExPFELpfROE1t7Dotty0yv+AcU7ZYMTzb1s8XITgy/13vWxGI9wDHzD4BiD81J+ simnyIg13cGrzldq0M4tWWC9TyQwrqIW8+pGo127SxZaAGaMY8gdHl5BwNe3RjYRv/bK kyBXyTjAOFMxQSFlNPo5i8qODbxsOZHG7GrrqsU0LqvYW1hldrqVhIW/rE67QlIL5yI9 V+Fw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=WeJByq3I424RHBGjH32sFcsG6B+iqGeZ0ID7b3v4bBs=; b=VpmnKLoeh7kwbBuJWvcDs53VxTnh7/TP0VYzny14NfPXK0W9KN93zQCu++qfN7n2RZ 8i5w75Umf+zYVQ9Ge87iQWQywrqsyrqKZRLm3EefwVfKeDelCEXt2Nw+s3fAKDnT+4Yi FgVPHfpjpfYESrp012e+p2xOW4CODoVClAunNZ/IaJOlE9R8rHEow5WroOKpsyx7WFYh HgVtkIFzajTHGVBeDiE1ySetogXO6+GyiG+rHdarRTfhqESRzFgOU3K8gi8GZS1ZimIA RMOzsAxZ6MKS8uHqgm0wvNCho+48PJJzkaDhi+ceMjcf5OQdyG+G4Jxh+TpXeZwKXEyT PD3Q== X-Gm-Message-State: APjAAAU1Elf4U9eyOCcRrmmSQYGHNp86AGr5Fb/gWyg34i/eM+7jbkVs 3Wp+JASBmXi1o+DfhmlXFPdZ X-Received: by 2002:a17:902:b084:: with SMTP id p4mr29165367plr.59.1559547305839; Mon, 03 Jun 2019 00:35:05 -0700 (PDT) Received: from localhost.localdomain ([2409:4072:716:e714:cd5e:23ab:e451:ee6a]) by smtp.gmail.com with ESMTPSA id r64sm17547366pfr.58.2019.06.03.00.35.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 03 Jun 2019 00:35:05 -0700 (PDT) From: Manivannan Sadhasivam To: linus.walleij@linaro.org, robh+dt@kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, haitao.suo@bitmain.com, darren.tsao@bitmain.com, linux-gpio@vger.kernel.org, alec.lin@bitmain.com, Manivannan Sadhasivam Subject: [PATCH 1/2] dt-bindings: pinctrl: Document drive strength settings for BM1880 SoC Date: Mon, 3 Jun 2019 13:04:20 +0530 Message-Id: <20190603073421.10314-1-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Document drive strength settings for Bitmain BM1880 SoC. Signed-off-by: Manivannan Sadhasivam --- .../bindings/pinctrl/bitmain,bm1880-pinctrl.txt | 11 +++++++++++ 1 file changed, 11 insertions(+) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/pinctrl/bitmain,bm1880-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/bitmain,bm1880-pinctrl.txt index 4eb089bcb5f3..4980776122cc 100644 --- a/Documentation/devicetree/bindings/pinctrl/bitmain,bm1880-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/bitmain,bm1880-pinctrl.txt @@ -100,6 +100,17 @@ Optional Properties: Valid values are: <0> - Slow <1> - Fast +- drive-strength: Integer. Selects the drive strength for the specified + pins in mA. + Valid values are: + <4> + <8> + <12> + <16> + <20> + <24> + <28> + <32> Example: pinctrl: pinctrl@400 { From patchwork Mon Jun 3 07:34:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 165584 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp4125046ili; Mon, 3 Jun 2019 00:35:12 -0700 (PDT) X-Google-Smtp-Source: APXvYqwySjeVf5OUEVuJZgBkjcTxSnUVGsz2cLt8liZ7Hck2QiQqVRT3DHQC232oc1z2LxjvjrJl X-Received: by 2002:a63:e50c:: with SMTP id r12mr26461034pgh.284.1559547312656; Mon, 03 Jun 2019 00:35:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1559547312; cv=none; d=google.com; s=arc-20160816; b=EOs8pe+Od1pRP25BzWxrw2d8EkadGaN2j61g5+EyOH+jnJ5aFIst0R9kPHmSv1XXT6 4/iO64ahCPWaBRHnAVcOgWQO2r7ZyMKJEvTm8sn0d/MvAO0Ouxy8v29lmXnJNZVBbhrH N4sR0fVjRC/lnYWLPMVXZmXmPIp3l+44x3p/DX0B4QAGD9P8leq6Z2abdosS+gqZB/h6 jHU+lYDKvkE0isFPWG6cZHFpBWvNktunRQdElfb8JuphzQKC8pixjAnOifBL49luACIu NhVIZg0l/chVJNfkwAhkAIgPOinhyzFziVazFcPknu2NjFT4XdFGHWksiMiqZ1XOeDcZ GArQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=3QNw8nhaZHDfKLrM0rv9vo2EpHsekryGUP7JjhXswAQ=; b=KpfxzxYbgi/Vi7QwCF/dIrWJq4xxBc678qKAz8F5D37XmqszqzJ2ipAnWNg5WejfYC GaKYWJRoRd42aWBhJi1G9+Vw0319I8RFxPRn444SVg/NJGSBHe9uVncXcysglkh0J+GV Sxgtqk+H9Xc+9xbKjegkx/o9NPQlZtI1PVrLBGjAXHJ5vLDPGCUJlldkE0mBEqfbvqrX ruBX3ecnorYjCL4DK5VtoKj/AFM9xJF+fuyu+WP+aV4MDuJyi3SSYiUC6Bre3jMdQIsy 6c2ryP1jwOIbaGoYB7y5IcQCBgkx78tOUpSEfZHFYzzJc9q+Z7+Y4TmTEIyG3u3QyV8R 8yYQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=llOF4BIu; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Manivannan Sadhasivam --- drivers/pinctrl/pinctrl-bm1880.c | 290 ++++++++++++++++++++++++++++++- 1 file changed, 287 insertions(+), 3 deletions(-) -- 2.17.1 diff --git a/drivers/pinctrl/pinctrl-bm1880.c b/drivers/pinctrl/pinctrl-bm1880.c index 1aaed46d5c30..63b130cb1ffb 100644 --- a/drivers/pinctrl/pinctrl-bm1880.c +++ b/drivers/pinctrl/pinctrl-bm1880.c @@ -4,8 +4,6 @@ * * Copyright (c) 2019 Linaro Ltd. * Author: Manivannan Sadhasivam - * - * TODO: Drive strength support */ #include @@ -29,6 +27,7 @@ * @ngroups: Number of @groups * @funcs: Pinmux functions * @nfuncs: Number of @funcs + * @pconf: Pinconf data */ struct bm1880_pinctrl { void __iomem *base; @@ -37,6 +36,7 @@ struct bm1880_pinctrl { unsigned int ngroups; const struct bm1880_pinmux_function *funcs; unsigned int nfuncs; + const struct bm1880_pinconf_data *pinconf; }; /** @@ -69,6 +69,14 @@ struct bm1880_pinmux_function { u8 mux_shift; }; +/** + * struct bm1880_pinconf_data - pinconf data + * @drv_bits: Drive strength bit width + */ +struct bm1880_pinconf_data { + u32 drv_bits; +}; + static const struct pinctrl_pin_desc bm1880_pins[] = { PINCTRL_PIN(0, "MIO0"), PINCTRL_PIN(1, "MIO1"), @@ -785,6 +793,126 @@ static const struct bm1880_pinmux_function bm1880_pmux_functions[] = { BM1880_PINMUX_FUNCTION(spi0, 1), }; +#define BM1880_PINCONF_DAT(_width) \ + { \ + .drv_bits = _width, \ + } + +static const struct bm1880_pinconf_data bm1880_pinconf[] = { + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x03), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), + BM1880_PINCONF_DAT(0x02), +}; + static int bm1880_pctrl_get_groups_count(struct pinctrl_dev *pctldev) { struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); @@ -878,9 +1006,145 @@ static int bm1880_pinmux_set_mux(struct pinctrl_dev *pctldev, #define BM1880_PINCONF_PULLCTRL(pin) BM1880_PINCONF(pin, 0) #define BM1880_PINCONF_PULLUP(pin) BM1880_PINCONF(pin, 1) #define BM1880_PINCONF_PULLDOWN(pin) BM1880_PINCONF(pin, 2) +#define BM1880_PINCONF_DRV(pin) BM1880_PINCONF(pin, 6) #define BM1880_PINCONF_SCHMITT(pin) BM1880_PINCONF(pin, 9) #define BM1880_PINCONF_SLEW(pin) BM1880_PINCONF(pin, 10) +static int bm1880_pinconf_drv_set(unsigned int mA, u32 width, + u32 *regval, u32 bit_offset) +{ + u32 _regval; + + _regval = *regval; + + /* + * There are two sets of drive strength bit width exposed by the + * SoC at 4mA step, hence we need to handle them separately. + */ + if (width == 0x03) { + switch (mA) { + case 4: + _regval &= ~(width << bit_offset); + _regval |= (0 << bit_offset); + break; + case 8: + _regval &= ~(width << bit_offset); + _regval |= (1 << bit_offset); + break; + case 12: + _regval &= ~(width << bit_offset); + _regval |= (2 << bit_offset); + break; + case 16: + _regval &= ~(width << bit_offset); + _regval |= (3 << bit_offset); + break; + case 20: + _regval &= ~(width << bit_offset); + _regval |= (4 << bit_offset); + break; + case 24: + _regval &= ~(width << bit_offset); + _regval |= (5 << bit_offset); + break; + case 28: + _regval &= ~(width << bit_offset); + _regval |= (6 << bit_offset); + break; + case 32: + _regval &= ~(width << bit_offset); + _regval |= (7 << bit_offset); + break; + default: + return -EINVAL; + } + } else { + switch (mA) { + case 4: + _regval &= ~(width << bit_offset); + _regval |= (0 << bit_offset); + break; + case 8: + _regval &= ~(width << bit_offset); + _regval |= (1 << bit_offset); + break; + case 12: + _regval &= ~(width << bit_offset); + _regval |= (2 << bit_offset); + break; + case 16: + _regval &= ~(width << bit_offset); + _regval |= (3 << bit_offset); + break; + default: + return -EINVAL; + } + } + + *regval = _regval; + + return 0; +} + +static int bm1880_pinconf_drv_get(u32 width, u32 drv) +{ + int ret = -ENOTSUPP; + + /* + * There are two sets of drive strength bit width exposed by the + * SoC at 4mA step, hence we need to handle them separately. + */ + if (width == 0x03) { + switch (drv) { + case 0: + ret = 4; + break; + case 1: + ret = 8; + break; + case 2: + ret = 12; + break; + case 3: + ret = 16; + break; + case 4: + ret = 20; + break; + case 5: + ret = 24; + break; + case 6: + ret = 28; + break; + case 7: + ret = 32; + break; + default: + break; + } + } else { + switch (drv) { + case 0: + ret = 4; + break; + case 1: + ret = 8; + break; + case 2: + ret = 12; + break; + case 3: + ret = 16; + break; + default: + break; + } + } + + return ret; +} + static int bm1880_pinconf_cfg_get(struct pinctrl_dev *pctldev, unsigned int pin, unsigned long *config) @@ -889,6 +1153,7 @@ static int bm1880_pinconf_cfg_get(struct pinctrl_dev *pctldev, unsigned int param = pinconf_to_config_param(*config); unsigned int arg = 0; u32 regval, offset, bit_offset; + int ret; offset = (pin >> 1) << 2; regval = readl_relaxed(pctrl->base + BM1880_REG_MUX + offset); @@ -914,6 +1179,15 @@ static int bm1880_pinconf_cfg_get(struct pinctrl_dev *pctldev, bit_offset = BM1880_PINCONF_SLEW(pin); arg = !!(regval & BIT(bit_offset)); break; + case PIN_CONFIG_DRIVE_STRENGTH: + bit_offset = BM1880_PINCONF_DRV(pin); + ret = bm1880_pinconf_drv_get(pctrl->pinconf[pin].drv_bits, + !!(regval & BIT(bit_offset))); + if (ret < 0) + return ret; + + arg = ret; + break; default: return -ENOTSUPP; } @@ -930,7 +1204,7 @@ static int bm1880_pinconf_cfg_set(struct pinctrl_dev *pctldev, { struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); u32 regval, offset, bit_offset; - int i; + int i, ret; offset = (pin >> 1) << 2; regval = readl_relaxed(pctrl->base + BM1880_REG_MUX + offset); @@ -966,6 +1240,15 @@ static int bm1880_pinconf_cfg_set(struct pinctrl_dev *pctldev, else regval &= ~BIT(bit_offset); break; + case PIN_CONFIG_DRIVE_STRENGTH: + bit_offset = BM1880_PINCONF_DRV(pin); + ret = bm1880_pinconf_drv_set(arg, + pctrl->pinconf[pin].drv_bits, + ®val, bit_offset); + if (ret < 0) + return ret; + + break; default: dev_warn(pctldev->dev, "unsupported configuration parameter '%u'\n", @@ -1041,6 +1324,7 @@ static int bm1880_pinctrl_probe(struct platform_device *pdev) pctrl->ngroups = ARRAY_SIZE(bm1880_pctrl_groups); pctrl->funcs = bm1880_pmux_functions; pctrl->nfuncs = ARRAY_SIZE(bm1880_pmux_functions); + pctrl->pinconf = bm1880_pinconf; pctrl->pctrldev = devm_pinctrl_register(&pdev->dev, &bm1880_desc, pctrl);