From patchwork Wed Apr 26 04:55:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshihiro Shimoda X-Patchwork-Id: 677254 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E0E6EC7EE24 for ; Wed, 26 Apr 2023 04:56:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239416AbjDZE4O (ORCPT ); Wed, 26 Apr 2023 00:56:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40100 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239385AbjDZE4M (ORCPT ); Wed, 26 Apr 2023 00:56:12 -0400 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 0B3D6273C; Tue, 25 Apr 2023 21:56:06 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.99,227,1677510000"; d="scan'208";a="157312770" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 26 Apr 2023 13:56:05 +0900 Received: from localhost.localdomain (unknown [10.166.15.32]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 23FE341763FC; Wed, 26 Apr 2023 13:56:05 +0900 (JST) From: Yoshihiro Shimoda To: jingoohan1@gmail.com, mani@kernel.org, gustavo.pimentel@synopsys.com, fancer.lancer@gmail.com, lpieralisi@kernel.org, robh+dt@kernel.org, kw@linux.com, bhelgaas@google.com, kishon@kernel.org Cc: marek.vasut+renesas@gmail.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Yoshihiro Shimoda Subject: [PATCH v14 02/21] PCI: Add PCI_HEADER_TYPE_MULTI_FUNC Date: Wed, 26 Apr 2023 13:55:38 +0900 Message-Id: <20230426045557.3613826-3-yoshihiro.shimoda.uh@renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230426045557.3613826-1-yoshihiro.shimoda.uh@renesas.com> References: <20230426045557.3613826-1-yoshihiro.shimoda.uh@renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add PCI_HEADER_TYPE_MULTI_FUNC macro which is "Multi-Function Device" of Header Type Register. Signed-off-by: Yoshihiro Shimoda --- drivers/pci/probe.c | 2 +- drivers/pci/quirks.c | 4 ++-- include/uapi/linux/pci_regs.h | 1 + 3 files changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 0b2826c4a832..56f01b48fb81 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -1836,7 +1836,7 @@ int pci_setup_device(struct pci_dev *dev) dev->dev.parent = dev->bus->bridge; dev->dev.bus = &pci_bus_type; dev->hdr_type = hdr_type & 0x7f; - dev->multifunction = !!(hdr_type & 0x80); + dev->multifunction = !!(hdr_type & PCI_HEADER_TYPE_MULTI_FUNC); dev->error_state = pci_channel_io_normal; set_pcie_port_type(dev); diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index f4e2a88729fd..8ceb970ccf1f 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -1750,7 +1750,7 @@ static void quirk_jmicron_ata(struct pci_dev *pdev) /* Update pdev accordingly */ pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr); pdev->hdr_type = hdr & 0x7f; - pdev->multifunction = !!(hdr & 0x80); + pdev->multifunction = !!(hdr & PCI_HEADER_TYPE_MULTI_FUNC); pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class); pdev->class = class >> 8; @@ -5567,7 +5567,7 @@ static void quirk_nvidia_hda(struct pci_dev *gpu) /* The GPU becomes a multi-function device when the HDA is enabled */ pci_read_config_byte(gpu, PCI_HEADER_TYPE, &hdr_type); - gpu->multifunction = !!(hdr_type & 0x80); + gpu->multifunction = !!(hdr_type & PCI_HEADER_TYPE_MULTI_FUNC); } DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY, 16, quirk_nvidia_hda); diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index 5d48413ac28f..a302b67d2834 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -80,6 +80,7 @@ #define PCI_HEADER_TYPE_NORMAL 0 #define PCI_HEADER_TYPE_BRIDGE 1 #define PCI_HEADER_TYPE_CARDBUS 2 +#define PCI_HEADER_TYPE_MULTI_FUNC 0x80 #define PCI_BIST 0x0f /* 8 bits */ #define PCI_BIST_CODE_MASK 0x0f /* Return result */ From patchwork Wed Apr 26 04:55:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshihiro Shimoda X-Patchwork-Id: 677253 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 91DA2C77B78 for ; Wed, 26 Apr 2023 04:56:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239417AbjDZE4T (ORCPT ); Wed, 26 Apr 2023 00:56:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40114 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239413AbjDZE4N (ORCPT ); Wed, 26 Apr 2023 00:56:13 -0400 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 385022D5E; Tue, 25 Apr 2023 21:56:07 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.99,227,1677510000"; d="scan'208";a="160778507" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 26 Apr 2023 13:56:05 +0900 Received: from localhost.localdomain (unknown [10.166.15.32]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 6B8874175EC6; Wed, 26 Apr 2023 13:56:05 +0900 (JST) From: Yoshihiro Shimoda To: jingoohan1@gmail.com, mani@kernel.org, gustavo.pimentel@synopsys.com, fancer.lancer@gmail.com, lpieralisi@kernel.org, robh+dt@kernel.org, kw@linux.com, bhelgaas@google.com, kishon@kernel.org Cc: marek.vasut+renesas@gmail.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Yoshihiro Shimoda , Bjorn Helgaas , Tom Joseph , Vignesh Raghavendra , Richard Zhu , Lucas Stach , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Minghuan Lian , Mingkai Hu , Roy Zang , Srikanth Thokala , Thierry Reding , Jonathan Hunter , Kunihiko Hayashi , Masami Hiramatsu , Shawn Lin , Heiko Stuebner , Jesper Nilsson Subject: [PATCH v14 04/21] PCI: Rename PCI_EPC_IRQ_LEGACY to PCI_EPC_IRQ_INTX Date: Wed, 26 Apr 2023 13:55:40 +0900 Message-Id: <20230426045557.3613826-5-yoshihiro.shimoda.uh@renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230426045557.3613826-1-yoshihiro.shimoda.uh@renesas.com> References: <20230426045557.3613826-1-yoshihiro.shimoda.uh@renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Using "INTx" instead of "legacy" is more specific. So, rename PCI_EPC_IRQ_LEGACY to PCI_EPC_IRQ_INTX. Suggested-by: Bjorn Helgaas Signed-off-by: Yoshihiro Shimoda Cc: Tom Joseph Cc: Vignesh Raghavendra Cc: Richard Zhu Cc: Lucas Stach Cc: Shawn Guo Cc: Sascha Hauer Cc: Pengutronix Kernel Team Cc: Fabio Estevam Cc: NXP Linux Team Cc: Minghuan Lian Cc: Mingkai Hu Cc: Roy Zang Cc: Jingoo Han Cc: Serge Semin Cc: Srikanth Thokala Cc: Thierry Reding Cc: Jonathan Hunter Cc: Kunihiko Hayashi Cc: Masami Hiramatsu Cc: Marek Vasut Cc: Shawn Lin Cc: Heiko Stuebner Cc: Kishon Vijay Abraham I Reviewed-by: Manivannan Sadhasivam Acked-by: Jesper Nilsson # ARTPEC Reviewed-by: Serge Semin --- drivers/pci/controller/cadence/pcie-cadence-ep.c | 2 +- drivers/pci/controller/dwc/pci-dra7xx.c | 2 +- drivers/pci/controller/dwc/pci-imx6.c | 2 +- drivers/pci/controller/dwc/pci-keystone.c | 2 +- drivers/pci/controller/dwc/pci-layerscape-ep.c | 2 +- drivers/pci/controller/dwc/pcie-artpec6.c | 2 +- drivers/pci/controller/dwc/pcie-designware-plat.c | 2 +- drivers/pci/controller/dwc/pcie-keembay.c | 2 +- drivers/pci/controller/dwc/pcie-qcom-ep.c | 2 +- drivers/pci/controller/dwc/pcie-tegra194.c | 2 +- drivers/pci/controller/dwc/pcie-uniphier-ep.c | 2 +- drivers/pci/controller/pcie-rcar-ep.c | 2 +- drivers/pci/controller/pcie-rockchip-ep.c | 2 +- drivers/pci/endpoint/functions/pci-epf-test.c | 12 ++++++------ include/linux/pci-epc.h | 4 ++-- 15 files changed, 21 insertions(+), 21 deletions(-) diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep.c b/drivers/pci/controller/cadence/pcie-cadence-ep.c index b8b655d4047e..2af8eb4e6d91 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-ep.c +++ b/drivers/pci/controller/cadence/pcie-cadence-ep.c @@ -539,7 +539,7 @@ static int cdns_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn, u8 vfn, struct device *dev = pcie->dev; switch (type) { - case PCI_EPC_IRQ_LEGACY: + case PCI_EPC_IRQ_INTX: if (vfn > 0) { dev_err(dev, "Cannot raise legacy interrupts for VF\n"); return -EINVAL; diff --git a/drivers/pci/controller/dwc/pci-dra7xx.c b/drivers/pci/controller/dwc/pci-dra7xx.c index 4ae807e7cf79..b42fb1cc8bc8 100644 --- a/drivers/pci/controller/dwc/pci-dra7xx.c +++ b/drivers/pci/controller/dwc/pci-dra7xx.c @@ -410,7 +410,7 @@ static int dra7xx_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no, struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci); switch (type) { - case PCI_EPC_IRQ_LEGACY: + case PCI_EPC_IRQ_INTX: dra7xx_pcie_raise_legacy_irq(dra7xx); break; case PCI_EPC_IRQ_MSI: diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 52906f999f2b..1f39e733ce19 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -1062,7 +1062,7 @@ static int imx6_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no, struct dw_pcie *pci = to_dw_pcie_from_ep(ep); switch (type) { - case PCI_EPC_IRQ_LEGACY: + case PCI_EPC_IRQ_INTX: return dw_pcie_ep_raise_legacy_irq(ep, func_no); case PCI_EPC_IRQ_MSI: return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num); diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 78818853af9e..3806f5530937 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -908,7 +908,7 @@ static int ks_pcie_am654_raise_irq(struct dw_pcie_ep *ep, u8 func_no, struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); switch (type) { - case PCI_EPC_IRQ_LEGACY: + case PCI_EPC_IRQ_INTX: ks_pcie_am654_raise_legacy_irq(ks_pcie); break; case PCI_EPC_IRQ_MSI: diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/controller/dwc/pci-layerscape-ep.c index c640db60edc6..ab3306e206d8 100644 --- a/drivers/pci/controller/dwc/pci-layerscape-ep.c +++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c @@ -65,7 +65,7 @@ static int ls_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no, struct dw_pcie *pci = to_dw_pcie_from_ep(ep); switch (type) { - case PCI_EPC_IRQ_LEGACY: + case PCI_EPC_IRQ_INTX: return dw_pcie_ep_raise_legacy_irq(ep, func_no); case PCI_EPC_IRQ_MSI: return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num); diff --git a/drivers/pci/controller/dwc/pcie-artpec6.c b/drivers/pci/controller/dwc/pcie-artpec6.c index 98102079e26d..128cb1118e3a 100644 --- a/drivers/pci/controller/dwc/pcie-artpec6.c +++ b/drivers/pci/controller/dwc/pcie-artpec6.c @@ -357,7 +357,7 @@ static int artpec6_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no, struct dw_pcie *pci = to_dw_pcie_from_ep(ep); switch (type) { - case PCI_EPC_IRQ_LEGACY: + case PCI_EPC_IRQ_INTX: dev_err(pci->dev, "EP cannot trigger legacy IRQs\n"); return -EINVAL; case PCI_EPC_IRQ_MSI: diff --git a/drivers/pci/controller/dwc/pcie-designware-plat.c b/drivers/pci/controller/dwc/pcie-designware-plat.c index 1fcfb840f238..fc3b02949218 100644 --- a/drivers/pci/controller/dwc/pcie-designware-plat.c +++ b/drivers/pci/controller/dwc/pcie-designware-plat.c @@ -48,7 +48,7 @@ static int dw_plat_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no, struct dw_pcie *pci = to_dw_pcie_from_ep(ep); switch (type) { - case PCI_EPC_IRQ_LEGACY: + case PCI_EPC_IRQ_INTX: return dw_pcie_ep_raise_legacy_irq(ep, func_no); case PCI_EPC_IRQ_MSI: return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num); diff --git a/drivers/pci/controller/dwc/pcie-keembay.c b/drivers/pci/controller/dwc/pcie-keembay.c index f90f36bac018..ceb940b327cb 100644 --- a/drivers/pci/controller/dwc/pcie-keembay.c +++ b/drivers/pci/controller/dwc/pcie-keembay.c @@ -290,7 +290,7 @@ static int keembay_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no, struct dw_pcie *pci = to_dw_pcie_from_ep(ep); switch (type) { - case PCI_EPC_IRQ_LEGACY: + case PCI_EPC_IRQ_INTX: /* Legacy interrupts are not supported in Keem Bay */ dev_err(pci->dev, "Legacy IRQ is not supported\n"); return -EINVAL; diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index 19b32839ea26..077afce48d0b 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -658,7 +658,7 @@ static int qcom_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no, struct dw_pcie *pci = to_dw_pcie_from_ep(ep); switch (type) { - case PCI_EPC_IRQ_LEGACY: + case PCI_EPC_IRQ_INTX: return dw_pcie_ep_raise_legacy_irq(ep, func_no); case PCI_EPC_IRQ_MSI: return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num); diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 09825b4a075e..4adba379b83d 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -1980,7 +1980,7 @@ static int tegra_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no, struct tegra_pcie_dw *pcie = to_tegra_pcie(pci); switch (type) { - case PCI_EPC_IRQ_LEGACY: + case PCI_EPC_IRQ_INTX: return tegra_pcie_ep_raise_legacy_irq(pcie, interrupt_num); case PCI_EPC_IRQ_MSI: diff --git a/drivers/pci/controller/dwc/pcie-uniphier-ep.c b/drivers/pci/controller/dwc/pcie-uniphier-ep.c index 4d0a587c0ba5..7787eedf87f4 100644 --- a/drivers/pci/controller/dwc/pcie-uniphier-ep.c +++ b/drivers/pci/controller/dwc/pcie-uniphier-ep.c @@ -262,7 +262,7 @@ static int uniphier_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no, struct dw_pcie *pci = to_dw_pcie_from_ep(ep); switch (type) { - case PCI_EPC_IRQ_LEGACY: + case PCI_EPC_IRQ_INTX: return uniphier_pcie_ep_raise_legacy_irq(ep); case PCI_EPC_IRQ_MSI: return uniphier_pcie_ep_raise_msi_irq(ep, func_no, diff --git a/drivers/pci/controller/pcie-rcar-ep.c b/drivers/pci/controller/pcie-rcar-ep.c index f9682df1da61..fbdf3d85301c 100644 --- a/drivers/pci/controller/pcie-rcar-ep.c +++ b/drivers/pci/controller/pcie-rcar-ep.c @@ -408,7 +408,7 @@ static int rcar_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn, u8 vfn, struct rcar_pcie_endpoint *ep = epc_get_drvdata(epc); switch (type) { - case PCI_EPC_IRQ_LEGACY: + case PCI_EPC_IRQ_INTX: return rcar_pcie_ep_assert_intx(ep, fn, 0); case PCI_EPC_IRQ_MSI: diff --git a/drivers/pci/controller/pcie-rockchip-ep.c b/drivers/pci/controller/pcie-rockchip-ep.c index d1a200b93b2b..ef9d1f6c382a 100644 --- a/drivers/pci/controller/pcie-rockchip-ep.c +++ b/drivers/pci/controller/pcie-rockchip-ep.c @@ -477,7 +477,7 @@ static int rockchip_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn, u8 vfn, struct rockchip_pcie_ep *ep = epc_get_drvdata(epc); switch (type) { - case PCI_EPC_IRQ_LEGACY: + case PCI_EPC_IRQ_INTX: return rockchip_pcie_ep_send_legacy_irq(ep, fn, 0); case PCI_EPC_IRQ_MSI: return rockchip_pcie_ep_send_msi_irq(ep, fn, interrupt_num); diff --git a/drivers/pci/endpoint/functions/pci-epf-test.c b/drivers/pci/endpoint/functions/pci-epf-test.c index 172e5ac0bd96..36a2a8120653 100644 --- a/drivers/pci/endpoint/functions/pci-epf-test.c +++ b/drivers/pci/endpoint/functions/pci-epf-test.c @@ -19,11 +19,11 @@ #include #include -#define IRQ_TYPE_LEGACY 0 +#define IRQ_TYPE_INTX 0 #define IRQ_TYPE_MSI 1 #define IRQ_TYPE_MSIX 2 -#define COMMAND_RAISE_LEGACY_IRQ BIT(0) +#define COMMAND_RAISE_INTX_IRQ BIT(0) #define COMMAND_RAISE_MSI_IRQ BIT(1) #define COMMAND_RAISE_MSIX_IRQ BIT(2) #define COMMAND_READ BIT(3) @@ -606,9 +606,9 @@ static void pci_epf_test_raise_irq(struct pci_epf_test *epf_test, u8 irq_type, reg->status |= STATUS_IRQ_RAISED; switch (irq_type) { - case IRQ_TYPE_LEGACY: + case IRQ_TYPE_INTX: pci_epc_raise_irq(epc, epf->func_no, epf->vfunc_no, - PCI_EPC_IRQ_LEGACY, 0); + PCI_EPC_IRQ_INTX, 0); break; case IRQ_TYPE_MSI: pci_epc_raise_irq(epc, epf->func_no, epf->vfunc_no, @@ -649,10 +649,10 @@ static void pci_epf_test_cmd_handler(struct work_struct *work) goto reset_handler; } - if (command & COMMAND_RAISE_LEGACY_IRQ) { + if (command & COMMAND_RAISE_INTX_IRQ) { reg->status = STATUS_IRQ_RAISED; pci_epc_raise_irq(epc, epf->func_no, epf->vfunc_no, - PCI_EPC_IRQ_LEGACY, 0); + PCI_EPC_IRQ_INTX, 0); goto reset_handler; } diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h index 301bb0e53707..c2572a93d73d 100644 --- a/include/linux/pci-epc.h +++ b/include/linux/pci-epc.h @@ -21,7 +21,7 @@ enum pci_epc_interface_type { enum pci_epc_irq_type { PCI_EPC_IRQ_UNKNOWN, - PCI_EPC_IRQ_LEGACY, + PCI_EPC_IRQ_INTX, PCI_EPC_IRQ_MSI, PCI_EPC_IRQ_MSIX, }; @@ -54,7 +54,7 @@ pci_epc_interface_string(enum pci_epc_interface_type type) * MSI-X capability register * @get_msix: ops to get the number of MSI-X interrupts allocated by the RC * from the MSI-X capability register - * @raise_irq: ops to raise a legacy, MSI or MSI-X interrupt + * @raise_irq: ops to raise an INTx, MSI or MSI-X interrupt * @map_msi_irq: ops to map physical address to MSI address and return MSI data * @start: ops to start the PCI link * @stop: ops to stop the PCI link From patchwork Wed Apr 26 04:55:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshihiro Shimoda X-Patchwork-Id: 677252 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CA9A7C7EE29 for ; Wed, 26 Apr 2023 04:56:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239426AbjDZE4U (ORCPT ); Wed, 26 Apr 2023 00:56:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40280 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239419AbjDZE4R (ORCPT ); Wed, 26 Apr 2023 00:56:17 -0400 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 14CCC273A; Tue, 25 Apr 2023 21:56:10 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.99,227,1677510000"; d="scan'208";a="157312776" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 26 Apr 2023 13:56:05 +0900 Received: from localhost.localdomain (unknown [10.166.15.32]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id B01EB41763FC; Wed, 26 Apr 2023 13:56:05 +0900 (JST) From: Yoshihiro Shimoda To: jingoohan1@gmail.com, mani@kernel.org, gustavo.pimentel@synopsys.com, fancer.lancer@gmail.com, lpieralisi@kernel.org, robh+dt@kernel.org, kw@linux.com, bhelgaas@google.com, kishon@kernel.org Cc: marek.vasut+renesas@gmail.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Yoshihiro Shimoda , Bjorn Helgaas Subject: [PATCH v14 05/21] PCI: dwc: Rename "legacy_irq" to "INTx_irq" in DWC core Date: Wed, 26 Apr 2023 13:55:41 +0900 Message-Id: <20230426045557.3613826-6-yoshihiro.shimoda.uh@renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230426045557.3613826-1-yoshihiro.shimoda.uh@renesas.com> References: <20230426045557.3613826-1-yoshihiro.shimoda.uh@renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Using "INTx" instead of "legacy" is more specific. So, rename dw_pcie_ep_raise_legacy_irq() to dw_pcie_ep_raise_intx_irq(). Suggested-by: Bjorn Helgaas Signed-off-by: Yoshihiro Shimoda Reviewed-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pci-imx6.c | 2 +- drivers/pci/controller/dwc/pci-layerscape-ep.c | 2 +- drivers/pci/controller/dwc/pcie-designware-ep.c | 6 +++--- drivers/pci/controller/dwc/pcie-designware-plat.c | 2 +- drivers/pci/controller/dwc/pcie-designware.h | 4 ++-- drivers/pci/controller/dwc/pcie-qcom-ep.c | 2 +- 6 files changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 1f39e733ce19..0831f3947220 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -1063,7 +1063,7 @@ static int imx6_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no, switch (type) { case PCI_EPC_IRQ_INTX: - return dw_pcie_ep_raise_legacy_irq(ep, func_no); + return dw_pcie_ep_raise_intx_irq(ep, func_no); case PCI_EPC_IRQ_MSI: return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num); case PCI_EPC_IRQ_MSIX: diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/controller/dwc/pci-layerscape-ep.c index ab3306e206d8..3d58fc1670b4 100644 --- a/drivers/pci/controller/dwc/pci-layerscape-ep.c +++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c @@ -66,7 +66,7 @@ static int ls_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no, switch (type) { case PCI_EPC_IRQ_INTX: - return dw_pcie_ep_raise_legacy_irq(ep, func_no); + return dw_pcie_ep_raise_intx_irq(ep, func_no); case PCI_EPC_IRQ_MSI: return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num); case PCI_EPC_IRQ_MSIX: diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index 205bbcc6af27..a80b9fd03638 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -480,16 +480,16 @@ static const struct pci_epc_ops epc_ops = { .get_features = dw_pcie_ep_get_features, }; -int dw_pcie_ep_raise_legacy_irq(struct dw_pcie_ep *ep, u8 func_no) +int dw_pcie_ep_raise_intx_irq(struct dw_pcie_ep *ep, u8 func_no) { struct dw_pcie *pci = to_dw_pcie_from_ep(ep); struct device *dev = pci->dev; - dev_err(dev, "EP cannot trigger legacy IRQs\n"); + dev_err(dev, "EP cannot trigger INTx IRQs\n"); return -EINVAL; } -EXPORT_SYMBOL_GPL(dw_pcie_ep_raise_legacy_irq); +EXPORT_SYMBOL_GPL(dw_pcie_ep_raise_intx_irq); int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no, u8 interrupt_num) diff --git a/drivers/pci/controller/dwc/pcie-designware-plat.c b/drivers/pci/controller/dwc/pcie-designware-plat.c index fc3b02949218..2689ff7939e4 100644 --- a/drivers/pci/controller/dwc/pcie-designware-plat.c +++ b/drivers/pci/controller/dwc/pcie-designware-plat.c @@ -49,7 +49,7 @@ static int dw_plat_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no, switch (type) { case PCI_EPC_IRQ_INTX: - return dw_pcie_ep_raise_legacy_irq(ep, func_no); + return dw_pcie_ep_raise_intx_irq(ep, func_no); case PCI_EPC_IRQ_MSI: return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num); case PCI_EPC_IRQ_MSIX: diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index adad0ea61799..9acf6c40d252 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -550,7 +550,7 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep); int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep); void dw_pcie_ep_init_notify(struct dw_pcie_ep *ep); void dw_pcie_ep_exit(struct dw_pcie_ep *ep); -int dw_pcie_ep_raise_legacy_irq(struct dw_pcie_ep *ep, u8 func_no); +int dw_pcie_ep_raise_intx_irq(struct dw_pcie_ep *ep, u8 func_no); int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no, u8 interrupt_num); int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no, @@ -583,7 +583,7 @@ static inline void dw_pcie_ep_exit(struct dw_pcie_ep *ep) { } -static inline int dw_pcie_ep_raise_legacy_irq(struct dw_pcie_ep *ep, u8 func_no) +static inline int dw_pcie_ep_raise_intx_irq(struct dw_pcie_ep *ep, u8 func_no) { return 0; } diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index 077afce48d0b..3061e5e13476 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -659,7 +659,7 @@ static int qcom_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no, switch (type) { case PCI_EPC_IRQ_INTX: - return dw_pcie_ep_raise_legacy_irq(ep, func_no); + return dw_pcie_ep_raise_intx_irq(ep, func_no); case PCI_EPC_IRQ_MSI: return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num); default: From patchwork Wed Apr 26 04:55:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshihiro Shimoda X-Patchwork-Id: 677250 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ABCF0C7EE37 for ; Wed, 26 Apr 2023 04:56:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239413AbjDZE4X (ORCPT ); Wed, 26 Apr 2023 00:56:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40158 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239420AbjDZE4S (ORCPT ); Wed, 26 Apr 2023 00:56:18 -0400 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 3D4582D4A; Tue, 25 Apr 2023 21:56:12 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.99,227,1677510000"; d="scan'208";a="157312781" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 26 Apr 2023 13:56:06 +0900 Received: from localhost.localdomain (unknown [10.166.15.32]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id F032641763FC; Wed, 26 Apr 2023 13:56:05 +0900 (JST) From: Yoshihiro Shimoda To: jingoohan1@gmail.com, mani@kernel.org, gustavo.pimentel@synopsys.com, fancer.lancer@gmail.com, lpieralisi@kernel.org, robh+dt@kernel.org, kw@linux.com, bhelgaas@google.com, kishon@kernel.org Cc: marek.vasut+renesas@gmail.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Yoshihiro Shimoda Subject: [PATCH v14 07/21] PCI: dwc: Add members into struct dw_pcie_outbound_atu Date: Wed, 26 Apr 2023 13:55:43 +0900 Message-Id: <20230426045557.3613826-8-yoshihiro.shimoda.uh@renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230426045557.3613826-1-yoshihiro.shimoda.uh@renesas.com> References: <20230426045557.3613826-1-yoshihiro.shimoda.uh@renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add "code" and "routing" into struct dw_pcie_outbound_atu for sending MSG by iATU in the PCIe endpoint mode in near the future. Signed-off-by: Yoshihiro Shimoda --- drivers/pci/controller/dwc/pcie-designware.c | 7 +++++-- drivers/pci/controller/dwc/pcie-designware.h | 5 +++++ 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 782c4b34d0a3..e8d4d5bde2d3 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -497,7 +497,7 @@ static int __dw_pcie_prog_outbound_atu(struct dw_pcie *pci, dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_TARGET, upper_32_bits(atu->pci_addr)); - val = atu->type | PCIE_ATU_FUNC_NUM(atu->func_no); + val = atu->type | atu->routing | PCIE_ATU_FUNC_NUM(atu->func_no); if (upper_32_bits(limit_addr) > upper_32_bits(atu->cpu_addr) && dw_pcie_ver_is_ge(pci, 460A)) val |= PCIE_ATU_INCREASE_REGION_SIZE; @@ -505,7 +505,10 @@ static int __dw_pcie_prog_outbound_atu(struct dw_pcie *pci, val = dw_pcie_enable_ecrc(val); dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL1, val); - dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2, PCIE_ATU_ENABLE); + val = PCIE_ATU_ENABLE; + if (atu->type == PCIE_ATU_TYPE_MSG) + val |= PCIE_ATU_INHIBIT_PAYLOAD | PCIE_ATU_HEADER_SUB_ENABLE | atu->code; + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2, val); /* * Make sure ATU enable takes effect before any subsequent config diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 81c7558a4718..954d504890a1 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -150,11 +150,14 @@ #define PCIE_ATU_TYPE_IO 0x2 #define PCIE_ATU_TYPE_CFG0 0x4 #define PCIE_ATU_TYPE_CFG1 0x5 +#define PCIE_ATU_TYPE_MSG 0x10 #define PCIE_ATU_TD BIT(8) #define PCIE_ATU_FUNC_NUM(pf) ((pf) << 20) #define PCIE_ATU_REGION_CTRL2 0x004 #define PCIE_ATU_ENABLE BIT(31) #define PCIE_ATU_BAR_MODE_ENABLE BIT(30) +#define PCIE_ATU_INHIBIT_PAYLOAD BIT(22) +#define PCIE_ATU_HEADER_SUB_ENABLE BIT(21) #define PCIE_ATU_FUNC_NUM_MATCH_EN BIT(19) #define PCIE_ATU_LOWER_BASE 0x008 #define PCIE_ATU_UPPER_BASE 0x00C @@ -298,6 +301,8 @@ struct dw_pcie_outbound_atu { int index; int type; u8 func_no; + u8 code; + u8 routing; }; struct dw_pcie_host_ops { From patchwork Wed Apr 26 04:55:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshihiro Shimoda X-Patchwork-Id: 677249 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 70E76C7EE22 for ; Wed, 26 Apr 2023 04:56:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239371AbjDZE43 (ORCPT ); Wed, 26 Apr 2023 00:56:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40792 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239418AbjDZE42 (ORCPT ); Wed, 26 Apr 2023 00:56:28 -0400 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 380F130C7; Tue, 25 Apr 2023 21:56:17 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.99,227,1677510000"; d="scan'208";a="157312789" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 26 Apr 2023 13:56:06 +0900 Received: from localhost.localdomain (unknown [10.166.15.32]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 385964176A8F; Wed, 26 Apr 2023 13:56:06 +0900 (JST) From: Yoshihiro Shimoda To: jingoohan1@gmail.com, mani@kernel.org, gustavo.pimentel@synopsys.com, fancer.lancer@gmail.com, lpieralisi@kernel.org, robh+dt@kernel.org, kw@linux.com, bhelgaas@google.com, kishon@kernel.org Cc: marek.vasut+renesas@gmail.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Yoshihiro Shimoda Subject: [PATCH v14 09/21] PCI: dwc: Add dw_pcie_link_set_max_link_width() Date: Wed, 26 Apr 2023 13:55:45 +0900 Message-Id: <20230426045557.3613826-10-yoshihiro.shimoda.uh@renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230426045557.3613826-1-yoshihiro.shimoda.uh@renesas.com> References: <20230426045557.3613826-1-yoshihiro.shimoda.uh@renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org To improve code readability, add dw_pcie_link_set_max_link_width(). Signed-off-by: Yoshihiro Shimoda Reviewed-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-designware.c | 46 ++++++++++++-------- 1 file changed, 28 insertions(+), 18 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index e8d4d5bde2d3..69358dc202f0 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -737,6 +737,33 @@ static void dw_pcie_link_set_max_speed(struct dw_pcie *pci, u32 link_gen) dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, cap | link_speed); } +static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_lanes) +{ + u32 val; + + if (!num_lanes) + return; + + /* Set link width speed control register */ + val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); + val &= ~PORT_LOGIC_LINK_WIDTH_MASK; + switch (num_lanes) { + case 1: + val |= PORT_LOGIC_LINK_WIDTH_1_LANES; + break; + case 2: + val |= PORT_LOGIC_LINK_WIDTH_2_LANES; + break; + case 4: + val |= PORT_LOGIC_LINK_WIDTH_4_LANES; + break; + case 8: + val |= PORT_LOGIC_LINK_WIDTH_8_LANES; + break; + } + dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); +} + void dw_pcie_iatu_detect(struct dw_pcie *pci) { int max_region, ob, ib; @@ -1044,22 +1071,5 @@ void dw_pcie_setup(struct dw_pcie *pci) } dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val); - /* Set link width speed control register */ - val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); - val &= ~PORT_LOGIC_LINK_WIDTH_MASK; - switch (pci->num_lanes) { - case 1: - val |= PORT_LOGIC_LINK_WIDTH_1_LANES; - break; - case 2: - val |= PORT_LOGIC_LINK_WIDTH_2_LANES; - break; - case 4: - val |= PORT_LOGIC_LINK_WIDTH_4_LANES; - break; - case 8: - val |= PORT_LOGIC_LINK_WIDTH_8_LANES; - break; - } - dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); + dw_pcie_link_set_max_link_width(pci, pci->num_lanes); } From patchwork Wed Apr 26 04:55:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshihiro Shimoda X-Patchwork-Id: 677248 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0DDC7C7618E for ; Wed, 26 Apr 2023 04:56:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239393AbjDZE4b (ORCPT ); Wed, 26 Apr 2023 00:56:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40884 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239435AbjDZE4a (ORCPT ); Wed, 26 Apr 2023 00:56:30 -0400 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id CA8252708; Tue, 25 Apr 2023 21:56:18 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.99,227,1677510000"; d="scan'208";a="157312792" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 26 Apr 2023 13:56:06 +0900 Received: from localhost.localdomain (unknown [10.166.15.32]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 584144175EC6; Wed, 26 Apr 2023 13:56:06 +0900 (JST) From: Yoshihiro Shimoda To: jingoohan1@gmail.com, mani@kernel.org, gustavo.pimentel@synopsys.com, fancer.lancer@gmail.com, lpieralisi@kernel.org, robh+dt@kernel.org, kw@linux.com, bhelgaas@google.com, kishon@kernel.org Cc: marek.vasut+renesas@gmail.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Yoshihiro Shimoda Subject: [PATCH v14 10/21] PCI: dwc: Add dw_pcie_link_set_max_width() Date: Wed, 26 Apr 2023 13:55:46 +0900 Message-Id: <20230426045557.3613826-11-yoshihiro.shimoda.uh@renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230426045557.3613826-1-yoshihiro.shimoda.uh@renesas.com> References: <20230426045557.3613826-1-yoshihiro.shimoda.uh@renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org To improve code readability, add dw_pcie_link_set_max_width(). The original code writes the PCIE_PORT_LINK_CONTROL register twice if the pci->num_lanes is not zero. But, it should avoid to write the register twice. So, refactor it. Signed-off-by: Yoshihiro Shimoda --- drivers/pci/controller/dwc/pcie-designware.c | 66 +++++++++++--------- 1 file changed, 35 insertions(+), 31 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 69358dc202f0..f8926d5ec422 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -737,6 +737,40 @@ static void dw_pcie_link_set_max_speed(struct dw_pcie *pci, u32 link_gen) dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, cap | link_speed); } +static void dw_pcie_link_set_max_width(struct dw_pcie *pci, u32 num_lanes) +{ + u32 val; + + /* Set the number of lanes */ + val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL); + val &= ~PORT_LINK_FAST_LINK_MODE; + val |= PORT_LINK_DLL_LINK_EN; + + /* Mask LINK_MODE if num_lanes is not zero */ + if (num_lanes) + val &= ~PORT_LINK_MODE_MASK; + + switch (num_lanes) { + case 1: + val |= PORT_LINK_MODE_1_LANES; + break; + case 2: + val |= PORT_LINK_MODE_2_LANES; + break; + case 4: + val |= PORT_LINK_MODE_4_LANES; + break; + case 8: + val |= PORT_LINK_MODE_8_LANES; + break; + default: + dev_dbg(pci->dev, "Using h/w default number of lanes\n"); + break; + } + + dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val); +} + static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_lanes) { u32 val; @@ -1040,36 +1074,6 @@ void dw_pcie_setup(struct dw_pcie *pci) dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, val); } - val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL); - val &= ~PORT_LINK_FAST_LINK_MODE; - val |= PORT_LINK_DLL_LINK_EN; - dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val); - - if (!pci->num_lanes) { - dev_dbg(pci->dev, "Using h/w default number of lanes\n"); - return; - } - - /* Set the number of lanes */ - val &= ~PORT_LINK_MODE_MASK; - switch (pci->num_lanes) { - case 1: - val |= PORT_LINK_MODE_1_LANES; - break; - case 2: - val |= PORT_LINK_MODE_2_LANES; - break; - case 4: - val |= PORT_LINK_MODE_4_LANES; - break; - case 8: - val |= PORT_LINK_MODE_8_LANES; - break; - default: - dev_err(pci->dev, "num-lanes %u: invalid value\n", pci->num_lanes); - return; - } - dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val); - + dw_pcie_link_set_max_width(pci, pci->num_lanes); dw_pcie_link_set_max_link_width(pci, pci->num_lanes); } From patchwork Wed Apr 26 04:55:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshihiro Shimoda X-Patchwork-Id: 677251 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 303E9C77B60 for ; Wed, 26 Apr 2023 04:56:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239419AbjDZE4V (ORCPT ); Wed, 26 Apr 2023 00:56:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40136 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239305AbjDZE4S (ORCPT ); Wed, 26 Apr 2023 00:56:18 -0400 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 72D8C2726; Tue, 25 Apr 2023 21:56:11 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.99,227,1677510000"; d="scan'208";a="160778522" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 26 Apr 2023 13:56:06 +0900 Received: from localhost.localdomain (unknown [10.166.15.32]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 7871F4176A83; Wed, 26 Apr 2023 13:56:06 +0900 (JST) From: Yoshihiro Shimoda To: jingoohan1@gmail.com, mani@kernel.org, gustavo.pimentel@synopsys.com, fancer.lancer@gmail.com, lpieralisi@kernel.org, robh+dt@kernel.org, kw@linux.com, bhelgaas@google.com, kishon@kernel.org Cc: marek.vasut+renesas@gmail.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Yoshihiro Shimoda Subject: [PATCH v14 11/21] PCI: dwc: Add dw_pcie_link_set_max_cap_width() Date: Wed, 26 Apr 2023 13:55:47 +0900 Message-Id: <20230426045557.3613826-12-yoshihiro.shimoda.uh@renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230426045557.3613826-1-yoshihiro.shimoda.uh@renesas.com> References: <20230426045557.3613826-1-yoshihiro.shimoda.uh@renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add dw_pcie_link_set_max_cap_width() to set PCI_EXP_LNKCAP_MLW. In accordance with the DW PCIe RC/EP HW manuals [1,2,3,...] aside with the PORT_LINK_CTRL_OFF.LINK_CAPABLE and GEN2_CTRL_OFF.NUM_OF_LANES[8:0] field there is another one which needs to be updated. It's LINK_CAPABILITIES_REG.PCIE_CAP_MAX_LINK_WIDTH. If it isn't done at the very least the maximum link-width capability CSR won't expose the actual maximum capability. [1] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port, Version 4.60a, March 2015, p.1032 [2] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port, Version 4.70a, March 2016, p.1065 [3] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port, Version 4.90a, March 2016, p.1057 ... [X] DesignWare Cores PCI Express Controller Databook - DWC PCIe Endpoint, Version 5.40a, March 2019, p.1396 [X+1] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port, Version 5.40a, March 2019, p.1266 The commit description is suggested by Serge Semin. Suggested-by: Serge Semin Signed-off-by: Yoshihiro Shimoda --- drivers/pci/controller/dwc/pcie-designware.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index f8926d5ec422..bdc5ebd7cd5f 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -737,6 +737,21 @@ static void dw_pcie_link_set_max_speed(struct dw_pcie *pci, u32 link_gen) dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, cap | link_speed); } +static void dw_pcie_link_set_max_cap_width(struct dw_pcie *pci, int num_lanes) +{ + u32 val; + u8 cap; + + if (!num_lanes) + return; + + cap = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + val = dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP); + val &= ~PCI_EXP_LNKCAP_MLW; + val |= num_lanes << PCI_EXP_LNKSTA_NLW_SHIFT; + dw_pcie_writel_dbi(pci, cap + PCI_EXP_LNKCAP, val); +} + static void dw_pcie_link_set_max_width(struct dw_pcie *pci, u32 num_lanes) { u32 val; @@ -1074,6 +1089,7 @@ void dw_pcie_setup(struct dw_pcie *pci) dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, val); } + dw_pcie_link_set_max_cap_width(pci, pci->num_lanes); dw_pcie_link_set_max_width(pci, pci->num_lanes); dw_pcie_link_set_max_link_width(pci, pci->num_lanes); } From patchwork Wed Apr 26 04:55:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshihiro Shimoda X-Patchwork-Id: 677246 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9ECB3C77B78 for ; Wed, 26 Apr 2023 04:56:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239389AbjDZE44 (ORCPT ); Wed, 26 Apr 2023 00:56:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41332 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239394AbjDZE4y (ORCPT ); Wed, 26 Apr 2023 00:56:54 -0400 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 6DD70359D; Tue, 25 Apr 2023 21:56:30 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.99,227,1677510000"; d="scan'208";a="157312805" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 26 Apr 2023 13:56:07 +0900 Received: from localhost.localdomain (unknown [10.166.15.32]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id E2C6441763FC; Wed, 26 Apr 2023 13:56:06 +0900 (JST) From: Yoshihiro Shimoda To: jingoohan1@gmail.com, mani@kernel.org, gustavo.pimentel@synopsys.com, fancer.lancer@gmail.com, lpieralisi@kernel.org, robh+dt@kernel.org, kw@linux.com, bhelgaas@google.com, kishon@kernel.org Cc: marek.vasut+renesas@gmail.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Yoshihiro Shimoda Subject: [PATCH v14 14/21] PCI: dwc: Introduce .ep_pre_init() and .ep_deinit() Date: Wed, 26 Apr 2023 13:55:50 +0900 Message-Id: <20230426045557.3613826-15-yoshihiro.shimoda.uh@renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230426045557.3613826-1-yoshihiro.shimoda.uh@renesas.com> References: <20230426045557.3613826-1-yoshihiro.shimoda.uh@renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Renesas R-Car Gen4 PCIe controllers require vender-specific initialization before .ep_init(). To use dw->dbi and dw->num-lanes in the initialization code, introduce .ep_pre_init() into struct dw_pcie_ep_ops. Also introduce .ep_deinit() to disable the controller by using vender-specific de-initialization. Signed-off-by: Yoshihiro Shimoda --- drivers/pci/controller/dwc/pcie-designware-ep.c | 6 ++++++ drivers/pci/controller/dwc/pcie-designware.h | 2 ++ 2 files changed, 8 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index bd63d224ed7f..66ca9a1640ac 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -671,6 +671,9 @@ void dw_pcie_ep_exit(struct dw_pcie_ep *ep) struct dw_pcie *pci = to_dw_pcie_from_ep(ep); struct pci_epc *epc = ep->epc; + if (ep->ops->ep_deinit) + ep->ops->ep_deinit(ep); + dw_pcie_edma_remove(pci); if (ep->intx_mem) @@ -784,6 +787,9 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) ep->phys_base = res->start; ep->addr_size = resource_size(res); + if (ep->ops->ep_pre_init) + ep->ops->ep_pre_init(ep); + dw_pcie_version_detect(pci); dw_pcie_iatu_detect(pci); diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index c4bdfed7b2e2..ae8ac15e53dc 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -336,7 +336,9 @@ struct dw_pcie_rp { }; struct dw_pcie_ep_ops { + void (*ep_pre_init)(struct dw_pcie_ep *ep); void (*ep_init)(struct dw_pcie_ep *ep); + void (*ep_deinit)(struct dw_pcie_ep *ep); int (*raise_irq)(struct dw_pcie_ep *ep, u8 func_no, enum pci_epc_irq_type type, u16 interrupt_num); const struct pci_epc_features* (*get_features)(struct dw_pcie_ep *ep); From patchwork Wed Apr 26 04:55:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshihiro Shimoda X-Patchwork-Id: 677245 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A8265C77B78 for ; Wed, 26 Apr 2023 04:57:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230435AbjDZE5J (ORCPT ); Wed, 26 Apr 2023 00:57:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41594 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239361AbjDZE5J (ORCPT ); Wed, 26 Apr 2023 00:57:09 -0400 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 8BCAE2D79; Tue, 25 Apr 2023 21:56:49 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.99,227,1677510000"; d="scan'208";a="157312813" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 26 Apr 2023 13:56:07 +0900 Received: from localhost.localdomain (unknown [10.166.15.32]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 6EED94175EC6; Wed, 26 Apr 2023 13:56:07 +0900 (JST) From: Yoshihiro Shimoda To: jingoohan1@gmail.com, mani@kernel.org, gustavo.pimentel@synopsys.com, fancer.lancer@gmail.com, lpieralisi@kernel.org, robh+dt@kernel.org, kw@linux.com, bhelgaas@google.com, kishon@kernel.org Cc: marek.vasut+renesas@gmail.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Yoshihiro Shimoda Subject: [PATCH v14 18/21] PCI: rcar-gen4: Add R-Car Gen4 PCIe Host support Date: Wed, 26 Apr 2023 13:55:54 +0900 Message-Id: <20230426045557.3613826-19-yoshihiro.shimoda.uh@renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230426045557.3613826-1-yoshihiro.shimoda.uh@renesas.com> References: <20230426045557.3613826-1-yoshihiro.shimoda.uh@renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add R-Car Gen4 PCIe Host support. This controller is based on Synopsys DesignWare PCIe, but this controller has vendor-specific registers so that requires initialization code like mode setting and retraining and so on. To reduce code delta, adds some helper functions which are used by both the host driver and the endpoint driver (whitch is added immediately afterwards) into a separate file. Signed-off-by: Yoshihiro Shimoda --- drivers/pci/controller/dwc/Kconfig | 9 + drivers/pci/controller/dwc/Makefile | 2 + .../pci/controller/dwc/pcie-rcar-gen4-host.c | 141 +++++++++++++ drivers/pci/controller/dwc/pcie-rcar-gen4.c | 187 ++++++++++++++++++ drivers/pci/controller/dwc/pcie-rcar-gen4.h | 48 +++++ 5 files changed, 387 insertions(+) create mode 100644 drivers/pci/controller/dwc/pcie-rcar-gen4-host.c create mode 100644 drivers/pci/controller/dwc/pcie-rcar-gen4.c create mode 100644 drivers/pci/controller/dwc/pcie-rcar-gen4.h diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig index ab96da43e0c2..64d4d37bc891 100644 --- a/drivers/pci/controller/dwc/Kconfig +++ b/drivers/pci/controller/dwc/Kconfig @@ -415,4 +415,13 @@ config PCIE_VISCONTI_HOST Say Y here if you want PCIe controller support on Toshiba Visconti SoC. This driver supports TMPV7708 SoC. +config PCIE_RCAR_GEN4 + tristate "Renesas R-Car Gen4 PCIe Host controller" + depends on ARCH_RENESAS || COMPILE_TEST + depends on PCI_MSI + select PCIE_DW_HOST + help + Say Y here if you want PCIe host controller support on R-Car Gen4 SoCs. + This uses the DesignWare core. + endmenu diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile index bf5c311875a1..486cf706b53d 100644 --- a/drivers/pci/controller/dwc/Makefile +++ b/drivers/pci/controller/dwc/Makefile @@ -26,6 +26,8 @@ obj-$(CONFIG_PCIE_TEGRA194) += pcie-tegra194.o obj-$(CONFIG_PCIE_UNIPHIER) += pcie-uniphier.o obj-$(CONFIG_PCIE_UNIPHIER_EP) += pcie-uniphier-ep.o obj-$(CONFIG_PCIE_VISCONTI_HOST) += pcie-visconti.o +pcie-rcar-gen4-host-drv-objs := pcie-rcar-gen4.o pcie-rcar-gen4-host.o +obj-$(CONFIG_PCIE_RCAR_GEN4) += pcie-rcar-gen4-host-drv.o # The following drivers are for devices that use the generic ACPI # pci_root.c driver but don't support standard ECAM config access. diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4-host.c b/drivers/pci/controller/dwc/pcie-rcar-gen4-host.c new file mode 100644 index 000000000000..df7d80f1874f --- /dev/null +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4-host.c @@ -0,0 +1,141 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * PCIe host controller driver for Renesas R-Car Gen4 Series SoCs + * Copyright (C) 2022-2023 Renesas Electronics Corporation + */ + +#include +#include +#include +#include +#include +#include + +#include "pcie-rcar-gen4.h" +#include "pcie-designware.h" + +static int rcar_gen4_pcie_host_init(struct dw_pcie_rp *pp) +{ + struct dw_pcie *dw = to_dw_pcie_from_pp(pp); + struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw); + int ret; + u32 val; + + gpiod_set_value_cansleep(dw->pe_rst, 1); + + ret = rcar_gen4_pcie_set_device_type(rcar, true, dw->num_lanes); + if (ret < 0) + return ret; + + dw_pcie_dbi_ro_wr_en(dw); + + /* + * According to the section 3.5.7.2 "RC Mode" in DWC PCIe Dual Mode + * Rev.5.20a, we should disable two BARs to avoid unnecessary memory + * assignment during device enumeration. + */ + dw_pcie_writel_dbi2(dw, PCI_BASE_ADDRESS_0, 0x0); + dw_pcie_writel_dbi2(dw, PCI_BASE_ADDRESS_1, 0x0); + + dw_pcie_dbi_ro_wr_dis(dw); + + if (IS_ENABLED(CONFIG_PCI_MSI)) { + /* Enable MSI interrupt signal */ + val = readl(rcar->base + PCIEINTSTS0EN); + val |= MSI_CTRL_INT; + writel(val, rcar->base + PCIEINTSTS0EN); + } + + msleep(100); /* pe_rst requires 100msec delay */ + + gpiod_set_value_cansleep(dw->pe_rst, 0); + + return 0; +} + +static const struct dw_pcie_host_ops rcar_gen4_pcie_host_ops = { + .host_init = rcar_gen4_pcie_host_init, +}; + +static int rcar_gen4_add_dw_pcie_rp(struct rcar_gen4_pcie *rcar, + struct platform_device *pdev) +{ + struct dw_pcie *dw = &rcar->dw; + struct dw_pcie_rp *pp = &dw->pp; + + pp->num_vectors = MAX_MSI_IRQS; + pp->ops = &rcar_gen4_pcie_host_ops; + dw_pcie_cap_set(dw, REQ_RES); + + return dw_pcie_host_init(pp); +} + +static void rcar_gen4_remove_dw_pcie_rp(struct rcar_gen4_pcie *rcar) +{ + dw_pcie_host_deinit(&rcar->dw.pp); + gpiod_set_value_cansleep(rcar->dw.pe_rst, 1); +} + +static int rcar_gen4_pcie_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct rcar_gen4_pcie *rcar; + int err; + + rcar = rcar_gen4_pcie_devm_alloc(dev); + if (!rcar) + return -ENOMEM; + + err = rcar_gen4_pcie_get_resources(rcar, pdev); + if (err < 0) { + dev_err(dev, "Failed to request resource: %d\n", err); + return err; + } + + platform_set_drvdata(pdev, rcar); + + err = rcar_gen4_pcie_prepare(rcar); + if (err < 0) + return err; + + rcar->needs_retrain = true; + err = rcar_gen4_add_dw_pcie_rp(rcar, pdev); + if (err < 0) + goto err_add; + + return 0; + +err_add: + rcar_gen4_pcie_unprepare(rcar); + + return err; +} + +static int rcar_gen4_pcie_remove(struct platform_device *pdev) +{ + struct rcar_gen4_pcie *rcar = platform_get_drvdata(pdev); + + rcar_gen4_remove_dw_pcie_rp(rcar); + rcar_gen4_pcie_unprepare(rcar); + + return 0; +} + +static const struct of_device_id rcar_gen4_pcie_of_match[] = { + { .compatible = "renesas,rcar-gen4-pcie", }, + {}, +}; + +static struct platform_driver rcar_gen4_pcie_driver = { + .driver = { + .name = "pcie-rcar-gen4", + .of_match_table = rcar_gen4_pcie_of_match, + .probe_type = PROBE_PREFER_ASYNCHRONOUS, + }, + .probe = rcar_gen4_pcie_probe, + .remove = rcar_gen4_pcie_remove, +}; +module_platform_driver(rcar_gen4_pcie_driver); + +MODULE_DESCRIPTION("Renesas R-Car Gen4 PCIe host controller driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/controller/dwc/pcie-rcar-gen4.c new file mode 100644 index 000000000000..ee916a149708 --- /dev/null +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c @@ -0,0 +1,187 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * PCIe host/endpoint controller driver for Renesas R-Car Gen4 Series SoCs + * Copyright (C) 2022-2023 Renesas Electronics Corporation + */ + +#include +#include +#include +#include +#include +#include + +#include "pcie-rcar-gen4.h" +#include "pcie-designware.h" + +/* Renesas-specific */ +#define PCIERSTCTRL1 0x0014 +#define APP_HOLD_PHY_RST BIT(16) +#define APP_LTSSM_ENABLE BIT(0) + +#define RETRAIN_MAX_RETRY 10 + +static void rcar_gen4_pcie_ltssm_enable(struct rcar_gen4_pcie *rcar, + bool enable) +{ + u32 val; + + val = readl(rcar->base + PCIERSTCTRL1); + if (enable) { + val |= APP_LTSSM_ENABLE; + val &= ~APP_HOLD_PHY_RST; + } else { + val &= ~APP_LTSSM_ENABLE; + val |= APP_HOLD_PHY_RST; + } + writel(val, rcar->base + PCIERSTCTRL1); +} + +static bool rcar_gen4_pcie_check_retrain_link(struct dw_pcie *dw) +{ + u8 offset = dw_pcie_find_capability(dw, PCI_CAP_ID_EXP); + u32 lnkcap = dw_pcie_readl_dbi(dw, offset + PCI_EXP_LNKCAP); + u32 lnkctl = dw_pcie_readl_dbi(dw, offset + PCI_EXP_LNKCTL); + u16 lnksta = dw_pcie_readw_dbi(dw, offset + PCI_EXP_LNKSTA); + int i; + + if ((lnksta & PCI_EXP_LNKSTA_CLS) == (lnkcap & PCI_EXP_LNKCAP_SLS)) + return true; + + lnkctl |= PCI_EXP_LNKCTL_RL; + dw_pcie_writel_dbi(dw, offset + PCI_EXP_LNKCTL, lnkctl); + + for (i = 0; i < RETRAIN_MAX_RETRY; i++) { + lnksta = dw_pcie_readw_dbi(dw, offset + PCI_EXP_LNKSTA); + if (lnksta & PCI_EXP_LNKSTA_LT) + return true; + usleep_range(1000, 1100); + } + + return false; +} + +static int rcar_gen4_pcie_link_up(struct dw_pcie *dw) +{ + struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw); + u32 val, mask; + + /* + * Require retraining here. Otherwise RDLH_LINK_UP of PCIEINTSTS0 which + * is this controller specific register may not be set. + */ + if (rcar->needs_retrain && !rcar_gen4_pcie_check_retrain_link(dw)) + return 0; + + val = readl(rcar->base + PCIEINTSTS0); + mask = RDLH_LINK_UP | SMLH_LINK_UP; + + return (val & mask) == mask; +} + +static int rcar_gen4_pcie_start_link(struct dw_pcie *dw) +{ + struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw); + + rcar_gen4_pcie_ltssm_enable(rcar, true); + + return 0; +} + +static void rcar_gen4_pcie_stop_link(struct dw_pcie *dw) +{ + struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw); + + rcar_gen4_pcie_ltssm_enable(rcar, false); +} + +int rcar_gen4_pcie_set_device_type(struct rcar_gen4_pcie *rcar, bool rc, + int num_lanes) +{ + u32 val; + + /* Note: Assume the rcar->rst which is Cold-reset is asserted here */ + val = readl(rcar->base + PCIEMSR0); + if (rc) + val |= DEVICE_TYPE_RC; + else + val |= DEVICE_TYPE_EP; + + if (num_lanes < 4) + val |= BIFUR_MOD_SET_ON; + + writel(val, rcar->base + PCIEMSR0); + + return reset_control_deassert(rcar->rst); +} + +int rcar_gen4_pcie_prepare(struct rcar_gen4_pcie *rcar) +{ + struct device *dev = rcar->dw.dev; + int err; + + pm_runtime_enable(dev); + err = pm_runtime_resume_and_get(dev); + if (err < 0) { + dev_err(dev, "Failed to resume/get Runtime PM\n"); + pm_runtime_disable(dev); + } + + return err; +} + +void rcar_gen4_pcie_unprepare(struct rcar_gen4_pcie *rcar) +{ + struct device *dev = rcar->dw.dev; + + if (!reset_control_status(rcar->rst)) + reset_control_assert(rcar->rst); + pm_runtime_put(dev); + pm_runtime_disable(dev); +} + +static int rcar_gen4_pcie_devm_reset_get(struct rcar_gen4_pcie *rcar, + struct device *dev) +{ + rcar->rst = devm_reset_control_get(dev, NULL); + if (IS_ERR(rcar->rst)) { + dev_err(dev, "Failed to get Cold-reset\n"); + return PTR_ERR(rcar->rst); + } + + return 0; +} + +int rcar_gen4_pcie_get_resources(struct rcar_gen4_pcie *rcar, + struct platform_device *pdev) +{ + struct dw_pcie *dw = &rcar->dw; + + /* Renesas-specific registers */ + rcar->base = devm_platform_ioremap_resource_byname(pdev, "app"); + if (IS_ERR(rcar->base)) + return PTR_ERR(rcar->base); + + return rcar_gen4_pcie_devm_reset_get(rcar, dw->dev); +} + +static const struct dw_pcie_ops dw_pcie_ops = { + .start_link = rcar_gen4_pcie_start_link, + .stop_link = rcar_gen4_pcie_stop_link, + .link_up = rcar_gen4_pcie_link_up, +}; + +struct rcar_gen4_pcie *rcar_gen4_pcie_devm_alloc(struct device *dev) +{ + struct rcar_gen4_pcie *rcar; + + rcar = devm_kzalloc(dev, sizeof(*rcar), GFP_KERNEL); + if (!rcar) + return NULL; + + rcar->dw.dev = dev; + rcar->dw.ops = &dw_pcie_ops; + dw_pcie_cap_set(&rcar->dw, EDMA_UNROLL); + + return rcar; +} diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.h b/drivers/pci/controller/dwc/pcie-rcar-gen4.h new file mode 100644 index 000000000000..7c765c2d79b9 --- /dev/null +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * PCIe host/endpoint controller driver for Renesas R-Car Gen4 Series SoCs + * Copyright (C) 2022-2023 Renesas Electronics Corporation + */ + +#ifndef _PCIE_RCAR_GEN4_H_ +#define _PCIE_RCAR_GEN4_H_ + +#include +#include +#include + +#include "pcie-designware.h" + +/* Renesas-specific */ +#define PCIEMSR0 0x0000 +#define BIFUR_MOD_SET_ON BIT(0) +#define DEVICE_TYPE_EP 0 +#define DEVICE_TYPE_RC BIT(4) + +#define PCIEINTSTS0 0x0084 +#define PCIEINTSTS0EN 0x0310 +#define MSI_CTRL_INT BIT(26) +#define SMLH_LINK_UP BIT(7) +#define RDLH_LINK_UP BIT(6) +#define PCIEDMAINTSTSEN 0x0314 +#define PCIEDMAINTSTSEN_INIT GENMASK(15, 0) + +struct rcar_gen4_pcie { + struct dw_pcie dw; + void __iomem *base; + struct reset_control *rst; + bool needs_retrain; +}; +#define to_rcar_gen4_pcie(x) dev_get_drvdata((x)->dev) + +u32 rcar_gen4_pcie_readl(struct rcar_gen4_pcie *pcie, u32 reg); +void rcar_gen4_pcie_writel(struct rcar_gen4_pcie *pcie, u32 reg, u32 val); +int rcar_gen4_pcie_set_device_type(struct rcar_gen4_pcie *rcar, bool rc, + int num_lanes); +int rcar_gen4_pcie_prepare(struct rcar_gen4_pcie *pcie); +void rcar_gen4_pcie_unprepare(struct rcar_gen4_pcie *pcie); +int rcar_gen4_pcie_get_resources(struct rcar_gen4_pcie *rcar, + struct platform_device *pdev); +struct rcar_gen4_pcie *rcar_gen4_pcie_devm_alloc(struct device *dev); + +#endif /* _PCIE_RCAR_GEN4_H_ */ From patchwork Wed Apr 26 04:55:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshihiro Shimoda X-Patchwork-Id: 677247 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 15AE4C77B78 for ; Wed, 26 Apr 2023 04:56:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239444AbjDZE4g (ORCPT ); Wed, 26 Apr 2023 00:56:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40948 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239034AbjDZE4f (ORCPT ); Wed, 26 Apr 2023 00:56:35 -0400 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 3FC6230CA; Tue, 25 Apr 2023 21:56:21 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.99,227,1677510000"; d="scan'208";a="160778539" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 26 Apr 2023 13:56:08 +0900 Received: from localhost.localdomain (unknown [10.166.15.32]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id DA59041763FB; Wed, 26 Apr 2023 13:56:07 +0900 (JST) From: Yoshihiro Shimoda To: jingoohan1@gmail.com, mani@kernel.org, gustavo.pimentel@synopsys.com, fancer.lancer@gmail.com, lpieralisi@kernel.org, robh+dt@kernel.org, kw@linux.com, bhelgaas@google.com, kishon@kernel.org Cc: marek.vasut+renesas@gmail.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Yoshihiro Shimoda Subject: [PATCH v14 21/21] misc: pci_endpoint_test: Add Device ID for R-Car S4-8 PCIe controller Date: Wed, 26 Apr 2023 13:55:57 +0900 Message-Id: <20230426045557.3613826-22-yoshihiro.shimoda.uh@renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230426045557.3613826-1-yoshihiro.shimoda.uh@renesas.com> References: <20230426045557.3613826-1-yoshihiro.shimoda.uh@renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add Renesas R8A779F0 in pci_device_id table so that pci-epf-test can be used for testing PCIe EP on R-Car S4-8. Signed-off-by: Yoshihiro Shimoda Acked-by: Manivannan Sadhasivam --- drivers/misc/pci_endpoint_test.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c index a7244de081ec..1d8f72b42c0a 100644 --- a/drivers/misc/pci_endpoint_test.c +++ b/drivers/misc/pci_endpoint_test.c @@ -81,6 +81,7 @@ #define PCI_DEVICE_ID_RENESAS_R8A774B1 0x002b #define PCI_DEVICE_ID_RENESAS_R8A774C0 0x002d #define PCI_DEVICE_ID_RENESAS_R8A774E1 0x0025 +#define PCI_DEVICE_ID_RENESAS_R8A779F0 0x0031 static DEFINE_IDA(pci_endpoint_test_ida); @@ -993,6 +994,9 @@ static const struct pci_device_id pci_endpoint_test_tbl[] = { { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774B1),}, { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774C0),}, { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774E1),}, + { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A779F0), + .driver_data = (kernel_ulong_t)&default_data, + }, { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_J721E), .driver_data = (kernel_ulong_t)&j721e_data, },