From patchwork Tue Jun 4 13:14:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 165764 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp5841644ili; Tue, 4 Jun 2019 06:17:07 -0700 (PDT) X-Google-Smtp-Source: APXvYqxPcXCwl6tSNW0NL7SLMVfBpk6kWS4/KOt592JjiQ3c+mzGNZzK6EKK2riFHay29EAzOXgq X-Received: by 2002:a62:5103:: with SMTP id f3mr38440292pfb.146.1559654227160; Tue, 04 Jun 2019 06:17:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1559654227; cv=none; d=google.com; s=arc-20160816; b=XCZCgDKDBBnBGXl12A40yElxAy+no4HxmHTS12xxExLRmYStgKj2o/dI0XjrdFXk/m JUW/GjfjC2Kl9peDAJXsI59VJabRKkXu73aPnLEGPHm22yJ0CP3knSJXx3YHIZC0YKf5 iYmupjomgisew/nsX3HbVtL9PjPWWJqxj0lCeldTd1L622sTl8cLfFG1MwU4LJyEoYJ9 QoVpkr19A3gyDjPgubV48RB6h/27Th5jM+Sd+JuP+OaGudoybPXW5uGrDS2Ul3IYN/gu Ju6tZXQ1yFEthh/HFANPhMlxlAiCrohXWu0Dg5IOPDJzUQlLJbnOWd96VhHCP+QDiIPl 8GLA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=d2Yf+EQVOcYUuyjIFqI4vpy6C4J9oA56z6GDwCfgJM8=; b=CZj6dSrx/XW0pxA37P8/COO5ic1llDSv3ScsioAMgk1uZ4nsYGyCSeYHvBGwonU2hQ Wn8Bwk9YZTqvK4yCHPU1dDuxtqE9OdeGJAD2DYko0yryK9Go0DNNY8CIhowhsObNqL8p T+jo7LOfj6n4jYaBvvksAqcJSPE4UhIqrAUnSBRYB5laaE/a+4ctVV2mq7Jm3H2/u8Di rqDFC9M+gYxWVzAr0BZOV7V8VL3o3+C6KoY2mvm1XkLvl7DAa4VxRoIZjeLcMAqybbl/ Qm8OHDEjwVKx8lxV7BuM7qWiT12Dttyw0eQ2nP7o0HQ0qmHvY7ZJpY6wx9nPar4P/JYq MISA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=iaiOtqAj; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Kishon Vijay Abraham I --- Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt | 1 + 1 file changed, 1 insertion(+) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt index 91de69c713a9..f02cccd1e0c5 100644 --- a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt +++ b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt @@ -27,6 +27,7 @@ Optional properties: - phys: From PHY bindings: List of Generic PHY phandles. One per lane if more than one in the list. If only one PHY listed it must manage all lanes. - phy-names: List of names to identify the PHY. +- iommu-map: As specified in Documentation/devicetree/bindings/pci/pci-iommu.txt Example: From patchwork Tue Jun 4 13:14:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 165767 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp5841985ili; Tue, 4 Jun 2019 06:17:21 -0700 (PDT) X-Google-Smtp-Source: APXvYqzzrRMkUwmSoMs6NXGb5r2uLSmOhhsbLmKmdIrnF9sudJVYOgZFpQMpH+9fRGVLA3b+F3gC X-Received: by 2002:aa7:9a92:: with SMTP id w18mr9062482pfi.167.1559654241067; Tue, 04 Jun 2019 06:17:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1559654241; cv=none; d=google.com; s=arc-20160816; b=E18wJGQLPYpYLtgJmZJqPFLogei24HyBcQj6jSIyAY3L0UYeCW3vJqlJaOLv+ypzLB H5IG4yNyuHng1fihB8YTuWmsX1XEuYRrrd1q1TQQaSXgChayWoAy2kt74GRfuXvo8cSf CovPxKoPYVtP18hl1dctjhITCZh7JSicRNQp5Nqm2hP4nlTiHzCNDT0n8ojpSuBSQrNY b/3zW94hSrXz2rtRN7CCiNhKVCU42iQb0n0EmoCK30EZrT8yN7xmfFdkRSFWisUA0+pL If7gKR4dUoY3BXZ7W1HoUj7WBPEHDu7c9tz4dtvJTEx3blgY2Zeq7DLxQL2GbpAdgLvd RW0w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=JE6qETej25St2h/Tbzot2sPw2x/y91yK0ZVgB4HQ7cI=; b=Dkh7WBqqOQjJPSedZ7DXnRq3vSw91vCpyis0VSrReL31aeU19Mr3yjG4+mBQFBrswT oSj8XR6jjeS3/uQ85OVTN352JylECWhBhn19xaUGDpOmQ4uMdh2BmyAIFaJzcoGbJthS TVYN+4GB7UcjglOU/sP0Umhi82M1hvbIULOo2oyI6WP9MqB5mCagU1syEk62iyQDRtKS 5tx1poO88Wf24D//6iEaAuddDHQsMcMisDBXGNnSBlxxxZx9eS3hwLNnlSSzXrWCZazk nT2/5wQMj2VOMCH5YFoQZsug22AyWqI0IwWNA3llBxQY9/9Osomln73FbliSoe1RW0ok zfKg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=lxaduQ80; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Kishon Vijay Abraham I --- Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt | 1 + 1 file changed, 1 insertion(+) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt index cbd16519ae13..afebfec102af 100644 --- a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt +++ b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt @@ -5,6 +5,7 @@ host-generic-pci.txt. Required properties: - compatible: Should contain "cdns,cdns-pcie-host" to identify the IP used. + Should contain "ti,j721e-cdns-pcie-host" for TI platforms. - reg: Should contain the controller register base address, PCIe configuration window base address, and AXI interface region base address respectively. - reg-names: Must be "reg", "cfg" and "mem" respectively. From patchwork Tue Jun 4 13:14:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 165771 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp5842740ili; Tue, 4 Jun 2019 06:17:52 -0700 (PDT) X-Google-Smtp-Source: APXvYqzHZJ0yi71b6FJA1PiKeRz80WBTLYm5aRTrYOg+uJjj9BAuvNdaPES3UzKUxOzlMG1lY6LU X-Received: by 2002:a17:902:8f87:: with SMTP id z7mr10993884plo.65.1559654272733; Tue, 04 Jun 2019 06:17:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1559654272; cv=none; d=google.com; s=arc-20160816; b=t8XdPAG6CDxQX7dMQYAXb1TrHvkT2uvCK4RRzcQD41YeKh5zO5lwy3YARRnpR3wsLg 8N3ZzP3ZkoQR5XifbHBRvmi3fY86UYjmYlbIOV/1+XZbE6LYY+Bx7Jw0fpmLQOkW40/n nRJZa9tHoFKFiDUjo2PnHY59cVfWy38qnkbn8V+BdvmrPSwRm04xTD1sJXmBu/8PxmR3 whxqXLMcER/yobbeUzJrlRCKBvrxxRL1bGYpYFAFxTWLrMx1qD9lTbAD4v/Gscw8do6d B8uafe7c58nhGRqonazdDv3gomWHa72Z2ocjMHq5pTmZu1hudqb3OKa0KMqUt/wd19Hl y7LA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=r7Ei7rsj5lX30OaH2FuRyDzaWU4cllou71wNl6pyjGU=; b=fzSX6Vpcu30XpiP3L3O20DMrj79vkqvtFf3vKYjeXo81JaFie3CdwrZeJ8K6fySS9Q nbZTl82M0QytoYgJVcxf9gSPG1f3Q7RsAkOFQ2wUNMDnVSAkJFYbMwEs5MTwi3nGKf7L ZWpFB8x4zJHx7P4bbrF8QoQf0IbIgeP+gppllUVduR0zNxPRu4dWXb8jpfqqMHx12CEP Hx5U7mgUi4kUGywy5xL7AXmDVPaJMdPB6Fn1rOrb/8dY9zm8WPYeYxFQ38C7rdtU3dKD dVDJMjKgvyiqfoZ+dxGoXg2C6B77aDndAvmCZrHmUDEnHlGh3V3zHbWO8VLCZFKWCbl3 5EhQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=LSVcOA+Y; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id bh2si24269828plb.430.2019.06.04.06.17.52; Tue, 04 Jun 2019 06:17:52 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=LSVcOA+Y; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727601AbfFDNRv (ORCPT + 30 others); Tue, 4 Jun 2019 09:17:51 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:50334 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727149AbfFDNRt (ORCPT ); Tue, 4 Jun 2019 09:17:49 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x54DHOCZ082297; Tue, 4 Jun 2019 08:17:24 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1559654244; bh=r7Ei7rsj5lX30OaH2FuRyDzaWU4cllou71wNl6pyjGU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=LSVcOA+Yvgp5r4q37wsXmkUbV/VfLRgfiNv3EB13v74k4jJgbghcsXk7Gnb59nUyf jSgBO6w/fIVnaXDF1mZkeFCQcxOtdDnsWypr0fkDmTYMDir+xvtwJ6WCRweqfrkiJy cZC3MNhpjHt2TvSlI8WXEamLJPJiycennA//lZtg= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x54DHOIc042670 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 4 Jun 2019 08:17:24 -0500 Received: from DLEE111.ent.ti.com (157.170.170.22) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Tue, 4 Jun 2019 08:17:24 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Tue, 4 Jun 2019 08:17:24 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x54DGdGN098972; Tue, 4 Jun 2019 08:17:19 -0500 From: Kishon Vijay Abraham I To: Tom Joseph , Bjorn Helgaas , Rob Herring , Mark Rutland , Lorenzo Pieralisi , Arnd Bergmann , Gustavo Pimentel CC: Greg Kroah-Hartman , Frank Rowand , Jingoo Han , , , , , , , Kishon Vijay Abraham I Subject: [RFC PATCH 07/30] PCI: cadence: Add read and write accessors to perform only 32-bit accesses Date: Tue, 4 Jun 2019 18:44:53 +0530 Message-ID: <20190604131516.13596-8-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190604131516.13596-1-kishon@ti.com> References: <20190604131516.13596-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Certain platforms like TI's J721E allows only 32-bit register accesses. Add read and write accessor to perform only 32-bit accesses in order to support platfroms like TI's J721E. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/pcie-cadence.c | 40 +++++++++++++++++++++++++++ drivers/pci/controller/pcie-cadence.h | 2 ++ 2 files changed, 42 insertions(+) -- 2.17.1 diff --git a/drivers/pci/controller/pcie-cadence.c b/drivers/pci/controller/pcie-cadence.c index cd795f6fc1e2..de5b3b06f2d0 100644 --- a/drivers/pci/controller/pcie-cadence.c +++ b/drivers/pci/controller/pcie-cadence.c @@ -7,6 +7,46 @@ #include "pcie-cadence.h" +u32 cdns_pcie_read32(void __iomem *addr, int size) +{ + void __iomem *aligned_addr = PTR_ALIGN_DOWN(addr, 0x4); + unsigned int offset = (unsigned long)addr & 0x3; + u32 val = readl(aligned_addr); + + if (!IS_ALIGNED((uintptr_t)addr, size)) { + pr_err("Invalid Address in function:%s\n", __func__); + return 0; + } + + if (size > 2) + return val; + + return (val >> (8 * offset)) & ((1 << (size * 8)) - 1); +} + +void cdns_pcie_write32(void __iomem *addr, int size, u32 value) +{ + void __iomem *aligned_addr = PTR_ALIGN_DOWN(addr, 0x4); + unsigned int offset = (unsigned long)addr & 0x3; + u32 mask; + u32 val; + + if (!IS_ALIGNED((uintptr_t)addr, size)) { + pr_err("Invalid Address in function:%s\n", __func__); + return; + } + + if (size > 2) { + writel(value, addr); + return; + } + + mask = ~(((1 << (size * 8)) - 1) << (offset * 8)); + val = readl(aligned_addr) & mask; + val |= value << (offset * 8); + writel(val, aligned_addr); +} + void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 fn, u32 r, bool is_io, u64 cpu_addr, u64 pci_addr, size_t size) diff --git a/drivers/pci/controller/pcie-cadence.h b/drivers/pci/controller/pcie-cadence.h index 0134c1b1ad65..d157bf5eabd5 100644 --- a/drivers/pci/controller/pcie-cadence.h +++ b/drivers/pci/controller/pcie-cadence.h @@ -406,6 +406,8 @@ void cdns_pcie_reset_outbound_region(struct cdns_pcie *pcie, u32 r); void cdns_pcie_disable_phy(struct cdns_pcie *pcie); int cdns_pcie_enable_phy(struct cdns_pcie *pcie); int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie); +u32 cdns_pcie_read32(void __iomem *addr, int size); +void cdns_pcie_write32(void __iomem *addr, int size, u32 value); extern const struct dev_pm_ops cdns_pcie_pm_ops; #endif /* _PCIE_CADENCE_H */ From patchwork Tue Jun 4 13:14:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 165776 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp5843547ili; Tue, 4 Jun 2019 06:18:32 -0700 (PDT) X-Google-Smtp-Source: APXvYqwvozFjIpA5p4yKdS0IlCH+nkpyhXzjGaS+cGwKrLMUnCWCw4mhr85jZBI/T1juYMmLpuGX X-Received: by 2002:a65:41c7:: with SMTP id b7mr35272760pgq.165.1559654311804; Tue, 04 Jun 2019 06:18:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1559654311; cv=none; d=google.com; s=arc-20160816; b=aOqa5XKZrG9IOz3KOQo+gjmtWWaGG8Lthuhk4FC13aYoL0FdxsE0RAcI123vuvdAvC 2fxUwDyrNTgRu65j2BoDHm93SPlQ/qJRhAh4vpRQEvUCT9DnTogdanwFqHO35birdNsL G6nrbO5EEb2LQMoivEjUOu+CRRTeU+pTeGUUYnBFF7g6hNyZgBKKk+WE8do1Fus8Ge+0 wJLsti2RvXriFVjGBjtpGOwqvfsuFINtQlN2bYC23w/OBervW7BSrSYYEh1FpSThuG5g B5QitVtGC89OnoXxTuIJG9h0Z0XBhVnk6UKQyMrNGbObqy33YXtLZmfM22E4Ki99e5Aq alyQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=T5pkgbPtfeYhwC2XYU7uxdS1O66/LVXpQwXXprThbgo=; b=EHtKLs/jHUnONBQ0nB+P4Lw74UYl97qMAIHWqhxVWtZ1wHMwY3cU3HqM0r3nbvauiR 0ahIIUcXwK2vdDdbIFVCwWp6zOzTqb0o/4TXB5C6nmAAM3oGiWtRUIyTkJqCXNGSunAy Yxya/01jh1ZXX7akl2CXn/IV9o9qwNJNQ0iiFbvDQDCTnNrTCBaHDajM+mjgaCTnWuZ6 9WkEQuGX+iTXHLtdyXMcTQm0iQFp+1Yj5ShbOPY7pRAX+B3MhykdAHVvS3jrivFArU1B m7vz2OaVwY8md+R6oiwuX1BBxVRLb6qe37TEtr6F+6omnyYJK7twV3bin9sruOvOuSXN Q17w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=oLZn9E4E; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e96si23950996plb.123.2019.06.04.06.18.31; Tue, 04 Jun 2019 06:18:31 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=oLZn9E4E; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727741AbfFDNSa (ORCPT + 30 others); Tue, 4 Jun 2019 09:18:30 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:35302 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727710AbfFDNS0 (ORCPT ); Tue, 4 Jun 2019 09:18:26 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x54DHUwP091935; Tue, 4 Jun 2019 08:17:30 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1559654250; bh=T5pkgbPtfeYhwC2XYU7uxdS1O66/LVXpQwXXprThbgo=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=oLZn9E4EQCSED8upH9gju2LbBt/+J0Y8RfNaABd8mWwDs+2AVvyWfnxH0ZFZZvODz yTzp2gGDRCi+k2WR02CLGV28NqOIRQhftLzWw8TnpdWV2+CBdZ3phLy3WjG3SWyZvs psjAghz2htn9X9FJ/jKV7UnHLp8B+eNgZAX5DHdI= Received: from DLEE103.ent.ti.com (dlee103.ent.ti.com [157.170.170.33]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x54DHUeM008068 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 4 Jun 2019 08:17:30 -0500 Received: from DLEE115.ent.ti.com (157.170.170.26) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Tue, 4 Jun 2019 08:17:29 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Tue, 4 Jun 2019 08:17:29 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x54DGdGO098972; Tue, 4 Jun 2019 08:17:24 -0500 From: Kishon Vijay Abraham I To: Tom Joseph , Bjorn Helgaas , Rob Herring , Mark Rutland , Lorenzo Pieralisi , Arnd Bergmann , Gustavo Pimentel CC: Greg Kroah-Hartman , Frank Rowand , Jingoo Han , , , , , , , Kishon Vijay Abraham I Subject: [RFC PATCH 08/30] PCI: cadence: Add support to use PCIe in J721E SoC Date: Tue, 4 Jun 2019 18:44:54 +0530 Message-ID: <20190604131516.13596-9-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190604131516.13596-1-kishon@ti.com> References: <20190604131516.13596-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Use J721E specific compatible in pcie-cadence-* drivers. Since PCIe in J721E SoC has a restriction that allows only 32-bit register access, use the 32-bit accessors for read and write. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/pcie-cadence-ep.c | 12 +++++- drivers/pci/controller/pcie-cadence-host.c | 47 +++++++++++++++++++++- 2 files changed, 55 insertions(+), 4 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/pcie-cadence-ep.c b/drivers/pci/controller/pcie-cadence-ep.c index 64ab5c53afb1..07f840cfba23 100644 --- a/drivers/pci/controller/pcie-cadence-ep.c +++ b/drivers/pci/controller/pcie-cadence-ep.c @@ -425,9 +425,17 @@ static const struct pci_epc_ops cdns_pcie_epc_ops = { .get_features = cdns_pcie_ep_get_features, }; -static const struct of_device_id cdns_pcie_ep_of_match[] = { - { .compatible = "cdns,cdns-pcie-ep" }, +static struct cdns_pcie_ep_data cdns_ti_pcie_ep_data = { + .read = cdns_pcie_read32, + .write = cdns_pcie_write32, +}; +static const struct of_device_id cdns_pcie_ep_of_match[] = { + { .compatible = "cdns,cdns-pcie-ep", + }, + { .compatible = "ti,j721e-cdns-pcie-ep", + .data = &cdns_ti_pcie_ep_data, + }, { }, }; diff --git a/drivers/pci/controller/pcie-cadence-host.c b/drivers/pci/controller/pcie-cadence-host.c index 75cf3c312ed2..ab6491b23775 100644 --- a/drivers/pci/controller/pcie-cadence-host.c +++ b/drivers/pci/controller/pcie-cadence-host.c @@ -93,9 +93,52 @@ static struct pci_ops cdns_pcie_host_ops = { .write = pci_generic_config_write, }; -static const struct of_device_id cdns_pcie_host_of_match[] = { - { .compatible = "cdns,cdns-pcie-host" }, +static int cdns_ti_pcie_config_read(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 *value) +{ + struct pci_host_bridge *bridge = pci_find_host_bridge(bus); + struct cdns_pcie_rc *rc = pci_host_bridge_priv(bridge); + unsigned int busn = bus->number; + + if (busn == rc->bus_range->start) + return pci_generic_config_read32(bus, devfn, where, size, + value); + + return pci_generic_config_read(bus, devfn, where, size, value); +} + +static int cdns_ti_pcie_config_write(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 value) +{ + struct pci_host_bridge *bridge = pci_find_host_bridge(bus); + struct cdns_pcie_rc *rc = pci_host_bridge_priv(bridge); + unsigned int busn = bus->number; + + if (busn == rc->bus_range->start) + return pci_generic_config_write32(bus, devfn, where, size, + value); + + return pci_generic_config_write(bus, devfn, where, size, value); +} + +static struct pci_ops cdns_ti_pcie_host_ops = { + .map_bus = cdns_pci_map_bus, + .read = cdns_ti_pcie_config_read, + .write = cdns_ti_pcie_config_write, +}; + +static struct cdns_pcie_host_data cdns_ti_pcie_host_data = { + .read = cdns_pcie_read32, + .write = cdns_pcie_write32, + .ops = &cdns_ti_pcie_host_ops, +}; +static const struct of_device_id cdns_pcie_host_of_match[] = { + { .compatible = "cdns,cdns-pcie-host", + }, + { .compatible = "ti,j721e-cdns-pcie-host", + .data = &cdns_ti_pcie_host_data, + }, { }, }; From patchwork Tue Jun 4 13:14:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 165780 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp5844148ili; Tue, 4 Jun 2019 06:18:58 -0700 (PDT) X-Google-Smtp-Source: APXvYqwdbU5YJypKk5fcHlRgx5/B6TfERP7rxwZwRST1xECTarobNeGChv3tUIXLe9FrGteTzto1 X-Received: by 2002:a17:90a:ad44:: with SMTP id w4mr36864949pjv.50.1559654338507; Tue, 04 Jun 2019 06:18:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1559654338; cv=none; d=google.com; s=arc-20160816; b=EYhWaH/huRtbLPcTWvkj4jhs2NwfpFq4onaXWEJXByO0kxARD0O7QXR2L4iGuMzddc NB9G9EpF0AyNy+3tYOO3QQX5uVgqF45sYTsCO6Frl3m7Ss/kFzvTPu6mCwpSzDftqoKD MtefctEKqznphC3AjYndPT06jhRMZ/4SIK0OiW9MZXC6DgXAZknei+LxvKcIdUXX9MAa kHxxlhAK90qCcBPnn1hAxBW4B/N88PqK/HvCqVRbdOOJOeYjYLBOk1Eavy3DzST65W2F XvroMjJrm7uhH0/We6VH5nyGIPospElrNS36lU2ruZy5HSX8LJ/k8+SS7bE6Y6mig+Ug w3xA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=RElHPxtACkCdk4rLufC/bmJZmseWFYOIIvYrh7aFO/8=; b=jEzGA0J93Afrva/frcOPNly5evdiSs5Y78FGdGgB6iEtWZNjii5JLpoFnXTaJT6sTY Rhls4g6ozqyclmXvquKbuNlVBbwWKouyllkwnsZ3Zxm6Etlv+ysB5N4JkTIZN5gHDdpy b5D1ic/ljtzRLbrmSJm3itVGgiolVpPs380fwmrjSfQUeCLAQAx6vq8LQsLhIGqFuTZF 3iTNRfxTnNsDmI/J7DXOG4fYphlqQRqDeVAytDkWsh7Lqb1sVZDuHkJgGTB819sTzhsV cavsmXe2JdeOQVs9wS1igqoJPzPSrjMu5ytIY4HsfQjz4PcelsxIVEh62rD4S/ceWb0X QGkA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=ctcAw7L7; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id w2si21821253pga.495.2019.06.04.06.18.58; Tue, 04 Jun 2019 06:18:58 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=ctcAw7L7; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727790AbfFDNSn (ORCPT + 30 others); Tue, 4 Jun 2019 09:18:43 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:55042 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727221AbfFDNSl (ORCPT ); Tue, 4 Jun 2019 09:18:41 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id x54DHf13028057; Tue, 4 Jun 2019 08:17:41 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1559654261; bh=RElHPxtACkCdk4rLufC/bmJZmseWFYOIIvYrh7aFO/8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=ctcAw7L7QUByHCOouvIbfAiWv5Zee8mbXY3jZXhr2OTNddfQLtmVD7zJnqx/VdTyr lC1MgB43JIWeJjcT739mZpUBUOpgDiQwkfxViuPTLl3GsgePCdIvDMwpmCh+CjaqWG lqtruagGs6y45G+xx4UhzoFRKD5nWMZRXj0nSwfY= Received: from DFLE107.ent.ti.com (dfle107.ent.ti.com [10.64.6.28]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x54DHeFX052834 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 4 Jun 2019 08:17:40 -0500 Received: from DFLE106.ent.ti.com (10.64.6.27) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Tue, 4 Jun 2019 08:17:40 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Tue, 4 Jun 2019 08:17:40 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x54DGdGQ098972; Tue, 4 Jun 2019 08:17:35 -0500 From: Kishon Vijay Abraham I To: Tom Joseph , Bjorn Helgaas , Rob Herring , Mark Rutland , Lorenzo Pieralisi , Arnd Bergmann , Gustavo Pimentel CC: Greg Kroah-Hartman , Frank Rowand , Jingoo Han , , , , , , , Kishon Vijay Abraham I Subject: [RFC PATCH 10/30] PCI: cadence: Use *_start_link() and *_wait_for_link() to establish link Date: Tue, 4 Jun 2019 18:44:56 +0530 Message-ID: <20190604131516.13596-11-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190604131516.13596-1-kishon@ti.com> References: <20190604131516.13596-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Use cdns_pcie_start_link() to start link training and cdns_pcie_wait_for_link() in order to wait to establish the link. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/pcie-cadence-ep.c | 11 ++++++++++- drivers/pci/controller/pcie-cadence-host.c | 11 +++++++++++ 2 files changed, 21 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/drivers/pci/controller/pcie-cadence-ep.c b/drivers/pci/controller/pcie-cadence-ep.c index b044167071e6..825a515821c3 100644 --- a/drivers/pci/controller/pcie-cadence-ep.c +++ b/drivers/pci/controller/pcie-cadence-ep.c @@ -21,6 +21,7 @@ /** * struct cdns_pcie_ep - private data for this PCIe endpoint controller driver * @pcie: Cadence PCIe controller + * @dev: pointer to PCIe EP device * @max_regions: maximum number of regions supported by hardware * @ob_region_map: bitmask of mapped outbound regions * @ob_addr: base addresses in the AXI bus where the outbound regions start @@ -37,6 +38,7 @@ */ struct cdns_pcie_ep { struct cdns_pcie pcie; + struct device *dev; u32 max_regions; unsigned long ob_region_map; phys_addr_t *ob_addr; @@ -386,6 +388,7 @@ static int cdns_pcie_ep_start(struct pci_epc *epc) struct cdns_pcie_ep *ep = epc_get_drvdata(epc); struct cdns_pcie *pcie = &ep->pcie; struct pci_epf *epf; + int ret = 0; u32 cfg; /* @@ -397,7 +400,11 @@ static int cdns_pcie_ep_start(struct pci_epc *epc) cfg |= BIT(epf->func_no); cdns_pcie_writel(pcie, CDNS_PCIE_LM_EP_FUNC_CFG, cfg); - return 0; + ret = cdns_pcie_start_link(pcie, true); + if (ret) + dev_err(ep->dev, "Failed to start link\n"); + + return ret; } static const struct pci_epc_features cdns_pcie_epc_features = { @@ -460,6 +467,8 @@ static int cdns_pcie_ep_probe(struct platform_device *pdev) if (!ep) return -ENOMEM; + ep->dev = dev; + pcie = &ep->pcie; pcie->is_rc = false; pcie->plat_data = pdev->dev.platform_data; diff --git a/drivers/pci/controller/pcie-cadence-host.c b/drivers/pci/controller/pcie-cadence-host.c index 2363f05e7c58..4ad8f2ece6e2 100644 --- a/drivers/pci/controller/pcie-cadence-host.c +++ b/drivers/pci/controller/pcie-cadence-host.c @@ -365,6 +365,14 @@ static int cdns_pcie_host_probe(struct platform_device *pdev) goto err_get_sync; } + ret = cdns_pcie_start_link(pcie, true); + if (ret) { + dev_err(dev, "Failed to start link\n"); + goto err_start_link; + } + + cdns_pcie_wait_for_link(dev, pcie); + ret = cdns_pcie_host_init(dev, &resources, rc); if (ret) goto err_init; @@ -386,6 +394,9 @@ static int cdns_pcie_host_probe(struct platform_device *pdev) pci_free_resource_list(&resources); err_init: + cdns_pcie_start_link(pcie, false); + + err_start_link: pm_runtime_put_sync(dev); err_get_sync: From patchwork Tue Jun 4 13:14:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 165773 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp5843038ili; Tue, 4 Jun 2019 06:18:06 -0700 (PDT) X-Google-Smtp-Source: APXvYqyEMGhc5GlRI0UjC2/SODbgDOWC6Hk4nGZvmJG3ari9j2lqOvYnfSisqV//OlA4H00swf+j X-Received: by 2002:a17:902:2d:: with SMTP id 42mr36733392pla.34.1559654286846; Tue, 04 Jun 2019 06:18:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1559654286; cv=none; d=google.com; s=arc-20160816; b=uKtj8jMkO2F/wDYHkaZScocpt+RaPpwOvH7ALV3SrOFi8tn/TgNLo/vYby6RTnKDD+ EDAkTNmYqS5ok/7Dunhxoo26dVHXvqULLPGK08Roq4x194dJMd3dvTSTEdCHqTGFnj1s GsU2c28HCPER1qjK2VcXpaKFIpqfJHmYBG+OTQ9wPdMUQGCXCiAbnnsVmCJeLSOw1oFF f3Dy4yp3ffGx26G7LmsfSpaQdgKxYwtiUukbim/kyw3Upk7mkuh2k7ocMCVsDKtpUrOc hzoCmowPOjuqSYkXtFeIfqmaxREuhuHj7ICAk9i29auXnkwmO9XTY3z/hhTSgeLa3+sw UsRA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=t0jA6IyzaKFpaRxG+xMzbQ3TeSZ/biJLiuqhdnBH3TQ=; b=QoXTeTcYPmjnZPq9sH7iIJ7bAay0YZIfK1c4Sv+BFNZqR8paao3vSKFrDtMP4OAnSn S2YmJ2RfVilCTRfv1ch0nwO8WSKQd8ISJPvyhPIBCW7miEySdLZ2jqb75dYwzitW0fTn 6C/2WAkGCHK/S5QSPYYHUWbgcWzVFqPH909dJnD/V0NELNRXYlF2xDqR7h0jGDQ88iBI ryts2z3hdjseG4D7CkwjPpODbZ5sAlXpipt4oXVsmYSjqhgMIy3Z00SEb8/6Ca9lwsh9 b7oVtKDcoCw03k65hr7dQNdUdjmUVxDSbv5ZGMU1C6vp7ib9AEuUaEVrWzu+kAx5OV7G QhXg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="KZr/Yb1n"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id j17si25536146pfn.226.2019.06.04.06.18.06; Tue, 04 Jun 2019 06:18:06 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="KZr/Yb1n"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727667AbfFDNSF (ORCPT + 30 others); Tue, 4 Jun 2019 09:18:05 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:50382 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727265AbfFDNSE (ORCPT ); Tue, 4 Jun 2019 09:18:04 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x54DHktZ082389; Tue, 4 Jun 2019 08:17:46 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1559654266; bh=t0jA6IyzaKFpaRxG+xMzbQ3TeSZ/biJLiuqhdnBH3TQ=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=KZr/Yb1n2JCx1xdXk+5fWxz251JLI16pKngaDfG2QC6hGXVLV4i5gvy6cCgIsJMjP c4WNdd1kbTd+yYCRuS/k+h6OJjnmI4OPZi0H3EJWyU1J15IIwDqImxqx57wu5Udo9Z bvFpZC/srm1v2Mm4BAhsZsXo0/fnO3zxZwm++kmk= Received: from DLEE104.ent.ti.com (dlee104.ent.ti.com [157.170.170.34]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x54DHkn2042937 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 4 Jun 2019 08:17:46 -0500 Received: from DLEE107.ent.ti.com (157.170.170.37) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Tue, 4 Jun 2019 08:17:46 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Tue, 4 Jun 2019 08:17:46 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x54DGdGR098972; Tue, 4 Jun 2019 08:17:41 -0500 From: Kishon Vijay Abraham I To: Tom Joseph , Bjorn Helgaas , Rob Herring , Mark Rutland , Lorenzo Pieralisi , Arnd Bergmann , Gustavo Pimentel CC: Greg Kroah-Hartman , Frank Rowand , Jingoo Han , , , , , , , Kishon Vijay Abraham I Subject: [RFC PATCH 11/30] PCI: cadence: Add support to drive PERST# line using GPIO Date: Tue, 4 Jun 2019 18:44:57 +0530 Message-ID: <20190604131516.13596-12-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190604131516.13596-1-kishon@ti.com> References: <20190604131516.13596-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org In platforms like TI's J721E EVM, the PERST# line is connected to a GPIO line and PERST# should be driven high to indicate the clocks are stable (As per Figure 2-10: Power Up of the PCIe CEM spec 3.0). Add support to make GPIO drive PERST# line. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/pcie-cadence-host.c | 26 ++++++++++++++++++++++ 1 file changed, 26 insertions(+) -- 2.17.1 diff --git a/drivers/pci/controller/pcie-cadence-host.c b/drivers/pci/controller/pcie-cadence-host.c index 4ad8f2ece6e2..8b3b9827a8d6 100644 --- a/drivers/pci/controller/pcie-cadence-host.c +++ b/drivers/pci/controller/pcie-cadence-host.c @@ -3,6 +3,8 @@ // Cadence PCIe host controller driver. // Author: Cyrille Pitchen +#include +#include #include #include #include @@ -287,6 +289,7 @@ static int cdns_pcie_host_probe(struct platform_device *pdev) struct pci_host_bridge *bridge; struct list_head resources; struct cdns_pcie_rc *rc; + struct gpio_desc *gpiod; struct cdns_pcie *pcie; struct resource *res; int ret; @@ -349,13 +352,36 @@ static int cdns_pcie_host_probe(struct platform_device *pdev) dev_err(dev, "missing \"mem\"\n"); return -EINVAL; } + pcie->mem_res = res; + gpiod = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); + if (IS_ERR(gpiod)) { + ret = PTR_ERR(gpiod); + if (ret != -EPROBE_DEFER) + dev_err(dev, "Failed to get reset GPIO\n"); + return ret; + } + ret = cdns_pcie_init_phy(dev, pcie); if (ret) { dev_err(dev, "failed to init phy\n"); return ret; } + + /* + * "Power Sequencing and Reset Signal Timings" table in + * PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 3.0 + * indicates PERST# should be deasserted after minimum of 100us + * once REFCLK is stable. The REFCLK to the connector in RC + * mode is selected while enabling the PHY. So deassert PERST# + * after 100 us. + */ + if (gpiod) { + usleep_range(100, 200); + gpiod_set_value_cansleep(gpiod, 1); + } + platform_set_drvdata(pdev, pcie); pm_runtime_enable(dev); From patchwork Tue Jun 4 13:14:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 165779 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp5843924ili; Tue, 4 Jun 2019 06:18:49 -0700 (PDT) X-Google-Smtp-Source: APXvYqx9C7OD5wNqq4ou2rDijx+Akdb+n89tyWDpCG2oV5vdKGovx5prmJmG0C8y99yMuxrqueMR X-Received: by 2002:a65:5203:: with SMTP id o3mr35002366pgp.379.1559654329329; Tue, 04 Jun 2019 06:18:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1559654329; cv=none; d=google.com; s=arc-20160816; b=s1RQOGxthHI1XE9tJzAlqd8Ry/q7z/bvUre1cU8rAKzCCwjxidijs6BmUCXsPsd2sc 7wvu1W9wDOPIMdsNJnMjx/6LEtyrW/9M1EOT3VrNe7/mUMye4pYRBLwCZ3QrjK2rsiuR LKNuEnrNtcbPANrelcz1btBfzFHFHsgJ9l9Ac5wpgtbcD9CGgNlK3IPCaBqRiVyH0VRr y6K55xXqT6OZ8cg7tsjFv/6zvndUAa7QQ0eHH9YlLWscwm5ga9ii6WSwOuvR6dcuTbED Gk7BHKAxav6C+JvR0aKoOEzNEtM4+XqbXy/UA9jnkBlqu+SgG5exsSYd2Ewju8RbHw2I OWYg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=hQ9HPR/YNox9fBqati4GtPS+LZvZ2MYHAw9Ko10HNPY=; b=U17sIjP2wU1rkfIlGIFLcNPrnsQhz8iTDt13+sKqWbd9IqN/ttGQxsBDmvCjRluxyt /crqtIZgBy0NSN0lqSfMyS8rQwnSI3zG90ptsLRxKDe9RbDsZDDA3ctpfWlvW84IlQM3 NY8eC+kwo59ZFdwKvn8AkUb8gVDy3BHEbamvtijEav7sWTJTtUvX1fMizQLmJQELtb5c AQJFVq60L6KzYP46HpLO+F0UpfzgJvH8v7kI+Z91A5rzqcthRZMEcQ1jP41mi0Xwm/ER xWiEAPDWarUK14pRRWRNXfcdzTjI9Vu4eMOesANUM/Rwr1iBX3yEQ3xhXeHnx7JPgSmV WHXg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=k8e6kTrr; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s17si10657627pfc.237.2019.06.04.06.18.48; Tue, 04 Jun 2019 06:18:49 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=k8e6kTrr; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727828AbfFDNSs (ORCPT + 30 others); Tue, 4 Jun 2019 09:18:48 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:50526 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727182AbfFDNSp (ORCPT ); Tue, 4 Jun 2019 09:18:45 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x54DHvTf082410; Tue, 4 Jun 2019 08:17:57 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1559654277; bh=hQ9HPR/YNox9fBqati4GtPS+LZvZ2MYHAw9Ko10HNPY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=k8e6kTrrmF72/kBZGQIod8qTZwihPV4aZ7b6UParflsTqEHLhIBBgqfKgXbiSKFfT /2nMeOosqgIMPvkzcYTcW/rWAfjjpkmYtSt1+zNJ+EQ2m0uBvLHNU0PvwdaklQMnxG VR4Y7UOIGYZdHCVyepenhJQNIhP+ZJJlHm9Rf7v4= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x54DHvkL001773 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 4 Jun 2019 08:17:57 -0500 Received: from DFLE107.ent.ti.com (10.64.6.28) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Tue, 4 Jun 2019 08:17:57 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Tue, 4 Jun 2019 08:17:57 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x54DGdGT098972; Tue, 4 Jun 2019 08:17:52 -0500 From: Kishon Vijay Abraham I To: Tom Joseph , Bjorn Helgaas , Rob Herring , Mark Rutland , Lorenzo Pieralisi , Arnd Bergmann , Gustavo Pimentel CC: Greg Kroah-Hartman , Frank Rowand , Jingoo Han , , , , , , , Kishon Vijay Abraham I Subject: [RFC PATCH 13/30] PCI: cadence: Use local management register to configure Vendor ID Date: Tue, 4 Jun 2019 18:44:59 +0530 Message-ID: <20190604131516.13596-14-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190604131516.13596-1-kishon@ti.com> References: <20190604131516.13596-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org PCI_VENDOR_ID in root port configuration space is read-only register and writing to it will have no effect. Use local management register to configure Vendor ID and Subsystem Vendor ID. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/pcie-cadence-host.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/pcie-cadence-host.c b/drivers/pci/controller/pcie-cadence-host.c index 14a54f6a11de..dcecf47805ad 100644 --- a/drivers/pci/controller/pcie-cadence-host.c +++ b/drivers/pci/controller/pcie-cadence-host.c @@ -148,6 +148,7 @@ static int cdns_pcie_host_init_root_port(struct cdns_pcie_rc *rc) { struct cdns_pcie *pcie = &rc->pcie; u32 value, ctrl; + u32 id; /* * Set the root complex BAR configuration register: @@ -167,8 +168,12 @@ static int cdns_pcie_host_init_root_port(struct cdns_pcie_rc *rc) cdns_pcie_writel(pcie, CDNS_PCIE_LM_RC_BAR_CFG, value); /* Set root port configuration space */ - if (rc->vendor_id != 0xffff) - cdns_pcie_rp_writew(pcie, PCI_VENDOR_ID, rc->vendor_id); + if (rc->vendor_id != 0xffff) { + id = CDNS_PCIE_LM_ID_VENDOR(rc->vendor_id) | + CDNS_PCIE_LM_ID_SUBSYS(rc->vendor_id); + cdns_pcie_writel(pcie, CDNS_PCIE_LM_ID, id); + } + if (rc->device_id != 0xffff) cdns_pcie_rp_writew(pcie, PCI_DEVICE_ID, rc->device_id); From patchwork Tue Jun 4 13:15:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 165783 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp5844392ili; Tue, 4 Jun 2019 06:19:09 -0700 (PDT) X-Google-Smtp-Source: APXvYqzxYsIPhDP6acZZ3+fLWPYxlAV94FIJ9bOtDQge1ZaNisTJIVMKpwp85BYZw3/vX7wpZx3g X-Received: by 2002:a62:7995:: with SMTP id u143mr38514938pfc.61.1559654349523; Tue, 04 Jun 2019 06:19:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1559654349; cv=none; d=google.com; s=arc-20160816; b=FYM/tsbSzEYyoQ8cC8Sb82J7irDHtyoIOMUAnEJlK1azxsGRqeC7dMzHJdr95CEBrp dJa0lIFHzrdMGmAg2Q3CMvcV76uo1FJYBwmsodUf5jk25xDlx9fikFxZnDVmysCnLJIH kJQYUfe1qveNJsPsF4UgkRLKcYGJ1JEUsdvsZvjK+U605t4Ph+e6kpOw4+ZLIiZbHTrb irqNhRKfyLKvDujUqSM7GkUxjVlvNS7qChvQynxc68rqlagy/9yL9Yny6Z9J29gYp0DC tt5Z6zlGWz6E/+s/Kw9SMtV9OWnz6gBAHQXhEj/qQSxY8CzjZgCU35zsMhGR/sdNtXpv ml4w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=iGGz8aJS305f8zkEMQQLmC9ZNt7J1jEUCbTcSQRPp8c=; b=sx6d6Ogp9Egfiv8ofMucbITKhfzdAzWJSvTAV5Jq0/kZ655bwLT4cJ+vtbcqoMG06w 8QIdtwOeoWuLsHeaTwf6TIJ8NlWmBzqu+AgvpmI3k3/eX3R52PZRRsxLrt5Em8mibyFR BriUseoDyerRONDjzQ4jCnhUzAvMmZ+lvI9ShKOjOzAROE+rWoIsutTz29JnEHOQLFES TrW98uUTnGspvVMbFmUCM/mB1mQQk4cxS+n3jLEXLjq1icJdIvn59L8BOdsTrTN2+b54 DTg/WZMxq0i3Vm/s1OI9DPQTPi6XkT6EmGpvPNUDwPgFkGbnoz5HEbMLAkhKBUaVrbym qmWg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=N8jkDEwp; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f4si19841722pgo.216.2019.06.04.06.19.09; Tue, 04 Jun 2019 06:19:09 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=N8jkDEwp; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727888AbfFDNTH (ORCPT + 30 others); Tue, 4 Jun 2019 09:19:07 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:39376 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727458AbfFDNTC (ORCPT ); Tue, 4 Jun 2019 09:19:02 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x54DIEoq119974; Tue, 4 Jun 2019 08:18:14 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1559654294; bh=iGGz8aJS305f8zkEMQQLmC9ZNt7J1jEUCbTcSQRPp8c=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=N8jkDEwpWuoOdA9t6AYdQYMuDLTffL+VUteLJp1OVzUM3ExXPoBOaemiDe1fXwRLR Glb+o8SJQmgSkmPXTcE5fy+Tosxatv+/DcmsyY7omogGVF2OYIUCZp5iShHHYCT7rO lpwRrvi1TP5cLGxqyTOADGGeWmDgY/RHw4XiW754= Received: from DLEE103.ent.ti.com (dlee103.ent.ti.com [157.170.170.33]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x54DIENZ009122 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 4 Jun 2019 08:18:14 -0500 Received: from DLEE106.ent.ti.com (157.170.170.36) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Tue, 4 Jun 2019 08:18:14 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Tue, 4 Jun 2019 08:18:14 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x54DGdGW098972; Tue, 4 Jun 2019 08:18:09 -0500 From: Kishon Vijay Abraham I To: Tom Joseph , Bjorn Helgaas , Rob Herring , Mark Rutland , Lorenzo Pieralisi , Arnd Bergmann , Gustavo Pimentel CC: Greg Kroah-Hartman , Frank Rowand , Jingoo Han , , , , , , , Kishon Vijay Abraham I Subject: [RFC PATCH 16/30] PCI: endpoint: Assign function number of each PF in EPC core Date: Tue, 4 Jun 2019 18:45:02 +0530 Message-ID: <20190604131516.13596-17-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190604131516.13596-1-kishon@ti.com> References: <20190604131516.13596-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The endpoint core relies on the drivers that invoke the API to bind a controller driver with a function driver to allocate and assign a function number to each physical function. Ideally the function numbers should be assinged by EPC core for each of the physical function that is bound to the EPC. Assign function number of each PF in EPC core and remove function number allocation in endpoint configfs. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/endpoint/pci-ep-cfs.c | 27 +++++---------------------- drivers/pci/endpoint/pci-epc-core.c | 12 +++++++++++- include/linux/pci-epc.h | 2 ++ 3 files changed, 18 insertions(+), 23 deletions(-) -- 2.17.1 diff --git a/drivers/pci/endpoint/pci-ep-cfs.c b/drivers/pci/endpoint/pci-ep-cfs.c index d1288a0bd530..e7e8367eead1 100644 --- a/drivers/pci/endpoint/pci-ep-cfs.c +++ b/drivers/pci/endpoint/pci-ep-cfs.c @@ -29,7 +29,6 @@ struct pci_epc_group { struct config_group group; struct pci_epc *epc; bool start; - unsigned long function_num_map; }; static inline struct pci_epf_group *to_pci_epf_group(struct config_item *item) @@ -89,37 +88,22 @@ static int pci_epc_epf_link(struct config_item *epc_item, struct config_item *epf_item) { int ret; - u32 func_no = 0; struct pci_epf_group *epf_group = to_pci_epf_group(epf_item); struct pci_epc_group *epc_group = to_pci_epc_group(epc_item); struct pci_epc *epc = epc_group->epc; struct pci_epf *epf = epf_group->epf; - func_no = find_first_zero_bit(&epc_group->function_num_map, - BITS_PER_LONG); - if (func_no >= BITS_PER_LONG) - return -EINVAL; - - set_bit(func_no, &epc_group->function_num_map); - epf->func_no = func_no; - ret = pci_epc_add_epf(epc, epf); if (ret) - goto err_add_epf; + return ret; ret = pci_epf_bind(epf); - if (ret) - goto err_epf_bind; + if (ret) { + pci_epc_remove_epf(epc, epf); + return ret; + } return 0; - -err_epf_bind: - pci_epc_remove_epf(epc, epf); - -err_add_epf: - clear_bit(func_no, &epc_group->function_num_map); - - return ret; } static void pci_epc_epf_unlink(struct config_item *epc_item, @@ -134,7 +118,6 @@ static void pci_epc_epf_unlink(struct config_item *epc_item, epc = epc_group->epc; epf = epf_group->epf; - clear_bit(epf->func_no, &epc_group->function_num_map); pci_epf_unbind(epf); pci_epc_remove_epf(epc, epf); } diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c index eea07f9ec5ff..e5d8d8370686 100644 --- a/drivers/pci/endpoint/pci-epc-core.c +++ b/drivers/pci/endpoint/pci-epc-core.c @@ -471,6 +471,8 @@ EXPORT_SYMBOL_GPL(pci_epc_write_header); */ int pci_epc_add_epf(struct pci_epc *epc, struct pci_epf *epf) { + u32 func_no = 0; + if (epf->epc) return -EBUSY; @@ -480,9 +482,16 @@ int pci_epc_add_epf(struct pci_epc *epc, struct pci_epf *epf) if (epf->func_no > epc->max_functions - 1) return -EINVAL; + mutex_lock(&epc->lock); + func_no = find_first_zero_bit(&epc->function_num_map, + BITS_PER_LONG); + if (func_no >= BITS_PER_LONG) + return -EINVAL; + + set_bit(func_no, &epc->function_num_map); + epf->func_no = func_no; epf->epc = epc; - mutex_lock(&epc->lock); list_add_tail(&epf->list, &epc->pci_epf); mutex_unlock(&epc->lock); @@ -503,6 +512,7 @@ void pci_epc_remove_epf(struct pci_epc *epc, struct pci_epf *epf) return; mutex_lock(&epc->lock); + clear_bit(epf->func_no, &epc->function_num_map); list_del(&epf->list); mutex_unlock(&epc->lock); } diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h index a430d02aa1ff..ad118a3f1330 100644 --- a/include/linux/pci-epc.h +++ b/include/linux/pci-epc.h @@ -89,6 +89,7 @@ struct pci_epc_mem { * @max_functions: max number of functions that can be configured in this EPC * @group: configfs group representing the PCI EPC device * @lock: mutex to protect pci_epc ops + * @function_num_map: bitmap to manage physical function number * @notifier: used to notify EPF of any EPC events (like linkup) */ struct pci_epc { @@ -100,6 +101,7 @@ struct pci_epc { struct config_group *group; /* mutex to protect against concurrent access of EP controller */ struct mutex lock; + unsigned long function_num_map; struct atomic_notifier_head notifier; }; From patchwork Tue Jun 4 13:15:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 165777 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp5843683ili; Tue, 4 Jun 2019 06:18:38 -0700 (PDT) X-Google-Smtp-Source: APXvYqyJ0MDUdr4WQzbk+HmnCiOVo8q/Lbv9fMxXKBJwqnLskV8GBTbUMJ7xNL09sZF5J1VfZ2k3 X-Received: by 2002:a63:4754:: with SMTP id w20mr34940587pgk.31.1559654317861; Tue, 04 Jun 2019 06:18:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1559654317; cv=none; d=google.com; s=arc-20160816; b=FzsBuGx7d1PXQ2Qe59uf8dZbbOCvL7Vz9HA/BGZmoYtrRhLjWjFGMEXBqqiPpd2hIa zFe1icYdyAWqAKBhG52fxvAKCYx952s4ZinJmf7x6hm1rHyE4ACFuZHkIzs1ahc576ZS dcWBlGzIlowR/+fKZZL74fxzNgNZECG/eK3aKI+QfB7+mZ8CzqHeEi+neAn1suRze3vC fOGetXeWXYohBvSlDHM70ukPQrPyp6NCjuUOIoOdhrHVWwBrpo+tsAa+XTVC9jIsBSlm HiL9i66rbgjJWpuQ3Sjrk4BykwG+04cH88giBHu9f9n2kgulkq87MmwdnpqVAVmaCXD9 ehbQ== ARC-Message-Signature: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id e96si23950996plb.123.2019.06.04.06.18.37; Tue, 04 Jun 2019 06:18:37 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=wna+KbYt; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727767AbfFDNSg (ORCPT + 30 others); Tue, 4 Jun 2019 09:18:36 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:39336 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727182AbfFDNSf (ORCPT ); Tue, 4 Jun 2019 09:18:35 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x54DIKwr120006; Tue, 4 Jun 2019 08:18:20 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1559654300; bh=oIzF4wPqwNRg9UTf2H8Siu9HoiPwFp65VY06zJhiVqk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=wna+KbYt+4VB/bLdy1bkRaCyULLvGVx/mI+oJUkghKX4lGJWopq+C4sXX9eMeiSpx O5qN4L99Jrr4vwmjyI4vpeX2RsUM7jj7GTW7lxK0KgEuwSBzV+lB1qycprJVS2u0O0 +m8ljAtaLaKCE72BeDwTxsNujVHrS3BOUK1eWMjQ= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x54DIKlP053724 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 4 Jun 2019 08:18:20 -0500 Received: from DLEE102.ent.ti.com (157.170.170.32) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Tue, 4 Jun 2019 08:18:19 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Tue, 4 Jun 2019 08:18:19 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x54DGdGX098972; Tue, 4 Jun 2019 08:18:14 -0500 From: Kishon Vijay Abraham I To: Tom Joseph , Bjorn Helgaas , Rob Herring , Mark Rutland , Lorenzo Pieralisi , Arnd Bergmann , Gustavo Pimentel CC: Greg Kroah-Hartman , Frank Rowand , Jingoo Han , , , , , , , Kishon Vijay Abraham I Subject: [RFC PATCH 17/30] PCI: endpoint: Protect concurrent access to pci_epf_ops with mutex Date: Tue, 4 Jun 2019 18:45:03 +0530 Message-ID: <20190604131516.13596-18-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190604131516.13596-1-kishon@ti.com> References: <20190604131516.13596-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Protect concurrent access to pci_epf_ops with mutex. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/endpoint/pci-epf-core.c | 11 ++++++++++- include/linux/pci-epf.h | 3 +++ 2 files changed, 13 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/drivers/pci/endpoint/pci-epf-core.c b/drivers/pci/endpoint/pci-epf-core.c index 93f28c65ace0..6e0648991b5c 100644 --- a/drivers/pci/endpoint/pci-epf-core.c +++ b/drivers/pci/endpoint/pci-epf-core.c @@ -35,7 +35,9 @@ void pci_epf_unbind(struct pci_epf *epf) return; } + mutex_lock(&epf->lock); epf->driver->ops->unbind(epf); + mutex_unlock(&epf->lock); module_put(epf->driver->owner); } EXPORT_SYMBOL_GPL(pci_epf_unbind); @@ -49,6 +51,8 @@ EXPORT_SYMBOL_GPL(pci_epf_unbind); */ int pci_epf_bind(struct pci_epf *epf) { + int ret; + if (!epf->driver) { dev_WARN(&epf->dev, "epf device not bound to driver\n"); return -EINVAL; @@ -57,7 +61,11 @@ int pci_epf_bind(struct pci_epf *epf) if (!try_module_get(epf->driver->owner)) return -EAGAIN; - return epf->driver->ops->bind(epf); + mutex_lock(&epf->lock); + ret = epf->driver->ops->bind(epf); + mutex_unlock(&epf->lock); + + return ret; } EXPORT_SYMBOL_GPL(pci_epf_bind); @@ -252,6 +260,7 @@ struct pci_epf *pci_epf_create(const char *name) device_initialize(dev); dev->bus = &pci_epf_bus_type; dev->type = &pci_epf_type; + mutex_init(&epf->lock); ret = dev_set_name(dev, "%s", name); if (ret) { diff --git a/include/linux/pci-epf.h b/include/linux/pci-epf.h index 4993f7f6439b..bcdf4f07bde7 100644 --- a/include/linux/pci-epf.h +++ b/include/linux/pci-epf.h @@ -110,6 +110,7 @@ struct pci_epf_bar { * @driver: the EPF driver to which this EPF device is bound * @list: to add pci_epf as a list of PCI endpoint functions to pci_epc * @nb: notifier block to notify EPF of any EPC events (like linkup) + * @lock: mutex to protect pci_epf_ops */ struct pci_epf { struct device dev; @@ -124,6 +125,8 @@ struct pci_epf { struct pci_epf_driver *driver; struct list_head list; struct notifier_block nb; + /* mutex to protect against concurrent access of pci_epf_ops */ + struct mutex lock; }; #define to_pci_epf(epf_dev) container_of((epf_dev), struct pci_epf, dev) From patchwork Tue Jun 4 13:15:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 165789 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp5845035ili; Tue, 4 Jun 2019 06:19:36 -0700 (PDT) X-Google-Smtp-Source: APXvYqx/aX1jRM8vatu2oTemWsCJat2amEWpRb5wKj7FbEuZJbBHgldzAqhNK55R/+QrF94LOZO9 X-Received: by 2002:a63:474a:: with SMTP id w10mr17756471pgk.352.1559654376015; Tue, 04 Jun 2019 06:19:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1559654376; cv=none; d=google.com; s=arc-20160816; b=OFycDqRdA47TOIAahSU7ZSlc2Q1GZ5Rgfk40zd/2vxm5onQIx4BkB5wj+pRxrvkamQ mb+Ltz69BZsaAM6uL9gDBSyiZeKX3LCIRxHV191425wXs/+nTjUNtV7//MVcIYhJ5lgS CqVbY2T066mDk7H0XJVwSgjZ65RgYBLjTpYqkW9SFPpJU3XO3W1YJj/FByc4e1FnbT8u GWbqmHsYMH90UfOgJTxBh6tblE98tJ1zcdckQG16E5OQXHWTbaaX24w48X4nYmAFUnGD 94QxyAs6X2IrYFURr1F7Ao5bQrlUmXiEug8pJQ3sDdA4LOFFj6VAn95Kb/pzWWW6z1qW 5haA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=RpjO9P/fHn964nb8jzwtD2iddPRG/sW3iiZvbwqx5/0=; b=KhmN/JoaWlDEAZxglv7nzHiTBw4aXgJnxZha6igfWGCIhulpnT0LKX/EJGM5QdCofB zuyRkxJh0yPj4rHym1uJxSWlQA8zoavOaW95nwAgHYoIHirVFNOLH2FQAlzmFlPBeAYd NTr3eD4pBcKelJx1CjMnG5WumoBrrGssXjikGMI6bU7u2zp29PYUZuTHOp4D0/yR12Z4 pMh45mz4ru02UhQEtuILFDP4WVPgAx2LUIOCwOM8MpIrGwyduTUrt1VKqerdhBM94qKU Ojv7pD1NQuEhQx1HsvqREoJu6T8FSpD2LtVpduzCeSFL9LjvcsyP3TJdysdea76adWBI vqVg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=wEBHLMMs; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/pcie-cadence-ep.c | 104 ++++++++++++++++++++--- drivers/pci/controller/pcie-cadence.h | 5 ++ 2 files changed, 98 insertions(+), 11 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/pcie-cadence-ep.c b/drivers/pci/controller/pcie-cadence-ep.c index df8fc495ffd9..3dc1a896c1e6 100644 --- a/drivers/pci/controller/pcie-cadence-ep.c +++ b/drivers/pci/controller/pcie-cadence-ep.c @@ -53,7 +53,18 @@ static int cdns_pcie_ep_write_header(struct pci_epc *epc, u8 fn, u8 vfn, struct pci_epf_header *hdr) { struct cdns_pcie_ep *ep = epc_get_drvdata(epc); + u32 cap = CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET; struct cdns_pcie *pcie = &ep->pcie; + u32 reg; + + if (vfn > 1) { + dev_dbg(&epc->dev, "Only Virtual Function #1 has deviceID\n"); + return 0; + } else if (vfn == 1) { + reg = cap + PCI_SRIOV_VF_DID; + cdns_pcie_ep_fn_writew(pcie, fn, reg, hdr->deviceid); + return 0; + } cdns_pcie_ep_fn_writew(pcie, fn, PCI_DEVICE_ID, hdr->deviceid); cdns_pcie_ep_fn_writeb(pcie, fn, PCI_REVISION_ID, hdr->revid); @@ -84,11 +95,13 @@ static int cdns_pcie_ep_set_bar(struct pci_epc *epc, u8 fn, u8 vfn, struct pci_epf_bar *epf_bar) { struct cdns_pcie_ep *ep = epc_get_drvdata(epc); + u32 cap = CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET; struct cdns_pcie *pcie = &ep->pcie; dma_addr_t bar_phys = epf_bar->phys_addr; enum pci_barno bar = epf_bar->barno; int flags = epf_bar->flags; u32 addr0, addr1, reg, cfg, b, aperture, ctrl; + u32 first_vf_offset, stride; u64 sz; /* BAR size is 2^(aperture + 7) */ @@ -124,19 +137,38 @@ static int cdns_pcie_ep_set_bar(struct pci_epc *epc, u8 fn, u8 vfn, addr0 = lower_32_bits(bar_phys); addr1 = upper_32_bits(bar_phys); + + if (vfn == 1) { + if (bar < BAR_4) { + reg = CDNS_PCIE_LM_EP_VFUNC_BAR_CFG0(fn); + b = bar; + } else { + reg = CDNS_PCIE_LM_EP_VFUNC_BAR_CFG1(fn); + b = bar - BAR_4; + } + } else { + if (bar < BAR_4) { + reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn); + b = bar; + } else { + reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn); + b = bar - BAR_4; + } + } + + if (vfn > 0) { + first_vf_offset = cdns_pcie_ep_fn_readw(pcie, fn, cap + + PCI_SRIOV_VF_OFFSET); + stride = cdns_pcie_ep_fn_readw(pcie, fn, cap + + PCI_SRIOV_VF_STRIDE); + fn = fn + first_vf_offset + ((vfn - 1) * stride); + } + cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar), addr0); cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar), addr1); - if (bar < BAR_4) { - reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn); - b = bar; - } else { - reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn); - b = bar - BAR_4; - } - cfg = cdns_pcie_readl(pcie, reg); cfg &= ~(CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) | CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b)); @@ -179,8 +211,18 @@ static int cdns_pcie_ep_map_addr(struct pci_epc *epc, u8 fn, u8 vfn, { struct cdns_pcie_ep *ep = epc_get_drvdata(epc); struct cdns_pcie *pcie = &ep->pcie; + u32 cap = CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET; + u32 first_vf_offset, stride; u32 r; + if (vfn > 0) { + first_vf_offset = cdns_pcie_ep_fn_readw(pcie, fn, cap + + PCI_SRIOV_VF_OFFSET); + stride = cdns_pcie_ep_fn_readw(pcie, fn, cap + + PCI_SRIOV_VF_STRIDE); + fn = fn + first_vf_offset + ((vfn - 1) * stride); + } + r = find_first_zero_bit(&ep->ob_region_map, sizeof(ep->ob_region_map) * BITS_PER_LONG); if (r >= ep->max_regions - 1) { @@ -220,9 +262,19 @@ static int cdns_pcie_ep_set_msi(struct pci_epc *epc, u8 fn, u8 vfn, u8 mmc) { struct cdns_pcie_ep *ep = epc_get_drvdata(epc); struct cdns_pcie *pcie = &ep->pcie; + u32 sriov_cap = CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET; u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET; + u32 first_vf_offset, stride; u16 flags; + if (vfn > 0) { + first_vf_offset = cdns_pcie_ep_fn_readw(pcie, fn, sriov_cap + + PCI_SRIOV_VF_OFFSET); + stride = cdns_pcie_ep_fn_readw(pcie, fn, sriov_cap + + PCI_SRIOV_VF_STRIDE); + fn = fn + first_vf_offset + ((vfn - 1) * stride); + } + /* * Set the Multiple Message Capable bitfield into the Message Control * register. @@ -240,9 +292,19 @@ static int cdns_pcie_ep_get_msi(struct pci_epc *epc, u8 fn, u8 vfn) { struct cdns_pcie_ep *ep = epc_get_drvdata(epc); struct cdns_pcie *pcie = &ep->pcie; + u32 sriov_cap = CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET; u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET; + u32 first_vf_offset, stride; u16 flags, mme; + if (vfn > 0) { + first_vf_offset = cdns_pcie_ep_fn_readw(pcie, fn, sriov_cap + + PCI_SRIOV_VF_OFFSET); + stride = cdns_pcie_ep_fn_readw(pcie, fn, sriov_cap + + PCI_SRIOV_VF_STRIDE); + fn = fn + first_vf_offset + ((vfn - 1) * stride); + } + /* Validate that the MSI feature is actually enabled. */ flags = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS); if (!(flags & PCI_MSI_FLAGS_ENABLE)) @@ -257,7 +319,7 @@ static int cdns_pcie_ep_get_msi(struct pci_epc *epc, u8 fn, u8 vfn) return mme; } -static void cdns_pcie_ep_assert_intx(struct cdns_pcie_ep *ep, u8 fn, +static void cdns_pcie_ep_assert_intx(struct cdns_pcie_ep *ep, u8 fn, u8 vfn, u8 intx, bool is_asserted) { struct cdns_pcie *pcie = &ep->pcie; @@ -320,10 +382,20 @@ static int cdns_pcie_ep_send_msi_irq(struct cdns_pcie_ep *ep, u8 fn, u8 vfn, u8 interrupt_num) { struct cdns_pcie *pcie = &ep->pcie; + u32 sriov_cap = CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET; u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET; u16 flags, mme, data, data_mask; u8 msi_count; u64 pci_addr, pci_addr_mask = 0xff; + u32 first_vf_offset, stride; + + if (vfn > 0) { + first_vf_offset = cdns_pcie_ep_fn_readw(pcie, fn, sriov_cap + + PCI_SRIOV_VF_OFFSET); + stride = cdns_pcie_ep_fn_readw(pcie, fn, sriov_cap + + PCI_SRIOV_VF_STRIDE); + fn = fn + first_vf_offset + ((vfn - 1) * stride); + } /* Check whether the MSI feature has been enabled by the PCI host. */ flags = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS); @@ -364,7 +436,7 @@ static int cdns_pcie_ep_send_msi_irq(struct cdns_pcie_ep *ep, u8 fn, u8 vfn, return 0; } -static int cdns_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn, +static int cdns_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn, u8 vfn, enum pci_epc_irq_type type, u16 interrupt_num) { @@ -414,10 +486,20 @@ static const struct pci_epc_features cdns_pcie_epc_features = { .msix_capable = false, }; +static const struct pci_epc_features cdns_pcie_epc_vf_features = { + .linkup_notifier = false, + .msi_capable = true, + .msix_capable = true, + .align = 65536, +}; + static const struct pci_epc_features* cdns_pcie_ep_get_features(struct pci_epc *epc, u8 func_no, u8 vfunc_no) { - return &cdns_pcie_epc_features; + if (!vfunc_no) + return &cdns_pcie_epc_features; + + return &cdns_pcie_epc_vf_features; } static const struct pci_epc_ops cdns_pcie_epc_ops = { diff --git a/drivers/pci/controller/pcie-cadence.h b/drivers/pci/controller/pcie-cadence.h index 3cef398b50da..8237847bbc4e 100644 --- a/drivers/pci/controller/pcie-cadence.h +++ b/drivers/pci/controller/pcie-cadence.h @@ -50,6 +50,10 @@ (CDNS_PCIE_LM_BASE + 0x0240 + (fn) * 0x0008) #define CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn) \ (CDNS_PCIE_LM_BASE + 0x0244 + (fn) * 0x0008) +#define CDNS_PCIE_LM_EP_VFUNC_BAR_CFG0(fn) \ + (CDNS_PCIE_LM_BASE + 0x0280 + (fn) * 0x0008) +#define CDNS_PCIE_LM_EP_VFUNC_BAR_CFG1(fn) \ + (CDNS_PCIE_LM_BASE + 0x0284 + (fn) * 0x0008) #define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) \ (GENMASK(4, 0) << ((b) * 8)) #define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, a) \ @@ -99,6 +103,7 @@ #define CDNS_PCIE_EP_FUNC_BASE(fn) (((fn) << 12) & GENMASK(19, 12)) #define CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET 0x90 +#define CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET 0x200 /* * Root Port Registers (PCI configuration space for the root port function) From patchwork Tue Jun 4 13:15:09 2019 Content-Type: text/plain; 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This can be used by platform specific driver to send platform data core driver. For e.g., this will be used by TI's J721E SoC specific PCIe driver to send ->start_link() ops and ->is_link_up() ops to Cadence core PCIe driver. Signed-off-by: Kishon Vijay Abraham I --- drivers/of/platform.c | 9 ++++----- include/linux/of_platform.h | 3 +++ 2 files changed, 7 insertions(+), 5 deletions(-) -- 2.17.1 diff --git a/drivers/of/platform.c b/drivers/of/platform.c index 04ad312fd85b..94e0f733461a 100644 --- a/drivers/of/platform.c +++ b/drivers/of/platform.c @@ -169,11 +169,9 @@ EXPORT_SYMBOL(of_device_alloc); * Returns pointer to created platform device, or NULL if a device was not * registered. Unavailable devices will not get registered. */ -static struct platform_device *of_platform_device_create_pdata( - struct device_node *np, - const char *bus_id, - void *platform_data, - struct device *parent) +struct platform_device * +of_platform_device_create_pdata(struct device_node *np, const char *bus_id, + void *platform_data, struct device *parent) { struct platform_device *dev; @@ -203,6 +201,7 @@ static struct platform_device *of_platform_device_create_pdata( of_node_clear_flag(np, OF_POPULATED); return NULL; } +EXPORT_SYMBOL(of_platform_device_create_pdata); /** * of_platform_device_create - Alloc, initialize and register an of_device diff --git a/include/linux/of_platform.h b/include/linux/of_platform.h index 84a966623e78..0f1f58775086 100644 --- a/include/linux/of_platform.h +++ b/include/linux/of_platform.h @@ -70,6 +70,9 @@ extern int of_platform_device_destroy(struct device *dev, void *data); extern int of_platform_bus_probe(struct device_node *root, const struct of_device_id *matches, struct device *parent); +extern struct platform_device * +of_platform_device_create_pdata(struct device_node *np, const char *bus_id, + void *platform_data, struct device *parent); #ifdef CONFIG_OF_ADDRESS extern int of_platform_populate(struct device_node *root, const struct of_device_id *matches, From patchwork Tue Jun 4 13:15:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 165787 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp5844678ili; Tue, 4 Jun 2019 06:19:20 -0700 (PDT) X-Google-Smtp-Source: APXvYqwAV+c8GO0f6eQv35OpoNC7ySBuGPz+ymkith+UTPBdlGIitcTua99ArY2cEf90stbFQXws X-Received: by 2002:a17:902:9041:: with SMTP id w1mr22651547plz.132.1559654360839; Tue, 04 Jun 2019 06:19:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1559654360; cv=none; d=google.com; s=arc-20160816; b=cBB1QDdCbTAxKhPJd+pDqzuTz/jndEHO/UJOKsJlsVVt2QE5k+W1AcZtMQH/e101g8 +VjSM87x8fHKrDvimKTiqhb2Qos9f/R2HULRvMtZaK3VkEqPCbCcVRQEGppkFQyZVquI VpmfGZSVsfrsxRUWTHoyE7h37ehlcdPuQQMJVM4NUOaKg9c0Q1CWrm1w0KjOwlLIOeNK a5xXunP6Zp8FEL3cpGTnBX3AvZ25KwXngLAt3II4bg3oV3yTyVBsfy1Jht9ybQk7qc+2 XUxzd2cTFx6p8eigrQqkXXLaBAP+NkrHNByG0g7SiKMNmQsw8EHjXNWf3u93qXXO03JN Ak8g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=5pm3KNyMGROABT0JcoQQvXj/6/ZjaGGLyc7JbsFcHVA=; b=T0LU+LwNuR0HixqL9x5cDbxagd5ScvL09MpuphPx3kwxQlmjTwVheWLtLHqDrIHwg/ Ybp7crNK7FqdqHcbVkbIB8wE7fQrrKya81Xkzppp23wnbJdr2Vms7PM6kTuJHsJY7DeP 39UQF7xdpcKWx/g8BPtlfUNrwdFcdmjxGO6YIDlxUtcbnnG83OQNb6FDDQM/tgQtxf7S 2VuoTgbsIPOf16dnMUrJE3qbvgOUWNw3j1qy+QH7NK/ktX0CpwKxtOiVAJ32lGf1w4MT pdSNKXkEo1ZLh1LeYQU8rNuKCdVJk3Awh/1z+kZCk2iY5Uw7pq90OGbRBZlHbcLsHaw/ SLJw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=pvsfkqLW; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Kishon Vijay Abraham I --- .../devicetree/bindings/pci/ti,j721e-pci.txt | 63 +++++++++++++++++++ include/dt-bindings/pci/pci.h | 12 ++++ 2 files changed, 75 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/ti,j721e-pci.txt create mode 100644 include/dt-bindings/pci/pci.h -- 2.17.1 diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci.txt b/Documentation/devicetree/bindings/pci/ti,j721e-pci.txt new file mode 100644 index 000000000000..9132eff7ea0d --- /dev/null +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci.txt @@ -0,0 +1,63 @@ +PCI Controller in J721E: +Required Properties: + - compatible: Should be "ti,j721e-pcie" + - reg : Two register ranges as listed in the reg-names property + - reg-names : The first entry must be "intd_cfg" used for handling legacy + interrupts. The second entry must be "user_cfg" and it has registers + for enabling the LTSSM. The third entry must be "vmap" and it has + registers for programming the requestor ID to VIRTID mapping and ATYPE. + - #address-cells : should be 1 to indicate the child node should use 1 cell + for address + - #size-cells : should be 1 to indicate the child node should use 1 cell for + size + - mode : should be for RC mode and should be for + EP mode + +Optional Properties: + - max-link-speed: As defined in Documentation/devicetree/bindings/pci/pci.txt + Default is GEN3 + - num-lanes: number of lanes to use. Default is '1' lane +It should have two child nodes, one for RC mode (pcie) and the other for EP +mode (pcie-ep). The child node for RC should follow the binding in +cdns,cdns-pcie-host.txt. The child node for the EP should follow the binding +in cdns,cdns-pcie-ep.txt + +Example: + pcie0: pcie@2900000 { + compatible = "ti,j721e-pcie"; + reg = <0x02900000 0x1000>, + <0x02907000 0x400>; + reg-names = "intd_cfg", "user_cfg"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pcie0_rc: pcie@d000000 { + compatible = "cdns,cdns-pcie-host"; + reg = <0x0d000000 0x00800000>, + <0x10000000 0x00001000>, + <0x10000000 0x08000000>; + reg-names = "reg", "cfg", "mem"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xff>; + linux,pci-domain = <0>; + cdns,max-outbound-regions = <16>; + cdns,no-bar-match-nbits = <32>; + vendor-id = /bits/ 16 <0x17cd>; + device-id = /bits/ 16 <0x0200>; + msi-map = <0x0 &gic_its 0x0 0x1000>; + ranges = <0x01000000 0x0 0x10001000 0x10001000 0x0 0x0010000>, + <0x02000000 0x0 0x10011000 0x10011000 0x0 0x7fef000>; + }; + + pcie0_ep: pcie-ep@d000000 { + compatible = "cdns,cdns-pcie-ep"; + reg = <0x0d000000 0x00800000>, + <0x10000000 0x08000000>; + reg-names = "reg", "mem"; + cdns,max-outbound-regions = <16>; + max-functions = /bits/ 8 <2>; + }; + }; diff --git a/include/dt-bindings/pci/pci.h b/include/dt-bindings/pci/pci.h new file mode 100644 index 000000000000..6fe7ccaf9e99 --- /dev/null +++ b/include/dt-bindings/pci/pci.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides constants for PCI bindings. + */ + +#ifndef _DT_BINDINGS_PCI_H +#define _DT_BINDINGS_PCI_H + +#define PCI_MODE_RC 1 +#define PCI_MODE_EP 2 + +#endif