From patchwork Thu Jun 6 01:02:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 165937 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp8057562ili; Wed, 5 Jun 2019 18:02:56 -0700 (PDT) X-Google-Smtp-Source: APXvYqzBJ5mKMRR7J2zoZHvUb6UzF96rA+NZ5MTNNi3UeJzDc+RW0eauyLdjyq8TTS7Xm3O9aqZX X-Received: by 2002:a62:63c6:: with SMTP id x189mr38020346pfb.31.1559782976780; Wed, 05 Jun 2019 18:02:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1559782976; cv=none; d=google.com; s=arc-20160816; b=WQCd1CKsPoHc/ecBuWU/0fZFhyDybJZx8zDRWTG4thXJcNSOpDG42pyguV5kDM3DY5 Uo+UEQSgCMoxrw7/ezUHQK8za1bMskPpY5ONA+7XLbQVUH6JtxhkWxFsSbXe/r5uKgBp ueN53NX+YBvqZSayuMskPRfwDTWUOYhwvltm80haOWUr3yOR2djWcRhfAKRutWxRQ7Kr ABbdHXC5FH5kh5JQV5cjI6/jklM9pY+C2BVF68kiols99MHB9Dsd21CbCLIaBo9VX+TD kyHjp7UL/tYDB7kVdox/JYl7ExXGLCQzppl7tYpTCF6B6hFKih/18XuAEDj8N/J40+zm rH7A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=CVfY2rC28TUuJiq3uH1wJEhWN7/kC8yOQdwb0MYva/0=; b=YXwBEgz9pMyXgGAa7sMBb1iwxxUW+9JteJqnIrH8lA71Whe73dG2Lo+M1dtYmMMMhz F4h5ETLHPpf51MbvE6ATaEVq7mCHdxYQSC8uy/rZGvkHCcN5AMENKto4A+IxQNYVce6K xA3+mLsBLGfWuLDt/ytC9UhzBBsIkrVuxK/8//5t7emJZfgluvRO3BWo8iOAeqIJhusW AqcPul1gIrNtUQsKlc+gHkybcdTM3aL3NhaGhBA42DjPP9sLC7cYxvbK/gMHRxVt1lz2 JDwecdpnm7/piiLMramtw0Vw4c9zCB+f4LlG0/2c1WVgH3YqCGBetNbtJnxszeifA+53 tf7w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=p3A3rKuH; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id t6si165761plr.245.2019.06.05.18.02.56; Wed, 05 Jun 2019 18:02:56 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=p3A3rKuH; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726685AbfFFBCz (ORCPT + 8 others); Wed, 5 Jun 2019 21:02:55 -0400 Received: from mail-pf1-f195.google.com ([209.85.210.195]:35676 "EHLO mail-pf1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726671AbfFFBCy (ORCPT ); Wed, 5 Jun 2019 21:02:54 -0400 Received: by mail-pf1-f195.google.com with SMTP id d126so394544pfd.2 for ; Wed, 05 Jun 2019 18:02:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=CVfY2rC28TUuJiq3uH1wJEhWN7/kC8yOQdwb0MYva/0=; b=p3A3rKuHCefXZWN7fWg4nX9E9dn1cL6KkVkiCyfgemW5z+YDAhDOOzLE2Wt6m3AywB PPWMt5gnn/3cS9b7n/IXqu8mD7tivfsbbGAs0NR1j1euURvrjyAtcN4QZi7A1zWxGAiV gpW2Anv4nHlPa0Z3Ft+nrox4RKEBmzlDe/09UkdUe8lfykT+C+KtqejLv/AlZdNxkt5G V0WX9bxKce6MZXbfnI4TbzUmgHfGxEspgmrh1PHamE+fBA1nkxZZ5ZetzV4VZEQAAydg oGtS0ZFd59yPQU/2+Q3okeTDPCVMUbDg3+PSBxlm9T0qVZNZ05tfFoIikARM3Tc2NUpp zq9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=CVfY2rC28TUuJiq3uH1wJEhWN7/kC8yOQdwb0MYva/0=; b=m+uBNR0oZMwiNdyvUZPFelzK2m8ALEquAm+etFQoX5Dr6yjT+gfoQDxEnV//iH7hWQ UQEOtHpz0+JlY/jEfwJsshCmg9pzCQ7CYLnQ1U8YQhHZfrh9whXYsst3NPRYoi22OmYk KHzYSYtpxh2y9bRsR5Ry1OjoFGkfHSAqgpWpClneE8Cl/XBh3CTRaiUGhRLjnev6/sda +CGQdcqAgdMgMVF83Z9i/+CePPn6MRWzfucZQaHGjdvIynwvv8Ju7HTedsQwmH9puNF9 ZARkuViCzrj01bLrCi9K1FUpzIEFCsRmL8N07lGvs6enG3y4ZQnw8LUB4z2xtmFFhUjr BIaw== X-Gm-Message-State: APjAAAXBImeP7gfQWhnTTLlfhfysI7Z6mza4boIEQLNbuwoXXQm4sIHh xWDzdeRWjcuP0Gd4CSBLfDEKmg== X-Received: by 2002:a62:ce07:: with SMTP id y7mr22987027pfg.12.1559782974090; Wed, 05 Jun 2019 18:02:54 -0700 (PDT) Received: from localhost.localdomain (104-188-17-28.lightspeed.sndgca.sbcglobal.net. [104.188.17.28]) by smtp.gmail.com with ESMTPSA id 144sm170856pfy.54.2019.06.05.18.02.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 05 Jun 2019 18:02:53 -0700 (PDT) From: Bjorn Andersson To: Linus Walleij , Rob Herring Cc: Andy Gross , Mark Rutland , Alim Akhtar , Avri Altman , Pedro Sousa , "James E.J. Bottomley" , "Martin K. Petersen" , Evan Green , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org Subject: [PATCH v2 1/3] pinctrl: qcom: sdm845: Expose ufs_reset as gpio Date: Wed, 5 Jun 2019 18:02:47 -0700 Message-Id: <20190606010249.3538-2-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190606010249.3538-1-bjorn.andersson@linaro.org> References: <20190606010249.3538-1-bjorn.andersson@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The ufs_reset pin is expected to be wired to the reset pin of the primary UFS memory but is pretty much just a general purpose output pinr Reorder the pins and expose it as gpio 150, so that the UFS driver can toggle it. Tested-by: John Stultz Signed-off-by: Bjorn Andersson --- Changes since v1: - None .../bindings/pinctrl/qcom,sdm845-pinctrl.txt | 2 +- drivers/pinctrl/qcom/pinctrl-sdm845.c | 12 ++++++------ 2 files changed, 7 insertions(+), 7 deletions(-) -- 2.18.0 diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt index 321bdb9be0d2..7462e3743c68 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt @@ -79,7 +79,7 @@ to specify in a pin configuration subnode: gpio0-gpio149 Supports mux, bias and drive-strength - sdc2_clk, sdc2_cmd, sdc2_data + sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset Supports bias and drive-strength - function: diff --git a/drivers/pinctrl/qcom/pinctrl-sdm845.c b/drivers/pinctrl/qcom/pinctrl-sdm845.c index c97f20fca5fd..e4e5acade086 100644 --- a/drivers/pinctrl/qcom/pinctrl-sdm845.c +++ b/drivers/pinctrl/qcom/pinctrl-sdm845.c @@ -420,10 +420,10 @@ DECLARE_MSM_GPIO_PINS(147); DECLARE_MSM_GPIO_PINS(148); DECLARE_MSM_GPIO_PINS(149); -static const unsigned int sdc2_clk_pins[] = { 150 }; -static const unsigned int sdc2_cmd_pins[] = { 151 }; -static const unsigned int sdc2_data_pins[] = { 152 }; -static const unsigned int ufs_reset_pins[] = { 153 }; +static const unsigned int ufs_reset_pins[] = { 150 }; +static const unsigned int sdc2_clk_pins[] = { 151 }; +static const unsigned int sdc2_cmd_pins[] = { 152 }; +static const unsigned int sdc2_data_pins[] = { 153 }; enum sdm845_functions { msm_mux_gpio, @@ -1271,10 +1271,10 @@ static const struct msm_pingroup sdm845_groups[] = { PINGROUP(147, NORTH, _, _, _, _, _, _, _, _, _, _), PINGROUP(148, NORTH, _, _, _, _, _, _, _, _, _, _), PINGROUP(149, NORTH, _, _, _, _, _, _, _, _, _, _), + UFS_RESET(ufs_reset, 0x99f000), SDC_QDSD_PINGROUP(sdc2_clk, 0x99a000, 14, 6), SDC_QDSD_PINGROUP(sdc2_cmd, 0x99a000, 11, 3), SDC_QDSD_PINGROUP(sdc2_data, 0x99a000, 9, 0), - UFS_RESET(ufs_reset, 0x99f000), }; static const struct msm_pinctrl_soc_data sdm845_pinctrl = { @@ -1284,7 +1284,7 @@ static const struct msm_pinctrl_soc_data sdm845_pinctrl = { .nfunctions = ARRAY_SIZE(sdm845_functions), .groups = sdm845_groups, .ngroups = ARRAY_SIZE(sdm845_groups), - .ngpios = 150, + .ngpios = 151, }; static int sdm845_pinctrl_probe(struct platform_device *pdev)