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[209.51.188.17]) by mx.google.com with ESMTPS id n21-20020ac85a15000000b003f0af4f4af0si5326257qta.572.2023.05.12.07.41.29 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 12 May 2023 07:41:29 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GrJuo8N9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pxTxK-0006m6-VE; Fri, 12 May 2023 10:41:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pxTxJ-0006lE-7i for qemu-devel@nongnu.org; Fri, 12 May 2023 10:41:13 -0400 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pxTxF-0004gz-JG for qemu-devel@nongnu.org; Fri, 12 May 2023 10:41:12 -0400 Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-3f4271185daso59001995e9.2 for ; Fri, 12 May 2023 07:41:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683902468; x=1686494468; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NHxiI1NhG4rA3nZaGSdOO6mlH5N9NfHL+3owTRsYSs4=; b=GrJuo8N9eY+5PfV4Ljz11Zy9T+NVtMeGfoDrQhP8XpZfgOnSOoY7cAhiVnJcAmgYoA Oy269pkMkVqKaPEr8gJEJJ3z1OXXAdEXlbwAAgKQSbGBf7qNoDJV0scONurbf5wl7B1h t/1WxxWqQydzVTNrB6AOdEFoBhN4I006WptYZZ3FBshEYnDzRMfBYBzGpnFRfPFiUGvg CI/uBrurOmvuZ5OQsthqYFZDAFyoKEap5UmT640NMw0bb42M6ddp/fEyykEZKW5fUwyz xmpV94Sy56rPT3eh+M3wrYFwF4yDjTH3+OyoA+/f3CnJBbfVI39RRP6rb1UQs6lHNyQU 5wiw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683902468; x=1686494468; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NHxiI1NhG4rA3nZaGSdOO6mlH5N9NfHL+3owTRsYSs4=; b=d3COHZdsxZsfknGb4gQPb05tQoi70/dtC+Yx9AM0OdSAaxtFGQz3UJF3+OV6QVhjMn 1uzewxKLo81c2yaWf3ql0avOBxMBKxufQih6BagOhx5ho3yfQjX66QMGI/1NJsD8EuF4 AbJ30Y3vqi2IC2lfLAY657xyEImRRvHAQBwr8Gw404p2wet/y0rYrI/5oTuW8Ix/7ZYy ihbvr+vzpFAEpOqNaPF4y1f76AOmls4X5sEBQEHZaN+v8wk1qZDytyywMOm+ygasdR4T 3ZW+m/0BHKnvKEQUFFHhwHL+NTQDx2EheyZHKpsdpGUU421Jpnu3xRu7eAj/Eemi354D yEZQ== X-Gm-Message-State: AC+VfDyDM5V6QfRwQ7IQEKNSUCiUnSnBfXQvEu3EuqzLdNYPOOBg4q2s qoIksxsw5AqyVeY8O1ZUksL/JA== X-Received: by 2002:a7b:cb94:0:b0:3f4:ec32:69fd with SMTP id m20-20020a7bcb94000000b003f4ec3269fdmr3500814wmi.40.1683902468052; Fri, 12 May 2023 07:41:08 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12-20020a7bcc0c000000b003f17848673fsm28916167wmh.27.2023.05.12.07.41.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 May 2023 07:41:07 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Richard Henderson Subject: [PATCH 01/20] target/arm: Split out disas_a64_legacy Date: Fri, 12 May 2023 15:40:47 +0100 Message-Id: <20230512144106.3608981-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230512144106.3608981-1-peter.maydell@linaro.org> References: <20230512144106.3608981-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson Split out all of the decode stuff from aarch64_tr_translate_insn. Call it disas_a64_legacy to indicate it will be replaced. Signed-off-by: Richard Henderson [PMM: Rebased] Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/tcg/translate-a64.c | 82 ++++++++++++++++++---------------- 1 file changed, 44 insertions(+), 38 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index dff391bfe24..8a0ede96440 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -14200,6 +14200,49 @@ static bool btype_destination_ok(uint32_t insn, bool bt, int btype) return false; } +/* C3.1 A64 instruction index by encoding */ +static void disas_a64_legacy(DisasContext *s, uint32_t insn) +{ + switch (extract32(insn, 25, 4)) { + case 0x0: + if (!extract32(insn, 31, 1) || !disas_sme(s, insn)) { + unallocated_encoding(s); + } + break; + case 0x1: case 0x3: /* UNALLOCATED */ + unallocated_encoding(s); + break; + case 0x2: + if (!disas_sve(s, insn)) { + unallocated_encoding(s); + } + break; + case 0x8: case 0x9: /* Data processing - immediate */ + disas_data_proc_imm(s, insn); + break; + case 0xa: case 0xb: /* Branch, exception generation and system insns */ + disas_b_exc_sys(s, insn); + break; + case 0x4: + case 0x6: + case 0xc: + case 0xe: /* Loads and stores */ + disas_ldst(s, insn); + break; + case 0x5: + case 0xd: /* Data processing - register */ + disas_data_proc_reg(s, insn); + break; + case 0x7: + case 0xf: /* Data processing - SIMD and floating point */ + disas_data_proc_simd_fp(s, insn); + break; + default: + assert(FALSE); /* all 15 cases should be handled above */ + break; + } +} + static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu) { @@ -14401,44 +14444,7 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) disas_sme_fa64(s, insn); } - switch (extract32(insn, 25, 4)) { - case 0x0: - if (!extract32(insn, 31, 1) || !disas_sme(s, insn)) { - unallocated_encoding(s); - } - break; - case 0x1: case 0x3: /* UNALLOCATED */ - unallocated_encoding(s); - break; - case 0x2: - if (!disas_sve(s, insn)) { - unallocated_encoding(s); - } - break; - case 0x8: case 0x9: /* Data processing - immediate */ - disas_data_proc_imm(s, insn); - break; - case 0xa: case 0xb: /* Branch, exception generation and system insns */ - disas_b_exc_sys(s, insn); - break; - case 0x4: - case 0x6: - case 0xc: - case 0xe: /* Loads and stores */ - disas_ldst(s, insn); - break; - case 0x5: - case 0xd: /* Data processing - register */ - disas_data_proc_reg(s, insn); - break; - case 0x7: - case 0xf: /* Data processing - SIMD and floating point */ - disas_data_proc_simd_fp(s, insn); - break; - default: - assert(FALSE); /* all 15 cases should be handled above */ - break; - } + disas_a64_legacy(s, insn); /* * After execution of most insns, btype is reset to 0. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12-20020a7bcc0c000000b003f17848673fsm28916167wmh.27.2023.05.12.07.41.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 May 2023 07:41:08 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Richard Henderson Subject: [PATCH 02/20] target/arm: Create decodetree skeleton for A64 Date: Fri, 12 May 2023 15:40:48 +0100 Message-Id: <20230512144106.3608981-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230512144106.3608981-1-peter.maydell@linaro.org> References: <20230512144106.3608981-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The A64 translator uses a hand-written decoder for everything except SVE or SME. It's fairly well structured, but it's becoming obvious that it's still more painful to add instructions to than the A32 translator, because putting a new instruction into the right place in a hand-written decoder is much harder than adding new instruction patterns to a decodetree file. As the first step in conversion to decodetree, create the skeleton of the decodetree decoder; where it does not handle instructions we will fall back to the legacy decoder (which will be for everything at the moment, since there are no patterns in a64.decode). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/tcg/a64.decode | 20 ++++++++++++++++++++ target/arm/tcg/translate-a64.c | 18 +++++++++++------- target/arm/tcg/meson.build | 1 + 3 files changed, 32 insertions(+), 7 deletions(-) create mode 100644 target/arm/tcg/a64.decode diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode new file mode 100644 index 00000000000..43321bbbb05 --- /dev/null +++ b/target/arm/tcg/a64.decode @@ -0,0 +1,20 @@ +# AArch64 A64 allowed instruction decoding +# +# Copyright (c) 2023 Linaro, Ltd +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2.1 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, see . + +# +# This file is processed by scripts/decodetree.py +# diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 8a0ede96440..7862e9dd4e3 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -56,6 +56,13 @@ enum a64_shift_type { A64_SHIFT_TYPE_ROR = 3 }; +/* + * Include the generated decoders. + */ + +#include "decode-sme-fa64.c.inc" +#include "decode-a64.c.inc" + /* Table based decoder typedefs - used when the relevant bits for decode * are too awkwardly scattered across the instruction (eg SIMD). */ @@ -14100,12 +14107,6 @@ static void disas_data_proc_simd_fp(DisasContext *s, uint32_t insn) } } -/* - * Include the generated SME FA64 decoder. - */ - -#include "decode-sme-fa64.c.inc" - static bool trans_OK(DisasContext *s, arg_OK *a) { return true; @@ -14444,7 +14445,10 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) disas_sme_fa64(s, insn); } - disas_a64_legacy(s, insn); + + if (!disas_a64(s, insn)) { + disas_a64_legacy(s, insn); + } /* * After execution of most insns, btype is reset to 0. diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build index 4d99f6dacb3..130ed62fcd7 100644 --- a/target/arm/tcg/meson.build +++ b/target/arm/tcg/meson.build @@ -13,6 +13,7 @@ gen = [ decodetree.process('a32-uncond.decode', extra_args: '--static-decode=disas_a32_uncond'), decodetree.process('t32.decode', extra_args: '--static-decode=disas_t32'), decodetree.process('t16.decode', extra_args: ['-w', '16', '--static-decode=disas_t16']), + decodetree.process('a64.decode', extra_args: ['--static-decode=disas_a64']), ] arm_ss.add(gen) From patchwork Fri May 12 14:40:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 681180 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a41:0:0:0:0:0 with SMTP id v1csp3995060wrs; Fri, 12 May 2023 07:45:35 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7Xua/N/GTPoEM5r/frDEnqMxFXNLlwjjc3VvrKQ9j+bj7J8dIgZDBcBkeX9LI1CEP/ajXi X-Received: by 2002:a05:6214:c8d:b0:577:5ffe:e0ce with SMTP id r13-20020a0562140c8d00b005775ffee0cemr34483079qvr.25.1683902735624; Fri, 12 May 2023 07:45:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683902735; cv=none; d=google.com; s=arc-20160816; b=ZqO2jc+k1vblPoJPssfMdiMTb8JHeDXu5ecG8Euf2oO5N7jCAgSsyr09LpplPwYZbJ ZRwiHnfxk0hAN7e4Hpr77oO1Ie8gIHmTEOMGiobjrthlsWGzrmtHzEUjy9RuKQi5jiNB vTKSipsLYNcyekE+epZEjpJd0KG1tyu8wx9uzluF1R6HPLPNZ0XgCm4OCHujA77yQFL6 Tps/nSiCwh218Nzqz08GKTNMWd3tnzMMR85jbzC23aYaGrMFNAiCjU5JJvoRAPX97FGf t22pDSg9tzLFF4Ou4EpXF7+ei6AgjnPgWf1OcVOtljg6O3H1vTsXAQfZk/3tjYk/rogB DV+A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=F7ZdreOn7GzP2/qhzWCJzqHK4hMlTf1RtG4DdFV8A+I=; b=gD7llqRBYTUErDNvVd+VDfPmI5vfcl5F8S9qdCXI/+RVHZt+jcAUu2KN9y7Z1LFzIS 3ZeakWqqki+aZEJ2yVJ1AagaK3VXw6GJDWDlGyWgIvrsp/IcLIGZfJk2aC2IX9s8SwFo 7yP8pN6qoY7a0umA1MhhwppgnQ/+xxFftgo2lBqo+qZKY6ZDKuMAGhPSu5FnMHfvW+Fr 1eESbUhhHP8Bh61baJSrtRtUMadqqpLq6O7pYHsy4jf0gg+yydG4UNkBSQAki/NSdlOh swwUX4TzXYlfm7l7iz8heoNRNb9ABs5PWiI6yoYJ5fcYMgXd0sO++YRBQRakQYDQw8SS tRLA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ruCmCfeA; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12-20020a7bcc0c000000b003f17848673fsm28916167wmh.27.2023.05.12.07.41.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 May 2023 07:41:08 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Richard Henderson Subject: [PATCH 03/20] target/arm: Pull calls to disas_sve() and disas_sme() out of legacy decoder Date: Fri, 12 May 2023 15:40:49 +0100 Message-Id: <20230512144106.3608981-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230512144106.3608981-1-peter.maydell@linaro.org> References: <20230512144106.3608981-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The SVE and SME decode is already done by decodetree. Pull the calls to these decoders out of the legacy decoder. This doesn't change behaviour because all the patterns in sve.decode and sme.decode already require the bits that the legacy decoder is decoding to have the correct values. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 20 ++++---------------- 1 file changed, 4 insertions(+), 16 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 7862e9dd4e3..2845febb713 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -14205,19 +14205,6 @@ static bool btype_destination_ok(uint32_t insn, bool bt, int btype) static void disas_a64_legacy(DisasContext *s, uint32_t insn) { switch (extract32(insn, 25, 4)) { - case 0x0: - if (!extract32(insn, 31, 1) || !disas_sme(s, insn)) { - unallocated_encoding(s); - } - break; - case 0x1: case 0x3: /* UNALLOCATED */ - unallocated_encoding(s); - break; - case 0x2: - if (!disas_sve(s, insn)) { - unallocated_encoding(s); - } - break; case 0x8: case 0x9: /* Data processing - immediate */ disas_data_proc_imm(s, insn); break; @@ -14239,7 +14226,7 @@ static void disas_a64_legacy(DisasContext *s, uint32_t insn) disas_data_proc_simd_fp(s, insn); break; default: - assert(FALSE); /* all 15 cases should be handled above */ + unallocated_encoding(s); break; } } @@ -14445,8 +14432,9 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) disas_sme_fa64(s, insn); } - - if (!disas_a64(s, insn)) { + if (!disas_a64(s, insn) && + !disas_sme(s,insn) && + !disas_sve(s, insn)) { disas_a64_legacy(s, insn); } From patchwork Fri May 12 14:40:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 681168 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a41:0:0:0:0:0 with SMTP id v1csp3993061wrs; Fri, 12 May 2023 07:41:22 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4z6nNFKJN/7M4a8WenmhnROARxaMHxBoSlgOpPjr2GXyl9X5tUZRJZA1FBSU2pCBTXK3ov X-Received: by 2002:a05:622a:1c5:b0:3f2:1d7d:6851 with SMTP id t5-20020a05622a01c500b003f21d7d6851mr41299543qtw.16.1683902482712; Fri, 12 May 2023 07:41:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683902482; cv=none; d=google.com; s=arc-20160816; b=OQQffWjs56ht8xoCEINeH1sdbpuwfLI4KxrVtG8bSUDCHI59Y+kUC8qO5hW9xTsoQH zBKtdF+9NN1nnACgJd7Ku0/I6p5JXwGjZpfAnX6RCW5dLHTVbGtPYz4mFEQsiqU3mzfv Me/Ei02kYV42u0Ya1AKbLZWCevOVAX7VyUAn+KUPtxLBegbpEzwEOLL6wrRE1jC2aeHy c/F7mgEvZjsaCpoWrrkbb1BNddwdnbVm+2BeK5F5BVNwWs9lsvlfmP5e2HwQxe3jOzQ6 Egyi6yr69jrJU/HJPuXqbm6V8JxumrGEMdoojESzjyo/IfQ2QoH3YBJmBMVheLD5ctqK M0xQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=aGMeEb09oEnMrpyNK209IcBkUtOebSdaEKZrMIshndE=; b=KVphsW30zNc2qMQ66ebTwu0rMPzVfwtE1y9gyAL/39CZPgH3wOTg/fy3LuWLK3ZRE7 6X61fflmekDerqQs4wdL9vfFfoEfRPaU8zkMcUScgzBkXTqpO5CUTZw8Chq7dFmQK31D p/8Lv0Z2k8ErJ9Lp/9D5ddYy+XHVR2pwFcvJWsJPZHdnWI93hg38PcecUFplTtkhk8xP 2iXV74eNyeAIkhV3OyvglHWNOIcJaeKnjSLaTq6Dgc+GgRCMc+4EpbZ+xZyenlZ4J4fx sghX3XbA3Lqgi6B9ECKL2+ZHy7CoB+pYi7I4mkdZQUOHrBq+9LxdU15KEE8QlVwmGo6Y 5muQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=daK08hxL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12-20020a7bcc0c000000b003f17848673fsm28916167wmh.27.2023.05.12.07.41.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 May 2023 07:41:09 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Richard Henderson Subject: [PATCH 04/20] target/arm: Convert PC-rel addressing to decodetree Date: Fri, 12 May 2023 15:40:50 +0100 Message-Id: <20230512144106.3608981-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230512144106.3608981-1-peter.maydell@linaro.org> References: <20230512144106.3608981-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson Convert the ADR and ADRP instructions. Signed-off-by: Richard Henderson [PMM: Rebased] Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/tcg/a64.decode | 13 ++++++++++++ target/arm/tcg/translate-a64.c | 38 +++++++++++++--------------------- 2 files changed, 27 insertions(+), 24 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 43321bbbb05..bcf46fc37d7 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -18,3 +18,16 @@ # # This file is processed by scripts/decodetree.py # + +&ri rd imm + + +### Data Processing - Immediate + +# PC-rel addressing + +%imm_pcrel 5:s19 29:2 +@pcrel . .. ..... ................... rd:5 &ri imm=%imm_pcrel + +ADR 0 .. 10000 ................... ..... @pcrel +ADRP 1 .. 10000 ................... ..... @pcrel diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 2845febb713..ce3e8b1d08e 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -4179,31 +4179,24 @@ static void disas_ldst(DisasContext *s, uint32_t insn) } } -/* PC-rel. addressing - * 31 30 29 28 24 23 5 4 0 - * +----+-------+-----------+-------------------+------+ - * | op | immlo | 1 0 0 0 0 | immhi | Rd | - * +----+-------+-----------+-------------------+------+ +/* + * PC-rel. addressing */ -static void disas_pc_rel_adr(DisasContext *s, uint32_t insn) + +static bool trans_ADR(DisasContext *s, arg_ri *a) { - unsigned int page, rd; - int64_t offset; + gen_pc_plus_diff(s, cpu_reg(s, a->rd), a->imm); + return true; +} - page = extract32(insn, 31, 1); - /* SignExtend(immhi:immlo) -> offset */ - offset = sextract64(insn, 5, 19); - offset = offset << 2 | extract32(insn, 29, 2); - rd = extract32(insn, 0, 5); +static bool trans_ADRP(DisasContext *s, arg_ri *a) +{ + int64_t offset = (int64_t)a->imm << 12; - if (page) { - /* ADRP (page based) */ - offset <<= 12; - /* The page offset is ok for CF_PCREL. */ - offset -= s->pc_curr & 0xfff; - } - - gen_pc_plus_diff(s, cpu_reg(s, rd), offset); + /* The page offset is ok for CF_PCREL. */ + offset -= s->pc_curr & 0xfff; + gen_pc_plus_diff(s, cpu_reg(s, a->rd), offset); + return true; } /* @@ -4656,9 +4649,6 @@ static void disas_extract(DisasContext *s, uint32_t insn) static void disas_data_proc_imm(DisasContext *s, uint32_t insn) { switch (extract32(insn, 23, 6)) { - case 0x20: case 0x21: /* PC-rel. addressing */ - disas_pc_rel_adr(s, insn); - break; case 0x22: /* Add/subtract (immediate) */ disas_add_sub_imm(s, insn); break; From patchwork Fri May 12 14:40:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 681177 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a41:0:0:0:0:0 with SMTP id v1csp3994273wrs; Fri, 12 May 2023 07:43:58 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6Ne3YyXBTT3zkhePgmz5DzhffDuhzclEGjou4/uIm8TXEVPJw82rmKBMmj8L0QbxU3XOjj X-Received: by 2002:a05:6214:e6b:b0:61b:2492:389d with SMTP id jz11-20020a0562140e6b00b0061b2492389dmr34012525qvb.14.1683902638130; Fri, 12 May 2023 07:43:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683902638; cv=none; d=google.com; s=arc-20160816; b=FAYtWgazTizm7HwLCRG/wbh6QxD/T1IVHX1H0sdE3SCCbDc3m/XEEFScwJUKIqy8uz 6u+tT7blY+MaCF/HNf6FPPdtwsuEjXdlRtVOlSGXdPyYJ5S1465WgAceQXLKfSFI3ptA 73ODhhz8XwKV1totW/aW2uut8fZtAbAGanWCPr/feHhsxwcnqYCx1C5SQZXlzVtVzUe4 xgEqX62AjAnY0YmGY5hnzW56Ja3VvAr29JNdXfMC31NP0hdEcEIiz22OVRH/VroQ/j+L 2Ogp3HuRQapnP/SgRY/h7ChPR6iDsiJIAq0efADZr0+8jSPEM1/AdlNgfXXNLN1bik83 IYMA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=frqXOGogEVBk8JyygFWcnqFlkBDGHEdOnDw7HOu9/7M=; b=gTbhWuLkhBYf+J2l3tx3uK3uImN+0ggrGK7RTM50iLIBNpt1/54gfikGHFx794cQfQ yHeAJ8BnCslpQYtFnXeoxWsJnGKpdf7CJTTxg0wmGch/n0UZelzzzzGrRB8z5jWqnOEI sgzgLLsRjIVpykZol2h0r3qZErWBeWFMe654PwnnCb58rOU9ZdIrjfl0S2pYKfHtsyOu je9jdZJX/fbnLM1jqtu/o5haZfEc/z/xExFpBOAkyXAWKNy27GnC7CgyATs4UUh9QMCi rFjTQwoypuVlafpT2wbTM0QELH2qmbgorD9irF8Uktn8ShJaoV+MN1Cal1Oo1mn7MjOb wR5Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=L2jGYeUJ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12-20020a7bcc0c000000b003f17848673fsm28916167wmh.27.2023.05.12.07.41.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 May 2023 07:41:10 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Richard Henderson Subject: [PATCH 05/20] target/arm: Split gen_add_CC and gen_sub_CC Date: Fri, 12 May 2023 15:40:51 +0100 Message-Id: <20230512144106.3608981-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230512144106.3608981-1-peter.maydell@linaro.org> References: <20230512144106.3608981-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson Split out specific 32-bit and 64-bit functions. These carry the same signature as tcg_gen_add_i64, and so will be easier to pass as callbacks. Retain gen_add_CC and gen_sub_CC during conversion. Signed-off-by: Richard Henderson [PMM: rebased] Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/tcg/translate-a64.c | 149 +++++++++++++++++++-------------- 1 file changed, 84 insertions(+), 65 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index ce3e8b1d08e..a3bccbd708a 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -682,83 +682,102 @@ static inline void gen_logic_CC(int sf, TCGv_i64 result) } /* dest = T0 + T1; compute C, N, V and Z flags */ +static void gen_add64_CC(TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1) +{ + TCGv_i64 result, flag, tmp; + result = tcg_temp_new_i64(); + flag = tcg_temp_new_i64(); + tmp = tcg_temp_new_i64(); + + tcg_gen_movi_i64(tmp, 0); + tcg_gen_add2_i64(result, flag, t0, tmp, t1, tmp); + + tcg_gen_extrl_i64_i32(cpu_CF, flag); + + gen_set_NZ64(result); + + tcg_gen_xor_i64(flag, result, t0); + tcg_gen_xor_i64(tmp, t0, t1); + tcg_gen_andc_i64(flag, flag, tmp); + tcg_gen_extrh_i64_i32(cpu_VF, flag); + + tcg_gen_mov_i64(dest, result); +} + +static void gen_add32_CC(TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1) +{ + TCGv_i32 t0_32 = tcg_temp_new_i32(); + TCGv_i32 t1_32 = tcg_temp_new_i32(); + TCGv_i32 tmp = tcg_temp_new_i32(); + + tcg_gen_movi_i32(tmp, 0); + tcg_gen_extrl_i64_i32(t0_32, t0); + tcg_gen_extrl_i64_i32(t1_32, t1); + tcg_gen_add2_i32(cpu_NF, cpu_CF, t0_32, tmp, t1_32, tmp); + tcg_gen_mov_i32(cpu_ZF, cpu_NF); + tcg_gen_xor_i32(cpu_VF, cpu_NF, t0_32); + tcg_gen_xor_i32(tmp, t0_32, t1_32); + tcg_gen_andc_i32(cpu_VF, cpu_VF, tmp); + tcg_gen_extu_i32_i64(dest, cpu_NF); +} + static void gen_add_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1) { if (sf) { - TCGv_i64 result, flag, tmp; - result = tcg_temp_new_i64(); - flag = tcg_temp_new_i64(); - tmp = tcg_temp_new_i64(); - - tcg_gen_movi_i64(tmp, 0); - tcg_gen_add2_i64(result, flag, t0, tmp, t1, tmp); - - tcg_gen_extrl_i64_i32(cpu_CF, flag); - - gen_set_NZ64(result); - - tcg_gen_xor_i64(flag, result, t0); - tcg_gen_xor_i64(tmp, t0, t1); - tcg_gen_andc_i64(flag, flag, tmp); - tcg_gen_extrh_i64_i32(cpu_VF, flag); - - tcg_gen_mov_i64(dest, result); + gen_add64_CC(dest, t0, t1); } else { - /* 32 bit arithmetic */ - TCGv_i32 t0_32 = tcg_temp_new_i32(); - TCGv_i32 t1_32 = tcg_temp_new_i32(); - TCGv_i32 tmp = tcg_temp_new_i32(); - - tcg_gen_movi_i32(tmp, 0); - tcg_gen_extrl_i64_i32(t0_32, t0); - tcg_gen_extrl_i64_i32(t1_32, t1); - tcg_gen_add2_i32(cpu_NF, cpu_CF, t0_32, tmp, t1_32, tmp); - tcg_gen_mov_i32(cpu_ZF, cpu_NF); - tcg_gen_xor_i32(cpu_VF, cpu_NF, t0_32); - tcg_gen_xor_i32(tmp, t0_32, t1_32); - tcg_gen_andc_i32(cpu_VF, cpu_VF, tmp); - tcg_gen_extu_i32_i64(dest, cpu_NF); + gen_add32_CC(dest, t0, t1); } } /* dest = T0 - T1; compute C, N, V and Z flags */ +static void gen_sub64_CC(TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1) +{ + /* 64 bit arithmetic */ + TCGv_i64 result, flag, tmp; + + result = tcg_temp_new_i64(); + flag = tcg_temp_new_i64(); + tcg_gen_sub_i64(result, t0, t1); + + gen_set_NZ64(result); + + tcg_gen_setcond_i64(TCG_COND_GEU, flag, t0, t1); + tcg_gen_extrl_i64_i32(cpu_CF, flag); + + tcg_gen_xor_i64(flag, result, t0); + tmp = tcg_temp_new_i64(); + tcg_gen_xor_i64(tmp, t0, t1); + tcg_gen_and_i64(flag, flag, tmp); + tcg_gen_extrh_i64_i32(cpu_VF, flag); + tcg_gen_mov_i64(dest, result); +} + +static void gen_sub32_CC(TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1) +{ + /* 32 bit arithmetic */ + TCGv_i32 t0_32 = tcg_temp_new_i32(); + TCGv_i32 t1_32 = tcg_temp_new_i32(); + TCGv_i32 tmp; + + tcg_gen_extrl_i64_i32(t0_32, t0); + tcg_gen_extrl_i64_i32(t1_32, t1); + tcg_gen_sub_i32(cpu_NF, t0_32, t1_32); + tcg_gen_mov_i32(cpu_ZF, cpu_NF); + tcg_gen_setcond_i32(TCG_COND_GEU, cpu_CF, t0_32, t1_32); + tcg_gen_xor_i32(cpu_VF, cpu_NF, t0_32); + tmp = tcg_temp_new_i32(); + tcg_gen_xor_i32(tmp, t0_32, t1_32); + tcg_gen_and_i32(cpu_VF, cpu_VF, tmp); + tcg_gen_extu_i32_i64(dest, cpu_NF); +} + static void gen_sub_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1) { if (sf) { - /* 64 bit arithmetic */ - TCGv_i64 result, flag, tmp; - - result = tcg_temp_new_i64(); - flag = tcg_temp_new_i64(); - tcg_gen_sub_i64(result, t0, t1); - - gen_set_NZ64(result); - - tcg_gen_setcond_i64(TCG_COND_GEU, flag, t0, t1); - tcg_gen_extrl_i64_i32(cpu_CF, flag); - - tcg_gen_xor_i64(flag, result, t0); - tmp = tcg_temp_new_i64(); - tcg_gen_xor_i64(tmp, t0, t1); - tcg_gen_and_i64(flag, flag, tmp); - tcg_gen_extrh_i64_i32(cpu_VF, flag); - tcg_gen_mov_i64(dest, result); + gen_sub64_CC(dest, t0, t1); } else { - /* 32 bit arithmetic */ - TCGv_i32 t0_32 = tcg_temp_new_i32(); - TCGv_i32 t1_32 = tcg_temp_new_i32(); - TCGv_i32 tmp; - - tcg_gen_extrl_i64_i32(t0_32, t0); - tcg_gen_extrl_i64_i32(t1_32, t1); - tcg_gen_sub_i32(cpu_NF, t0_32, t1_32); - tcg_gen_mov_i32(cpu_ZF, cpu_NF); - tcg_gen_setcond_i32(TCG_COND_GEU, cpu_CF, t0_32, t1_32); - tcg_gen_xor_i32(cpu_VF, cpu_NF, t0_32); - tmp = tcg_temp_new_i32(); - tcg_gen_xor_i32(tmp, t0_32, t1_32); - tcg_gen_and_i32(cpu_VF, cpu_VF, tmp); - tcg_gen_extu_i32_i64(dest, cpu_NF); + gen_sub32_CC(dest, t0, t1); } } From patchwork Fri May 12 14:40:52 2023 Content-Type: text/plain; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12-20020a7bcc0c000000b003f17848673fsm28916167wmh.27.2023.05.12.07.41.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 May 2023 07:41:10 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Richard Henderson Subject: [PATCH 06/20] target/arm: Convert Add/subtract (immediate) to decodetree Date: Fri, 12 May 2023 15:40:52 +0100 Message-Id: <20230512144106.3608981-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230512144106.3608981-1-peter.maydell@linaro.org> References: <20230512144106.3608981-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson Convert the ADD and SUB (immediate) instructions. Signed-off-by: Richard Henderson [PMM: Rebased; adjusted to use translate.h's TRANS macro] Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/tcg/translate.h | 5 +++ target/arm/tcg/a64.decode | 17 ++++++++ target/arm/tcg/translate-a64.c | 73 ++++++++++------------------------ 3 files changed, 42 insertions(+), 53 deletions(-) diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index f02d4685b4c..a9d1f4adc28 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -220,6 +220,11 @@ static inline int rsub_8(DisasContext *s, int x) return 8 - x; } +static inline int shl_12(DisasContext *s, int x) +{ + return x << 12; +} + static inline int neon_3same_fp_size(DisasContext *s, int x) { /* Convert 0==fp32, 1==fp16 into a MO_* value */ diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index bcf46fc37d7..30c2ac7e271 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -20,6 +20,7 @@ # &ri rd imm +&rri_sf rd rn imm sf ### Data Processing - Immediate @@ -31,3 +32,19 @@ ADR 0 .. 10000 ................... ..... @pcrel ADRP 1 .. 10000 ................... ..... @pcrel + +# Add/subtract (immediate) + +%imm12_sh12 10:12 !function=shl_12 +@addsub_imm sf:1 .. ...... . imm:12 rn:5 rd:5 +@addsub_imm12 sf:1 .. ...... . ............ rn:5 rd:5 imm=%imm12_sh12 + +ADD_i . 00 100010 0 ............ ..... ..... @addsub_imm +ADD_i . 00 100010 1 ............ ..... ..... @addsub_imm12 +ADDS_i . 01 100010 0 ............ ..... ..... @addsub_imm +ADDS_i . 01 100010 1 ............ ..... ..... @addsub_imm12 + +SUB_i . 10 100010 0 ............ ..... ..... @addsub_imm +SUB_i . 10 100010 1 ............ ..... ..... @addsub_imm12 +SUBS_i . 11 100010 0 ............ ..... ..... @addsub_imm +SUBS_i . 11 100010 1 ............ ..... ..... @addsub_imm12 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index a3bccbd708a..fb12122a3fb 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -4198,6 +4198,22 @@ static void disas_ldst(DisasContext *s, uint32_t insn) } } +typedef void ArithTwoOp(TCGv_i64, TCGv_i64, TCGv_i64); + +static bool gen_rri(DisasContext *s, arg_rri_sf *a, + bool rd_sp, bool rn_sp, ArithTwoOp *fn) +{ + TCGv_i64 tcg_rn = rn_sp ? cpu_reg_sp(s, a->rn) : cpu_reg(s, a->rn); + TCGv_i64 tcg_rd = rd_sp ? cpu_reg_sp(s, a->rd) : cpu_reg(s, a->rd); + TCGv_i64 tcg_imm = tcg_constant_i64(a->imm); + + fn(tcg_rd, tcg_rn, tcg_imm); + if (!a->sf) { + tcg_gen_ext32u_i64(tcg_rd, tcg_rd); + } + return true; +} + /* * PC-rel. addressing */ @@ -4220,57 +4236,11 @@ static bool trans_ADRP(DisasContext *s, arg_ri *a) /* * Add/subtract (immediate) - * - * 31 30 29 28 23 22 21 10 9 5 4 0 - * +--+--+--+-------------+--+-------------+-----+-----+ - * |sf|op| S| 1 0 0 0 1 0 |sh| imm12 | Rn | Rd | - * +--+--+--+-------------+--+-------------+-----+-----+ - * - * sf: 0 -> 32bit, 1 -> 64bit - * op: 0 -> add , 1 -> sub - * S: 1 -> set flags - * sh: 1 -> LSL imm by 12 */ -static void disas_add_sub_imm(DisasContext *s, uint32_t insn) -{ - int rd = extract32(insn, 0, 5); - int rn = extract32(insn, 5, 5); - uint64_t imm = extract32(insn, 10, 12); - bool shift = extract32(insn, 22, 1); - bool setflags = extract32(insn, 29, 1); - bool sub_op = extract32(insn, 30, 1); - bool is_64bit = extract32(insn, 31, 1); - - TCGv_i64 tcg_rn = cpu_reg_sp(s, rn); - TCGv_i64 tcg_rd = setflags ? cpu_reg(s, rd) : cpu_reg_sp(s, rd); - TCGv_i64 tcg_result; - - if (shift) { - imm <<= 12; - } - - tcg_result = tcg_temp_new_i64(); - if (!setflags) { - if (sub_op) { - tcg_gen_subi_i64(tcg_result, tcg_rn, imm); - } else { - tcg_gen_addi_i64(tcg_result, tcg_rn, imm); - } - } else { - TCGv_i64 tcg_imm = tcg_constant_i64(imm); - if (sub_op) { - gen_sub_CC(is_64bit, tcg_result, tcg_rn, tcg_imm); - } else { - gen_add_CC(is_64bit, tcg_result, tcg_rn, tcg_imm); - } - } - - if (is_64bit) { - tcg_gen_mov_i64(tcg_rd, tcg_result); - } else { - tcg_gen_ext32u_i64(tcg_rd, tcg_result); - } -} +TRANS(ADD_i, gen_rri, a, 1, 1, tcg_gen_add_i64) +TRANS(SUB_i, gen_rri, a, 1, 1, tcg_gen_sub_i64) +TRANS(ADDS_i, gen_rri, a, 0, 1, a->sf ? gen_add64_CC : gen_add32_CC) +TRANS(SUBS_i, gen_rri, a, 0, 1, a->sf ? gen_sub64_CC : gen_sub32_CC) /* * Add/subtract (immediate, with tags) @@ -4668,9 +4638,6 @@ static void disas_extract(DisasContext *s, uint32_t insn) static void disas_data_proc_imm(DisasContext *s, uint32_t insn) { switch (extract32(insn, 23, 6)) { - case 0x22: /* Add/subtract (immediate) */ - disas_add_sub_imm(s, insn); - break; case 0x23: /* Add/subtract (immediate, with tags) */ disas_add_sub_imm_with_tags(s, insn); break; From patchwork Fri May 12 14:40:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 681185 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a41:0:0:0:0:0 with SMTP id v1csp3995097wrs; Fri, 12 May 2023 07:45:38 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7T9xX/WfsZSLG5Ex6+hmEXSHlxSLIYPopC2uERw8+v+Tzc9I8CUpCVoDUzNsKzyw3FAdcw X-Received: by 2002:a05:622a:1a19:b0:3b9:b6e3:c78e with SMTP id f25-20020a05622a1a1900b003b9b6e3c78emr39535371qtb.8.1683902738386; Fri, 12 May 2023 07:45:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683902738; cv=none; d=google.com; s=arc-20160816; b=gR39wGUcvt9PAOux0V9fXrVoQW+flUm9vDir9Hm+qRLYyeflXirSEmD81d6aoLVYxF 4mosMR+5MXXtN1buTVfJzvu9I5j4nu8sW2Ia0UgAH3l8+J/yi9Jm43PErAINEpUxQRWN xeRauLLpYm8NXqVLy/rqeSzkkkZQH+HvKfkfVf2Scyi7EQ6G6cBEt4T+F5J+5+k3SKVL kNrJJnUXyf9nP0WEEqPYIE1XINqOzgZ9RNuCtTAuKDtpTE7Y2QTHg9jCXQas+UV+9PhX vOpcIcIiIlNYeQe8fPLZHxDgyMBsQUCaWhHgjVO3AXd01lmlcM2IxsNknct/0kNsTPia a0lw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=hQ1oqtC4DuCr//tYDK0BhT/RRzDG+KYHXcvP6HahZio=; b=ZEx+baJL4ovPjVJkrnWxtXg3cGjK0ut8mdSPjukCPsP8GokdaQLGOYoQPD2x4vEAIu 08Cxhcj9c2OJ4r0UTE50EzmImk5dvuJ3TaD+LfhruQiTbONsmkD0Eq0uW9Qj3l+hMx63 i2NcYy5rCibYm3tzMxQ6CgClhzj6CsVmbZhvIb+WKn9q36n6dLWauNEthkG7GR20HoiW ubd3gTfIygcKuw4tvclllCjZCMqwjLVKIrUNPL/GLv7GuY7GI4fUET2lNPCpUkbD/LIr V2TShqcXxB6SCzmaoaj5zsJncLExzmaUMUb0It1YXmLZ3qxx4sTZy7Y+CBFyZJcjg1AR 5fpQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Lv05wGfS; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12-20020a7bcc0c000000b003f17848673fsm28916167wmh.27.2023.05.12.07.41.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 May 2023 07:41:11 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Richard Henderson Subject: [PATCH 07/20] target/arm: Convert Add/subtract (immediate with tags) to decodetree Date: Fri, 12 May 2023 15:40:53 +0100 Message-Id: <20230512144106.3608981-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230512144106.3608981-1-peter.maydell@linaro.org> References: <20230512144106.3608981-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson Convert the ADDG and SUBG (immediate) instructions. Signed-off-by: Richard Henderson [PMM: Rebased; use TRANS_FEAT()] Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/tcg/a64.decode | 8 +++++++ target/arm/tcg/translate-a64.c | 38 ++++++++++------------------------ 2 files changed, 19 insertions(+), 27 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 30c2ac7e271..ed03d9e1349 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -48,3 +48,11 @@ SUB_i . 10 100010 0 ............ ..... ..... @addsub_imm SUB_i . 10 100010 1 ............ ..... ..... @addsub_imm12 SUBS_i . 11 100010 0 ............ ..... ..... @addsub_imm SUBS_i . 11 100010 1 ............ ..... ..... @addsub_imm12 + +# Add/subtract (immediate with tags) + +&rri_tag rd rn uimm6 uimm4 +@addsub_imm_tag . .. ...... . uimm6:6 .. uimm4:4 rn:5 rd:5 &rri_tag + +ADDG_i 1 00 100011 0 ...... 00 .... ..... ..... @addsub_imm_tag +SUBG_i 1 10 100011 0 ...... 00 .... ..... ..... @addsub_imm_tag diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index fb12122a3fb..3636eaadce6 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -4244,49 +4244,36 @@ TRANS(SUBS_i, gen_rri, a, 0, 1, a->sf ? gen_sub64_CC : gen_sub32_CC) /* * Add/subtract (immediate, with tags) - * - * 31 30 29 28 23 22 21 16 14 10 9 5 4 0 - * +--+--+--+-------------+--+---------+--+-------+-----+-----+ - * |sf|op| S| 1 0 0 0 1 1 |o2| uimm6 |o3| uimm4 | Rn | Rd | - * +--+--+--+-------------+--+---------+--+-------+-----+-----+ - * - * op: 0 -> add, 1 -> sub */ -static void disas_add_sub_imm_with_tags(DisasContext *s, uint32_t insn) + +static bool gen_add_sub_imm_with_tags(DisasContext *s, arg_rri_tag *a, + bool sub_op) { - int rd = extract32(insn, 0, 5); - int rn = extract32(insn, 5, 5); - int uimm4 = extract32(insn, 10, 4); - int uimm6 = extract32(insn, 16, 6); - bool sub_op = extract32(insn, 30, 1); TCGv_i64 tcg_rn, tcg_rd; int imm; - /* Test all of sf=1, S=0, o2=0, o3=0. */ - if ((insn & 0xa040c000u) != 0x80000000u || - !dc_isar_feature(aa64_mte_insn_reg, s)) { - unallocated_encoding(s); - return; - } - - imm = uimm6 << LOG2_TAG_GRANULE; + imm = a->uimm6 << LOG2_TAG_GRANULE; if (sub_op) { imm = -imm; } - tcg_rn = cpu_reg_sp(s, rn); - tcg_rd = cpu_reg_sp(s, rd); + tcg_rn = cpu_reg_sp(s, a->rn); + tcg_rd = cpu_reg_sp(s, a->rd); if (s->ata) { gen_helper_addsubg(tcg_rd, cpu_env, tcg_rn, tcg_constant_i32(imm), - tcg_constant_i32(uimm4)); + tcg_constant_i32(a->uimm4)); } else { tcg_gen_addi_i64(tcg_rd, tcg_rn, imm); gen_address_with_allocation_tag0(tcg_rd, tcg_rd); } + return true; } +TRANS_FEAT(ADDG_i, aa64_mte_insn_reg, gen_add_sub_imm_with_tags, a, false) +TRANS_FEAT(SUBG_i, aa64_mte_insn_reg, gen_add_sub_imm_with_tags, a, true) + /* The input should be a value in the bottom e bits (with higher * bits zero); returns that value replicated into every element * of size e in a 64 bit integer. @@ -4638,9 +4625,6 @@ static void disas_extract(DisasContext *s, uint32_t insn) static void disas_data_proc_imm(DisasContext *s, uint32_t insn) { switch (extract32(insn, 23, 6)) { - case 0x23: /* Add/subtract (immediate, with tags) */ - disas_add_sub_imm_with_tags(s, insn); - break; case 0x24: /* Logical (immediate) */ disas_logic_imm(s, insn); break; From patchwork Fri May 12 14:40:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 681188 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a41:0:0:0:0:0 with SMTP id v1csp3995711wrs; Fri, 12 May 2023 07:46:54 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4pmkz+jeNnIxEL1ix5v/z1QPagNmfknbFCTWLK3VDkUDIqqd/GFBYvjy5GCaU+Zbc243Hh X-Received: by 2002:a05:622a:1:b0:3f3:a3f5:a3b2 with SMTP id x1-20020a05622a000100b003f3a3f5a3b2mr15840920qtw.8.1683902814075; Fri, 12 May 2023 07:46:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683902814; cv=none; d=google.com; s=arc-20160816; b=S1LjnOvJyNOkd7KOC/cp0DMjcoPTZxbcy26B7Y7l0RR4g0hIzJh18ed8748erixDq4 hkpxFszqhVGcABdxMp4ue5YTH2A16eNBAn1vzwp0MKr1lJpIfabm2mJ4bAQvcFWyxIiV iezMKSFm6T67qUuwXaLjlZJooEgybthro/dYdVBmiJOtENMX97g8bqpIUe/umV4orCI0 ucYO6jstSagbPrYX4nmpodAxZjU0s8E4ZWMZ3D2cbrbRBSUdC7ChXeCSaWwhArWNMcpd mnPO6s9DWQ71zPFQGmL8qX2LHu6itthIgXK54wFB0I2cfphDIXlAOQc8ou66qFlE2ZtK 5udA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=revwXBl9aAHbzWWzTWkngt/4BFcUn4Y6B3F5VwQ0pkc=; b=BCGVMTiJyT2XuqDw/mOcoaRXoBIA+o1VxMNvsWSOdkvbHGTC7vdBGxYT6aUlKgWSCk V3o2/4kHj5pq1UyoDJk4//KcSwWlZfOo01dBwMmYcKPp2jCbRyXAnl+VyGxqrjZZngHv /kfUBOuCp7vxwM707FAjsb4Uzb1w9bBHzD1t8uLl8eNpFz9ifnjZ3g/3D8vgYc0K7Ncv YtjBACJhqjg/MOlMbHLdHpEke+x4NkI7DD6IoEqL0284TOiLwsxhp45QU9nqFyeyoYU1 fGB/jlbgOo9ooOt087R1uXtVspmtGP+zTqivQYRNPnM1atvRPIt45tUSk0MnlJecNXC7 DfOg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=AebWqY1u; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12-20020a7bcc0c000000b003f17848673fsm28916167wmh.27.2023.05.12.07.41.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 May 2023 07:41:11 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Richard Henderson Subject: [PATCH 08/20] target/arm: Replace bitmask64 with MAKE_64BIT_MASK Date: Fri, 12 May 2023 15:40:54 +0100 Message-Id: <20230512144106.3608981-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230512144106.3608981-1-peter.maydell@linaro.org> References: <20230512144106.3608981-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson Use the bitops.h macro rather than rolling our own here. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/tcg/translate-a64.c | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 3636eaadce6..ca944344a6b 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -4288,13 +4288,6 @@ static uint64_t bitfield_replicate(uint64_t mask, unsigned int e) return mask; } -/* Return a value with the bottom len bits set (where 0 < len <= 64) */ -static inline uint64_t bitmask64(unsigned int length) -{ - assert(length > 0 && length <= 64); - return ~0ULL >> (64 - length); -} - /* Simplified variant of pseudocode DecodeBitMasks() for the case where we * only require the wmask. Returns false if the imms/immr/immn are a reserved * value (ie should cause a guest UNDEF exception), and true if they are @@ -4350,10 +4343,10 @@ bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn, /* Create the value of one element: s+1 set bits rotated * by r within the element (which is e bits wide)... */ - mask = bitmask64(s + 1); + mask = MAKE_64BIT_MASK(0, s + 1); if (r) { mask = (mask >> r) | (mask << (e - r)); - mask &= bitmask64(e); + mask &= MAKE_64BIT_MASK(0, e); } /* ...then replicate the element over the whole 64 bit value */ mask = bitfield_replicate(mask, e); From patchwork Fri May 12 14:40:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 681178 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a41:0:0:0:0:0 with SMTP id v1csp3994281wrs; Fri, 12 May 2023 07:43:58 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7kgbEOUEFZzqw7Bo21JUPEwsPGnMj3ieMt11RJvt3ca/cmJnzE8Q4WhNy4W0+pIMvccFaw X-Received: by 2002:ac8:7c4d:0:b0:3f1:a6d:d976 with SMTP id o13-20020ac87c4d000000b003f10a6dd976mr36968665qtv.48.1683902638544; Fri, 12 May 2023 07:43:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683902638; cv=none; d=google.com; s=arc-20160816; b=VGOrSgjvNxcvxdlgFsGtv51w8mU8k3BFvebnZWBAxCPLgOCjhEmFUqhWy1J3ma9gwE G9MalanMvvuIH3W2fNFOJGvFpyG4ZEeUsMPwudripr61hylowtCpw6oyw1RvbyIYaMsO 0mDcsthNY6SNI3BTfNhlv49D9HqS6xPvkEo8WzdrAXRXmsXx4tCesG0XEN2zmhWaLHRA 4RMPjqrtmqLgLHOOgUK0dwP3TxeWTJfi9LSzql/qVOP1MeMq220AyVlYoCgejk3ZNJDj /m8KAExj/Nd18JNwQmjjJE/3e4eIXvMJPvoNrf9FrAlevkitI4n84SRYA/J8YSA8PtXW Dy/Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=8VmUpPNfulKIqx7VImc6HCqVD/o1vD/KA6yv49cC5Pk=; b=FCySEckvbP5fk1hq9ztGmxE/VWQlI+Oct0Pj4m/67yrJrHwXKOeLifyyCyyj++Msxo G8eyQrlGY5rGI291cRmV41dxQpWhlXyTxpczKujkG7/L7RjlnxP5Divn3u7tXnJM/ziH +sVLJ+CDT4mLq31u+3YZjohr3EUBh2E/X8LFayFoYIhlu3CL+sWxOnez1QOZ5/rf8JC6 s6f2Rzy9gVFqOEI3pivQrj2GfKG1qHG7FR4CzHh/JPOC4AqCOD0mnOtFEA6dAsPzF6Nh YJ71PrUKbTfiREA4gxHpFanM140gP3dYKjQ6n0JbmVj0K7ZYGfapbfg9hl6eO6HxegK0 kaKw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WkN4qbdM; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12-20020a7bcc0c000000b003f17848673fsm28916167wmh.27.2023.05.12.07.41.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 May 2023 07:41:12 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Richard Henderson Subject: [PATCH 09/20] target/arm: Convert Logical (immediate) to decodetree Date: Fri, 12 May 2023 15:40:55 +0100 Message-Id: <20230512144106.3608981-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230512144106.3608981-1-peter.maydell@linaro.org> References: <20230512144106.3608981-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson Convert the ADD, ORR, EOR, ANDS (immediate) instructions. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell [PMM: rebased] Signed-off-by: Peter Maydell --- target/arm/tcg/a64.decode | 15 ++++++ target/arm/tcg/translate-a64.c | 94 +++++++++++----------------------- 2 files changed, 44 insertions(+), 65 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index ed03d9e1349..1933afa457b 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -56,3 +56,18 @@ SUBS_i . 11 100010 1 ............ ..... ..... @addsub_imm12 ADDG_i 1 00 100011 0 ...... 00 .... ..... ..... @addsub_imm_tag SUBG_i 1 10 100011 0 ...... 00 .... ..... ..... @addsub_imm_tag + +# Logical (immediate) + +&rri_log rd rn sf dbm +@logic_imm_64 1 .. ...... dbm:13 rn:5 rd:5 &rri_log sf=1 +@logic_imm_32 0 .. ...... 0 dbm:12 rn:5 rd:5 &rri_log sf=0 + +AND_i . 00 100100 . ...... ...... ..... ..... @logic_imm_64 +AND_i . 00 100100 . ...... ...... ..... ..... @logic_imm_32 +ORR_i . 01 100100 . ...... ...... ..... ..... @logic_imm_64 +ORR_i . 01 100100 . ...... ...... ..... ..... @logic_imm_32 +EOR_i . 10 100100 . ...... ...... ..... ..... @logic_imm_64 +EOR_i . 10 100100 . ...... ...... ..... ..... @logic_imm_32 +ANDS_i . 11 100100 . ...... ...... ..... ..... @logic_imm_64 +ANDS_i . 11 100100 . ...... ...... ..... ..... @logic_imm_32 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index ca944344a6b..1273c4de456 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -4288,7 +4288,12 @@ static uint64_t bitfield_replicate(uint64_t mask, unsigned int e) return mask; } -/* Simplified variant of pseudocode DecodeBitMasks() for the case where we +/* + * Logical (immediate) + */ + +/* + * Simplified variant of pseudocode DecodeBitMasks() for the case where we * only require the wmask. Returns false if the imms/immr/immn are a reserved * value (ie should cause a guest UNDEF exception), and true if they are * valid, in which case the decoded bit pattern is written to result. @@ -4354,78 +4359,40 @@ bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn, return true; } -/* Logical (immediate) - * 31 30 29 28 23 22 21 16 15 10 9 5 4 0 - * +----+-----+-------------+---+------+------+------+------+ - * | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd | - * +----+-----+-------------+---+------+------+------+------+ - */ -static void disas_logic_imm(DisasContext *s, uint32_t insn) +static bool gen_rri_log(DisasContext *s, arg_rri_log *a, bool set_cc, + void (*fn)(TCGv_i64, TCGv_i64, int64_t)) { - unsigned int sf, opc, is_n, immr, imms, rn, rd; TCGv_i64 tcg_rd, tcg_rn; - uint64_t wmask; - bool is_and = false; + uint64_t imm; - sf = extract32(insn, 31, 1); - opc = extract32(insn, 29, 2); - is_n = extract32(insn, 22, 1); - immr = extract32(insn, 16, 6); - imms = extract32(insn, 10, 6); - rn = extract32(insn, 5, 5); - rd = extract32(insn, 0, 5); - - if (!sf && is_n) { - unallocated_encoding(s); - return; + /* Some immediate field values are reserved. */ + if (!logic_imm_decode_wmask(&imm, extract32(a->dbm, 12, 1), + extract32(a->dbm, 0, 6), + extract32(a->dbm, 6, 6))) { + return false; + } + if (!a->sf) { + imm &= 0xffffffffull; } - if (opc == 0x3) { /* ANDS */ - tcg_rd = cpu_reg(s, rd); - } else { - tcg_rd = cpu_reg_sp(s, rd); - } - tcg_rn = cpu_reg(s, rn); + tcg_rd = set_cc ? cpu_reg(s, a->rd) : cpu_reg_sp(s, a->rd); + tcg_rn = cpu_reg(s, a->rn); - if (!logic_imm_decode_wmask(&wmask, is_n, imms, immr)) { - /* some immediate field values are reserved */ - unallocated_encoding(s); - return; + fn(tcg_rd, tcg_rn, imm); + if (set_cc) { + gen_logic_CC(a->sf, tcg_rd); } - - if (!sf) { - wmask &= 0xffffffff; - } - - switch (opc) { - case 0x3: /* ANDS */ - case 0x0: /* AND */ - tcg_gen_andi_i64(tcg_rd, tcg_rn, wmask); - is_and = true; - break; - case 0x1: /* ORR */ - tcg_gen_ori_i64(tcg_rd, tcg_rn, wmask); - break; - case 0x2: /* EOR */ - tcg_gen_xori_i64(tcg_rd, tcg_rn, wmask); - break; - default: - assert(FALSE); /* must handle all above */ - break; - } - - if (!sf && !is_and) { - /* zero extend final result; we know we can skip this for AND - * since the immediate had the high 32 bits clear. - */ + if (!a->sf) { tcg_gen_ext32u_i64(tcg_rd, tcg_rd); } - - if (opc == 3) { /* ANDS */ - gen_logic_CC(sf, tcg_rd); - } + return true; } +TRANS(AND_i, gen_rri_log, a, false, tcg_gen_andi_i64) +TRANS(ORR_i, gen_rri_log, a, false, tcg_gen_ori_i64) +TRANS(EOR_i, gen_rri_log, a, false, tcg_gen_xori_i64) +TRANS(ANDS_i, gen_rri_log, a, true, tcg_gen_andi_i64) + /* * Move wide (immediate) * @@ -4618,9 +4585,6 @@ static void disas_extract(DisasContext *s, uint32_t insn) static void disas_data_proc_imm(DisasContext *s, uint32_t insn) { switch (extract32(insn, 23, 6)) { - case 0x24: /* Logical (immediate) */ - disas_logic_imm(s, insn); - break; case 0x25: /* Move wide (immediate) */ disas_movw_imm(s, insn); break; From patchwork Fri May 12 14:40:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 681174 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a41:0:0:0:0:0 with SMTP id v1csp3993946wrs; Fri, 12 May 2023 07:43:14 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4wNA6pmfAh395UqG9J3ePpGM0SUMX9JACszrR10gG4ZJvExzvIBt/VaBWOBx25S64YUztk X-Received: by 2002:a05:6214:20ac:b0:621:26de:2c9d with SMTP id 12-20020a05621420ac00b0062126de2c9dmr24514514qvd.50.1683902594222; Fri, 12 May 2023 07:43:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683902594; cv=none; d=google.com; s=arc-20160816; b=HjoCkZ3ZMy+h6jPIMUaLIqyCgT87x/gETxiAxSZJ/vKfmaI42aLyh0D0ZqwUM9fZ5X pHHpHXJe8FoLmpY7OZrawEN3o+vHMsZgXzesywmJo2v26Meuo4295UoadxwDE84QEQsw pZSbVvxbMToKGsvrDMMTALvdolHGYH9GfswsUXJ38SADDaZ6IZaIiCcHnAeRQTVFyWLx 0I2ZTCFd/ioGxJtxT956rYbTMMMUQ4WCZgNW5PNhQKxtEAcOwhFgDMxxkyUFy15qxipa rvypO7Dx2X3S3aqdjQgl+ffRgtrIiLB4Ca47y8Nd8bSy8czizlk+N6RaPzInlZXSa7WG 0qvw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Nzdtd8sSIBwgurLXo/J3BqpDdo3UGdPx+81efDnWFSc=; b=cTfFdv53d1nHh2ucSO1Fz80JMGGOdqPK9a0gDhPEn1fxHcDlOvwXy+FmSBqXgodui2 BUNR3vxPMRPOwVCUZtfEYG6nBYEX1lbGCFx2tq54OzPvysIuaNyRGQta9vUAKBbwBDxA 8SL0UOc/fdC9bHAH3aRtA3am0EtWcNAMyRgGyhFgn8Bx/mo9WSThv+cJcIdqYE+0+Uyx VjIP9KJAuif5n1N0oAD3VyBRhVGqbUwPnaKPilV7Ov7WE4W3U29qrgnIF+cnWsPA5BsA hfPPQYP08iWLP9SuJT5s/nEGPuLo2vcsLcRaMmijuqbrfCt0XgQ24TicAAtJU7gE2l8t hAcA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=nYq+L2cq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12-20020a7bcc0c000000b003f17848673fsm28916167wmh.27.2023.05.12.07.41.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 May 2023 07:41:12 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Richard Henderson Subject: [PATCH 10/20] target/arm: Convert Move wide (immediate) to decodetree Date: Fri, 12 May 2023 15:40:56 +0100 Message-Id: <20230512144106.3608981-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230512144106.3608981-1-peter.maydell@linaro.org> References: <20230512144106.3608981-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson Convert the MON, MOVZ, MOVK instructions. Signed-off-by: Richard Henderson [PMM: Rebased] Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/tcg/a64.decode | 13 ++++++ target/arm/tcg/translate-a64.c | 73 ++++++++++++++-------------------- 2 files changed, 42 insertions(+), 44 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 1933afa457b..350b37c8f37 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -71,3 +71,16 @@ EOR_i . 10 100100 . ...... ...... ..... ..... @logic_imm_64 EOR_i . 10 100100 . ...... ...... ..... ..... @logic_imm_32 ANDS_i . 11 100100 . ...... ...... ..... ..... @logic_imm_64 ANDS_i . 11 100100 . ...... ...... ..... ..... @logic_imm_32 + +# Move wide (immediate) + +&movw rd sf imm hw +@movw_64 1 .. ...... hw:2 imm:16 rd:5 &movw sf=1 +@movw_32 0 .. ...... 0 hw:1 imm:16 rd:5 &movw sf=0 + +MOVN . 00 100101 .. ................ ..... @movw_64 +MOVN . 00 100101 .. ................ ..... @movw_32 +MOVZ . 10 100101 .. ................ ..... @movw_64 +MOVZ . 10 100101 .. ................ ..... @movw_32 +MOVK . 11 100101 .. ................ ..... @movw_64 +MOVK . 11 100101 .. ................ ..... @movw_32 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 1273c4de456..a36b98925fb 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -4395,52 +4395,40 @@ TRANS(ANDS_i, gen_rri_log, a, true, tcg_gen_andi_i64) /* * Move wide (immediate) - * - * 31 30 29 28 23 22 21 20 5 4 0 - * +--+-----+-------------+-----+----------------+------+ - * |sf| opc | 1 0 0 1 0 1 | hw | imm16 | Rd | - * +--+-----+-------------+-----+----------------+------+ - * - * sf: 0 -> 32 bit, 1 -> 64 bit - * opc: 00 -> N, 10 -> Z, 11 -> K - * hw: shift/16 (0,16, and sf only 32, 48) */ -static void disas_movw_imm(DisasContext *s, uint32_t insn) + +static bool trans_MOVZ(DisasContext *s, arg_movw *a) { - int rd = extract32(insn, 0, 5); - uint64_t imm = extract32(insn, 5, 16); - int sf = extract32(insn, 31, 1); - int opc = extract32(insn, 29, 2); - int pos = extract32(insn, 21, 2) << 4; - TCGv_i64 tcg_rd = cpu_reg(s, rd); + int pos = a->hw << 4; + tcg_gen_movi_i64(cpu_reg(s, a->rd), (uint64_t)a->imm << pos); + return true; +} - if (!sf && (pos >= 32)) { - unallocated_encoding(s); - return; - } +static bool trans_MOVN(DisasContext *s, arg_movw *a) +{ + int pos = a->hw << 4; + uint64_t imm = a->imm; - switch (opc) { - case 0: /* MOVN */ - case 2: /* MOVZ */ - imm <<= pos; - if (opc == 0) { - imm = ~imm; - } - if (!sf) { - imm &= 0xffffffffu; - } - tcg_gen_movi_i64(tcg_rd, imm); - break; - case 3: /* MOVK */ - tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_constant_i64(imm), pos, 16); - if (!sf) { - tcg_gen_ext32u_i64(tcg_rd, tcg_rd); - } - break; - default: - unallocated_encoding(s); - break; + imm = ~(imm << pos); + if (!a->sf) { + imm = (uint32_t)imm; } + tcg_gen_movi_i64(cpu_reg(s, a->rd), imm); + return true; +} + +static bool trans_MOVK(DisasContext *s, arg_movw *a) +{ + int pos = a->hw << 4; + TCGv_i64 tcg_rd, tcg_im; + + tcg_rd = cpu_reg(s, a->rd); + tcg_im = tcg_constant_i64(a->imm); + tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_im, pos, 16); + if (!a->sf) { + tcg_gen_ext32u_i64(tcg_rd, tcg_rd); + } + return true; } /* Bitfield @@ -4585,9 +4573,6 @@ static void disas_extract(DisasContext *s, uint32_t insn) static void disas_data_proc_imm(DisasContext *s, uint32_t insn) { switch (extract32(insn, 23, 6)) { - case 0x25: /* Move wide (immediate) */ - disas_movw_imm(s, insn); - break; case 0x26: /* Bitfield */ disas_bitfield(s, insn); break; From patchwork Fri May 12 14:40:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 681184 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a41:0:0:0:0:0 with SMTP id v1csp3995080wrs; Fri, 12 May 2023 07:45:37 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5fU18tSHFy+92fXZM5sR8S1lxZ8PXTwAarfbnxJEQTPJe5/wJmqC7ZHsnvzKHiXz+uiT5+ X-Received: by 2002:ac8:5a4a:0:b0:3f3:8e14:f5ad with SMTP id o10-20020ac85a4a000000b003f38e14f5admr29066819qta.23.1683902736959; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12-20020a7bcc0c000000b003f17848673fsm28916167wmh.27.2023.05.12.07.41.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 May 2023 07:41:13 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Richard Henderson Subject: [PATCH 11/20] target/arm: Convert Bitfield to decodetree Date: Fri, 12 May 2023 15:40:57 +0100 Message-Id: <20230512144106.3608981-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230512144106.3608981-1-peter.maydell@linaro.org> References: <20230512144106.3608981-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson Convert the BFM, SBFM, UBFM instructions. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell [PMM: Rebased] Signed-off-by: Peter Maydell --- target/arm/tcg/a64.decode | 13 +++ target/arm/tcg/translate-a64.c | 144 ++++++++++++++++++--------------- 2 files changed, 94 insertions(+), 63 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 350b37c8f37..4d5709f9857 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -84,3 +84,16 @@ MOVZ . 10 100101 .. ................ ..... @movw_64 MOVZ . 10 100101 .. ................ ..... @movw_32 MOVK . 11 100101 .. ................ ..... @movw_64 MOVK . 11 100101 .. ................ ..... @movw_32 + +# Bitfield + +&bitfield rd rn sf immr imms +@bitfield_64 1 .. ...... 1 immr:6 imms:6 rn:5 rd:5 &bitfield sf=1 +@bitfield_32 0 .. ...... 0 0 immr:5 0 imms:5 rn:5 rd:5 &bitfield sf=0 + +SBFM . 00 100110 . ...... ...... ..... ..... @bitfield_64 +SBFM . 00 100110 . ...... ...... ..... ..... @bitfield_32 +BFM . 01 100110 . ...... ...... ..... ..... @bitfield_64 +BFM . 01 100110 . ...... ...... ..... ..... @bitfield_32 +UBFM . 10 100110 . ...... ...... ..... ..... @bitfield_64 +UBFM . 10 100110 . ...... ...... ..... ..... @bitfield_32 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index a36b98925fb..f5649de60a8 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -4431,82 +4431,103 @@ static bool trans_MOVK(DisasContext *s, arg_movw *a) return true; } -/* Bitfield - * 31 30 29 28 23 22 21 16 15 10 9 5 4 0 - * +----+-----+-------------+---+------+------+------+------+ - * | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd | - * +----+-----+-------------+---+------+------+------+------+ +/* + * Bitfield */ -static void disas_bitfield(DisasContext *s, uint32_t insn) + +static bool trans_SBFM(DisasContext *s, arg_SBFM *a) { - unsigned int sf, n, opc, ri, si, rn, rd, bitsize, pos, len; - TCGv_i64 tcg_rd, tcg_tmp; + TCGv_i64 tcg_rd = cpu_reg(s, a->rd); + TCGv_i64 tcg_tmp = read_cpu_reg(s, a->rn, 1); + unsigned int bitsize = a->sf ? 64 : 32; + unsigned int ri = a->immr; + unsigned int si = a->imms; + unsigned int pos, len; - sf = extract32(insn, 31, 1); - opc = extract32(insn, 29, 2); - n = extract32(insn, 22, 1); - ri = extract32(insn, 16, 6); - si = extract32(insn, 10, 6); - rn = extract32(insn, 5, 5); - rd = extract32(insn, 0, 5); - bitsize = sf ? 64 : 32; - - if (sf != n || ri >= bitsize || si >= bitsize || opc > 2) { - unallocated_encoding(s); - return; - } - - tcg_rd = cpu_reg(s, rd); - - /* Suppress the zero-extend for !sf. Since RI and SI are constrained - to be smaller than bitsize, we'll never reference data outside the - low 32-bits anyway. */ - tcg_tmp = read_cpu_reg(s, rn, 1); - - /* Recognize simple(r) extractions. */ if (si >= ri) { /* Wd = Wn */ len = (si - ri) + 1; - if (opc == 0) { /* SBFM: ASR, SBFX, SXTB, SXTH, SXTW */ - tcg_gen_sextract_i64(tcg_rd, tcg_tmp, ri, len); - goto done; - } else if (opc == 2) { /* UBFM: UBFX, LSR, UXTB, UXTH */ - tcg_gen_extract_i64(tcg_rd, tcg_tmp, ri, len); - return; + tcg_gen_sextract_i64(tcg_rd, tcg_tmp, ri, len); + if (!a->sf) { + tcg_gen_ext32u_i64(tcg_rd, tcg_rd); } - /* opc == 1, BFXIL fall through to deposit */ + } else { + /* Wd<32+s-r,32-r> = Wn */ + len = si + 1; + pos = (bitsize - ri) & (bitsize - 1); + + if (len < ri) { + /* + * Sign extend the destination field from len to fill the + * balance of the word. Let the deposit below insert all + * of those sign bits. + */ + tcg_gen_sextract_i64(tcg_tmp, tcg_tmp, 0, len); + len = ri; + } + + /* + * We start with zero, and we haven't modified any bits outside + * bitsize, therefore no final zero-extension is unneeded for !sf. + */ + tcg_gen_deposit_z_i64(tcg_rd, tcg_tmp, pos, len); + } + return true; +} + +static bool trans_UBFM(DisasContext *s, arg_UBFM *a) +{ + TCGv_i64 tcg_rd = cpu_reg(s, a->rd); + TCGv_i64 tcg_tmp = read_cpu_reg(s, a->rn, 1); + unsigned int bitsize = a->sf ? 64 : 32; + unsigned int ri = a->immr; + unsigned int si = a->imms; + unsigned int pos, len; + + tcg_rd = cpu_reg(s, a->rd); + tcg_tmp = read_cpu_reg(s, a->rn, 1); + + if (si >= ri) { + /* Wd = Wn */ + len = (si - ri) + 1; + tcg_gen_extract_i64(tcg_rd, tcg_tmp, ri, len); + } else { + /* Wd<32+s-r,32-r> = Wn */ + len = si + 1; + pos = (bitsize - ri) & (bitsize - 1); + tcg_gen_deposit_z_i64(tcg_rd, tcg_tmp, pos, len); + } + return true; +} + +static bool trans_BFM(DisasContext *s, arg_BFM *a) +{ + TCGv_i64 tcg_rd = cpu_reg(s, a->rd); + TCGv_i64 tcg_tmp = read_cpu_reg(s, a->rn, 1); + unsigned int bitsize = a->sf ? 64 : 32; + unsigned int ri = a->immr; + unsigned int si = a->imms; + unsigned int pos, len; + + tcg_rd = cpu_reg(s, a->rd); + tcg_tmp = read_cpu_reg(s, a->rn, 1); + + if (si >= ri) { + /* Wd = Wn */ tcg_gen_shri_i64(tcg_tmp, tcg_tmp, ri); + len = (si - ri) + 1; pos = 0; } else { - /* Handle the ri > si case with a deposit - * Wd<32+s-r,32-r> = Wn - */ + /* Wd<32+s-r,32-r> = Wn */ len = si + 1; pos = (bitsize - ri) & (bitsize - 1); } - if (opc == 0 && len < ri) { - /* SBFM: sign extend the destination field from len to fill - the balance of the word. Let the deposit below insert all - of those sign bits. */ - tcg_gen_sextract_i64(tcg_tmp, tcg_tmp, 0, len); - len = ri; - } - - if (opc == 1) { /* BFM, BFXIL */ - tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, pos, len); - } else { - /* SBFM or UBFM: We start with zero, and we haven't modified - any bits outside bitsize, therefore the zero-extension - below is unneeded. */ - tcg_gen_deposit_z_i64(tcg_rd, tcg_tmp, pos, len); - return; - } - - done: - if (!sf) { /* zero extend final result */ + tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, pos, len); + if (!a->sf) { tcg_gen_ext32u_i64(tcg_rd, tcg_rd); } + return true; } /* Extract @@ -4573,9 +4594,6 @@ static void disas_extract(DisasContext *s, uint32_t insn) static void disas_data_proc_imm(DisasContext *s, uint32_t insn) { switch (extract32(insn, 23, 6)) { - case 0x26: /* Bitfield */ - disas_bitfield(s, insn); - break; case 0x27: /* Extract */ disas_extract(s, insn); break; From patchwork Fri May 12 14:40:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 681181 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a41:0:0:0:0:0 with SMTP id v1csp3995063wrs; Fri, 12 May 2023 07:45:35 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4UDXct4lXohPBREIM3lTIOLtf/K8rG43x/tshOrIp2JLgWviA060rG/cu3sEgkp7WPz+wH X-Received: by 2002:a05:622a:15c6:b0:3f4:e4c1:5f65 with SMTP id d6-20020a05622a15c600b003f4e4c15f65mr9431738qty.23.1683902735744; Fri, 12 May 2023 07:45:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683902735; cv=none; d=google.com; s=arc-20160816; b=BtjHkWSZJ0hg2R2CoqymLdWl/38++L2JF/juOGlKMUcDIlKXmELsbW7vHSKnFNsCHU nVjQT5TNPD1s8Cs2Az/cVUPCHJ6x44G0ZuwX4euJY/Je+39zaqbVZcywRlzt4KGty1za seYXBx004sXIfpz6B+inQH0emCjdKIJcbMg8GW5qSLiaSP+2h7ECKj4MS5ovUZHrJiOE Ufn7FRNs8S6vskNq1S1ZjrPTVsy3VdppMrcb4mr6sPtFwP4mecLwDjpBdkDwsqvlUT8U HEtq7lzSg2SJCtEO2sqemhUjWvArD1XO5xgjYw7kf20DBkKD48FlITss1dLlmC0aWldZ vGAA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=WFWx3ixalVla371utWzQEGMgJNlwfauaj/lO3THOe6A=; b=tRl43k6tv13q9mId7B9ukOUtjG1WOinBNUv0YJoXGgaabxffUSSyjZvCD4LBfhsyR3 ukhJ9rcWwfPfxVCwJfzagMT4OKDepkE7OnEBtsADkMwYSsmY8a6O8cWspbQA7cYzh/E1 HauprC3/HPW46XXTMH2Zre924gd6/j3xv2YlfRiBKspJxL9KtAvh+RJz8IfNl3b4xbGQ qFcmj/rzTomUvYiLq9v7j+aoxX0ygUU1xSoAGSf97EPi2JSwXEw2qrF/p3KLRaAOkG+B wGO0ogd1ygXsegtmDs2TExsMVLp3DBydGD12YHPxT54ATiuQOZ5ZGn+ijj0+DZnWuDP3 21wQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ku+z6cFi; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12-20020a7bcc0c000000b003f17848673fsm28916167wmh.27.2023.05.12.07.41.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 May 2023 07:41:13 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Richard Henderson Subject: [PATCH 12/20] target/arm: Convert Extract instructions to decodetree Date: Fri, 12 May 2023 15:40:58 +0100 Message-Id: <20230512144106.3608981-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230512144106.3608981-1-peter.maydell@linaro.org> References: <20230512144106.3608981-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Convert the EXTR instruction to decodetree (this is the only one in the 'Extract" class). This is the last of the dp-immediate insns in the legacy decoder, so we can now remove disas_data_proc_imm(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/tcg/a64.decode | 9 ++++ target/arm/tcg/translate-a64.c | 94 +++++++++++----------------------- 2 files changed, 38 insertions(+), 65 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 4d5709f9857..eb5d4cb0d57 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -97,3 +97,12 @@ BFM . 01 100110 . ...... ...... ..... ..... @bitfield_64 BFM . 01 100110 . ...... ...... ..... ..... @bitfield_32 UBFM . 10 100110 . ...... ...... ..... ..... @bitfield_64 UBFM . 10 100110 . ...... ...... ..... ..... @bitfield_32 + +# Extract + +&extract rd rn rm imm sf +@extract_64 1 .. ...... 1 . rm:5 imm:6 rn:5 rd:5 &extract sf=1 +@extract_32 0 .. ...... 0 . rm:5 0 imm:5 rn:5 rd:5 &extract sf=0 + +EXTR . 00 100111 . 0 ..... ...... ..... ..... @extract_64 +EXTR . 00 100111 . 0 ..... ...... ..... ..... @extract_32 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index f5649de60a8..4319559057f 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -4530,77 +4530,44 @@ static bool trans_BFM(DisasContext *s, arg_BFM *a) return true; } -/* Extract - * 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0 - * +----+------+-------------+---+----+------+--------+------+------+ - * | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd | - * +----+------+-------------+---+----+------+--------+------+------+ - */ -static void disas_extract(DisasContext *s, uint32_t insn) +static bool trans_EXTR(DisasContext *s, arg_extract *a) { - unsigned int sf, n, rm, imm, rn, rd, bitsize, op21, op0; + TCGv_i64 tcg_rd, tcg_rm, tcg_rn; - sf = extract32(insn, 31, 1); - n = extract32(insn, 22, 1); - rm = extract32(insn, 16, 5); - imm = extract32(insn, 10, 6); - rn = extract32(insn, 5, 5); - rd = extract32(insn, 0, 5); - op21 = extract32(insn, 29, 2); - op0 = extract32(insn, 21, 1); - bitsize = sf ? 64 : 32; + tcg_rd = cpu_reg(s, a->rd); - if (sf != n || op21 || op0 || imm >= bitsize) { - unallocated_encoding(s); - } else { - TCGv_i64 tcg_rd, tcg_rm, tcg_rn; - - tcg_rd = cpu_reg(s, rd); - - if (unlikely(imm == 0)) { - /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts, - * so an extract from bit 0 is a special case. - */ - if (sf) { - tcg_gen_mov_i64(tcg_rd, cpu_reg(s, rm)); - } else { - tcg_gen_ext32u_i64(tcg_rd, cpu_reg(s, rm)); - } + if (unlikely(a->imm == 0)) { + /* + * tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts, + * so an extract from bit 0 is a special case. + */ + if (a->sf) { + tcg_gen_mov_i64(tcg_rd, cpu_reg(s, a->rm)); } else { - tcg_rm = cpu_reg(s, rm); - tcg_rn = cpu_reg(s, rn); + tcg_gen_ext32u_i64(tcg_rd, cpu_reg(s, a->rm)); + } + } else { + tcg_rm = cpu_reg(s, a->rm); + tcg_rn = cpu_reg(s, a->rn); - if (sf) { - /* Specialization to ROR happens in EXTRACT2. */ - tcg_gen_extract2_i64(tcg_rd, tcg_rm, tcg_rn, imm); + if (a->sf) { + /* Specialization to ROR happens in EXTRACT2. */ + tcg_gen_extract2_i64(tcg_rd, tcg_rm, tcg_rn, a->imm); + } else { + TCGv_i32 t0 = tcg_temp_new_i32(); + + tcg_gen_extrl_i64_i32(t0, tcg_rm); + if (a->rm == a->rn) { + tcg_gen_rotri_i32(t0, t0, a->imm); } else { - TCGv_i32 t0 = tcg_temp_new_i32(); - - tcg_gen_extrl_i64_i32(t0, tcg_rm); - if (rm == rn) { - tcg_gen_rotri_i32(t0, t0, imm); - } else { - TCGv_i32 t1 = tcg_temp_new_i32(); - tcg_gen_extrl_i64_i32(t1, tcg_rn); - tcg_gen_extract2_i32(t0, t0, t1, imm); - } - tcg_gen_extu_i32_i64(tcg_rd, t0); + TCGv_i32 t1 = tcg_temp_new_i32(); + tcg_gen_extrl_i64_i32(t1, tcg_rn); + tcg_gen_extract2_i32(t0, t0, t1, a->imm); } + tcg_gen_extu_i32_i64(tcg_rd, t0); } } -} - -/* Data processing - immediate */ -static void disas_data_proc_imm(DisasContext *s, uint32_t insn) -{ - switch (extract32(insn, 23, 6)) { - case 0x27: /* Extract */ - disas_extract(s, insn); - break; - default: - unallocated_encoding(s); - break; - } + return true; } /* Shift a TCGv src by TCGv shift_amount, put result in dst. @@ -14125,9 +14092,6 @@ static bool btype_destination_ok(uint32_t insn, bool bt, int btype) static void disas_a64_legacy(DisasContext *s, uint32_t insn) { switch (extract32(insn, 25, 4)) { - case 0x8: case 0x9: /* Data processing - immediate */ - disas_data_proc_imm(s, insn); - break; case 0xa: case 0xb: /* Branch, exception generation and system insns */ disas_b_exc_sys(s, insn); break; From patchwork Fri May 12 14:40:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 681173 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a41:0:0:0:0:0 with SMTP id v1csp3993938wrs; Fri, 12 May 2023 07:43:13 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6Q0KNDtmgtQRcMe4oj2yf/qMJ+TFlGny4UA2Jy63Rxp6D/0WBclv1tYHFJD8j38HtS8S1h X-Received: by 2002:a05:622a:3cc:b0:3eb:13e5:7bd9 with SMTP id k12-20020a05622a03cc00b003eb13e57bd9mr39184220qtx.27.1683902593034; Fri, 12 May 2023 07:43:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683902593; cv=none; d=google.com; s=arc-20160816; b=E8GyNSLpjZFADSX8rmvacy8Aw7qvgw4u4y1BUIOff58ZVJv+lyW/WVam8V6ZwKylWv 2k/GGpxh4pOj7ijxe0RmkHxUIWn2WjW0Hu7ozdnsDFSg4Fi4W1Ef9BWvDiXnxhCgMARN YJHzQnkQyEQvoDKXM3RqrfsBGjglYvKi9onxvDjclc6efX0zPjUSP/jTgrMkEkRnQ37g UvlZk1hjLkTl0xd0AOcH7ix6gDt5RgNBe5orm7OofkC9sYCHm2Md2kfayHvav394uW5P gkPTm0LIbSXVmrJinG5epHPRNhaN8I3j6Z3C/CSIDdaEB7Q/EOGbswCV2McKwN1fhG9X ZEXg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=yE0yzHpn5HGcapGUBNgyOVRbnrVrPALQXSeI3NGRfYY=; b=lZ9mCtwBHKY2pvgGXaJK70URDnU3/uKy3yBRGUVe/bUTVoM7E+xcoXeTiTq2UuRXpr rFxyijx1Ea0gsbkiKZwdGOIm6tDyO0R9u3CMuQpeNRJRS5geRW8obrHxJxudRFdYzTM8 RAcirUqLV6WZbJlZcip49JYVWV9aLygaKMCnNNg1M9NIoJ4SQsOp9MR0CbFe3aphlcdp ob/E3WMF/g7UYO3Rer2mrJ77N9M6YNR50LDichy6PMwb2oBYOW9uIrte/S9RDpeZMrho ocDuyaptVSpNYdZ9GlAWw5L7qQGLcfBZnZrdxmv2ZU5y/1/Hz9btxXztspuCgHpBSUjq 1LFw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=oQjj7qB4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12-20020a7bcc0c000000b003f17848673fsm28916167wmh.27.2023.05.12.07.41.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 May 2023 07:41:14 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Richard Henderson Subject: [PATCH 13/20] target/arm: Convert unconditional branch immediate to decodetree Date: Fri, 12 May 2023 15:40:59 +0100 Message-Id: <20230512144106.3608981-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230512144106.3608981-1-peter.maydell@linaro.org> References: <20230512144106.3608981-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Convert the unconditional branch immediate insns B and BL to decodetree. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/tcg/a64.decode | 9 +++++++++ target/arm/tcg/translate-a64.c | 31 +++++++++++-------------------- 2 files changed, 20 insertions(+), 20 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index eb5d4cb0d57..d54c6522028 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -21,6 +21,7 @@ &ri rd imm &rri_sf rd rn imm sf +&i imm ### Data Processing - Immediate @@ -106,3 +107,11 @@ UBFM . 10 100110 . ...... ...... ..... ..... @bitfield_32 EXTR . 00 100111 . 0 ..... ...... ..... ..... @extract_64 EXTR . 00 100111 . 0 ..... ...... ..... ..... @extract_32 + +# Branches + +%imm26 0:s26 !function=times_4 +@branch . ..... .......................... &i imm=%imm26 + +B 0 00101 .......................... @branch +BL 1 00101 .......................... @branch diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 4319559057f..fe6b4a68288 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -1319,24 +1319,19 @@ static inline AArch64DecodeFn *lookup_disas_fn(const AArch64DecodeTable *table, * match up with those in the manual. */ -/* Unconditional branch (immediate) - * 31 30 26 25 0 - * +----+-----------+-------------------------------------+ - * | op | 0 0 1 0 1 | imm26 | - * +----+-----------+-------------------------------------+ - */ -static void disas_uncond_b_imm(DisasContext *s, uint32_t insn) +static bool trans_B(DisasContext *s, arg_i *a) { - int64_t diff = sextract32(insn, 0, 26) * 4; - - if (insn & (1U << 31)) { - /* BL Branch with link */ - gen_pc_plus_diff(s, cpu_reg(s, 30), curr_insn_len(s)); - } - - /* B Branch / BL Branch with link */ reset_btype(s); - gen_goto_tb(s, 0, diff); + gen_goto_tb(s, 0, a->imm); + return true; +} + +static bool trans_BL(DisasContext *s, arg_i *a) +{ + gen_pc_plus_diff(s, cpu_reg(s, 30), curr_insn_len(s)); + reset_btype(s); + gen_goto_tb(s, 0, a->imm); + return true; } /* Compare and branch (immediate) @@ -2413,10 +2408,6 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) static void disas_b_exc_sys(DisasContext *s, uint32_t insn) { switch (extract32(insn, 25, 7)) { - case 0x0a: case 0x0b: - case 0x4a: case 0x4b: /* Unconditional branch (immediate) */ - disas_uncond_b_imm(s, insn); - break; case 0x1a: case 0x5a: /* Compare & branch (immediate) */ disas_comp_b_imm(s, insn); break; From patchwork Fri May 12 14:41:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 681176 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a41:0:0:0:0:0 with SMTP id v1csp3994068wrs; Fri, 12 May 2023 07:43:28 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4FQ2JjRa5NnwT5iNq1Sr/Lueu9g+t69vE78nL7dGGqFomTfy5CrsUbBIszZggyxBmEbzEQ X-Received: by 2002:ad4:5961:0:b0:621:4551:c6dc with SMTP id eq1-20020ad45961000000b006214551c6dcmr13153344qvb.39.1683902608150; Fri, 12 May 2023 07:43:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683902608; cv=none; d=google.com; s=arc-20160816; b=FcYRry7WoHe5MID8DW+JRrFRgwslbCRrVIdNT0C5bof0Qx1OlOGAokWKrgi6s3SzC3 /1OTjzKCbHHUEFltMzEd5ipyd/00SoFjNOTvMBqg4SdZy++U3i3zABPqqUr8Rvc4GwJO gcGPLgNqcgIJEfcZBJndsNdBhmGQN2jFwfre6klGUT6yoPcuhFEgw0ok3oUAXqWRy/CY uIwn8/yfAxFFmmRkhWc2W58gSmLAfYIw8Ohdqs6SANFiTZPmUu4zN1tyGpOWsUGPI/7o +0KlrCfKZvEPy++2/T9xqHXdBb/LN1mbF5YCutCQafeD++rwZLsg9/R8R+tizc6hIitT MMBQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=b35BwkiFX8fqUrD1Px2IqZe/3AgM9JZzroufYhPa+ao=; b=byJicebLpLnw+BGIyB52b9APw3qOcGtUahMasUUgZVSY5KznlCP+yzR0S8KT8Xxbz/ rlK6ktGWyPXl87iDqKm1whCU1PBkogfTDKAAO6xtLvIkXQ16mi4qSxr/WoCd4iBfl5HS fiFryQQVp7Yn2GkeoEhPI9s4wz8OZvSWl/BXfDcww5HL9yoYDUiOnp0AhRawCnfK3hqe icL+OuGFjxNsKs0tnxTFrRLcY5+pkx8K2h7kG1+F2P31wbI+WP6hvrJN99Dtrwks7722 3D4/LhvDnmqgsFhAl41I9HPF7pJlu1RWKIi1as0j1kFj116iVJroAKpUrOzZk4KeSXcW TwVw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=T+6MivRR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12-20020a7bcc0c000000b003f17848673fsm28916167wmh.27.2023.05.12.07.41.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 May 2023 07:41:14 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Richard Henderson Subject: [PATCH 14/20] target/arm: Convert CBZ, CBNZ to decodetree Date: Fri, 12 May 2023 15:41:00 +0100 Message-Id: <20230512144106.3608981-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230512144106.3608981-1-peter.maydell@linaro.org> References: <20230512144106.3608981-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Convert the compare-and-branch-immediate insns CBZ and CBNZ to decodetree. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/tcg/a64.decode | 6 ++++++ target/arm/tcg/translate-a64.c | 26 ++++++-------------------- 2 files changed, 12 insertions(+), 20 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index d54c6522028..86220569e13 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -115,3 +115,9 @@ EXTR . 00 100111 . 0 ..... ...... ..... ..... @extract_32 B 0 00101 .......................... @branch BL 1 00101 .......................... @branch + +%imm19 5:s19 !function=times_4 +&cbz rt imm sf nz +@cbz sf:1 ...... nz:1 ................... rt:5 &cbz imm=%imm19 + +CBZ . 011010 . ................... ..... @cbz diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index fe6b4a68288..5da551385bd 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -1334,33 +1334,22 @@ static bool trans_BL(DisasContext *s, arg_i *a) return true; } -/* Compare and branch (immediate) - * 31 30 25 24 23 5 4 0 - * +----+-------------+----+---------------------+--------+ - * | sf | 0 1 1 0 1 0 | op | imm19 | Rt | - * +----+-------------+----+---------------------+--------+ - */ -static void disas_comp_b_imm(DisasContext *s, uint32_t insn) + +static bool trans_CBZ(DisasContext *s, arg_cbz *a) { - unsigned int sf, op, rt; - int64_t diff; DisasLabel match; TCGv_i64 tcg_cmp; - sf = extract32(insn, 31, 1); - op = extract32(insn, 24, 1); /* 0: CBZ; 1: CBNZ */ - rt = extract32(insn, 0, 5); - diff = sextract32(insn, 5, 19) * 4; - - tcg_cmp = read_cpu_reg(s, rt, sf); + tcg_cmp = read_cpu_reg(s, a->rt, a->sf); reset_btype(s); match = gen_disas_label(s); - tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ, + tcg_gen_brcondi_i64(a->nz ? TCG_COND_NE : TCG_COND_EQ, tcg_cmp, 0, match.label); gen_goto_tb(s, 0, 4); set_disas_label(s, match); - gen_goto_tb(s, 1, diff); + gen_goto_tb(s, 1, a->imm); + return true; } /* Test and branch (immediate) @@ -2408,9 +2397,6 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) static void disas_b_exc_sys(DisasContext *s, uint32_t insn) { switch (extract32(insn, 25, 7)) { - case 0x1a: case 0x5a: /* Compare & branch (immediate) */ - disas_comp_b_imm(s, insn); - break; case 0x1b: case 0x5b: /* Test & branch (immediate) */ disas_test_b_imm(s, insn); break; From patchwork Fri May 12 14:41:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 681183 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a41:0:0:0:0:0 with SMTP id v1csp3995075wrs; Fri, 12 May 2023 07:45:37 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6448b8+u6XR7EtuQSimYERAh0vfzwHipLJSpVqaA11BqRVduzBpjT/CCBKwwcipelYP1/V X-Received: by 2002:ac8:588d:0:b0:3e3:8e55:1e64 with SMTP id t13-20020ac8588d000000b003e38e551e64mr36956261qta.14.1683902736847; Fri, 12 May 2023 07:45:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683902736; cv=none; d=google.com; s=arc-20160816; b=kOCrJSJEuzojCqY9vXEelXS9GqoQ3fST3Yn5pRuS12AHsVstnjOCpy5q2PgrHl/rOL j2Vgk6Y0rqVAQzvvoci1u7nhjoDMlYrrYu5jfR4vgkdQmFc+9dwEpkgWMG5qoGC38bS5 Mz8AM2YmiuI8aLliml7BSLg/K1XhwwsL53xelT7+0pTOtbzIZF8s1K3btxyIRsDZ/jqm NK1TREPvczj355mwHNXLD6k1p5nyRxkWtEafo1ZKPxNGAjZahixV1ceUyWjdIcchw2LJ V/bg9GKwNbSCFABVCXvUDq+mMVIp076V+b2cshBpNaFuj2ALJa2vmNeSQokfTTyRhEBC cWjg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=MFhepMGaE0XG072ziJIvurTDqYdBHGuPC3+MsbwqRWw=; b=oPoKtFxb5yQdncfW2MeBGFuR16kGOWwA6xLPAoLXo2q8Z0W7eu1hUc9Xv89dMWwb5w oREVCFE5Ans7wrMjRC/TC5mmfih9nhJKSJUNvKA9wTeJlMuVbFZDc6gbpcq3QjqVsOBZ pLlj6mTEfh+7jyguIPM6OlvjnD20jnv0ztRKBefMo6IdNjLjH9vFlARu4mx153bN2Kgz Kh67FddmLAFiGVB5eAGt97KS0waHuk4U/gh+MR72uwdypqJe/D9CUnJoVKbqdJoTWjNC OfLEXnRsCom0KcdtK1dOzXE8KSPHQl2UWMMwQb2MEgeDGoRwjwtERPLquszoZBLP8i5V 2FuQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=L5by0c0K; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12-20020a7bcc0c000000b003f17848673fsm28916167wmh.27.2023.05.12.07.41.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 May 2023 07:41:15 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Richard Henderson Subject: [PATCH 15/20] target/arm: Convert TBZ, TBNZ to decodetree Date: Fri, 12 May 2023 15:41:01 +0100 Message-Id: <20230512144106.3608981-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230512144106.3608981-1-peter.maydell@linaro.org> References: <20230512144106.3608981-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Convert the test-and-branch-immediate insns TBZ and TBNZ to decodetree. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/tcg/a64.decode | 7 +++++++ target/arm/tcg/translate-a64.c | 25 +++++-------------------- 2 files changed, 12 insertions(+), 20 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 86220569e13..68dc820ece0 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -121,3 +121,10 @@ BL 1 00101 .......................... @branch @cbz sf:1 ...... nz:1 ................... rt:5 &cbz imm=%imm19 CBZ . 011010 . ................... ..... @cbz + +%imm14 5:s14 !function=times_4 +%imm31_19 31:1 19:5 +&tbz rt imm nz bitpos +@tbz . ...... nz:1 ..... .............. rt:5 &tbz imm=%imm14 bitpos=%imm31_19 + +TBZ . 011011 . ..... .............. ..... @tbz diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 5da551385bd..bd59d0616e3 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -1352,35 +1352,23 @@ static bool trans_CBZ(DisasContext *s, arg_cbz *a) return true; } -/* Test and branch (immediate) - * 31 30 25 24 23 19 18 5 4 0 - * +----+-------------+----+-------+-------------+------+ - * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt | - * +----+-------------+----+-------+-------------+------+ - */ -static void disas_test_b_imm(DisasContext *s, uint32_t insn) +static bool trans_TBZ(DisasContext *s, arg_tbz *a) { - unsigned int bit_pos, op, rt; - int64_t diff; DisasLabel match; TCGv_i64 tcg_cmp; - bit_pos = (extract32(insn, 31, 1) << 5) | extract32(insn, 19, 5); - op = extract32(insn, 24, 1); /* 0: TBZ; 1: TBNZ */ - diff = sextract32(insn, 5, 14) * 4; - rt = extract32(insn, 0, 5); - tcg_cmp = tcg_temp_new_i64(); - tcg_gen_andi_i64(tcg_cmp, cpu_reg(s, rt), (1ULL << bit_pos)); + tcg_gen_andi_i64(tcg_cmp, cpu_reg(s, a->rt), (1ULL << a->bitpos)); reset_btype(s); match = gen_disas_label(s); - tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ, + tcg_gen_brcondi_i64(a->nz ? TCG_COND_NE : TCG_COND_EQ, tcg_cmp, 0, match.label); gen_goto_tb(s, 0, 4); set_disas_label(s, match); - gen_goto_tb(s, 1, diff); + gen_goto_tb(s, 1, a->imm); + return true; } /* Conditional branch (immediate) @@ -2397,9 +2385,6 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) static void disas_b_exc_sys(DisasContext *s, uint32_t insn) { switch (extract32(insn, 25, 7)) { - case 0x1b: case 0x5b: /* Test & branch (immediate) */ - disas_test_b_imm(s, insn); - break; case 0x2a: /* Conditional branch (immediate) */ disas_cond_b_imm(s, insn); break; From patchwork Fri May 12 14:41:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 681175 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a41:0:0:0:0:0 with SMTP id v1csp3993951wrs; Fri, 12 May 2023 07:43:15 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5STridWWJPMtcc/HR1u4uqreyRcNyGWMU5ZjMjb90QdMg0Y4yBSSj3SqOzVOpCiSM1wahD X-Received: by 2002:ac8:57cb:0:b0:3f4:e9af:85a3 with SMTP id w11-20020ac857cb000000b003f4e9af85a3mr10136408qta.62.1683902594933; Fri, 12 May 2023 07:43:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683902594; cv=none; d=google.com; s=arc-20160816; b=PjJDtITkMBPo1voSk4J4BBPQKqVFxVVJ3emT2RvijPnEL5ygAdAP6Sfj2VyKNT4u5p sDOkhqGrt798rOGY0EyDYKmUxjeCr2NLtXg8a5q2pZ8EbajhX0BdxFp0Wt94bTB61mUU dewjpQTAUwH/bQHsZjVpe8p9g9+jIw9uEasZtaGXGXQyukUtEdUBRud6DxP9D2+KYV8Y ZJ7hlx/7P7P6GlFBDEVq6Fq6yhPPkJXLxriDYuPyavoZ38Jvz6I8IOO4o4Y4MMvYzt/b 2h7HbTEaHtadKsjeQrrAjUgUy+SAtvIPWCQ4bF3c96oYiJHWflnIM808eErwLbdS8lRm uaiQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=F0QOGVZAMk1HDBJjf1QtYWjsE8LxD2Kt5Aw9i/wccVs=; b=RVm5ReNArKMoTEe2YRdYIjlJHFTJv096+zLiPTwpIU6bVzL5YgTyhFMiq9yViFXfwe 8iueZi/YKuNkg5WEB9YUAcT9KV+NVdvJiLx3q4v8fOTVMBXMBydKBjBmCT8D1s42Gbtt z3ozE2myy2thf3t+M8esVLvp53hYqc+1ih5RZ5wOJhK40DKepGBgIfUb4RY5FG8IaaVU NwROYjvt3kv+ageSU41FjyW6paY1UzMD7r829rAt0oMqj4VZYmyiMOItnEhkw2a+rv9h QmDfIPfHh7PbDxR9Ut4Euz7NjjSdLr1xMtpyJvI+ccUtAju29Apzj7i2t7mYFDtYe5YS INrA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=e7Qb+rhi; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12-20020a7bcc0c000000b003f17848673fsm28916167wmh.27.2023.05.12.07.41.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 May 2023 07:41:15 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Richard Henderson Subject: [PATCH 16/20] target/arm: Convert conditional branch insns to decodetree Date: Fri, 12 May 2023 15:41:02 +0100 Message-Id: <20230512144106.3608981-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230512144106.3608981-1-peter.maydell@linaro.org> References: <20230512144106.3608981-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Convert the immediate conditional branch insn B.cond to decodetree. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/tcg/a64.decode | 2 ++ target/arm/tcg/translate-a64.c | 30 ++++++------------------------ 2 files changed, 8 insertions(+), 24 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 68dc820ece0..8514235a723 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -128,3 +128,5 @@ CBZ . 011010 . ................... ..... @cbz @tbz . ...... nz:1 ..... .............. rt:5 &tbz imm=%imm14 bitpos=%imm31_19 TBZ . 011011 . ..... .............. ..... @tbz + +B_cond 0101010 0 ................... 0 cond:4 imm=%imm19 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index bd59d0616e3..724dca8c579 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -1371,36 +1371,21 @@ static bool trans_TBZ(DisasContext *s, arg_tbz *a) return true; } -/* Conditional branch (immediate) - * 31 25 24 23 5 4 3 0 - * +---------------+----+---------------------+----+------+ - * | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond | - * +---------------+----+---------------------+----+------+ - */ -static void disas_cond_b_imm(DisasContext *s, uint32_t insn) +static bool trans_B_cond(DisasContext *s, arg_B_cond *a) { - unsigned int cond; - int64_t diff; - - if ((insn & (1 << 4)) || (insn & (1 << 24))) { - unallocated_encoding(s); - return; - } - diff = sextract32(insn, 5, 19) * 4; - cond = extract32(insn, 0, 4); - reset_btype(s); - if (cond < 0x0e) { + if (a->cond < 0x0e) { /* genuinely conditional branches */ DisasLabel match = gen_disas_label(s); - arm_gen_test_cc(cond, match.label); + arm_gen_test_cc(a->cond, match.label); gen_goto_tb(s, 0, 4); set_disas_label(s, match); - gen_goto_tb(s, 1, diff); + gen_goto_tb(s, 1, a->imm); } else { /* 0xe and 0xf are both "always" conditions */ - gen_goto_tb(s, 0, diff); + gen_goto_tb(s, 0, a->imm); } + return true; } /* HINT instruction group, including various allocated HINTs */ @@ -2385,9 +2370,6 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) static void disas_b_exc_sys(DisasContext *s, uint32_t insn) { switch (extract32(insn, 25, 7)) { - case 0x2a: /* Conditional branch (immediate) */ - disas_cond_b_imm(s, insn); - break; case 0x6a: /* Exception generation / System */ if (insn & (1 << 24)) { if (extract32(insn, 22, 2) == 0) { From patchwork Fri May 12 14:41:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 681187 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a41:0:0:0:0:0 with SMTP id v1csp3995643wrs; Fri, 12 May 2023 07:46:46 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ76I5IR+sBbNgzhaPrTQNbri+3hCXQEr1cZ0Aw3FBx7Ti9uHoj+S6cC/z12RN4eHcg6BMNb X-Received: by 2002:a05:6214:268d:b0:621:3b88:7b09 with SMTP id gm13-20020a056214268d00b006213b887b09mr22657470qvb.35.1683902806487; Fri, 12 May 2023 07:46:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683902806; cv=none; d=google.com; s=arc-20160816; b=dBhMozDDS7+VbcjU6sLEZO78OVC1LUMwv1eaXMjJRt0Fg3i4FJQ5wicDRCphHVeCF9 3YztpCuXk6e8O/y1iaoLLUBF1jULojO1Hik07npMlK1FhASV4yXeLKnC8OkuW+lW8Cp8 LCtGNhYJvUuGfN9WtCsulgcE30AXFexhYRm2AlORLTDkpPshjGQUohLodA8UqgfT6C+3 tmqOsSsIbF9ZDAZBK84x1iN5dcS3U/snjamNWo9juPnBK5aZehSFqgNimyqAyqJFH4Hh jR35PJQuLlfYyZ77bbCui5apuFKWrxHwJOAR33xYpq/ZSDTCZmyzv4ckjyiGumDE86GU IJiQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=7akZCgLrkYKZD7/0pb1eqcMpMk4KlEV9ol5sKLINuho=; b=o+k8UQPhGPm+nrA+QFrY9zsdR1n4BL+9OGXt7qbrL684xhDTJzVr0dlNCH8mWhNwGl zHXmF0VETBLqth0atMPtTwpui75vgRGJaWsqbwyIHBY0cQM/7UzDgRa/F6mYSomY3xTa 61h3ePvoLafKX6+r2kzmvxJICqiLaAVzIlD2BBz6OCnFheBz5ASebTxjYfPIB0xOth2K qW6nBca1NR5Z0RSQrUD2oXRZ1/5VQD4qPWlkeX1rPVRHV4vNv+weMUjH1iP/oLCYpnh9 QJOjJEPU5rzrS0iDTOJoXHse5ZtnJ2z0NfRSaAPiHqRCLc+SIJd+3UEpM0VB42N5DbQJ razg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=S4Bit7qz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12-20020a7bcc0c000000b003f17848673fsm28916167wmh.27.2023.05.12.07.41.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 May 2023 07:41:16 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Richard Henderson Subject: [PATCH 17/20] target/arm: Convert BR, BLR, RET to decodetree Date: Fri, 12 May 2023 15:41:03 +0100 Message-Id: <20230512144106.3608981-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230512144106.3608981-1-peter.maydell@linaro.org> References: <20230512144106.3608981-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Convert the simple (non-pointer-auth) BR, BLR and RET insns to decodetree. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/tcg/a64.decode | 5 ++++ target/arm/tcg/translate-a64.c | 55 ++++++++++++++++++++++++++++++---- 2 files changed, 54 insertions(+), 6 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 8514235a723..aa035f39558 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -19,6 +19,7 @@ # This file is processed by scripts/decodetree.py # +&r rn &ri rd imm &rri_sf rd rn imm sf &i imm @@ -130,3 +131,7 @@ CBZ . 011010 . ................... ..... @cbz TBZ . 011011 . ..... .............. ..... @tbz B_cond 0101010 0 ................... 0 cond:4 imm=%imm19 + +BR 1101011 0000 11111 000000 rn:5 00000 &r +BLR 1101011 0001 11111 000000 rn:5 00000 &r +RET 1101011 0010 11111 000000 rn:5 00000 &r diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 724dca8c579..853a01ac5be 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -1388,6 +1388,53 @@ static bool trans_B_cond(DisasContext *s, arg_B_cond *a) return true; } +static void set_btype_for_br(DisasContext *s, int rn) +{ + if (dc_isar_feature(aa64_bti, s)) { + /* BR to {x16,x17} or !guard -> 1, else 3. */ + set_btype(s, rn == 16 || rn == 17 || !s->guarded_page ? 1 : 3); + } +} + +static void set_btype_for_blr(DisasContext *s) +{ + if (dc_isar_feature(aa64_bti, s)) { + /* BLR sets BTYPE to 2, regardless of source guarded page. */ + set_btype(s, 2); + } +} + +static bool trans_BR(DisasContext *s, arg_r *a) +{ + gen_a64_set_pc(s, cpu_reg(s, a->rn)); + set_btype_for_br(s, a->rn); + s->base.is_jmp = DISAS_JUMP; + return true; +} + +static bool trans_BLR(DisasContext *s, arg_r *a) +{ + TCGv_i64 dst = cpu_reg(s, a->rn); + TCGv_i64 lr = cpu_reg(s, 30); + if (dst == lr) { + TCGv_i64 tmp = tcg_temp_new_i64(); + tcg_gen_mov_i64(tmp, dst); + dst = tmp; + } + gen_pc_plus_diff(s, lr, curr_insn_len(s)); + gen_a64_set_pc(s, dst); + set_btype_for_blr(s); + s->base.is_jmp = DISAS_JUMP; + return true; +} + +static bool trans_RET(DisasContext *s, arg_r *a) +{ + gen_a64_set_pc(s, cpu_reg(s, a->rn)); + s->base.is_jmp = DISAS_JUMP; + return true; +} + /* HINT instruction group, including various allocated HINTs */ static void handle_hint(DisasContext *s, uint32_t insn, unsigned int op1, unsigned int op2, unsigned int crm) @@ -2186,12 +2233,8 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) btype_mod = opc; switch (op3) { case 0: - /* BR, BLR, RET */ - if (op4 != 0) { - goto do_unallocated; - } - dst = cpu_reg(s, rn); - break; + /* BR, BLR, RET : handled in decodetree */ + goto do_unallocated; case 2: case 3: From patchwork Fri May 12 14:41:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 681186 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a41:0:0:0:0:0 with SMTP id v1csp3995614wrs; Fri, 12 May 2023 07:46:42 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7EzlleFHg1tdqkugGTx7mGI4S1Y0yD22+ukQD7NHga86T8vQoDbHcr6pJvnReCSs/YBPt0 X-Received: by 2002:a67:b646:0:b0:432:81e1:c296 with SMTP id e6-20020a67b646000000b0043281e1c296mr9172198vsm.24.1683902802004; Fri, 12 May 2023 07:46:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683902801; cv=none; d=google.com; s=arc-20160816; b=Ue9sy41vO+XTL2R79ZtzHePcu2mE0oETe5cBO8ULM/puUCy4mGZ6sZ2Vi3gcwsNPmA Lerwuaz+6G2wtBNuyFQUnInq9b5uqKzijvgt6DMLNo3eQQOUfjFDBd/UWqvUtl0VmxDe VIELGoyBXOuqV+mX5uC64dk9hDhzGiO/GC7abd7X0Mwm2VzhAIUBQdDjs6IOw1WPvb28 2QQ8JXRBvUtY7s/+rZZ9O1okWwi2JLN0HtXC9SXG+C8LbW9AJGRtxYD+4wlGd2OLbadc +KSYWOAbyGIybnIKIOXMkLGS2Q6JbQ8PKC7ZyKynNv445WNWG7yhO6I/JUof3Evtx8v/ jkJg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=WvyKjvvZPjQfu6e5IbjWblRQ9GYWJyDmT7w7l2HjFqA=; b=j/zelXTPJerF06PVv5QolDyEoCQ7FZSskynJmrbq1+jA0mGiIXxg5b997pnKqezgxn aPtNiPirPSc4VMFl178leyRN4iwA53NQcc+hhBMrzKKX2QUeLn+zBcrxMqJqFMxdwK+s SLshQojOj0alJDSgDk8ZuWn8YbinkxrSAPiZdk/aQfDY58t05p4kBfRwKaRtbiJ0eDV/ /uL7DwCT4knkWzAmggilIGvLGGDDA192eQoNqnielBJs4LAJxkudFKAJ2zpNt8ALivD3 o3lSUtrFGpcecDIFe1eHtKAZDPzgWQHmofGl09GJGg3ATeB9hcq+sPCDXeuu6JefCZ5t CDSA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=lFbkBrdf; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12-20020a7bcc0c000000b003f17848673fsm28916167wmh.27.2023.05.12.07.41.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 May 2023 07:41:16 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Richard Henderson Subject: [PATCH 18/20] target/arm: Convert BRA[AB]Z, BLR[AB]Z, RETA[AB] to decodetree Date: Fri, 12 May 2023 15:41:04 +0100 Message-Id: <20230512144106.3608981-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230512144106.3608981-1-peter.maydell@linaro.org> References: <20230512144106.3608981-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Convert the single-register pointer-authentication variants of BR, BLR, RET to decodetree. (BRAA/BLRAA are in a different branch of the legacy decoder and will be dealt with in the next commit.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/tcg/a64.decode | 7 ++ target/arm/tcg/translate-a64.c | 132 +++++++++++++++++++-------------- 2 files changed, 84 insertions(+), 55 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index aa035f39558..22e3a5cea0c 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -135,3 +135,10 @@ B_cond 0101010 0 ................... 0 cond:4 imm=%imm19 BR 1101011 0000 11111 000000 rn:5 00000 &r BLR 1101011 0001 11111 000000 rn:5 00000 &r RET 1101011 0010 11111 000000 rn:5 00000 &r + +&braz rn m +BRAZ 1101011 0000 11111 00001 m:1 rn:5 11111 &braz # BRAAZ, BRABZ +BLRAZ 1101011 0001 11111 00001 m:1 rn:5 11111 &braz # BLRAAZ, BLRABZ + +&reta m +RETA 1101011 0010 11111 00001 m:1 11111 11111 &reta # RETAA, RETAB diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 853a01ac5be..e5b9171313b 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -1435,6 +1435,75 @@ static bool trans_RET(DisasContext *s, arg_r *a) return true; } +static TCGv_i64 auth_branch_target(DisasContext *s, TCGv_i64 dst, + TCGv_i64 modifier, bool use_key_a) +{ + TCGv_i64 truedst; + /* + * Return the branch target for a BRAA/RETA/etc, which is either + * just the destination dst, or that value with the pauth check + * done and the code removed from the high bits. + */ + if (!s->pauth_active) { + return dst; + } + + truedst = tcg_temp_new_i64(); + if (use_key_a) { + gen_helper_autia(truedst, cpu_env, dst, modifier); + } else { + gen_helper_autib(truedst, cpu_env, dst, modifier); + } + return truedst; +} + +static bool trans_BRAZ(DisasContext *s, arg_braz *a) +{ + TCGv_i64 dst; + + if (!dc_isar_feature(aa64_pauth, s)) { + return false; + } + + dst = auth_branch_target(s, cpu_reg(s, a->rn), tcg_constant_i64(0), !a->m); + gen_a64_set_pc(s, dst); + set_btype_for_br(s, a->rn); + s->base.is_jmp = DISAS_JUMP; + return true; +} + +static bool trans_BLRAZ(DisasContext *s, arg_braz *a) +{ + TCGv_i64 dst, lr; + + if (!dc_isar_feature(aa64_pauth, s)) { + return false; + } + + dst = auth_branch_target(s, cpu_reg(s, a->rn), tcg_constant_i64(0), !a->m); + lr = cpu_reg(s, 30); + if (dst == lr) { + TCGv_i64 tmp = tcg_temp_new_i64(); + tcg_gen_mov_i64(tmp, dst); + dst = tmp; + } + gen_pc_plus_diff(s, lr, curr_insn_len(s)); + gen_a64_set_pc(s, dst); + set_btype_for_blr(s); + s->base.is_jmp = DISAS_JUMP; + return true; +} + +static bool trans_RETA(DisasContext *s, arg_reta *a) +{ + TCGv_i64 dst; + + dst = auth_branch_target(s, cpu_reg(s, 30), cpu_X[31], !a->m); + gen_a64_set_pc(s, dst); + s->base.is_jmp = DISAS_JUMP; + return true; +} + /* HINT instruction group, including various allocated HINTs */ static void handle_hint(DisasContext *s, uint32_t insn, unsigned int op1, unsigned int op2, unsigned int crm) @@ -2227,61 +2296,14 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) } switch (opc) { - case 0: /* BR */ - case 1: /* BLR */ - case 2: /* RET */ - btype_mod = opc; - switch (op3) { - case 0: - /* BR, BLR, RET : handled in decodetree */ - goto do_unallocated; - - case 2: - case 3: - if (!dc_isar_feature(aa64_pauth, s)) { - goto do_unallocated; - } - if (opc == 2) { - /* RETAA, RETAB */ - if (rn != 0x1f || op4 != 0x1f) { - goto do_unallocated; - } - rn = 30; - modifier = cpu_X[31]; - } else { - /* BRAAZ, BRABZ, BLRAAZ, BLRABZ */ - if (op4 != 0x1f) { - goto do_unallocated; - } - modifier = tcg_constant_i64(0); - } - if (s->pauth_active) { - dst = tcg_temp_new_i64(); - if (op3 == 2) { - gen_helper_autia(dst, cpu_env, cpu_reg(s, rn), modifier); - } else { - gen_helper_autib(dst, cpu_env, cpu_reg(s, rn), modifier); - } - } else { - dst = cpu_reg(s, rn); - } - break; - - default: - goto do_unallocated; - } - /* BLR also needs to load return address */ - if (opc == 1) { - TCGv_i64 lr = cpu_reg(s, 30); - if (dst == lr) { - TCGv_i64 tmp = tcg_temp_new_i64(); - tcg_gen_mov_i64(tmp, dst); - dst = tmp; - } - gen_pc_plus_diff(s, lr, curr_insn_len(s)); - } - gen_a64_set_pc(s, dst); - break; + case 0: + case 1: + case 2: + /* + * BR, BLR, RET, RETAA, RETAB, BRAAZ, BRABZ, BLRAAZ, BLRABZ: + * handled in decodetree + */ + goto do_unallocated; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12-20020a7bcc0c000000b003f17848673fsm28916167wmh.27.2023.05.12.07.41.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 May 2023 07:41:17 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Richard Henderson Subject: [PATCH 19/20] target/arm: Convert BRAA, BRAB, BLRAA, BLRAB to decodetree Date: Fri, 12 May 2023 15:41:05 +0100 Message-Id: <20230512144106.3608981-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230512144106.3608981-1-peter.maydell@linaro.org> References: <20230512144106.3608981-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Convert the last four BR-with-pointer-auth insns to decodetree. The remaining cases in the outer switch in disas_uncond_b_reg() all return early rather than leaving the case statement, so we can delete the now-unused code at the end of that function. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/tcg/a64.decode | 4 ++ target/arm/tcg/translate-a64.c | 97 ++++++++++++++-------------------- 2 files changed, 43 insertions(+), 58 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 22e3a5cea0c..5b055efdc19 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -142,3 +142,7 @@ BLRAZ 1101011 0001 11111 00001 m:1 rn:5 11111 &braz # BLRAAZ, BLRABZ &reta m RETA 1101011 0010 11111 00001 m:1 11111 11111 &reta # RETAA, RETAB + +&bra rn rm m +BRA 1101011 1000 11111 00001 m:1 rn:5 rm:5 &bra # BRAA, BRAB +BLRA 1101011 1001 11111 00001 m:1 rn:5 rm:5 &bra # BLRAA, BLRAB diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index e5b9171313b..54e3571a89c 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -1504,6 +1504,41 @@ static bool trans_RETA(DisasContext *s, arg_reta *a) return true; } +static bool trans_BRA(DisasContext *s, arg_bra *a) +{ + TCGv_i64 dst; + + if (!dc_isar_feature(aa64_pauth, s)) { + return false; + } + dst = auth_branch_target(s, cpu_reg(s,a->rn), cpu_reg_sp(s, a->rm), !a->m); + gen_a64_set_pc(s, dst); + set_btype_for_br(s, a->rn); + s->base.is_jmp = DISAS_JUMP; + return true; +} + +static bool trans_BLRA(DisasContext *s, arg_bra *a) +{ + TCGv_i64 dst, lr; + + if (!dc_isar_feature(aa64_pauth, s)) { + return false; + } + dst = auth_branch_target(s, cpu_reg(s, a->rn), cpu_reg_sp(s, a->rm), !a->m); + lr = cpu_reg(s, 30); + if (dst == lr) { + TCGv_i64 tmp = tcg_temp_new_i64(); + tcg_gen_mov_i64(tmp, dst); + dst = tmp; + } + gen_pc_plus_diff(s, lr, curr_insn_len(s)); + gen_a64_set_pc(s, dst); + set_btype_for_blr(s); + s->base.is_jmp = DISAS_JUMP; + return true; +} + /* HINT instruction group, including various allocated HINTs */ static void handle_hint(DisasContext *s, uint32_t insn, unsigned int op1, unsigned int op2, unsigned int crm) @@ -2281,7 +2316,6 @@ static void disas_exc(DisasContext *s, uint32_t insn) static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) { unsigned int opc, op2, op3, rn, op4; - unsigned btype_mod = 2; /* 0: BR, 1: BLR, 2: other */ TCGv_i64 dst; TCGv_i64 modifier; @@ -2299,45 +2333,14 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) case 0: case 1: case 2: + case 8: + case 9: /* - * BR, BLR, RET, RETAA, RETAB, BRAAZ, BRABZ, BLRAAZ, BLRABZ: - * handled in decodetree + * BR, BLR, RET, RETAA, RETAB, BRAAZ, BRABZ, BLRAAZ, BLRABZ, + * BRAA, BLRAA: handled in decodetree */ goto do_unallocated; - case 8: /* BRAA */ - case 9: /* BLRAA */ - if (!dc_isar_feature(aa64_pauth, s)) { - goto do_unallocated; - } - if ((op3 & ~1) != 2) { - goto do_unallocated; - } - btype_mod = opc & 1; - if (s->pauth_active) { - dst = tcg_temp_new_i64(); - modifier = cpu_reg_sp(s, op4); - if (op3 == 2) { - gen_helper_autia(dst, cpu_env, cpu_reg(s, rn), modifier); - } else { - gen_helper_autib(dst, cpu_env, cpu_reg(s, rn), modifier); - } - } else { - dst = cpu_reg(s, rn); - } - /* BLRAA also needs to load return address */ - if (opc == 9) { - TCGv_i64 lr = cpu_reg(s, 30); - if (dst == lr) { - TCGv_i64 tmp = tcg_temp_new_i64(); - tcg_gen_mov_i64(tmp, dst); - dst = tmp; - } - gen_pc_plus_diff(s, lr, curr_insn_len(s)); - } - gen_a64_set_pc(s, dst); - break; - case 4: /* ERET */ if (s->current_el == 0) { goto do_unallocated; @@ -2407,28 +2410,6 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) unallocated_encoding(s); return; } - - switch (btype_mod) { - case 0: /* BR */ - if (dc_isar_feature(aa64_bti, s)) { - /* BR to {x16,x17} or !guard -> 1, else 3. */ - set_btype(s, rn == 16 || rn == 17 || !s->guarded_page ? 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12-20020a7bcc0c000000b003f17848673fsm28916167wmh.27.2023.05.12.07.41.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 May 2023 07:41:17 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Richard Henderson Subject: [PATCH 20/20] target/arm: Convert ERET, ERETAA, ERETAB to decodetree Date: Fri, 12 May 2023 15:41:06 +0100 Message-Id: <20230512144106.3608981-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230512144106.3608981-1-peter.maydell@linaro.org> References: <20230512144106.3608981-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Convert the exception-return insns ERET, ERETA and ERETB to decodetree. These were the last insns left in the legacy decoder function disas_uncond_reg_b(), which allows us to remove it. The old decoder explicitly decoded the DRPS instruction, only in order to call unallocated_encoding() on it, exactly as would have happened if it hadn't decoded it. This is because this insn always UNDEFs unless the CPU is in halting-debug state, which we don't emulate. So we list the pattern in a comment in a64.decode, but don't actively decode it. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/tcg/a64.decode | 8 ++ target/arm/tcg/translate-a64.c | 160 +++++++++++---------------------- 2 files changed, 60 insertions(+), 108 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 5b055efdc19..ae2874017d8 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -146,3 +146,11 @@ RETA 1101011 0010 11111 00001 m:1 11111 11111 &reta # RETAA, RETAB &bra rn rm m BRA 1101011 1000 11111 00001 m:1 rn:5 rm:5 &bra # BRAA, BRAB BLRA 1101011 1001 11111 00001 m:1 rn:5 rm:5 &bra # BLRAA, BLRAB + +ERET 1101011 0100 11111 000000 11111 00000 +ERETA 1101011 0100 11111 00001 m:1 11111 11111 &reta # ERETAA, ERETAB + +# We don't need to decode DRPS because it always UNDEFs except when +# the processor is in halting debug state (which we don't implement). +# The pattern is listed here as documentation. +# DRPS 1101011 0101 11111 000000 11111 00000 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 54e3571a89c..2cd31f85d79 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -1539,6 +1539,58 @@ static bool trans_BLRA(DisasContext *s, arg_bra *a) return true; } +static bool trans_ERET(DisasContext *s, arg_ERET *a) +{ + TCGv_i64 dst; + + if (s->current_el == 0) { + return false; + } + if (s->fgt_eret) { + gen_exception_insn_el(s, 0, EXCP_UDEF, 0, 2); + return true; + } + dst = tcg_temp_new_i64(); + tcg_gen_ld_i64(dst, cpu_env, + offsetof(CPUARMState, elr_el[s->current_el])); + + if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); + } + + gen_helper_exception_return(cpu_env, dst); + /* Must exit loop to check un-masked IRQs */ + s->base.is_jmp = DISAS_EXIT; + return true; +} + +static bool trans_ERETA(DisasContext *s, arg_reta *a) +{ + TCGv_i64 dst; + + if (!dc_isar_feature(aa64_pauth, s)) { + return false; + } + /* The FGT trap takes precedence over an auth trap. */ + if (s->fgt_eret) { + gen_exception_insn_el(s, 0, EXCP_UDEF, a->m ? 3 : 2, 2); + return true; + } + dst = tcg_temp_new_i64(); + tcg_gen_ld_i64(dst, cpu_env, + offsetof(CPUARMState, elr_el[s->current_el])); + + dst = auth_branch_target(s, dst, cpu_X[31], !a->m); + if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); + } + + gen_helper_exception_return(cpu_env, dst); + /* Must exit loop to check un-masked IRQs */ + s->base.is_jmp = DISAS_EXIT; + return true; +} + /* HINT instruction group, including various allocated HINTs */ static void handle_hint(DisasContext *s, uint32_t insn, unsigned int op1, unsigned int op2, unsigned int crm) @@ -2307,111 +2359,6 @@ static void disas_exc(DisasContext *s, uint32_t insn) } } -/* Unconditional branch (register) - * 31 25 24 21 20 16 15 10 9 5 4 0 - * +---------------+-------+-------+-------+------+-------+ - * | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 | - * +---------------+-------+-------+-------+------+-------+ - */ -static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) -{ - unsigned int opc, op2, op3, rn, op4; - TCGv_i64 dst; - TCGv_i64 modifier; - - opc = extract32(insn, 21, 4); - op2 = extract32(insn, 16, 5); - op3 = extract32(insn, 10, 6); - rn = extract32(insn, 5, 5); - op4 = extract32(insn, 0, 5); - - if (op2 != 0x1f) { - goto do_unallocated; - } - - switch (opc) { - case 0: - case 1: - case 2: - case 8: - case 9: - /* - * BR, BLR, RET, RETAA, RETAB, BRAAZ, BRABZ, BLRAAZ, BLRABZ, - * BRAA, BLRAA: handled in decodetree - */ - goto do_unallocated; - - case 4: /* ERET */ - if (s->current_el == 0) { - goto do_unallocated; - } - switch (op3) { - case 0: /* ERET */ - if (op4 != 0) { - goto do_unallocated; - } - if (s->fgt_eret) { - gen_exception_insn_el(s, 0, EXCP_UDEF, syn_erettrap(op3), 2); - return; - } - dst = tcg_temp_new_i64(); - tcg_gen_ld_i64(dst, cpu_env, - offsetof(CPUARMState, elr_el[s->current_el])); - break; - - case 2: /* ERETAA */ - case 3: /* ERETAB */ - if (!dc_isar_feature(aa64_pauth, s)) { - goto do_unallocated; - } - if (rn != 0x1f || op4 != 0x1f) { - goto do_unallocated; - } - /* The FGT trap takes precedence over an auth trap. */ - if (s->fgt_eret) { - gen_exception_insn_el(s, 0, EXCP_UDEF, syn_erettrap(op3), 2); - return; - } - dst = tcg_temp_new_i64(); - tcg_gen_ld_i64(dst, cpu_env, - offsetof(CPUARMState, elr_el[s->current_el])); - if (s->pauth_active) { - modifier = cpu_X[31]; - if (op3 == 2) { - gen_helper_autia(dst, cpu_env, dst, modifier); - } else { - gen_helper_autib(dst, cpu_env, dst, modifier); - } - } - break; - - default: - goto do_unallocated; - } - if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } - - gen_helper_exception_return(cpu_env, dst); - /* Must exit loop to check un-masked IRQs */ - s->base.is_jmp = DISAS_EXIT; - return; - - case 5: /* DRPS */ - if (op3 != 0 || op4 != 0 || rn != 0x1f) { - goto do_unallocated; - } else { - unallocated_encoding(s); - } - return; - - default: - do_unallocated: - unallocated_encoding(s); - return; - } -} - /* Branches, exception generating and system instructions */ static void disas_b_exc_sys(DisasContext *s, uint32_t insn) { @@ -2427,9 +2374,6 @@ static void disas_b_exc_sys(DisasContext *s, uint32_t insn) disas_exc(s, insn); } break; - case 0x6b: /* Unconditional branch (register) */ - disas_uncond_b_reg(s, insn); - break; default: unallocated_encoding(s); break;