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[209.51.188.17]) by mx.google.com with ESMTPS id q6-20020a056102204600b0043600154b2dsi1917470vsr.605.2023.05.12.10.04.02 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 12 May 2023 10:04:02 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=RlOsSVfc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pxWA8-0001CW-NU; Fri, 12 May 2023 13:02:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pxWA2-0001Ai-Bh for qemu-devel@nongnu.org; Fri, 12 May 2023 13:02:30 -0400 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pxWA0-0002Ai-Ke for qemu-devel@nongnu.org; Fri, 12 May 2023 13:02:29 -0400 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-3f423521b10so47667635e9.0 for ; Fri, 12 May 2023 10:02:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683910945; x=1686502945; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=zSeckB/DU/ftoxKs9zBa0uYqulCiNpn9zBPfGQQqV0Y=; b=RlOsSVfcNLRYGCxjhQmpNDzp+tByx80LezNUtv8G7omXcCeNcpgwb/ZOpAf1uqb8z5 tuw95c+90zr5z1fZD0Ih8MA8FrZZPLl0cJKSy+mufJ++/xEgeF/m5mGlraFMhRN3+pIV axX8N6XvnQsxvgBJvSpGRK5FVB5iW2LcFfqHwoxSk40kTstwRV8kgD5BfNWzpwLOakyw lbwa0beBtrwvFNyOBdlwgQ7yNsKbJJb5XT8WUx4lFiCZfTICXvh0R3+YJsFrSKxPZUJc p5qm9Tbgg38Ec4u4Q8o6EjtBmI3nExk8dNZogMX3WxH6v8V04nltBVQYunTpuKbXOOCB gUJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683910945; x=1686502945; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zSeckB/DU/ftoxKs9zBa0uYqulCiNpn9zBPfGQQqV0Y=; b=OgUl88oY09UHt3O+MVuz6ors6gnDi8ZRfWbaLfup7ib4x8FODNr94IuRCn8fQFjAfj pF74Kz0UisLe7IUgVcv+aa55oKFHuOReP0p2Q02sAmdaOoNVOjpzQVkqTKvv3TiqnmKI uVW9716/DphR8A2dgcS8ZS9CjO4eOHoSz6L76i9SPDTLPjnpBNXJ/V4NkAigD4wRTq2Z 9gy9xftANiaHN16cRoEVAHYZbvY3l9d0dDsPvwfIHTXgr1YlGAXhXnzebisknrKF3i6X wdX+9JrC/tCGsc26MKC4+zf7QeK8PtEt2XAe5QLe2t8JR8GWMEHPiSs0BeuADT6u7+1H x+jQ== X-Gm-Message-State: AC+VfDx6DCBTMHfMs9WO1JH2r+D3S4ZocJHf1DHXpOvrnxw9ooRyLdiO JpGKXQweH0MQmUXao7UOSRcZRUAkfGC6Z33OyZE= X-Received: by 2002:a05:600c:3787:b0:3f4:2bcd:5a6e with SMTP id o7-20020a05600c378700b003f42bcd5a6emr8770251wmr.30.1683910945703; Fri, 12 May 2023 10:02:25 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id p26-20020a05600c205a00b003f4f1b884b3sm3521004wmg.20.2023.05.12.10.02.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 May 2023 10:02:25 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 1/2] target/arm: Saturate L2CTLR_EL1 core count field rather than overflowing Date: Fri, 12 May 2023 18:02:22 +0100 Message-Id: <20230512170223.3801643-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230512170223.3801643-1-peter.maydell@linaro.org> References: <20230512170223.3801643-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The IMPDEF sysreg L2CTLR_EL1 found on the Cortex-A35, A53, A57, A72 and which we (arguably dubiously) also provide in '-cpu max' has a 2 bit field for the number of processors in the cluster. On real hardware this must be sufficient because it can only be configured with up to 4 CPUs in the cluster. However on QEMU if the board code does not explicitly configure the code into clusters with the right CPU count we default to "give the value assuming that all CPUs in the system are in a single cluster", which might be too big to fit in the field. Instead of just overflowing this 2-bit field, saturate to 3 (meaning "4 CPUs", so at least we don't overwrite other fields in the register. It's unlikely that any guest code really cares about the value in this field; at least, if it does it probably also wants the system to be more closely matching real hardware, i.e. not to have more than 4 CPUs. This issue has been present since the L2CTLR was first added in commit 377a44ec8f2fac5b back in 2014. It was only noticed because Coverity complains (CID 1509227) that the shift might overflow 32 bits and inadvertently sign extend into the top half of the 64 bit value. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cortex-regs.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/target/arm/cortex-regs.c b/target/arm/cortex-regs.c index 17708480e75..ae817b08ddf 100644 --- a/target/arm/cortex-regs.c +++ b/target/arm/cortex-regs.c @@ -15,8 +15,15 @@ static uint64_t l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) { ARMCPU *cpu = env_archcpu(env); - /* Number of cores is in [25:24]; otherwise we RAZ */ - return (cpu->core_count - 1) << 24; + /* + * Number of cores is in [25:24]; otherwise we RAZ. + * If the board didn't configure the CPUs into clusters, + * we default to "all CPUs in one cluster", which might be + * more than the 4 that the hardware permits and which is + * all you can report in this two-bit field. Saturate to + * 0b11 (== 4 CPUs) rather than overflowing the field. + */ + return MIN(cpu->core_count - 1, 3) << 24; } static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = { From patchwork Fri May 12 17:02:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 681203 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a41:0:0:0:0:0 with SMTP id v1csp4063500wrs; Fri, 12 May 2023 10:03:30 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7jpFTHtMr8zO7qNdGT9P0THpbA5Eb3JTEwO6G+6VkGk1FiO7+DdTqae3gzEsfKtpnr3y98 X-Received: by 2002:a05:6102:2445:b0:436:1ee5:5367 with SMTP id g5-20020a056102244500b004361ee55367mr5346842vss.4.1683911010591; Fri, 12 May 2023 10:03:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683911010; cv=none; d=google.com; s=arc-20160816; b=K0YuItk1tVydcwQyiC41akuvzCbTzfBlvSAA++guXPj1nbBiCv1+C1t6K8lvVXXn4k vJL7nkC8nLPGlgxcb6mBs7vLGCB9BWXK2V4kR+15uZFWSR6KZxQyblhTnFK6cUrKfzLs SlVvF+J71stNR02CD9ciO4jikteE5+t+WkyoTSeUqKN4XkbxiqFieVzuyNZrXMISEyaH lHgBpwigLl9i5U6tnNQFWPfARCiQfdM0vkNL/DaMawPI1p6nxgUlrV/OkumwwbTA3A1U 4BNVecn3iystrRUcoa6NyaXasY1p6zyBiS1fj8JXoAbNIvePPrlkp2SlWkaZZi8jNrj2 4lxg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=MFCeM+1XGtMQYF2UODCgJ1l9ex3LQoWfG2ZoWUc7ySU=; b=DM+Zl/Hg/GTNYmFcDt1eEBzeTT6Xrcb3RXRrTZBZnWbqRh5kFupwcOiO7Lsapw1IKQ xcaEMIlyjj4E7ucbxUEia9rbDZL7CZ956yyasj3G+YUh9r/dqCbJXy380galLXvFc9Pw Cy2vXOrrUWdvZ4MDhot0ElpglK0F8Gu1uHES6nYy6PzEh4HWzJ2PiRKGPsOszVLmDShE 7ntptdoWbYXLXdU+b/IPXeDwIqI47hsBh72z1oobPbcH2JeJ5HVZAioholEBM1rFPaJx /9WRs6u4drdeXQXgqIjh0mVCJT9gaEsxylsCCa5ZZwMjQR/6WBHt1ICJEzGMLKDT7vBc XGIw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=G4bRWB2H; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id p26-20020a05600c205a00b003f4f1b884b3sm3521004wmg.20.2023.05.12.10.02.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 May 2023 10:02:25 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 2/2] hw/arm/vexpress: Avoid trivial memory leak of 'flashalias' Date: Fri, 12 May 2023 18:02:23 +0100 Message-Id: <20230512170223.3801643-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230512170223.3801643-1-peter.maydell@linaro.org> References: <20230512170223.3801643-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In the vexpress board code, we allocate a new MemoryRegion at the top of vexpress_common_init() but only set it up and use it inside the "if (map[VE_NORFLASHALIAS] != -1)" conditional, so we leak it if not. This isn't a very interesting leak as it's a tiny amount of memory once at startup, but it's easy to fix. We could silence Coverity simply by moving the g_new() into the if() block, but this use of g_new(MemoryRegion, 1) is a legacy from when this board model was originally written; we wouldn't do that if we wrote it today. The MemoryRegions are conceptually a part of the board and must not go away until the whole board is done with (at the end of the simulation), so they belong in its state struct. This machine already has a VexpressMachineState struct that extends MachineState, so statically put the MemoryRegions in there instead of dynamically allocating them separately at runtime. Spotted by Coverity (CID 1509083). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- hw/arm/vexpress.c | 40 ++++++++++++++++++++-------------------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c index 34b012b528b..56abadd9b8b 100644 --- a/hw/arm/vexpress.c +++ b/hw/arm/vexpress.c @@ -173,6 +173,11 @@ struct VexpressMachineClass { struct VexpressMachineState { MachineState parent; + MemoryRegion vram; + MemoryRegion sram; + MemoryRegion flashalias; + MemoryRegion lowram; + MemoryRegion a15sram; bool secure; bool virt; }; @@ -182,7 +187,7 @@ struct VexpressMachineState { #define TYPE_VEXPRESS_A15_MACHINE MACHINE_TYPE_NAME("vexpress-a15") OBJECT_DECLARE_TYPE(VexpressMachineState, VexpressMachineClass, VEXPRESS_MACHINE) -typedef void DBoardInitFn(const VexpressMachineState *machine, +typedef void DBoardInitFn(VexpressMachineState *machine, ram_addr_t ram_size, const char *cpu_type, qemu_irq *pic); @@ -263,14 +268,13 @@ static void init_cpus(MachineState *ms, const char *cpu_type, } } -static void a9_daughterboard_init(const VexpressMachineState *vms, +static void a9_daughterboard_init(VexpressMachineState *vms, ram_addr_t ram_size, const char *cpu_type, qemu_irq *pic) { MachineState *machine = MACHINE(vms); MemoryRegion *sysmem = get_system_memory(); - MemoryRegion *lowram = g_new(MemoryRegion, 1); ram_addr_t low_ram_size; if (ram_size > 0x40000000) { @@ -287,9 +291,9 @@ static void a9_daughterboard_init(const VexpressMachineState *vms, * address space should in theory be remappable to various * things including ROM or RAM; we always map the RAM there. */ - memory_region_init_alias(lowram, NULL, "vexpress.lowmem", machine->ram, - 0, low_ram_size); - memory_region_add_subregion(sysmem, 0x0, lowram); + memory_region_init_alias(&vms->lowram, NULL, "vexpress.lowmem", + machine->ram, 0, low_ram_size); + memory_region_add_subregion(sysmem, 0x0, &vms->lowram); memory_region_add_subregion(sysmem, 0x60000000, machine->ram); /* 0x1e000000 A9MPCore (SCU) private memory region */ @@ -348,14 +352,13 @@ static VEDBoardInfo a9_daughterboard = { .init = a9_daughterboard_init, }; -static void a15_daughterboard_init(const VexpressMachineState *vms, +static void a15_daughterboard_init(VexpressMachineState *vms, ram_addr_t ram_size, const char *cpu_type, qemu_irq *pic) { MachineState *machine = MACHINE(vms); MemoryRegion *sysmem = get_system_memory(); - MemoryRegion *sram = g_new(MemoryRegion, 1); { /* We have to use a separate 64 bit variable here to avoid the gcc @@ -386,9 +389,9 @@ static void a15_daughterboard_init(const VexpressMachineState *vms, /* 0x2b060000: SP805 watchdog: not modelled */ /* 0x2b0a0000: PL341 dynamic memory controller: not modelled */ /* 0x2e000000: system SRAM */ - memory_region_init_ram(sram, NULL, "vexpress.a15sram", 0x10000, + memory_region_init_ram(&vms->a15sram, NULL, "vexpress.a15sram", 0x10000, &error_fatal); - memory_region_add_subregion(sysmem, 0x2e000000, sram); + memory_region_add_subregion(sysmem, 0x2e000000, &vms->a15sram); /* 0x7ffb0000: DMA330 DMA controller: not modelled */ /* 0x7ffd0000: PL354 static memory controller: not modelled */ @@ -547,10 +550,6 @@ static void vexpress_common_init(MachineState *machine) I2CBus *i2c; ram_addr_t vram_size, sram_size; MemoryRegion *sysmem = get_system_memory(); - MemoryRegion *vram = g_new(MemoryRegion, 1); - MemoryRegion *sram = g_new(MemoryRegion, 1); - MemoryRegion *flashalias = g_new(MemoryRegion, 1); - MemoryRegion *flash0mem; const hwaddr *map = daughterboard->motherboard_map; int i; @@ -662,24 +661,25 @@ static void vexpress_common_init(MachineState *machine) if (map[VE_NORFLASHALIAS] != -1) { /* Map flash 0 as an alias into low memory */ + MemoryRegion *flash0mem; flash0mem = sysbus_mmio_get_region(SYS_BUS_DEVICE(pflash0), 0); - memory_region_init_alias(flashalias, NULL, "vexpress.flashalias", + memory_region_init_alias(&vms->flashalias, NULL, "vexpress.flashalias", flash0mem, 0, VEXPRESS_FLASH_SIZE); - memory_region_add_subregion(sysmem, map[VE_NORFLASHALIAS], flashalias); + memory_region_add_subregion(sysmem, map[VE_NORFLASHALIAS], &vms->flashalias); } dinfo = drive_get(IF_PFLASH, 0, 1); ve_pflash_cfi01_register(map[VE_NORFLASH1], "vexpress.flash1", dinfo); sram_size = 0x2000000; - memory_region_init_ram(sram, NULL, "vexpress.sram", sram_size, + memory_region_init_ram(&vms->sram, NULL, "vexpress.sram", sram_size, &error_fatal); - memory_region_add_subregion(sysmem, map[VE_SRAM], sram); + memory_region_add_subregion(sysmem, map[VE_SRAM], &vms->sram); vram_size = 0x800000; - memory_region_init_ram(vram, NULL, "vexpress.vram", vram_size, + memory_region_init_ram(&vms->vram, NULL, "vexpress.vram", vram_size, &error_fatal); - memory_region_add_subregion(sysmem, map[VE_VIDEORAM], vram); + memory_region_add_subregion(sysmem, map[VE_VIDEORAM], &vms->vram); /* 0x4e000000 LAN9118 Ethernet */ if (nd_table[0].used) {