From patchwork Tue May 30 19:51:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Bernhard_Rosenkr=C3=A4nzer?= X-Patchwork-Id: 687135 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F3E86C7EE31 for ; Tue, 30 May 2023 19:51:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231583AbjE3Tvl (ORCPT ); Tue, 30 May 2023 15:51:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38500 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232721AbjE3Tvk (ORCPT ); Tue, 30 May 2023 15:51:40 -0400 Received: from mail-wr1-x42f.google.com (mail-wr1-x42f.google.com [IPv6:2a00:1450:4864:20::42f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D1A5D106 for ; Tue, 30 May 2023 12:51:37 -0700 (PDT) Received: by mail-wr1-x42f.google.com with SMTP id ffacd0b85a97d-30789a4c537so3347294f8f.0 for ; Tue, 30 May 2023 12:51:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20221208.gappssmtp.com; s=20221208; t=1685476296; x=1688068296; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xMbc7ZMxh3N33Yc+ipgSHRqfEAA1Um0qlVG11Tvtq50=; b=SQBjpmxhV4in/9DZqzAkeEBpua4/dKoQjL/6zGi7N6k7Qnv+gudpP6eiebLLyKWWtv xcYOgCaDTg9Ad6kH84wmmIvD3sSwJON2ESqPBayJ+uk49FpaAoc+m3ak7XPNUzCl/Fa/ DPelZdwKMFeb9F8UrqQtyJyG2E5fpEElIzdROCJL2NMRSj7EDuZL8vxmaBcmn8YCdFA3 cj80QMxxkZ6GnJ4vhksdj/6L86a/wybg48m/BNYVSNkulCNi3aVORvgK1+ftAYJytKTb hZWrAGW3J1UYmQzUEK+V4+e3lqyGKQ0CFdEkiX8wthmR+6XZUucxm4Q2YkX1iTpha4VD rQ+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685476296; x=1688068296; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xMbc7ZMxh3N33Yc+ipgSHRqfEAA1Um0qlVG11Tvtq50=; b=Dr9y8dBNYYqAiroFb48tjQMpouZ5rA4g1/sZx4sfrUJxzPXuxTZJDl00onJjdFPs1s xufjPzK/JpoH520jMJdo/lW8Ux2aoG2RfNRxVY3XfOTwxVbXkH2NcVTj6ybJS+c1R15c Cli2/u3IfWFrwVMoTVLR4S8xyv53zUxswhuM74cqAKCyidTKI7afRPXxHIho0rei4Cxb O4uSq6p/DTiNrqPFwOiwbPCuVZFBubC37Up3Xmr+f4UllOSG+ew5IbKPR1Q7AXSXBxlt AN+5Cda3d5FR9MbrxkusP/RPZnyKf7duXw/3cRnjGB7PIvkmf/gQWeDfOMZgA4cvlFV1 Zebw== X-Gm-Message-State: AC+VfDxISJ9plP9FlnkD7zNeiS2D8RFHWXJXzXiys/J7VXAcqL8EIMjr 0WEhLELUvSfnWDfGZmiwCvqnKT6YO79SfMp7f9BJ0g== X-Google-Smtp-Source: ACHHUZ7riltF1w2kMK9/FEao5kDHEzupgwhRZfvGHIzNT/weB2JE4bnLo/0VpcWlOnNPmEC32Zpg7Q== X-Received: by 2002:a5d:4d51:0:b0:306:2c39:5d52 with SMTP id a17-20020a5d4d51000000b003062c395d52mr2033984wru.57.1685476296347; Tue, 30 May 2023 12:51:36 -0700 (PDT) Received: from ph18.baylibre (laubervilliers-658-1-213-31.w90-63.abo.wanadoo.fr. [90.63.244.31]) by smtp.gmail.com with ESMTPSA id n11-20020adfe34b000000b003078cd719ffsm4271545wrj.95.2023.05.30.12.51.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 May 2023 12:51:35 -0700 (PDT) From: =?utf-8?q?Bernhard_Rosenkr=C3=A4nzer?= To: daniel.lezcano@linaro.org, angelogioacchino.delregno@collabora.com, rafael@kernel.org, amitk@kernel.org, rui.zhang@intel.com, matthias.bgg@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, rdunlap@infradead.org, ye.xingchen@zte.com.cn, p.zabel@pengutronix.de Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, wenst@chromium.org, james.lo@mediatek.com, rex-bc.chen@mediatek.com, nfraprado@collabora.com, abailon@baylibre.com, amergnat@baylibre.com, khilman@baylibre.com Subject: [PATCH v4 1/5] dt-bindings: thermal: mediatek: Add LVTS thermal controller definition for mt8192 Date: Tue, 30 May 2023 21:51:28 +0200 Message-ID: <20230530195132.2286163-2-bero@baylibre.com> X-Mailer: git-send-email 2.41.0.rc2 In-Reply-To: <20230530195132.2286163-1-bero@baylibre.com> References: <20230530195132.2286163-1-bero@baylibre.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Balsam CHIHI Add LVTS thermal controller definition for MT8192. Signed-off-by: Balsam CHIHI Reviewed-by: AngeloGioacchino Del Regno Acked-by: Krzysztof Kozlowski Signed-off-by: Bernhard Rosenkränzer Reviewed-by: Matthias Brugger --- .../thermal/mediatek,lvts-thermal.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/include/dt-bindings/thermal/mediatek,lvts-thermal.h b/include/dt-bindings/thermal/mediatek,lvts-thermal.h index 8fa5a46675c46..5e9eb62174268 100644 --- a/include/dt-bindings/thermal/mediatek,lvts-thermal.h +++ b/include/dt-bindings/thermal/mediatek,lvts-thermal.h @@ -26,4 +26,23 @@ #define MT8195_AP_CAM0 15 #define MT8195_AP_CAM1 16 +#define MT8192_MCU_BIG_CPU0 0 +#define MT8192_MCU_BIG_CPU1 1 +#define MT8192_MCU_BIG_CPU2 2 +#define MT8192_MCU_BIG_CPU3 3 +#define MT8192_MCU_LITTLE_CPU0 4 +#define MT8192_MCU_LITTLE_CPU1 5 +#define MT8192_MCU_LITTLE_CPU2 6 +#define MT8192_MCU_LITTLE_CPU3 7 + +#define MT8192_AP_VPU0 8 +#define MT8192_AP_VPU1 9 +#define MT8192_AP_GPU0 10 +#define MT8192_AP_GPU1 11 +#define MT8192_AP_INFRA 12 +#define MT8192_AP_CAM 13 +#define MT8192_AP_MD0 14 +#define MT8192_AP_MD1 15 +#define MT8192_AP_MD2 16 + #endif /* __MEDIATEK_LVTS_DT_H */ From patchwork Tue May 30 19:51:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Bernhard_Rosenkr=C3=A4nzer?= X-Patchwork-Id: 687134 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0C524C77B73 for ; Tue, 30 May 2023 19:51:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233446AbjE3Tvp (ORCPT ); Tue, 30 May 2023 15:51:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38522 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233420AbjE3Tvl (ORCPT ); Tue, 30 May 2023 15:51:41 -0400 Received: from mail-wm1-x32d.google.com (mail-wm1-x32d.google.com [IPv6:2a00:1450:4864:20::32d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E623D10B for ; Tue, 30 May 2023 12:51:38 -0700 (PDT) Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-3f6042d605dso35513765e9.2 for ; Tue, 30 May 2023 12:51:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20221208.gappssmtp.com; s=20221208; t=1685476297; x=1688068297; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Z41wTT110P1GAe0L+S4OKXh20Gfqxsl4liUxJPQgofw=; b=tEmQmpa44HZ/kv6vTlX8wyeO/afOACS5eUcBQq2VJB/P9Q3YypdEbY6cnBK/8GN8bX 6TsjtwoSjliRb37xd9swXOthPTRt9HZjkIJlh1VXVkepdyiVC/hXUaN+Ax1Dsis4Vq7V n1a3Ci1olvT0RHTiDJm+AN67H+F/igCZP2S/93Y/BNs8fB3gf+aMy+64mZ29DqDqgEKb bTPewOBAxf4FvdW6S6/7Vs4npnOP1Jrla9Ok/PybMioQuJweLF/Lpr2vOVo3mKidb+gk Awkwi/vYduXHg0boGmaAzO2yMYJNQ3bvkPhA0OUU8HmGJXnqprqRCbIP5j2aQBQeHqHr fWlA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685476297; x=1688068297; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Z41wTT110P1GAe0L+S4OKXh20Gfqxsl4liUxJPQgofw=; b=UixSBz7nNmEYNvadK+79A5eoo68AZVLLcpWSSCPLv7BGB3sjbjdz4iQ1nVSeoyZstO Lmd3T2sUjDrY2tVItn6AwJE/OceKddjPsAZaBd1Q/606SgppFU9gU37Y7jyo9HAcebAn oLSXnTZIuI5lTHQBCVjX1vUQH+B+TNfCZMkxmrZVcoulsKn7mBKY7zh/nukjO6qUT7vi ZcKHCfhMvWuuc28KGqFDW5DYPx/YSvJuS02QemrFv3vzTYJuYS1mBxYvQb3pXxmyIUnB 9o61m3qvGsJ83clswntnwwTHhD48gyWclScqudZDOPU1pudiSnAU70/L/5qf+E6v/NKz R6Rw== X-Gm-Message-State: AC+VfDwqNjPZot+wQ+gukKvhKVyC/uChOfI85C2U2UUVofljDc0YjYQN JHjcF2W0r/7YcbYQFf7hhAhpgg== X-Google-Smtp-Source: ACHHUZ4ld9edihUQyCtHl6jda9XcQZmLvXT+gVCe4WVzk5SUgm2lOiWkYBStVyWeeuO0aIpiTxtF6A== X-Received: by 2002:a5d:4050:0:b0:309:49e6:9047 with SMTP id w16-20020a5d4050000000b0030949e69047mr2494496wrp.16.1685476297465; Tue, 30 May 2023 12:51:37 -0700 (PDT) Received: from ph18.baylibre (laubervilliers-658-1-213-31.w90-63.abo.wanadoo.fr. [90.63.244.31]) by smtp.gmail.com with ESMTPSA id n11-20020adfe34b000000b003078cd719ffsm4271545wrj.95.2023.05.30.12.51.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 May 2023 12:51:37 -0700 (PDT) From: =?utf-8?q?Bernhard_Rosenkr=C3=A4nzer?= To: daniel.lezcano@linaro.org, angelogioacchino.delregno@collabora.com, rafael@kernel.org, amitk@kernel.org, rui.zhang@intel.com, matthias.bgg@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, rdunlap@infradead.org, ye.xingchen@zte.com.cn, p.zabel@pengutronix.de Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, wenst@chromium.org, james.lo@mediatek.com, rex-bc.chen@mediatek.com, nfraprado@collabora.com, abailon@baylibre.com, amergnat@baylibre.com, khilman@baylibre.com Subject: [PATCH v4 2/5] thermal/drivers/mediatek/lvts_thermal: Add suspend and resume Date: Tue, 30 May 2023 21:51:29 +0200 Message-ID: <20230530195132.2286163-3-bero@baylibre.com> X-Mailer: git-send-email 2.41.0.rc2 In-Reply-To: <20230530195132.2286163-1-bero@baylibre.com> References: <20230530195132.2286163-1-bero@baylibre.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Balsam CHIHI Add suspend and resume support to LVTS driver. Signed-off-by: Balsam CHIHI Signed-off-by: Bernhard Rosenkränzer Reviewed-by: Matthias Brugger --- drivers/thermal/mediatek/lvts_thermal.c | 34 +++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/mediatek/lvts_thermal.c index d0a3f95b7884b..5ea8a9d569ea6 100644 --- a/drivers/thermal/mediatek/lvts_thermal.c +++ b/drivers/thermal/mediatek/lvts_thermal.c @@ -1169,6 +1169,38 @@ static int lvts_remove(struct platform_device *pdev) return 0; } +static int lvts_suspend(struct platform_device *pdev, pm_message_t state) +{ + struct lvts_domain *lvts_td; + int i; + + lvts_td = platform_get_drvdata(pdev); + + for (i = 0; i < lvts_td->num_lvts_ctrl; i++) + lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], false); + + clk_disable_unprepare(lvts_td->clk); + + return 0; +} + +static int lvts_resume(struct platform_device *pdev) +{ + struct lvts_domain *lvts_td; + int i, ret; + + lvts_td = platform_get_drvdata(pdev); + + ret = clk_prepare_enable(lvts_td->clk); + if (ret) + return ret; + + for (i = 0; i < lvts_td->num_lvts_ctrl; i++) + lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], true); + + return 0; +} + static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] = { { .cal_offset = { 0x04, 0x07 }, @@ -1268,6 +1300,8 @@ MODULE_DEVICE_TABLE(of, lvts_of_match); static struct platform_driver lvts_driver = { .probe = lvts_probe, .remove = lvts_remove, + .suspend = lvts_suspend, + .resume = lvts_resume, .driver = { .name = "mtk-lvts-thermal", .of_match_table = lvts_of_match, From patchwork Tue May 30 19:51:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Bernhard_Rosenkr=C3=A4nzer?= X-Patchwork-Id: 688107 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6B243C77B7A for ; Tue, 30 May 2023 19:51:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233441AbjE3Tvn (ORCPT ); Tue, 30 May 2023 15:51:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38544 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233433AbjE3Tvm (ORCPT ); Tue, 30 May 2023 15:51:42 -0400 Received: from mail-wm1-x333.google.com (mail-wm1-x333.google.com [IPv6:2a00:1450:4864:20::333]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 37CF8E8 for ; Tue, 30 May 2023 12:51:40 -0700 (PDT) Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-3f606a80d34so35672835e9.0 for ; Tue, 30 May 2023 12:51:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20221208.gappssmtp.com; s=20221208; t=1685476298; x=1688068298; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ciWtK/NV8FJwvyzOz+YO15ef5XwL4+CYCLNYB+bwuds=; b=amWzlV4cUJwRSvVCHD47QtIGQYkQihWeUb6kkEeS9PsJ7yT5cSpV0t69U7p7qTx+tc sJBeS6pZOMO85JE+SrxTSENln9XPDdXoipBNYonn4M6WzdEZXVmSQoaPr22g95QDxkCC +Nc34hiSj3Dms6CQbjzTYnXnUHYLO1XnRRD6QElWs4jJ2T/VI4XDW/PpYlkqDLCyCwXI E1CnOUR7p5tIl06Q3MQVwuXDeJExh9wRN6h0t332A7wm9VAf3F1yGnvkN0k4F27jO2Bp A0TJraKaUMzKkiTfOwQATi0vrM6nVPGaTP/8G/mMByKgvEIXEZDb2MwvFJEuSz89L1R2 c08g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685476298; x=1688068298; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ciWtK/NV8FJwvyzOz+YO15ef5XwL4+CYCLNYB+bwuds=; b=VZpexbvJtaNQAWPy1OLA+c+w2pdvG93fMsmsaixCHsS7BShtijab1ETlGKnJb5UEXc 7ZDOfHo0X2FtisX0RpKTim3BocVqqSbJwfTKyRWd0sS1WISbjcQXWDUb/n/1koJ/HzO+ v5G6FQ3HMx9NiYOGxZlOSYwWXvY2CLrgEgGSVfwB7bOZLzAaRvdAYZ6thc5mtDY45jxY 34qJSX6QkaJqpXR0NRWVHGNM/zONmU+O9TD4ggsKMoDLF22eoZ+xnlec4TZNFA1mxFmc FHeGhVBkuFi7J72/svxSbQp1hHqtwYmuS7k5ZiiwRnWbiWW4YkPwomjy8ZBrncMcU6Ts ea1A== X-Gm-Message-State: AC+VfDze+ev1MX7W0ptS49YPVerqjMHQKHjXB4A5nRoce1hVrvMnthql 85TFsMapx5cISathCk2qJRvzMg== X-Google-Smtp-Source: ACHHUZ7wLw7B5SQOBmSWu9Gdf34n6YO0nlX43uCpfTVKq0k35p5Eiji6ld9Pge94hGzHZLjsnZoiJw== X-Received: by 2002:a1c:7215:0:b0:3f4:239c:f19 with SMTP id n21-20020a1c7215000000b003f4239c0f19mr2605232wmc.36.1685476298560; Tue, 30 May 2023 12:51:38 -0700 (PDT) Received: from ph18.baylibre (laubervilliers-658-1-213-31.w90-63.abo.wanadoo.fr. [90.63.244.31]) by smtp.gmail.com with ESMTPSA id n11-20020adfe34b000000b003078cd719ffsm4271545wrj.95.2023.05.30.12.51.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 May 2023 12:51:38 -0700 (PDT) From: =?utf-8?q?Bernhard_Rosenkr=C3=A4nzer?= To: daniel.lezcano@linaro.org, angelogioacchino.delregno@collabora.com, rafael@kernel.org, amitk@kernel.org, rui.zhang@intel.com, matthias.bgg@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, rdunlap@infradead.org, ye.xingchen@zte.com.cn, p.zabel@pengutronix.de Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, wenst@chromium.org, james.lo@mediatek.com, rex-bc.chen@mediatek.com, nfraprado@collabora.com, abailon@baylibre.com, amergnat@baylibre.com, khilman@baylibre.com Subject: [PATCH v4 3/5] thermal/drivers/mediatek/lvts_thermal: Add mt8192 support Date: Tue, 30 May 2023 21:51:30 +0200 Message-ID: <20230530195132.2286163-4-bero@baylibre.com> X-Mailer: git-send-email 2.41.0.rc2 In-Reply-To: <20230530195132.2286163-1-bero@baylibre.com> References: <20230530195132.2286163-1-bero@baylibre.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Balsam CHIHI Add LVTS Driver support for MT8192. Co-developed-by : Nícolas F. R. A. Prado Signed-off-by: Nícolas F. R. A. Prado Signed-off-by: Balsam CHIHI Reviewed-by: Nícolas F. R. A. Prado Signed-off-by: Bernhard Rosenkränzer Reviewed-by: Matthias Brugger --- drivers/thermal/mediatek/lvts_thermal.c | 95 +++++++++++++++++++++++++ 1 file changed, 95 insertions(+) diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/mediatek/lvts_thermal.c index 5ea8a9d569ea6..d5e5214784ece 100644 --- a/drivers/thermal/mediatek/lvts_thermal.c +++ b/drivers/thermal/mediatek/lvts_thermal.c @@ -80,6 +80,7 @@ #define LVTS_MSR_FILTERED_MODE 1 #define LVTS_HW_SHUTDOWN_MT8195 105000 +#define LVTS_HW_SHUTDOWN_MT8192 105000 static int golden_temp = LVTS_GOLDEN_TEMP_DEFAULT; static int coeff_b = LVTS_COEFF_B; @@ -1280,6 +1281,88 @@ static const struct lvts_ctrl_data mt8195_lvts_ap_data_ctrl[] = { } }; +static const struct lvts_ctrl_data mt8192_lvts_mcu_data_ctrl[] = { + { + .cal_offset = { 0x04, 0x08 }, + .lvts_sensor = { + { .dt_id = MT8192_MCU_BIG_CPU0 }, + { .dt_id = MT8192_MCU_BIG_CPU1 } + }, + .num_lvts_sensor = 2, + .offset = 0x0, + .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192, + .mode = LVTS_MSR_FILTERED_MODE, + }, + { + .cal_offset = { 0x0c, 0x10 }, + .lvts_sensor = { + { .dt_id = MT8192_MCU_BIG_CPU2 }, + { .dt_id = MT8192_MCU_BIG_CPU3 } + }, + .num_lvts_sensor = 2, + .offset = 0x100, + .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192, + .mode = LVTS_MSR_FILTERED_MODE, + }, + { + .cal_offset = { 0x14, 0x18, 0x1c, 0x20 }, + .lvts_sensor = { + { .dt_id = MT8192_MCU_LITTLE_CPU0 }, + { .dt_id = MT8192_MCU_LITTLE_CPU1 }, + { .dt_id = MT8192_MCU_LITTLE_CPU2 }, + { .dt_id = MT8192_MCU_LITTLE_CPU3 } + }, + .num_lvts_sensor = 4, + .offset = 0x200, + .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192, + .mode = LVTS_MSR_FILTERED_MODE, + } +}; + +static const struct lvts_ctrl_data mt8192_lvts_ap_data_ctrl[] = { + { + .cal_offset = { 0x24, 0x28 }, + .lvts_sensor = { + { .dt_id = MT8192_AP_VPU0 }, + { .dt_id = MT8192_AP_VPU1 } + }, + .num_lvts_sensor = 2, + .offset = 0x0, + .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192, + }, + { + .cal_offset = { 0x2c, 0x30 }, + .lvts_sensor = { + { .dt_id = MT8192_AP_GPU0 }, + { .dt_id = MT8192_AP_GPU1 } + }, + .num_lvts_sensor = 2, + .offset = 0x100, + .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192, + }, + { + .cal_offset = { 0x34, 0x38 }, + .lvts_sensor = { + { .dt_id = MT8192_AP_INFRA }, + { .dt_id = MT8192_AP_CAM }, + }, + .num_lvts_sensor = 2, + .offset = 0x200, + .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192, + }, + { + .cal_offset = { 0x3c, 0x40, 0x44 }, + .lvts_sensor = { + { .dt_id = MT8192_AP_MD0 }, + { .dt_id = MT8192_AP_MD1 }, + { .dt_id = MT8192_AP_MD2 } + }, + .num_lvts_sensor = 3, + .offset = 0x300, + .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192, + } +}; + static const struct lvts_data mt8195_lvts_mcu_data = { .lvts_ctrl = mt8195_lvts_mcu_data_ctrl, .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl), @@ -1290,9 +1373,21 @@ static const struct lvts_data mt8195_lvts_ap_data = { .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_ap_data_ctrl), }; +static const struct lvts_data mt8192_lvts_mcu_data = { + .lvts_ctrl = mt8192_lvts_mcu_data_ctrl, + .num_lvts_ctrl = ARRAY_SIZE(mt8192_lvts_mcu_data_ctrl), +}; + +static const struct lvts_data mt8192_lvts_ap_data = { + .lvts_ctrl = mt8192_lvts_ap_data_ctrl, + .num_lvts_ctrl = ARRAY_SIZE(mt8192_lvts_ap_data_ctrl), +}; + static const struct of_device_id lvts_of_match[] = { { .compatible = "mediatek,mt8195-lvts-mcu", .data = &mt8195_lvts_mcu_data }, { .compatible = "mediatek,mt8195-lvts-ap", .data = &mt8195_lvts_ap_data }, + { .compatible = "mediatek,mt8192-lvts-mcu", .data = &mt8192_lvts_mcu_data }, + { .compatible = "mediatek,mt8192-lvts-ap", .data = &mt8192_lvts_ap_data }, {}, }; MODULE_DEVICE_TABLE(of, lvts_of_match); From patchwork Tue May 30 19:51:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Bernhard_Rosenkr=C3=A4nzer?= X-Patchwork-Id: 688106 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 65FF6C7EE24 for ; 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[90.63.244.31]) by smtp.gmail.com with ESMTPSA id n11-20020adfe34b000000b003078cd719ffsm4271545wrj.95.2023.05.30.12.51.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 May 2023 12:51:39 -0700 (PDT) From: =?utf-8?q?Bernhard_Rosenkr=C3=A4nzer?= To: daniel.lezcano@linaro.org, angelogioacchino.delregno@collabora.com, rafael@kernel.org, amitk@kernel.org, rui.zhang@intel.com, matthias.bgg@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, rdunlap@infradead.org, ye.xingchen@zte.com.cn, p.zabel@pengutronix.de Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, wenst@chromium.org, james.lo@mediatek.com, rex-bc.chen@mediatek.com, nfraprado@collabora.com, abailon@baylibre.com, amergnat@baylibre.com, khilman@baylibre.com Subject: [PATCH v4 4/5] arm64: dts: mediatek: mt8192: Add thermal nodes and thermal zones Date: Tue, 30 May 2023 21:51:31 +0200 Message-ID: <20230530195132.2286163-5-bero@baylibre.com> X-Mailer: git-send-email 2.41.0.rc2 In-Reply-To: <20230530195132.2286163-1-bero@baylibre.com> References: <20230530195132.2286163-1-bero@baylibre.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Balsam CHIHI Add thermal nodes and thermal zones for the mt8192. The mt8192 SoC has several hotspots around the CPUs. Specify the targeted temperature threshold to apply the mitigation and define the associated cooling devices. Signed-off-by: Balsam CHIHI Reviewed-by: Nícolas F. R. A. Prado [bero@baylibre.com: cosmetic changes, reduce lvts_ap size] Signed-off-by: Bernhard Rosenkränzer --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 454 +++++++++++++++++++++++ 1 file changed, 454 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 65bc8b4046211..82d6629e38c26 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -14,6 +14,8 @@ #include #include #include +#include +#include / { compatible = "mediatek,mt8192"; @@ -71,6 +73,7 @@ cpu0: cpu@0 { d-cache-sets = <128>; next-level-cache = <&l2_0>; capacity-dmips-mhz = <530>; + #cooling-cells = <2>; }; cpu1: cpu@100 { @@ -88,6 +91,7 @@ cpu1: cpu@100 { d-cache-sets = <128>; next-level-cache = <&l2_0>; capacity-dmips-mhz = <530>; + #cooling-cells = <2>; }; cpu2: cpu@200 { @@ -105,6 +109,7 @@ cpu2: cpu@200 { d-cache-sets = <128>; next-level-cache = <&l2_0>; capacity-dmips-mhz = <530>; + #cooling-cells = <2>; }; cpu3: cpu@300 { @@ -122,6 +127,7 @@ cpu3: cpu@300 { d-cache-sets = <128>; next-level-cache = <&l2_0>; capacity-dmips-mhz = <530>; + #cooling-cells = <2>; }; cpu4: cpu@400 { @@ -139,6 +145,7 @@ cpu4: cpu@400 { d-cache-sets = <256>; next-level-cache = <&l2_1>; capacity-dmips-mhz = <1024>; + #cooling-cells = <2>; }; cpu5: cpu@500 { @@ -156,6 +163,7 @@ cpu5: cpu@500 { d-cache-sets = <256>; next-level-cache = <&l2_1>; capacity-dmips-mhz = <1024>; + #cooling-cells = <2>; }; cpu6: cpu@600 { @@ -173,6 +181,7 @@ cpu6: cpu@600 { d-cache-sets = <256>; next-level-cache = <&l2_1>; capacity-dmips-mhz = <1024>; + #cooling-cells = <2>; }; cpu7: cpu@700 { @@ -190,6 +199,7 @@ cpu7: cpu@700 { d-cache-sets = <256>; next-level-cache = <&l2_1>; capacity-dmips-mhz = <1024>; + #cooling-cells = <2>; }; cpu-map { @@ -775,6 +785,17 @@ spi0: spi@1100a000 { status = "disabled"; }; + lvts_ap: thermal-sensor@1100b000 { + compatible = "mediatek,mt8192-lvts-ap"; + reg = <0 0x1100b000 0 0xc00>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_THERM>; + resets = <&infracfg MT8192_INFRA_RST0_THERM_CTRL_SWRST>; + nvmem-cells = <&lvts_e_data1>; + nvmem-cell-names = "lvts-calib-data-1"; + #thermal-sensor-cells = <1>; + }; + pwm0: pwm@1100e000 { compatible = "mediatek,mt8183-disp-pwm"; reg = <0 0x1100e000 0 0x1000>; @@ -1101,6 +1122,17 @@ nor_flash: spi@11234000 { status = "disabled"; }; + lvts_mcu: thermal-sensor@11278000 { + compatible = "mediatek,mt8192-lvts-mcu"; + reg = <0 0x11278000 0 0x1000>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_THERM>; + resets = <&infracfg MT8192_INFRA_RST4_THERM_CTRL_MCU_SWRST>; + nvmem-cells = <&lvts_e_data1>; + nvmem-cell-names = "lvts-calib-data-1"; + #thermal-sensor-cells = <1>; + }; + efuse: efuse@11c10000 { compatible = "mediatek,mt8192-efuse", "mediatek,efuse"; reg = <0 0x11c10000 0 0x1000>; @@ -1827,4 +1859,426 @@ larb2: larb@1f002000 { power-domains = <&spm MT8192_POWER_DOMAIN_MDP>; }; }; + + thermal_zones: thermal-zones { + cpu0-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; + thermal-sensors = <&lvts_mcu MT8192_MCU_LITTLE_CPU0>; + + trips { + cpu0_alert: trip-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu0_crit: trip-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu0_alert>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu1-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; + thermal-sensors = <&lvts_mcu MT8192_MCU_LITTLE_CPU1>; + + trips { + cpu1_alert: trip-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu1_crit: trip-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu1_alert>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu2-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; + thermal-sensors = <&lvts_mcu MT8192_MCU_LITTLE_CPU2>; + + trips { + cpu2_alert: trip-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu2_crit: trip-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu2_alert>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu3-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; + thermal-sensors = <&lvts_mcu MT8192_MCU_LITTLE_CPU3>; + + trips { + cpu3_alert: trip-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu3_crit: trip-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu3_alert>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu4-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; + thermal-sensors = <&lvts_mcu MT8192_MCU_BIG_CPU0>; + + trips { + cpu4_alert: trip-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu4_crit: trip-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu4_alert>; + cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu5-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; + thermal-sensors = <&lvts_mcu MT8192_MCU_BIG_CPU1>; + + trips { + cpu5_alert: trip-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu5_crit: trip-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu5_alert>; + cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu6-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; + thermal-sensors = <&lvts_mcu MT8192_MCU_BIG_CPU2>; + + trips { + cpu6_alert: trip-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu6_crit: trip-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu6_alert>; + cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu7-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; + thermal-sensors = <&lvts_mcu MT8192_MCU_BIG_CPU3>; + + trips { + cpu7_alert: trip-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu7_crit: trip-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu7_alert>; + cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + vpu0-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; + thermal-sensors = <&lvts_ap MT8192_AP_VPU0>; + + trips { + vpu0_alert: trip-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + vpu0_crit: trip-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + vpu1-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; + thermal-sensors = <&lvts_ap MT8192_AP_VPU1>; + + trips { + vpu1_alert: trip-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + vpu1_crit: trip-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + gpu0-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; + thermal-sensors = <&lvts_ap MT8192_AP_GPU0>; + + trips { + gpu0_alert: trip-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + gpu0_crit: trip-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + gpu1-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; + thermal-sensors = <&lvts_ap MT8192_AP_GPU1>; + + trips { + gpu1_alert: trip-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + gpu1_crit: trip-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + infra-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; + thermal-sensors = <&lvts_ap MT8192_AP_INFRA>; + + trips { + infra_alert: trip-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + infra_crit: trip-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cam-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; + thermal-sensors = <&lvts_ap MT8192_AP_CAM>; + + trips { + cam_alert: trip-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cam_crit: trip-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + md0-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; + thermal-sensors = <&lvts_ap MT8192_AP_MD0>; + + trips { + md0_alert: trip-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + md0_crit: trip-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + md1-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; + thermal-sensors = <&lvts_ap MT8192_AP_MD1>; + + trips { + md1_alert: trip-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + md1_crit: trip-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + md2-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; + thermal-sensors = <&lvts_ap MT8192_AP_MD2>; + + trips { + md2_alert: trip-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + md2_crit: trip-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; }; From patchwork Tue May 30 19:51:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Bernhard_Rosenkr=C3=A4nzer?= X-Patchwork-Id: 687133 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 45004C77B7A for ; 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[90.63.244.31]) by smtp.gmail.com with ESMTPSA id n11-20020adfe34b000000b003078cd719ffsm4271545wrj.95.2023.05.30.12.51.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 May 2023 12:51:40 -0700 (PDT) From: =?utf-8?q?Bernhard_Rosenkr=C3=A4nzer?= To: daniel.lezcano@linaro.org, angelogioacchino.delregno@collabora.com, rafael@kernel.org, amitk@kernel.org, rui.zhang@intel.com, matthias.bgg@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, rdunlap@infradead.org, ye.xingchen@zte.com.cn, p.zabel@pengutronix.de Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, wenst@chromium.org, james.lo@mediatek.com, rex-bc.chen@mediatek.com, nfraprado@collabora.com, abailon@baylibre.com, amergnat@baylibre.com, khilman@baylibre.com Subject: [PATCH v4 5/5] thermal/drivers/mediatek/lvts_thermal: Update calibration data documentation Date: Tue, 30 May 2023 21:51:32 +0200 Message-ID: <20230530195132.2286163-6-bero@baylibre.com> X-Mailer: git-send-email 2.41.0.rc2 In-Reply-To: <20230530195132.2286163-1-bero@baylibre.com> References: <20230530195132.2286163-1-bero@baylibre.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Balsam CHIHI Update LVTS calibration data documentation for mt8192 and mt8195. Signed-off-by: Balsam CHIHI Reviewed-by: Nícolas F. R. A. Prado [bero@baylibre.com: Fix issues pointed out by Nícolas F. R. A. Prado ] Signed-off-by: Bernhard Rosenkränzer Reviewed-by: AngeloGioacchino Del Regno --- drivers/thermal/mediatek/lvts_thermal.c | 31 +++++++++++++++++++++++-- 1 file changed, 29 insertions(+), 2 deletions(-) diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/mediatek/lvts_thermal.c index d5e5214784ece..9185d02003633 100644 --- a/drivers/thermal/mediatek/lvts_thermal.c +++ b/drivers/thermal/mediatek/lvts_thermal.c @@ -531,7 +531,8 @@ static int lvts_sensor_init(struct device *dev, struct lvts_ctrl *lvts_ctrl, * The efuse blob values follows the sensor enumeration per thermal * controller. The decoding of the stream is as follow: * - * stream index map for MCU Domain : + * MT8195 : + * Stream index map for MCU Domain mt8195 : * * <-----mcu-tc#0-----> <-----sensor#0-----> <-----sensor#1-----> * 0x01 | 0x02 | 0x03 | 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09 @@ -542,7 +543,7 @@ static int lvts_sensor_init(struct device *dev, struct lvts_ctrl *lvts_ctrl, * <-----mcu-tc#2-----> <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> <-----sensor#7-----> * 0x13 | 0x14 | 0x15 | 0x16 | 0x17 | 0x18 | 0x19 | 0x1A | 0x1B | 0x1C | 0x1D | 0x1E | 0x1F | 0x20 | 0x21 * - * stream index map for AP Domain : + * Stream index map for AP Domain mt8195 : * * <-----ap--tc#0-----> <-----sensor#0-----> <-----sensor#1-----> * 0x22 | 0x23 | 0x24 | 0x25 | 0x26 | 0x27 | 0x28 | 0x29 | 0x2A @@ -556,6 +557,32 @@ static int lvts_sensor_init(struct device *dev, struct lvts_ctrl *lvts_ctrl, * <-----ap--tc#3-----> <-----sensor#7-----> <-----sensor#8-----> * 0x40 | 0x41 | 0x42 | 0x43 | 0x44 | 0x45 | 0x46 | 0x47 | 0x48 * + * MT8192 : + * Stream index map for MCU Domain mt8192 : + * + * <-----mcu-tc#0-----> <-----sensor#0-----> <-----sensor#1-----> + * 0x01 | 0x02 | 0x03 | 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09 | 0x0A | 0x0B + * + * <-----sensor#2-----> <-----sensor#3-----> + * 0x0C | 0x0D | 0x0E | 0x0F | 0x10 | 0x11 | 0x12 | 0x13 + * + * <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> <-----sensor#7-----> + * 0x14 | 0x15 | 0x16 | 0x17 | 0x18 | 0x19 | 0x1A | 0x1B | 0x1C | 0x1D | 0x1E | 0x1F | 0x20 | 0x21 | 0x22 | 0x23 + * + * Stream index map for AP Domain mt8192 : + * + * <-----sensor#0-----> <-----sensor#1-----> + * 0x24 | 0x25 | 0x26 | 0x27 | 0x28 | 0x29 | 0x2A | 0x2B + * + * <-----sensor#2-----> <-----sensor#3-----> + * 0x2C | 0x2D | 0x2E | 0x2F | 0x30 | 0x31 | 0x32 | 0x33 + * + * <-----sensor#4-----> <-----sensor#5-----> + * 0x34 | 0x35 | 0x36 | 0x37 | 0x38 | 0x39 | 0x3A | 0x3B + * + * <-----sensor#6-----> <-----sensor#7-----> <-----sensor#8-----> + * 0x3C | 0x3D | 0x3E | 0x3F | 0x40 | 0x41 | 0x42 | 0x43 | 0x44 | 0x45 | 0x46 | 0x47 + * * The data description gives the offset of the calibration data in * this bytes stream for each sensor. */