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[209.51.188.17]) by mx.google.com with ESMTPS id y6-20020ac85f46000000b003f518050361si9005015qta.778.2023.05.31.15.35.24 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 31 May 2023 15:35:25 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="YylBRMK/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q4UOF-0002WU-Ja; Wed, 31 May 2023 18:33:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q4UOD-0002PI-Sh for qemu-devel@nongnu.org; Wed, 31 May 2023 18:33:57 -0400 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q4UOA-00051o-5p for qemu-devel@nongnu.org; Wed, 31 May 2023 18:33:57 -0400 Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-3f6094cb2d2so1910315e9.2 for ; Wed, 31 May 2023 15:33:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685572429; x=1688164429; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xkoRU3l97/30UWV/TA7AZTeSTQhuq1S7+Fh1SEZ9jOM=; b=YylBRMK/L9OS+eZBH7SnMJ6Pt7wA6dpH6UR6ds4CTy4tYK2Xd1Wt8KKi5S4R30tHNA ibjb7ijRdcBdFNcOkngju06IYvk3VTzSBF0N/owBwaXWoOWVSk7Be+Rqmx/f28usK1du lAZ4wsocPXbxHa2OnV7cj02bCsLooUKHK9VTn00o5AZpo/F5F+GdbBR2b5O5UUCrcOJ0 lThIi+HcBY1m+KKLr5UJ0LtjsB4IXCWCfPb+WKc9neGGlBSmUP/oUZ10GlBo+5E93EYe bGaqj54wskmcuEtihxCpNfwrNfewVvU9lXmsRLDdjAttO0uGNutyeq2Ryp53yr9WF5e9 SBWA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685572429; x=1688164429; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xkoRU3l97/30UWV/TA7AZTeSTQhuq1S7+Fh1SEZ9jOM=; b=Z6faj7lVmwn5pZyaih5VG2HL9gsWY6hmnoPtQ+zBC7cvEpcfFYMxjFbi0RZ9uEqQh2 PV4YMGdC4GfYKcy8ouCZ8husrHscj4FtM0zyC3+xgRfpfhLui5PbRxB/qasK4/O9PsBT fsymbTuhshzslR8+2xIAxcljeVNzBp2fhaiyAoMvhjkONVV7VQ8I2ffhPLt5OGBYkGT9 88B00KPjocvrAu/l1DnX524qL8LJsq4me4UIPvb0YyQmJgRrX0IUFU1gaQoBzW7SEMtf r1Kjp7GnsaFXH/AIQnNcY9iEeAhdf41mbTIWytBTwbtLOympUQZStVOEqRDToEkv46Gf pfAg== X-Gm-Message-State: AC+VfDzbIBo/Yirm+j7VZV/8BdN4F9Qxc/yu3XgYwYNABUhRLlcTVtnY E1GnL67mQfhYpiG+bJnhiZmyuBCFUywQ1CV3tPM= X-Received: by 2002:a05:600c:378b:b0:3f6:1a9:b9db with SMTP id o11-20020a05600c378b00b003f601a9b9dbmr476000wmr.21.1685572429395; Wed, 31 May 2023 15:33:49 -0700 (PDT) Received: from localhost.localdomain ([176.176.146.12]) by smtp.gmail.com with ESMTPSA id k15-20020a7bc40f000000b003f5ffba9ae1sm97659wmi.24.2023.05.31.15.33.48 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 31 May 2023 15:33:49 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , qemu-arm@nongnu.org, qemu-ppc@nongnu.org, Eduardo Habkost , Markus Armbruster , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , Mark Cave-Ayland , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH 1/7] hw/arm/xlnx-versal: Do not open-code sysbus_connect_irq() Date: Thu, 1 Jun 2023 00:33:35 +0200 Message-Id: <20230531223341.34827-2-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230531223341.34827-1-philmd@linaro.org> References: <20230531223341.34827-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The SYSBUS_DEVICE_GPIO_IRQ definition should be internal to the SysBus API. Here we simply open-coded sysbus_connect_irq(). Replace to use the proper API. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- hw/arm/xlnx-versal.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c index 69b1b99e93..de5af506f7 100644 --- a/hw/arm/xlnx-versal.c +++ b/hw/arm/xlnx-versal.c @@ -704,9 +704,7 @@ static void versal_unimp(Versal *s) gpio_in); gpio_in = qdev_get_gpio_in_named(DEVICE(s), "irq-parity-imr-dummy", 0); - qdev_connect_gpio_out_named(DEVICE(&s->pmc.iou.slcr), - SYSBUS_DEVICE_GPIO_IRQ, 0, - gpio_in); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->pmc.iou.slcr), 0, gpio_in); } static void versal_realize(DeviceState *dev, Error **errp) From patchwork Wed May 31 22:33:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 687318 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp36619wru; Wed, 31 May 2023 15:35:13 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7Wfh+1rOIevX6iwldONihLsPCjQO1OL+C2q5VYIM+DBHKhNObx4luAuI4rMIzXfKNxZW4j X-Received: by 2002:ac8:5883:0:b0:3f6:c172:b5a9 with SMTP id t3-20020ac85883000000b003f6c172b5a9mr6186647qta.45.1685572512731; Wed, 31 May 2023 15:35:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685572512; cv=none; d=google.com; s=arc-20160816; b=K8W1gJILjPMQZ9cMGUPVdFGVbB1NxGJP5KBrXNpVF10s5xSo4uKKJTRKRYtr9iKCpj yZJVZ7blCMbVbXAB9yZSTDeKym3y5MkUDr2zuegEypThoQbewafj7EHknHkzXCYHYFou A2q7666kKr+93fH+WP9MqxfdKZwxH5wjICO+DttVs4pIiFJukyh7j6VHolAZMxWc+0Nn E0ZRC6IOKAcQ5zUVryw8aRHUkVVZn5Jg39EVkh0IaMt+/jnJFt1HoxIh2Kg9oiIWYZQD ch7ERZy+ZSCru1dsPAWhzneqXoLrpNu9hOQ8HDFdx0OFNKZultJNb4KDez5S0+99mVOM P/pw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=cytFQrzGMvOi8slgASF27XRO51GqurNYCbfldEiqvjA=; b=pCn9XwGUzHhsPRKONQnue8RlrVYath8C67O94S+FCdjpMRcsC3EhCSm2yhG7UoMlo7 su5LJOyCLLNi/JzalLoMFfyzhgYxTXY5f6BUQAetS/LSFLavntGWQimUCr88owQqz6sq LohKTZ82LcUJsiFAQJOlloGlI76IPkI4epoMdPJCZ2YnaJZnJVChfzpK8KhcofnarB8a nuN4SONNhPyS5AKYx9HH7gxK4zABANAvkAWRhmfh5cgg+2KHja0wyjtolAJ4l9C+KyiI besV7ExrhwmtA4BHrCtRM5AMf6SHwGc47H7WmJY1Pcr4hkTawt/vX1Em3qUfOFhW2w20 M7qA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="K4/ToxIZ"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id y8-20020a05622a120800b003ef46ab6bafsi8874784qtx.569.2023.05.31.15.35.12 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 31 May 2023 15:35:12 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="K4/ToxIZ"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q4UOG-0002ad-PW; Wed, 31 May 2023 18:34:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q4UOF-0002U8-7L for qemu-devel@nongnu.org; Wed, 31 May 2023 18:33:59 -0400 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q4UOC-00052e-Ar for qemu-devel@nongnu.org; Wed, 31 May 2023 18:33:58 -0400 Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-3f603d4bc5bso1779035e9.3 for ; Wed, 31 May 2023 15:33:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685572434; x=1688164434; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=cytFQrzGMvOi8slgASF27XRO51GqurNYCbfldEiqvjA=; b=K4/ToxIZHVVXnyynSouEA6kbrFdLazOsGjRujeP4hK5R+TjDVxqilU0DGuVrGcK326 ij4uX1sqzjEGMCjVtwF8m7nqnz3+1pwmVo+0pcl8AUF9Dy/HeFpBpTgzlIomBWzdSfWk Yiwea0jFmuof6ZlMomw7hWPjvVYJQGg0bjEY8zGwGT5ax9flktMVbUrfCPth4FbSqm9G nlvFGrYKjYFoi8g+ifK0duMN7NTLHe5BdqldV2lg5QSOU2TxuV/5mFmBJia0EO5B/Yj4 AbVGIAI1kS+7a4MIkN9QNaloGQ+Ss2usHNRQug5bB/pBq82XZxpbBCWr9pHVf7vsImda oP8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685572434; x=1688164434; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cytFQrzGMvOi8slgASF27XRO51GqurNYCbfldEiqvjA=; b=jwU3Wx9CwsAua81PRC0lujxqdjKZD5vrTRVXOJCPpyjGMxjfZ3VgTMgFPZI68Mlcm5 +GZZWodVsJmE4t5DGSdKDRzlawWiv/rkZgJYcg3zhbBslfh/+QSKvLK/stKHDRbwV2AH qsidVHiJY0wR1EuE7aTGlA5HJqtNiHw4/TLeOIv/065fEan6U6UyfTT4dbOf5W2XASxQ p+Uj7+cPW3TYOoX0WnE6ZGakSI63yfn7BIk0RGqfzY5VWSpw1OncSB3fmq7NEggVWQ4V I6ltD8a0/WtkuF3AN6UFRWp42o+JkxKyCof2StIzN1weGIxKjjAsFJraI3SyHaUTEkDN HxfQ== X-Gm-Message-State: AC+VfDw9wf5M8u7rljsqltEsC4uIWvMHgqNhBmuIHNf+YvlBs5E0AkLQ 7AnYvq64AI9PxaKgsKE//KBZ2p8kwC9ixxYPrRI= X-Received: by 2002:a1c:4c12:0:b0:3f4:271a:8aaf with SMTP id z18-20020a1c4c12000000b003f4271a8aafmr609146wmf.38.1685572434603; Wed, 31 May 2023 15:33:54 -0700 (PDT) Received: from localhost.localdomain ([176.176.146.12]) by smtp.gmail.com with ESMTPSA id f1-20020a1c6a01000000b003f423508c6bsm68086wmc.44.2023.05.31.15.33.53 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 31 May 2023 15:33:54 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , qemu-arm@nongnu.org, qemu-ppc@nongnu.org, Eduardo Habkost , Markus Armbruster , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , Mark Cave-Ayland , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH 2/7] hw/usb/xlnx: Do not open-code sysbus_pass_irq() Date: Thu, 1 Jun 2023 00:33:36 +0200 Message-Id: <20230531223341.34827-3-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230531223341.34827-1-philmd@linaro.org> References: <20230531223341.34827-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The SYSBUS_DEVICE_GPIO_IRQ definition should be internal to the SysBus API. Here we simply open-coded sysbus_pass_irq(). Replace to use the proper API. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- hw/usb/xlnx-usb-subsystem.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/usb/xlnx-usb-subsystem.c b/hw/usb/xlnx-usb-subsystem.c index d8deeb6ced..462ce6c3ff 100644 --- a/hw/usb/xlnx-usb-subsystem.c +++ b/hw/usb/xlnx-usb-subsystem.c @@ -49,7 +49,7 @@ static void versal_usb2_realize(DeviceState *dev, Error **errp) } sysbus_init_mmio(sbd, &s->dwc3_mr); sysbus_init_mmio(sbd, &s->usb2Ctrl_mr); - qdev_pass_gpios(DEVICE(&s->dwc3.sysbus_xhci), dev, SYSBUS_DEVICE_GPIO_IRQ); + sysbus_pass_irq(sbd, SYS_BUS_DEVICE(&s->dwc3.sysbus_xhci)); } static void versal_usb2_init(Object *obj) From patchwork Wed May 31 22:33:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 687319 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp36641wru; Wed, 31 May 2023 15:35:16 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6HVO/LsDzua5PiiR3JRexijqohIvD7RK4UkxKdW/dxOQAYbsk6875ulyMtJkQDyslBTFow X-Received: by 2002:ad4:5d46:0:b0:621:363c:ea9f with SMTP id jk6-20020ad45d46000000b00621363cea9fmr10838150qvb.19.1685572516049; Wed, 31 May 2023 15:35:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685572516; cv=none; d=google.com; s=arc-20160816; b=e1ZOqkmN1A+vn9uSuQ/OwTzjC3WnhE7JEu49ICW2+MLjGerxMX2+uNuz7CceXcE7G8 tKFyF8xn8+asluXBqStzZC4PfV7GJMCDBAvWdQulA+AEzmxXbymfmNhxAXOg9sh9RWTb JIr2Y15JifCAmG6XAIGvr2AFPfZz9Ei69/x+BmJXOpyY+OXGb7Ugx0XKxlzzRgd31jjg nu0sxRqbzSzPSJGJ1wNa0EDklgE9qVDIVxYVjg3iYaLt6RRgG/VhGuVisFsmEeo/V2Wy wFecsMRDnIKHdKtsX3YbZAdc9id3gizQN9rgZeM3qfgEl630ACsPPstJEk2dtOJl48pn 4tag== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=huoGF1vYpA+J+Saxjh1v1lIbOm2BUrExA4kLN7TpUYc=; b=yGPAwGX/8EU0ckd6OS2O3ayDUYH5m+mUQGOWZAjSJvuC17ACbOyye0QiDvM7ihhuek bcgWJY/Z4QKIcgEIj3sEjj8v/5SgEHXcARXt3ANpqrf6Q+0k6jsuayqhmCeaXQHcCYB0 pqCven/X1xtN4cusyBSZ6hIHGFQtrczwbf0n+VPCVbkH8GNz2qaF4MtHskOH+AFaende kauswT7M36mC9iYvT7sILF0IGemMo/9V26aImVxD89L7bl/OY4Q/nsxt1KqaISz2YStW uHtUSeD7avAmKQOtY+blrJg1ONKxT2wUFoP7S8tZ30heE088qtYKtN6AouX0NMZuAFeM LjzQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="XZ/ae1B+"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id kc28-20020a056214411c00b0056e9871bbc0si555405qvb.23.2023.05.31.15.35.15 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 31 May 2023 15:35:16 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="XZ/ae1B+"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q4UOM-0002yC-Iy; Wed, 31 May 2023 18:34:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q4UOL-0002sc-KT for qemu-devel@nongnu.org; Wed, 31 May 2023 18:34:05 -0400 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q4UOH-000541-D5 for qemu-devel@nongnu.org; Wed, 31 May 2023 18:34:04 -0400 Received: by mail-wm1-x335.google.com with SMTP id 5b1f17b1804b1-3f60e730bf2so1773465e9.1 for ; Wed, 31 May 2023 15:34:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685572440; x=1688164440; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=huoGF1vYpA+J+Saxjh1v1lIbOm2BUrExA4kLN7TpUYc=; b=XZ/ae1B+AbGLfAiYT+qvhpC/hTbBlAdYbyxYK/eCFXw+MZswDkKYkq7h8JRPg4MLqq nODQkjZA6MWrJXbqtmKLuZ3W5hULG8Q9a9PVg0g+/8cB4Dor5CDrhDx9RuNfzDAZWraW deMLKuOjI4GOzUBJ7zuPBfZeoDwHqIRwc4VQrHmYzWpilCO0QlQ91HjsaZtHMAtASpDh MNsO2KNHEjNqbLXsIBSmM9eC6TMKRvRP4iF678pDHMvkgBeBvE27fVKeO0zoSnWdDXmH +CP+I5F55TOQSBaPRg2ZC8uFuToGmDVup7LOjGOOH5Wwv3Rn9DpLDNcdqtMCTkMbNSZ4 caiw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685572440; x=1688164440; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=huoGF1vYpA+J+Saxjh1v1lIbOm2BUrExA4kLN7TpUYc=; b=YqqvSAgRw+MnPn8Dm16RC1D6FNHPr86DSna76Q9EEkSoMcUwNpHTCv0QgULZ+qtIco /9keToLiAzPaBaZskBrHTEd0jQufgBBxmOi3x29kfe7yQ9YaGmBc4eI60UwJvvR/FF4I ZxnzqSgjd58zlRevykMnmsbeJwqrxl09EFGcLbwjDYHu4NcA+09ANXBmJky/XGRW4dz9 XPFvj3eu3iJPjvGAvydgC8bG50RkxNinV3Cz2ZwsDgu4iSzRi777+UY97+PGEVWQd2gN FnfItp/JVlh64wYZbKt7GnPosf9Gyw6dEPGSJyuL00gQ7HgRE8og6IkkhVS0UFFJppxq Au9Q== X-Gm-Message-State: AC+VfDxVMtmb3q73z8rxrwvAReTMlLibDZqXzhhhulJJHTqVbaIJNdJ0 2yoH2CS2ou7MPAkzVldC720eF1Ft7WA38TEIdRM= X-Received: by 2002:a05:600c:114f:b0:3f5:ce4:6c3f with SMTP id z15-20020a05600c114f00b003f50ce46c3fmr611316wmz.7.1685572439802; Wed, 31 May 2023 15:33:59 -0700 (PDT) Received: from localhost.localdomain ([176.176.146.12]) by smtp.gmail.com with ESMTPSA id b9-20020adfe309000000b003079986fd71sm8325422wrj.88.2023.05.31.15.33.58 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 31 May 2023 15:33:59 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , qemu-arm@nongnu.org, qemu-ppc@nongnu.org, Eduardo Habkost , Markus Armbruster , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , Mark Cave-Ayland , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH 3/7] hw/sysbus: Introduce sysbus_init_irqs() Date: Thu, 1 Jun 2023 00:33:37 +0200 Message-Id: <20230531223341.34827-4-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230531223341.34827-1-philmd@linaro.org> References: <20230531223341.34827-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philmd@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The SysBus API currently only provides a method to initialize a single IRQ: sysbus_init_irq(). When we want to initialize multiple SysBus IRQs, we have to call this function multiple times. In order to allow further simplifications, introduce the sysbus_init_irqs() method. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- include/hw/sysbus.h | 1 + hw/core/sysbus.c | 7 ++++++- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/include/hw/sysbus.h b/include/hw/sysbus.h index 3564b7b6a2..bc174b2dc3 100644 --- a/include/hw/sysbus.h +++ b/include/hw/sysbus.h @@ -70,6 +70,7 @@ typedef void FindSysbusDeviceFunc(SysBusDevice *sbdev, void *opaque); void sysbus_init_mmio(SysBusDevice *dev, MemoryRegion *memory); MemoryRegion *sysbus_mmio_get_region(SysBusDevice *dev, int n); void sysbus_init_irq(SysBusDevice *dev, qemu_irq *p); +void sysbus_init_irqs(SysBusDevice *dev, qemu_irq *p, unsigned count); void sysbus_pass_irq(SysBusDevice *dev, SysBusDevice *target); void sysbus_init_ioports(SysBusDevice *dev, uint32_t ioport, uint32_t size); diff --git a/hw/core/sysbus.c b/hw/core/sysbus.c index 35f902b582..a1b4c362c9 100644 --- a/hw/core/sysbus.c +++ b/hw/core/sysbus.c @@ -175,10 +175,15 @@ void sysbus_mmio_map_overlap(SysBusDevice *dev, int n, hwaddr addr, sysbus_mmio_map_common(dev, n, addr, true, priority); } +void sysbus_init_irqs(SysBusDevice *dev, qemu_irq *p, unsigned count) +{ + qdev_init_gpio_out_named(DEVICE(dev), p, SYSBUS_DEVICE_GPIO_IRQ, count); +} + /* Request an IRQ source. The actual IRQ object may be populated later. */ void sysbus_init_irq(SysBusDevice *dev, qemu_irq *p) { - qdev_init_gpio_out_named(DEVICE(dev), p, SYSBUS_DEVICE_GPIO_IRQ, 1); + sysbus_init_irqs(dev, p, 1); } /* Pass IRQs from a target device. */ From patchwork Wed May 31 22:33:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 687320 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp36655wru; Wed, 31 May 2023 15:35:19 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4O+5o7cldgTFfyulEeB02YOnID0hLfu3mmQYUAEFzCp9DJFE/NsKZ68KwFTY6L/yhU1v9R X-Received: by 2002:ad4:5ec7:0:b0:625:aa48:fb71 with SMTP id jm7-20020ad45ec7000000b00625aa48fb71mr9517846qvb.59.1685572519462; Wed, 31 May 2023 15:35:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685572519; cv=none; d=google.com; s=arc-20160816; b=FIxeBgYUHzOuU9ZI5sImrLvSeWWsHYVjPYEVMXYzAh5pFWtz31LEmbU6ZOdXDMgpy5 tHc1lvrP59t/BuM01gOaltzv0gj1MJzs1BCk9RGcwmnVZz6xCMxF29B+NFgLIMleSla4 rRDBvs/3oJQZUMHiVoSSCHAFK1O1huw45eDY/f3oeYnF5cnKxRAvdoPoaTCAtoeyo2jz 4AXpS951Twc9TxQdCN5WgeIquek9DxO86odRwpBsIzicpSqaahJjB0ajvIeRqWsQKXB9 hod+rJ6+h4AnHpzKc6m3w/2EHoCZS9+53f+fcxFrUVdnfmmVNKDEw8xFZELjYQvhrq9d P68Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=b5ueUgIQTlD0vpS7sELdcFGXSEew10rN9NLHJA/jJ1g=; b=bFfcwCjTeJ7dhuqz0X3OKAh5gryqv6YfgK36SpN1gNmI2QJiiZ7sxn+GAWIh8tAW/E 5NhRU9k4++R/oMbFTMFrg82f8JlU+S/5zVXrjPiiBndNQBIgepJe2ve2+3A1gZpOTOqL ekhFZANWKvwWD1/a243NXS4iBcUHDLFm2k45tuMteBhmh+Si/lEYMHz5ZyBi6zYp4oX4 japyNvacRN2FRql+TaNSZgje+/gaSZBLa1/7Q3ZxVfegBpQSkK+t6h8HchQIsYbsdBRA U5cEMDxIE6txK22AM4/wttpg4Ao4EPbkwtGWcAcRAUF3e2SPz3VbFf3/ebWGsvu/TIPC XzTw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jHMY5DoT; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id gw11-20020a0562140f0b00b0062613d09f90si7309852qvb.239.2023.05.31.15.35.19 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 31 May 2023 15:35:19 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jHMY5DoT; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q4UOQ-0003Mm-Vz; Wed, 31 May 2023 18:34:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q4UOO-0003Ae-RC for qemu-devel@nongnu.org; Wed, 31 May 2023 18:34:08 -0400 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q4UOM-00054j-Kn for qemu-devel@nongnu.org; Wed, 31 May 2023 18:34:08 -0400 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-3f603ff9c02so1845285e9.2 for ; Wed, 31 May 2023 15:34:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685572445; x=1688164445; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=b5ueUgIQTlD0vpS7sELdcFGXSEew10rN9NLHJA/jJ1g=; b=jHMY5DoTxQ7YAUVMoM48yiG7puIlcKtdgWhlj2cFlzMDgEbz00rQ4sg1k1sZwi9FKO FgBsAKh2MXxTclcZn89RPydJOA9wNCyABqDCLCq7Ecfd3wx7XBY1oCzwNaFY/UW06hFj fUrRv9ApXiEVg2MWxfgFbNsnyyVefp/AHy0dl6WrmoAkxVKMjniJzY3ZCdG5rtemNPwD mU/ARzFyn/2cmcddYGAraxK/74rdNrtXDb2Xhd/xKDqTT6rvYqCi3/xowsn7/96ASkCy rXyKBPuV6uA2tYwHX34JNzCaUSJf6bcCT8Slxu5GDYufDWGecwY38YbNxVQ7fmJc6AFA VWoQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685572445; x=1688164445; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=b5ueUgIQTlD0vpS7sELdcFGXSEew10rN9NLHJA/jJ1g=; b=bybk8gfV2mACFzH7feqCOJnLPPasrKbpQdqyEPCNNcYf4ULhJ5WI5AgHI1uVRtmPmh hUbGSxFjU5s/8xybPuiTidUaBB7aglL7vYbHER33NXvzia+u35MDF6imX00C5oQYJD4g Y1YT7K2px3nLfZkoBImnoWFDLnhUUzupbgnBIRAUDQJ2oG5CqPNi/oqCEecIa5XNJn4f 3m6WUuG98eSGq0fZPaCwuClK3fmD6MkWOg805IxP08Z6DUBNQ+6GtDxRE6oDZrexTqCu BSAwFsBOylZpu3pePEHzNnj6YJUXLwlOpe8aIc5SHgS9psYLrOrE4Fx4D8naEkiL3RcI l9hg== X-Gm-Message-State: AC+VfDxl9//EZpoG0ng/S91RBe+qiZWcGGahDVuDnGF5yjLkNmu/jibr Ex+QEVkNtot6VKWQmB34e90kl9g44oMeT0T3kRM= X-Received: by 2002:a05:600c:3650:b0:3f6:2d8:4823 with SMTP id y16-20020a05600c365000b003f602d84823mr538248wmq.3.1685572445190; Wed, 31 May 2023 15:34:05 -0700 (PDT) Received: from localhost.localdomain ([176.176.146.12]) by smtp.gmail.com with ESMTPSA id n23-20020a7bc5d7000000b003f6041f5a6csm114610wmk.12.2023.05.31.15.34.03 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 31 May 2023 15:34:04 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , qemu-arm@nongnu.org, qemu-ppc@nongnu.org, Eduardo Habkost , Markus Armbruster , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , Mark Cave-Ayland , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH 4/7] hw/usb/hcd-xhci: Use sysbus_init_irqs() Date: Thu, 1 Jun 2023 00:33:38 +0200 Message-Id: <20230531223341.34827-5-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230531223341.34827-1-philmd@linaro.org> References: <20230531223341.34827-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The SYSBUS_DEVICE_GPIO_IRQ definition should be internal to the SysBus API. Use the recently introduced sysbus_init_irqs() method to avoid using this internal definition. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- hw/usb/hcd-xhci-sysbus.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/hw/usb/hcd-xhci-sysbus.c b/hw/usb/hcd-xhci-sysbus.c index faf57b4797..e512849b34 100644 --- a/hw/usb/hcd-xhci-sysbus.c +++ b/hw/usb/hcd-xhci-sysbus.c @@ -40,9 +40,6 @@ static void xhci_sysbus_realize(DeviceState *dev, Error **errp) if (!qdev_realize(DEVICE(&s->xhci), NULL, errp)) { return; } - s->irq = g_new0(qemu_irq, s->xhci.numintrs); - qdev_init_gpio_out_named(dev, s->irq, SYSBUS_DEVICE_GPIO_IRQ, - s->xhci.numintrs); if (s->xhci.dma_mr) { s->xhci.as = g_malloc0(sizeof(AddressSpace)); address_space_init(s->xhci.as, s->xhci.dma_mr, NULL); @@ -50,6 +47,8 @@ static void xhci_sysbus_realize(DeviceState *dev, Error **errp) s->xhci.as = &address_space_memory; } + s->irq = g_new0(qemu_irq, s->xhci.numintrs); + sysbus_init_irqs(SYS_BUS_DEVICE(dev), s->irq, s->xhci.numintrs); sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->xhci.mem); } From patchwork Wed May 31 22:33:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 687322 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp36708wru; Wed, 31 May 2023 15:35:31 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4cb5csSsjh8NQq4JepLRFEFHi5X2FSZWmyqhj8yeD1TCRPLeOd6GTikaBwpdScLkwXH/ue X-Received: by 2002:a05:620a:3b18:b0:75b:399a:2224 with SMTP id tl24-20020a05620a3b1800b0075b399a2224mr6600086qkn.28.1685572530910; Wed, 31 May 2023 15:35:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685572530; cv=none; d=google.com; s=arc-20160816; b=DlfNh0iotUkdCJjrdVuZQPK9t6Lc0J3f3rrIVD10/lgD1FdC4uhs/25ZqVw+gx4Uwo +G0DElXl5HLQ8Sr8CDVpP5Xtte0JxBVjOP3QHLkSx7bqt6b9pjpVXXfKtdRAOTqmej7T gPhnPMVxdVAhBfjdf6io2j+zKCeWvS2ANEhx5Isqhno5cHir69Pau4BcVce4xdNAw3Wl 4qf78ZSJhbnkqcZbgloNj9wPP5dp7XHjzQ9zmV1bf6ZYPAVIwSmIE78UbfvoILGDjm4y 5cEc0s7D6gXkbK2i+caHM1sG75EF8texmvsYGg/L0VFmB+oYVWUjP/YbfIPVQVV93C9M VQiw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=UhcA2XjpvZA5C8xTPJzpjClC6ek2VDg4k24l/0BltKI=; b=AzVInrMztrBzAvl+rUIFi8oSCARKsoEj2QvztrfKGpuMljthmmwxYR/tjknUlIz1l3 5kmEB4q5dWjDkqnqbOr3oNSmaoa5vJpVofdLMMeUFYIC2SRxMXK1fTd8JscS9I3kkf0q r2JVGSfEgb3ucdHWlQ9CvOOAA3n3OZhZXNyruD7FI5/Tk60Y9T60UT6hG30zGFG/U0pJ phpYpMjS3Al9i9/xpm9M/oVSG8yw5pJQ20BiS6n7zrwSTglGej2Z6YCwBmxyXIGWQPQl xiT/LVKQYCj99NTVAbS33Kg4EWgb+NEYGYRYzk45DF/t/V+YnNfJNDS/I5P+00K4NmUj VTig== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=DBiO+QLd; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- include/hw/sysbus.h | 2 -- hw/core/sysbus.c | 2 ++ 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/include/hw/sysbus.h b/include/hw/sysbus.h index bc174b2dc3..cdd83c555e 100644 --- a/include/hw/sysbus.h +++ b/include/hw/sysbus.h @@ -26,8 +26,6 @@ OBJECT_DECLARE_TYPE(SysBusDevice, SysBusDeviceClass, * classes overriding it are not required to invoke its implementation. */ -#define SYSBUS_DEVICE_GPIO_IRQ "sysbus-irq" - struct SysBusDeviceClass { /*< private >*/ DeviceClass parent_class; diff --git a/hw/core/sysbus.c b/hw/core/sysbus.c index a1b4c362c9..f0ba57dcbf 100644 --- a/hw/core/sysbus.c +++ b/hw/core/sysbus.c @@ -24,6 +24,8 @@ #include "monitor/monitor.h" #include "exec/address-spaces.h" +#define SYSBUS_DEVICE_GPIO_IRQ "sysbus-irq" + static void sysbus_dev_print(Monitor *mon, DeviceState *dev, int indent); static char *sysbus_get_fw_dev_path(DeviceState *dev); From patchwork Wed May 31 22:33:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 687323 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp36804wru; Wed, 31 May 2023 15:35:50 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6KfmZKNhTvGz7fxSyYx2/DUdxOLAhpOHW53EsxDb79iR7K97Cgm2cMoP39u79w4QEVs1Qj X-Received: by 2002:a37:34a:0:b0:75b:23a1:8349 with SMTP id 71-20020a37034a000000b0075b23a18349mr6450169qkd.68.1685572549903; Wed, 31 May 2023 15:35:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685572549; cv=none; d=google.com; s=arc-20160816; b=q4QzfRPfmulBcORiI6oBAnc1hyzKIX8vk3IU3w/HqiJu6Op/yjchOw08DbtSaOM6Hn hRJAYB+m9+wm9dvHuFeQhGM2zhcfazYltSEqsiaCv1Rk7HNA+pEFHC90OJqw9rIe4aAu BRZwJEmn1d9Ygdnsp2Ud6kHWIx2mgik82zEjszL4EyZ/gY04rzlr+ilZyQv+bIwni+Ft OvdZbGnDM0hk5u6jmEoQbrkTgrkxh+emsax6oFIuFISxDncrd+4+8WQ1wyFAsDFEhPEn npfVBZT13lgeVOg6HL+QjgCDOr9/PDgh/BlfjevfHaD2CQfoqfU7Abd896Ck3xxq9FZO ZhbQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=hD5SWLVogZIj3Sd56IpeZ4SmSKFNXjKZY8kepnkg57M=; b=x3tU54YvhCrr7TWTcDh4GJ5j7SSwYNaVq+ZNSh4IdWpdEHOSPQfxzlB8OFxUqKYW/j 7pHhzKNPb8RECurl+tZFJeTrraPgJe68awAyohQOwCjnS5iQhm+Obh6CdkXRR8GN4ufu /iECtIyT/LdFVQO0cLPCoNfw3dZJFr5CAlSac0pzTNd1iGzf4Emw8nCWV3FmE3n9fnEM 7TR8yjlpz0DIUcrhTp9dTrv3fHMjo4tL0ddpAQtDWUmi5LdhDUYZP0YIqW83UY2p5fgq KARDLIiMMsm/+Dw8fRMaGEquwNW9vl+xVvZ++2hlptEOUJslXvmn877+X4AmWLIysZM4 AWFw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Dymjd7We; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Wed, 31 May 2023 15:34:15 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , qemu-arm@nongnu.org, qemu-ppc@nongnu.org, Eduardo Habkost , Markus Armbruster , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , Mark Cave-Ayland , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH 6/7] hw: Simplify using sysbus_init_irqs() [automatic] Date: Thu, 1 Jun 2023 00:33:40 +0200 Message-Id: <20230531223341.34827-7-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230531223341.34827-1-philmd@linaro.org> References: <20230531223341.34827-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::133; envelope-from=philmd@linaro.org; helo=mail-lf1-x133.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Change created mechanically using the following coccinelle semantic patch: @@ expression array; identifier i; expression sbd, count; @@ - for (i = 0; i < count; i++) { - sysbus_init_irq(sbd, &array[i]); - } + sysbus_init_irqs(sbd, array, count); Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- hw/arm/smmuv3.c | 6 +----- hw/arm/stellaris.c | 5 +---- hw/arm/strongarm.c | 5 +---- hw/arm/versatilepb.c | 5 +---- hw/char/pl011.c | 5 +---- hw/char/renesas_sci.c | 5 +---- hw/core/platform-bus.c | 5 +---- hw/dma/pl330.c | 4 +--- hw/dma/sifive_pdma.c | 5 +---- hw/gpio/sifive_gpio.c | 5 +---- hw/i386/kvm/xen_evtchn.c | 5 +---- hw/intc/arm_gic_common.c | 20 +++++--------------- hw/intc/arm_gicv2m.c | 5 +---- hw/intc/exynos4210_combiner.c | 5 +---- hw/intc/loongarch_extioi.c | 6 ++---- hw/intc/loongson_liointc.c | 5 +---- hw/intc/openpic.c | 6 ++---- hw/intc/slavio_intctl.c | 6 ++---- hw/misc/avr_power.c | 4 +--- hw/misc/macio/gpio.c | 5 +---- hw/misc/stm32f4xx_exti.c | 5 +---- hw/net/cadence_gem.c | 5 +---- hw/net/mcf_fec.c | 5 +---- hw/pci-host/designware.c | 5 +---- hw/pci-host/ppce500.c | 4 +--- hw/pci-host/raven.c | 4 +--- hw/pci-host/sh_pci.c | 5 +---- hw/pci-host/versatile.c | 4 +--- hw/ppc/ppc405_uc.c | 10 ++-------- hw/ppc/ppc440_uc.c | 6 ++---- hw/ppc/ppc4xx_devs.c | 4 +--- hw/ppc/ppc4xx_pci.c | 5 +---- hw/ssi/ibex_spi_host.c | 5 +---- hw/ssi/imx_spi.c | 5 +---- hw/ssi/sifive_spi.c | 5 +---- hw/ssi/xilinx_spi.c | 5 +---- hw/ssi/xilinx_spips.c | 4 +--- hw/ssi/xlnx-versal-ospi.c | 4 +--- hw/timer/allwinner-a10-pit.c | 4 +--- hw/timer/exynos4210_mct.c | 4 +--- hw/timer/hpet.c | 4 +--- hw/timer/renesas_cmt.c | 5 +---- hw/timer/sifive_pwm.c | 5 +---- 43 files changed, 52 insertions(+), 177 deletions(-) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 932f009697..f080d97d3f 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -1692,11 +1692,7 @@ static const MemoryRegionOps smmu_mem_ops = { static void smmu_init_irq(SMMUv3State *s, SysBusDevice *dev) { - int i; - - for (i = 0; i < ARRAY_SIZE(s->irq); i++) { - sysbus_init_irq(dev, &s->irq[i]); - } + sysbus_init_irqs(dev, s->irq, ARRAY_SIZE(s->irq)); } static void smmu_reset_hold(Object *obj) diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index f7e99baf62..4bf9ef05c8 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -934,11 +934,8 @@ static void stellaris_adc_init(Object *obj) DeviceState *dev = DEVICE(obj); StellarisADCState *s = STELLARIS_ADC(obj); SysBusDevice *sbd = SYS_BUS_DEVICE(obj); - int n; - for (n = 0; n < 4; n++) { - sysbus_init_irq(sbd, &s->irq[n]); - } + sysbus_init_irqs(sbd, s->irq, 4); memory_region_init_io(&s->iomem, obj, &stellaris_adc_ops, s, "adc", 0x1000); diff --git a/hw/arm/strongarm.c b/hw/arm/strongarm.c index cc73145053..f785dcf08e 100644 --- a/hw/arm/strongarm.c +++ b/hw/arm/strongarm.c @@ -658,7 +658,6 @@ static void strongarm_gpio_initfn(Object *obj) DeviceState *dev = DEVICE(obj); StrongARMGPIOInfo *s = STRONGARM_GPIO(obj); SysBusDevice *sbd = SYS_BUS_DEVICE(obj); - int i; qdev_init_gpio_in(dev, strongarm_gpio_set, 28); qdev_init_gpio_out(dev, s->handler, 28); @@ -667,9 +666,7 @@ static void strongarm_gpio_initfn(Object *obj) "gpio", 0x1000); sysbus_init_mmio(sbd, &s->iomem); - for (i = 0; i < 11; i++) { - sysbus_init_irq(sbd, &s->irqs[i]); - } + sysbus_init_irqs(sbd, s->irqs, 11); sysbus_init_irq(sbd, &s->irqX); } diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c index 05b9462a5b..6a5b1fc53e 100644 --- a/hw/arm/versatilepb.c +++ b/hw/arm/versatilepb.c @@ -160,12 +160,9 @@ static void vpb_sic_init(Object *obj) DeviceState *dev = DEVICE(obj); vpb_sic_state *s = VERSATILE_PB_SIC(obj); SysBusDevice *sbd = SYS_BUS_DEVICE(obj); - int i; qdev_init_gpio_in(dev, vpb_sic_set_irq, 32); - for (i = 0; i < 32; i++) { - sysbus_init_irq(sbd, &s->parent[i]); - } + sysbus_init_irqs(sbd, s->parent, 32); s->irq = 31; memory_region_init_io(&s->iomem, obj, &vpb_sic_ops, s, "vpb-sic", 0x1000); diff --git a/hw/char/pl011.c b/hw/char/pl011.c index 77bbc2a982..2056e32385 100644 --- a/hw/char/pl011.c +++ b/hw/char/pl011.c @@ -442,13 +442,10 @@ static void pl011_init(Object *obj) { SysBusDevice *sbd = SYS_BUS_DEVICE(obj); PL011State *s = PL011(obj); - int i; memory_region_init_io(&s->iomem, OBJECT(s), &pl011_ops, s, "pl011", 0x1000); sysbus_init_mmio(sbd, &s->iomem); - for (i = 0; i < ARRAY_SIZE(s->irq); i++) { - sysbus_init_irq(sbd, &s->irq[i]); - } + sysbus_init_irqs(sbd, s->irq, ARRAY_SIZE(s->irq)); s->clk = qdev_init_clock_in(DEVICE(obj), "clk", pl011_clock_update, s, ClockUpdate); diff --git a/hw/char/renesas_sci.c b/hw/char/renesas_sci.c index 1c63467290..d404976279 100644 --- a/hw/char/renesas_sci.c +++ b/hw/char/renesas_sci.c @@ -286,15 +286,12 @@ static void rsci_init(Object *obj) { SysBusDevice *d = SYS_BUS_DEVICE(obj); RSCIState *sci = RSCI(obj); - int i; memory_region_init_io(&sci->memory, OBJECT(sci), &sci_ops, sci, "renesas-sci", 0x8); sysbus_init_mmio(d, &sci->memory); - for (i = 0; i < SCI_NR_IRQ; i++) { - sysbus_init_irq(d, &sci->irq[i]); - } + sysbus_init_irqs(d, sci->irq, SCI_NR_IRQ); timer_init_ns(&sci->timer, QEMU_CLOCK_VIRTUAL, txend, sci); } diff --git a/hw/core/platform-bus.c b/hw/core/platform-bus.c index b8487b26b6..5e75324434 100644 --- a/hw/core/platform-bus.c +++ b/hw/core/platform-bus.c @@ -182,7 +182,6 @@ static void platform_bus_realize(DeviceState *dev, Error **errp) { PlatformBusDevice *pbus; SysBusDevice *d; - int i; d = SYS_BUS_DEVICE(dev); pbus = PLATFORM_BUS_DEVICE(dev); @@ -193,9 +192,7 @@ static void platform_bus_realize(DeviceState *dev, Error **errp) pbus->used_irqs = bitmap_new(pbus->num_irqs); pbus->irqs = g_new0(qemu_irq, pbus->num_irqs); - for (i = 0; i < pbus->num_irqs; i++) { - sysbus_init_irq(d, &pbus->irqs[i]); - } + sysbus_init_irqs(d, pbus->irqs, pbus->num_irqs); /* some devices might be initialized before so update used IRQs map */ plaform_bus_refresh_irqs(pbus); diff --git a/hw/dma/pl330.c b/hw/dma/pl330.c index e7e67dd8b6..d1c24fa7b8 100644 --- a/hw/dma/pl330.c +++ b/hw/dma/pl330.c @@ -1620,9 +1620,7 @@ static void pl330_realize(DeviceState *dev, Error **errp) s->manager.is_manager = true; s->irq = g_new0(qemu_irq, s->num_events); - for (i = 0; i < s->num_events; i++) { - sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]); - } + sysbus_init_irqs(SYS_BUS_DEVICE(dev), s->irq, s->num_events); qdev_init_gpio_in(dev, pl330_dma_stop_irq, PL330_PERIPH_NUM); diff --git a/hw/dma/sifive_pdma.c b/hw/dma/sifive_pdma.c index 1dd88f3479..61c138323b 100644 --- a/hw/dma/sifive_pdma.c +++ b/hw/dma/sifive_pdma.c @@ -454,15 +454,12 @@ static const MemoryRegionOps sifive_pdma_ops = { static void sifive_pdma_realize(DeviceState *dev, Error **errp) { SiFivePDMAState *s = SIFIVE_PDMA(dev); - int i; memory_region_init_io(&s->iomem, OBJECT(dev), &sifive_pdma_ops, s, TYPE_SIFIVE_PDMA, SIFIVE_PDMA_REG_SIZE); sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); - for (i = 0; i < SIFIVE_PDMA_IRQS; i++) { - sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]); - } + sysbus_init_irqs(SYS_BUS_DEVICE(dev), s->irq, SIFIVE_PDMA_IRQS); } static void sifive_pdma_class_init(ObjectClass *klass, void *data) diff --git a/hw/gpio/sifive_gpio.c b/hw/gpio/sifive_gpio.c index 78bf29e996..fcb863a3ef 100644 --- a/hw/gpio/sifive_gpio.c +++ b/hw/gpio/sifive_gpio.c @@ -362,10 +362,7 @@ static void sifive_gpio_realize(DeviceState *dev, Error **errp) TYPE_SIFIVE_GPIO, SIFIVE_GPIO_SIZE); sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio); - - for (int i = 0; i < s->ngpio; i++) { - sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]); - } + sysbus_init_irqs(SYS_BUS_DEVICE(dev), s->irq, s->ngpio); qdev_init_gpio_in(DEVICE(s), sifive_gpio_set, s->ngpio); qdev_init_gpio_out(DEVICE(s), s->output, s->ngpio); diff --git a/hw/i386/kvm/xen_evtchn.c b/hw/i386/kvm/xen_evtchn.c index 3048329474..12c4419907 100644 --- a/hw/i386/kvm/xen_evtchn.c +++ b/hw/i386/kvm/xen_evtchn.c @@ -303,16 +303,13 @@ void xen_evtchn_create(void) { XenEvtchnState *s = XEN_EVTCHN(sysbus_create_simple(TYPE_XEN_EVTCHN, -1, NULL)); - int i; xen_evtchn_singleton = s; qemu_mutex_init(&s->port_lock); s->gsi_bh = aio_bh_new(qemu_get_aio_context(), gsi_assert_bh, s); - for (i = 0; i < IOAPIC_NUM_PINS; i++) { - sysbus_init_irq(SYS_BUS_DEVICE(s), &s->gsis[i]); - } + sysbus_init_irqs(SYS_BUS_DEVICE(s), s->gsis, IOAPIC_NUM_PINS); /* * The Xen scheme for encoding PIRQ# into an MSI message is not diff --git a/hw/intc/arm_gic_common.c b/hw/intc/arm_gic_common.c index a379cea395..1742c752eb 100644 --- a/hw/intc/arm_gic_common.c +++ b/hw/intc/arm_gic_common.c @@ -143,22 +143,12 @@ void gic_init_irqs_and_mmio(GICState *s, qemu_irq_handler handler, i += (GIC_INTERNAL * s->num_cpu); qdev_init_gpio_in(DEVICE(s), handler, i); - for (i = 0; i < s->num_cpu; i++) { - sysbus_init_irq(sbd, &s->parent_irq[i]); - } - for (i = 0; i < s->num_cpu; i++) { - sysbus_init_irq(sbd, &s->parent_fiq[i]); - } - for (i = 0; i < s->num_cpu; i++) { - sysbus_init_irq(sbd, &s->parent_virq[i]); - } - for (i = 0; i < s->num_cpu; i++) { - sysbus_init_irq(sbd, &s->parent_vfiq[i]); - } + sysbus_init_irqs(sbd, s->parent_irq, s->num_cpu); + sysbus_init_irqs(sbd, s->parent_fiq, s->num_cpu); + sysbus_init_irqs(sbd, s->parent_virq, s->num_cpu); + sysbus_init_irqs(sbd, s->parent_vfiq, s->num_cpu); if (s->virt_extn) { - for (i = 0; i < s->num_cpu; i++) { - sysbus_init_irq(sbd, &s->maintenance_irq[i]); - } + sysbus_init_irqs(sbd, s->maintenance_irq, s->num_cpu); } /* Distributor */ diff --git a/hw/intc/arm_gicv2m.c b/hw/intc/arm_gicv2m.c index d564b857eb..8167d5886c 100644 --- a/hw/intc/arm_gicv2m.c +++ b/hw/intc/arm_gicv2m.c @@ -135,7 +135,6 @@ static const MemoryRegionOps gicv2m_ops = { static void gicv2m_realize(DeviceState *dev, Error **errp) { ARMGICv2mState *s = ARM_GICV2M(dev); - int i; if (s->num_spi > GICV2M_NUM_SPI_MAX) { error_setg(errp, @@ -151,9 +150,7 @@ static void gicv2m_realize(DeviceState *dev, Error **errp) return; } - for (i = 0; i < s->num_spi; i++) { - sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->spi[i]); - } + sysbus_init_irqs(SYS_BUS_DEVICE(dev), s->spi, s->num_spi); msi_nonbroken = true; kvm_gsi_direct_mapping = true; diff --git a/hw/intc/exynos4210_combiner.c b/hw/intc/exynos4210_combiner.c index 4ba448fdb1..eb793e5623 100644 --- a/hw/intc/exynos4210_combiner.c +++ b/hw/intc/exynos4210_combiner.c @@ -309,16 +309,13 @@ static void exynos4210_combiner_init(Object *obj) DeviceState *dev = DEVICE(obj); Exynos4210CombinerState *s = EXYNOS4210_COMBINER(obj); SysBusDevice *sbd = SYS_BUS_DEVICE(obj); - unsigned int i; /* Allocate general purpose input signals and connect a handler to each of * them */ qdev_init_gpio_in(dev, exynos4210_combiner_handler, IIC_NIRQ); /* Connect SysBusDev irqs to device specific irqs */ - for (i = 0; i < IIC_NGRP; i++) { - sysbus_init_irq(sbd, &s->output_irq[i]); - } + sysbus_init_irqs(sbd, s->output_irq, IIC_NGRP); memory_region_init_io(&s->iomem, obj, &exynos4210_combiner_ops, s, "exynos4210-combiner", IIC_REGION_SIZE); diff --git a/hw/intc/loongarch_extioi.c b/hw/intc/loongarch_extioi.c index 0e7a3e32f3..db941de20e 100644 --- a/hw/intc/loongarch_extioi.c +++ b/hw/intc/loongarch_extioi.c @@ -273,11 +273,9 @@ static void loongarch_extioi_instance_init(Object *obj) { SysBusDevice *dev = SYS_BUS_DEVICE(obj); LoongArchExtIOI *s = LOONGARCH_EXTIOI(obj); - int i, cpu, pin; + int cpu, pin; - for (i = 0; i < EXTIOI_IRQS; i++) { - sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]); - } + sysbus_init_irqs(SYS_BUS_DEVICE(dev), s->irq, EXTIOI_IRQS); qdev_init_gpio_in(DEVICE(obj), extioi_setirq, EXTIOI_IRQS); diff --git a/hw/intc/loongson_liointc.c b/hw/intc/loongson_liointc.c index cc11b544cb..37b5f473d4 100644 --- a/hw/intc/loongson_liointc.c +++ b/hw/intc/loongson_liointc.c @@ -221,13 +221,10 @@ static void irq_handler(void *opaque, int irq, int level) static void loongson_liointc_init(Object *obj) { struct loongson_liointc *p = LOONGSON_LIOINTC(obj); - int i; qdev_init_gpio_in(DEVICE(obj), irq_handler, 32); - for (i = 0; i < NUM_PARENTS; i++) { - sysbus_init_irq(SYS_BUS_DEVICE(obj), &p->parent_irq[i]); - } + sysbus_init_irqs(SYS_BUS_DEVICE(obj), p->parent_irq, NUM_PARENTS); memory_region_init_io(&p->mmio, obj, &pic_ops, p, TYPE_LOONGSON_LIOINTC, R_END); diff --git a/hw/intc/openpic.c b/hw/intc/openpic.c index c757adbe53..da9b833c33 100644 --- a/hw/intc/openpic.c +++ b/hw/intc/openpic.c @@ -1505,7 +1505,7 @@ static void openpic_realize(DeviceState *dev, Error **errp) { SysBusDevice *d = SYS_BUS_DEVICE(dev); OpenPICState *opp = OPENPIC(dev); - int i, j; + int i; int list_count = 0; static const MemReg list_le[] = { {"glb", &openpic_glb_ops_le, @@ -1597,9 +1597,7 @@ static void openpic_realize(DeviceState *dev, Error **errp) for (i = 0; i < opp->nb_cpus; i++) { opp->dst[i].irqs = g_new0(qemu_irq, OPENPIC_OUTPUT_NB); - for (j = 0; j < OPENPIC_OUTPUT_NB; j++) { - sysbus_init_irq(d, &opp->dst[i].irqs[j]); - } + sysbus_init_irqs(d, opp->dst[i].irqs, OPENPIC_OUTPUT_NB); opp->dst[i].raised.queue_size = IRQQUEUE_SIZE_BITS; opp->dst[i].raised.queue = bitmap_new(IRQQUEUE_SIZE_BITS); diff --git a/hw/intc/slavio_intctl.c b/hw/intc/slavio_intctl.c index f7e59ba643..e2a3bd3e86 100644 --- a/hw/intc/slavio_intctl.c +++ b/hw/intc/slavio_intctl.c @@ -419,7 +419,7 @@ static void slavio_intctl_init(Object *obj) DeviceState *dev = DEVICE(obj); SLAVIO_INTCTLState *s = SLAVIO_INTCTL(obj); SysBusDevice *sbd = SYS_BUS_DEVICE(obj); - unsigned int i, j; + unsigned int i; char slave_name[45]; qdev_init_gpio_in(dev, slavio_set_irq_all, 32 + MAX_CPUS); @@ -430,9 +430,7 @@ static void slavio_intctl_init(Object *obj) for (i = 0; i < MAX_CPUS; i++) { snprintf(slave_name, sizeof(slave_name), "slave-interrupt-controller-%i", i); - for (j = 0; j < MAX_PILS; j++) { - sysbus_init_irq(sbd, &s->cpu_irqs[i][j]); - } + sysbus_init_irqs(sbd, s->cpu_irqs[i], MAX_PILS); memory_region_init_io(&s->slaves[i].iomem, OBJECT(s), &slavio_intctl_mem_ops, &s->slaves[i], slave_name, INTCTL_SIZE); diff --git a/hw/misc/avr_power.c b/hw/misc/avr_power.c index a5412f2cfe..5c6806ecbc 100644 --- a/hw/misc/avr_power.c +++ b/hw/misc/avr_power.c @@ -83,10 +83,8 @@ static void avr_mask_init(Object *dev) memory_region_init_io(&s->iomem, dev, &avr_mask_ops, s, TYPE_AVR_MASK, 0x01); sysbus_init_mmio(busdev, &s->iomem); + sysbus_init_irqs(busdev, s->irq, 8); - for (int i = 0; i < 8; i++) { - sysbus_init_irq(busdev, &s->irq[i]); - } s->val = 0x00; } diff --git a/hw/misc/macio/gpio.c b/hw/misc/macio/gpio.c index 4deb330471..bfbcf4ed87 100644 --- a/hw/misc/macio/gpio.c +++ b/hw/misc/macio/gpio.c @@ -153,11 +153,8 @@ static void macio_gpio_init(Object *obj) { SysBusDevice *sbd = SYS_BUS_DEVICE(obj); MacIOGPIOState *s = MACIO_GPIO(obj); - int i; - for (i = 0; i < 10; i++) { - sysbus_init_irq(sbd, &s->gpio_extirqs[i]); - } + sysbus_init_irqs(sbd, s->gpio_extirqs, 10); memory_region_init_io(&s->gpiomem, OBJECT(s), &macio_gpio_ops, obj, "gpio", 0x30); diff --git a/hw/misc/stm32f4xx_exti.c b/hw/misc/stm32f4xx_exti.c index 02e7810046..3bfefbf49b 100644 --- a/hw/misc/stm32f4xx_exti.c +++ b/hw/misc/stm32f4xx_exti.c @@ -135,11 +135,8 @@ static const MemoryRegionOps stm32f4xx_exti_ops = { static void stm32f4xx_exti_init(Object *obj) { STM32F4xxExtiState *s = STM32F4XX_EXTI(obj); - int i; - for (i = 0; i < NUM_INTERRUPT_OUT_LINES; i++) { - sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq[i]); - } + sysbus_init_irqs(SYS_BUS_DEVICE(obj), s->irq, NUM_INTERRUPT_OUT_LINES); memory_region_init_io(&s->mmio, obj, &stm32f4xx_exti_ops, s, TYPE_STM32F4XX_EXTI, 0x400); diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index 42ea2411a2..2a2293e0cc 100644 --- a/hw/net/cadence_gem.c +++ b/hw/net/cadence_gem.c @@ -1606,7 +1606,6 @@ static NetClientInfo net_gem_info = { static void gem_realize(DeviceState *dev, Error **errp) { CadenceGEMState *s = CADENCE_GEM(dev); - int i; address_space_init(&s->dma_as, s->dma_mr ? s->dma_mr : get_system_memory(), "dma"); @@ -1626,9 +1625,7 @@ static void gem_realize(DeviceState *dev, Error **errp) return; } - for (i = 0; i < s->num_priority_queues; ++i) { - sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]); - } + sysbus_init_irqs(SYS_BUS_DEVICE(dev), s->irq, s->num_priority_queues); qemu_macaddr_default_if_unset(&s->conf.macaddr); diff --git a/hw/net/mcf_fec.c b/hw/net/mcf_fec.c index 8aa27bd322..34d5ecce5e 100644 --- a/hw/net/mcf_fec.c +++ b/hw/net/mcf_fec.c @@ -651,13 +651,10 @@ static void mcf_fec_instance_init(Object *obj) { SysBusDevice *sbd = SYS_BUS_DEVICE(obj); mcf_fec_state *s = MCF_FEC_NET(obj); - int i; memory_region_init_io(&s->iomem, obj, &mcf_fec_ops, s, "fec", 0x400); sysbus_init_mmio(sbd, &s->iomem); - for (i = 0; i < FEC_NUM_IRQ; i++) { - sysbus_init_irq(sbd, &s->irq[i]); - } + sysbus_init_irqs(sbd, s->irq, FEC_NUM_IRQ); } static Property mcf_fec_properties[] = { diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c index 9e183caa48..b75fd3d5f5 100644 --- a/hw/pci-host/designware.c +++ b/hw/pci-host/designware.c @@ -668,11 +668,8 @@ static void designware_pcie_host_realize(DeviceState *dev, Error **errp) PCIHostState *pci = PCI_HOST_BRIDGE(dev); DesignwarePCIEHost *s = DESIGNWARE_PCIE_HOST(dev); SysBusDevice *sbd = SYS_BUS_DEVICE(dev); - size_t i; - for (i = 0; i < ARRAY_SIZE(s->pci.irqs); i++) { - sysbus_init_irq(sbd, &s->pci.irqs[i]); - } + sysbus_init_irqs(sbd, s->pci.irqs, ARRAY_SIZE(s->pci.irqs)); memory_region_init_io(&s->mmio, OBJECT(s), diff --git a/hw/pci-host/ppce500.c b/hw/pci-host/ppce500.c index 38814247f2..98ee49e4ee 100644 --- a/hw/pci-host/ppce500.c +++ b/hw/pci-host/ppce500.c @@ -446,9 +446,7 @@ static void e500_pcihost_realize(DeviceState *dev, Error **errp) h = PCI_HOST_BRIDGE(dev); s = PPC_E500_PCI_HOST_BRIDGE(dev); - for (i = 0; i < ARRAY_SIZE(s->irq); i++) { - sysbus_init_irq(sbd, &s->irq[i]); - } + sysbus_init_irqs(sbd, s->irq, ARRAY_SIZE(s->irq)); for (i = 0; i < PCI_NUM_PINS; i++) { s->irq_num[i] = s->first_pin_irq + i; diff --git a/hw/pci-host/raven.c b/hw/pci-host/raven.c index 9a11ac4b2b..dd22964c27 100644 --- a/hw/pci-host/raven.c +++ b/hw/pci-host/raven.c @@ -239,9 +239,7 @@ static void raven_pcihost_realizefn(DeviceState *d, Error **errp) int i; if (s->is_legacy_prep) { - for (i = 0; i < PCI_NUM_PINS; i++) { - sysbus_init_irq(dev, &s->pci_irqs[i]); - } + sysbus_init_irqs(dev, s->pci_irqs, PCI_NUM_PINS); } else { /* According to PReP specification section 6.1.6 "System Interrupt * Assignments", all PCI interrupts are routed via IRQ 15 */ diff --git a/hw/pci-host/sh_pci.c b/hw/pci-host/sh_pci.c index 77e7bbc65f..6aade6e5d7 100644 --- a/hw/pci-host/sh_pci.c +++ b/hw/pci-host/sh_pci.c @@ -121,11 +121,8 @@ static void sh_pci_device_realize(DeviceState *dev, Error **errp) SysBusDevice *sbd = SYS_BUS_DEVICE(dev); SHPCIState *s = SH_PCI_HOST_BRIDGE(dev); PCIHostState *phb = PCI_HOST_BRIDGE(s); - int i; - for (i = 0; i < 4; i++) { - sysbus_init_irq(sbd, &s->irq[i]); - } + sysbus_init_irqs(sbd, s->irq, 4); phb->bus = pci_register_root_bus(dev, "pci", sh_pci_set_irq, sh_pci_map_irq, s->irq, diff --git a/hw/pci-host/versatile.c b/hw/pci-host/versatile.c index 60d4e7cd92..3eb9ad6f5c 100644 --- a/hw/pci-host/versatile.c +++ b/hw/pci-host/versatile.c @@ -412,9 +412,7 @@ static void pci_vpb_realize(DeviceState *dev, Error **errp) object_initialize(&s->pci_dev, sizeof(s->pci_dev), TYPE_VERSATILE_PCI_HOST); - for (i = 0; i < 4; i++) { - sysbus_init_irq(sbd, &s->irq[i]); - } + sysbus_init_irqs(sbd, s->irq, 4); if (s->realview) { mapfn = pci_vpb_rv_map_irq; diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index 0cc68178ad..5faa40a9d4 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -265,11 +265,8 @@ static void ppc405_dma_realize(DeviceState *dev, Error **errp) { Ppc405DmaState *dma = PPC405_DMA(dev); Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev); - int i; - for (i = 0; i < ARRAY_SIZE(dma->irqs); i++) { - sysbus_init_irq(SYS_BUS_DEVICE(dma), &dma->irqs[i]); - } + sysbus_init_irqs(SYS_BUS_DEVICE(dma), dma->irqs, ARRAY_SIZE(dma->irqs)); ppc4xx_dcr_register(dcr, DMA0_CR0, dma, &dcr_read_dma, &dcr_write_dma); ppc4xx_dcr_register(dcr, DMA0_CT0, dma, &dcr_read_dma, &dcr_write_dma); @@ -702,15 +699,12 @@ static void ppc405_gpt_realize(DeviceState *dev, Error **errp) { Ppc405GptState *s = PPC405_GPT(dev); SysBusDevice *sbd = SYS_BUS_DEVICE(dev); - int i; s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &ppc4xx_gpt_cb, s); memory_region_init_io(&s->iomem, OBJECT(s), &gpt_ops, s, "gpt", 0xd4); sysbus_init_mmio(sbd, &s->iomem); - for (i = 0; i < ARRAY_SIZE(s->irqs); i++) { - sysbus_init_irq(sbd, &s->irqs[i]); - } + sysbus_init_irqs(sbd, s->irqs, ARRAY_SIZE(s->irqs)); } static void ppc405_gpt_finalize(Object *obj) diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c index 651263926e..89e16766e4 100644 --- a/hw/ppc/ppc440_uc.c +++ b/hw/ppc/ppc440_uc.c @@ -1004,7 +1004,7 @@ static void ppc460ex_pcie_realize(DeviceState *dev, Error **errp) { PPC460EXPCIEState *s = PPC460EX_PCIE_HOST(dev); PCIHostState *pci = PCI_HOST_BRIDGE(dev); - int i, id; + int id; char buf[16]; switch (s->dcrn_base) { @@ -1020,9 +1020,7 @@ static void ppc460ex_pcie_realize(DeviceState *dev, Error **errp) } snprintf(buf, sizeof(buf), "pcie%d-io", id); memory_region_init(&s->iomem, OBJECT(s), buf, UINT64_MAX); - for (i = 0; i < 4; i++) { - sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]); - } + sysbus_init_irqs(SYS_BUS_DEVICE(dev), s->irq, 4); snprintf(buf, sizeof(buf), "pcie.%d", id); pci->bus = pci_register_root_bus(DEVICE(s), buf, ppc460ex_set_irq, pci_swizzle_map_irq_fn, s, &s->iomem, diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c index c1d111465d..f938ac80a4 100644 --- a/hw/ppc/ppc4xx_devs.c +++ b/hw/ppc/ppc4xx_devs.c @@ -193,9 +193,7 @@ static void ppc4xx_mal_realize(DeviceState *dev, Error **errp) mal->rxctpr = g_new0(uint32_t, mal->rxcnum); mal->rcbs = g_new0(uint32_t, mal->rxcnum); - for (i = 0; i < ARRAY_SIZE(mal->irqs); i++) { - sysbus_init_irq(SYS_BUS_DEVICE(dev), &mal->irqs[i]); - } + sysbus_init_irqs(SYS_BUS_DEVICE(dev), mal->irqs, ARRAY_SIZE(mal->irqs)); ppc4xx_dcr_register(dcr, MAL0_CFG, mal, &dcr_read_mal, &dcr_write_mal); ppc4xx_dcr_register(dcr, MAL0_ESR, mal, &dcr_read_mal, &dcr_write_mal); diff --git a/hw/ppc/ppc4xx_pci.c b/hw/ppc/ppc4xx_pci.c index 1d4a50fa7c..55957af77d 100644 --- a/hw/ppc/ppc4xx_pci.c +++ b/hw/ppc/ppc4xx_pci.c @@ -318,14 +318,11 @@ static void ppc4xx_pcihost_realize(DeviceState *dev, Error **errp) PPC4xxPCIState *s; PCIHostState *h; PCIBus *b; - int i; h = PCI_HOST_BRIDGE(dev); s = PPC4xx_PCI_HOST_BRIDGE(dev); - for (i = 0; i < ARRAY_SIZE(s->irq); i++) { - sysbus_init_irq(sbd, &s->irq[i]); - } + sysbus_init_irqs(sbd, s->irq, ARRAY_SIZE(s->irq)); b = pci_register_root_bus(dev, NULL, ppc4xx_pci_set_irq, ppc4xx_pci_map_irq, s->irq, get_system_memory(), diff --git a/hw/ssi/ibex_spi_host.c b/hw/ssi/ibex_spi_host.c index 1ee7d88c22..512b09d13e 100644 --- a/hw/ssi/ibex_spi_host.c +++ b/hw/ssi/ibex_spi_host.c @@ -589,14 +589,11 @@ static void fifo_trigger_update(void *opaque) static void ibex_spi_host_realize(DeviceState *dev, Error **errp) { IbexSPIHostState *s = IBEX_SPI_HOST(dev); - int i; s->ssi = ssi_create_bus(dev, "ssi"); s->cs_lines = g_new0(qemu_irq, s->num_cs); - for (i = 0; i < s->num_cs; ++i) { - sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->cs_lines[i]); - } + sysbus_init_irqs(SYS_BUS_DEVICE(dev), s->cs_lines, s->num_cs); /* Setup CONFIGOPTS Multi-register */ s->config_opts = g_new0(uint32_t, s->num_cs); diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index 189423bb3a..86c130c77b 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -458,7 +458,6 @@ static const struct MemoryRegionOps imx_spi_ops = { static void imx_spi_realize(DeviceState *dev, Error **errp) { IMXSPIState *s = IMX_SPI(dev); - int i; s->bus = ssi_create_bus(dev, "spi"); @@ -467,9 +466,7 @@ static void imx_spi_realize(DeviceState *dev, Error **errp) sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq); - for (i = 0; i < ECSPI_NUM_CS; ++i) { - sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->cs_lines[i]); - } + sysbus_init_irqs(SYS_BUS_DEVICE(dev), s->cs_lines, ECSPI_NUM_CS); fifo32_create(&s->tx_fifo, ECSPI_FIFO_SIZE); fifo32_create(&s->rx_fifo, ECSPI_FIFO_SIZE); diff --git a/hw/ssi/sifive_spi.c b/hw/ssi/sifive_spi.c index 1b4a401ca1..928c7c5035 100644 --- a/hw/ssi/sifive_spi.c +++ b/hw/ssi/sifive_spi.c @@ -310,15 +310,12 @@ static void sifive_spi_realize(DeviceState *dev, Error **errp) { SysBusDevice *sbd = SYS_BUS_DEVICE(dev); SiFiveSPIState *s = SIFIVE_SPI(dev); - int i; s->spi = ssi_create_bus(dev, "spi"); sysbus_init_irq(sbd, &s->irq); s->cs_lines = g_new0(qemu_irq, s->num_cs); - for (i = 0; i < s->num_cs; i++) { - sysbus_init_irq(sbd, &s->cs_lines[i]); - } + sysbus_init_irqs(sbd, s->cs_lines, s->num_cs); memory_region_init_io(&s->mmio, OBJECT(s), &sifive_spi_ops, s, TYPE_SIFIVE_SPI, 0x1000); diff --git a/hw/ssi/xilinx_spi.c b/hw/ssi/xilinx_spi.c index d4de2e7aab..e0ea0bb1cf 100644 --- a/hw/ssi/xilinx_spi.c +++ b/hw/ssi/xilinx_spi.c @@ -327,7 +327,6 @@ static void xilinx_spi_realize(DeviceState *dev, Error **errp) { SysBusDevice *sbd = SYS_BUS_DEVICE(dev); XilinxSPI *s = XILINX_SPI(dev); - int i; DB_PRINT("\n"); @@ -335,9 +334,7 @@ static void xilinx_spi_realize(DeviceState *dev, Error **errp) sysbus_init_irq(sbd, &s->irq); s->cs_lines = g_new0(qemu_irq, s->num_cs); - for (i = 0; i < s->num_cs; ++i) { - sysbus_init_irq(sbd, &s->cs_lines[i]); - } + sysbus_init_irqs(sbd, s->cs_lines, s->num_cs); memory_region_init_io(&s->mmio, OBJECT(s), &spi_ops, s, "xilinx-spi", R_MAX * 4); diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index 97009d3a5d..c696a07916 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -1294,9 +1294,7 @@ static void xilinx_spips_realize(DeviceState *dev, Error **errp) s->cs_lines_state = g_new0(bool, s->num_cs * s->num_busses); sysbus_init_irq(sbd, &s->irq); - for (i = 0; i < s->num_cs * s->num_busses; ++i) { - sysbus_init_irq(sbd, &s->cs_lines[i]); - } + sysbus_init_irqs(sbd, s->cs_lines, s->num_cs * s->num_busses); memory_region_init_io(&s->iomem, OBJECT(s), xsc->reg_ops, s, "spi", XLNX_ZYNQMP_SPIPS_R_MAX * 4); diff --git a/hw/ssi/xlnx-versal-ospi.c b/hw/ssi/xlnx-versal-ospi.c index c762e0b367..b280fbedaf 100644 --- a/hw/ssi/xlnx-versal-ospi.c +++ b/hw/ssi/xlnx-versal-ospi.c @@ -1740,9 +1740,7 @@ static void xlnx_versal_ospi_realize(DeviceState *dev, Error **errp) s->num_cs = 4; s->spi = ssi_create_bus(dev, "spi0"); s->cs_lines = g_new0(qemu_irq, s->num_cs); - for (int i = 0; i < s->num_cs; ++i) { - sysbus_init_irq(sbd, &s->cs_lines[i]); - } + sysbus_init_irqs(sbd, s->cs_lines, s->num_cs); fifo8_create(&s->rx_fifo, RXFF_SZ); fifo8_create(&s->tx_fifo, TXFF_SZ); diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c index 971f78462a..1126d19127 100644 --- a/hw/timer/allwinner-a10-pit.c +++ b/hw/timer/allwinner-a10-pit.c @@ -263,9 +263,7 @@ static void a10_pit_init(Object *obj) SysBusDevice *sbd = SYS_BUS_DEVICE(obj); uint8_t i; - for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) { - sysbus_init_irq(sbd, &s->irq[i]); - } + sysbus_init_irqs(sbd, s->irq, AW_A10_PIT_TIMER_NR); memory_region_init_io(&s->iomem, OBJECT(s), &a10_pit_ops, s, TYPE_AW_A10_PIT, 0x400); sysbus_init_mmio(sbd, &s->iomem); diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c index 446bbd2b96..6a53068a1d 100644 --- a/hw/timer/exynos4210_mct.c +++ b/hw/timer/exynos4210_mct.c @@ -1521,9 +1521,7 @@ static void exynos4210_mct_init(Object *obj) } /* IRQs */ - for (i = 0; i < MCT_GT_CMP_NUM; i++) { - sysbus_init_irq(dev, &s->g_timer.irq[i]); - } + sysbus_init_irqs(dev, s->g_timer.irq, MCT_GT_CMP_NUM); for (i = 0; i < 2; i++) { sysbus_init_irq(dev, &s->l_timer[i].irq); } diff --git a/hw/timer/hpet.c b/hw/timer/hpet.c index 6998094233..95b68f1c90 100644 --- a/hw/timer/hpet.c +++ b/hw/timer/hpet.c @@ -756,9 +756,7 @@ static void hpet_realize(DeviceState *dev, Error **errp) s->hpet_id = hpet_cfg.count++; - for (i = 0; i < HPET_NUM_IRQ_ROUTES; i++) { - sysbus_init_irq(sbd, &s->irqs[i]); - } + sysbus_init_irqs(sbd, s->irqs, HPET_NUM_IRQ_ROUTES); if (s->num_timers < HPET_MIN_TIMERS) { s->num_timers = HPET_MIN_TIMERS; diff --git a/hw/timer/renesas_cmt.c b/hw/timer/renesas_cmt.c index 69eabc678a..3fae6d40d7 100644 --- a/hw/timer/renesas_cmt.c +++ b/hw/timer/renesas_cmt.c @@ -225,15 +225,12 @@ static void rcmt_init(Object *obj) { SysBusDevice *d = SYS_BUS_DEVICE(obj); RCMTState *cmt = RCMT(obj); - int i; memory_region_init_io(&cmt->memory, OBJECT(cmt), &cmt_ops, cmt, "renesas-cmt", 0x10); sysbus_init_mmio(d, &cmt->memory); - for (i = 0; i < ARRAY_SIZE(cmt->cmi); i++) { - sysbus_init_irq(d, &cmt->cmi[i]); - } + sysbus_init_irqs(d, cmt->cmi, ARRAY_SIZE(cmt->cmi)); timer_init_ns(&cmt->timer[0], QEMU_CLOCK_VIRTUAL, timer_event0, cmt); timer_init_ns(&cmt->timer[1], QEMU_CLOCK_VIRTUAL, timer_event1, cmt); } diff --git a/hw/timer/sifive_pwm.c b/hw/timer/sifive_pwm.c index c664480ccf..d5f1273232 100644 --- a/hw/timer/sifive_pwm.c +++ b/hw/timer/sifive_pwm.c @@ -414,11 +414,8 @@ static Property sifive_pwm_properties[] = { static void sifive_pwm_init(Object *obj) { SiFivePwmState *s = SIFIVE_PWM(obj); - int i; - for (i = 0; i < SIFIVE_PWM_IRQS; i++) { - sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irqs[i]); - } + sysbus_init_irqs(SYS_BUS_DEVICE(obj), s->irqs, SIFIVE_PWM_IRQS); memory_region_init_io(&s->mmio, obj, &sifive_pwm_ops, s, TYPE_SIFIVE_PWM, 0x100); From patchwork Wed May 31 22:33:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 687325 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp36870wru; 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Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- hw/intc/loongarch_extioi.c | 3 +-- hw/intc/omap_intc.c | 3 +-- hw/pci-host/gpex.c | 2 +- hw/timer/renesas_tmr.c | 9 +++------ 4 files changed, 6 insertions(+), 11 deletions(-) diff --git a/hw/intc/loongarch_extioi.c b/hw/intc/loongarch_extioi.c index db941de20e..c579636215 100644 --- a/hw/intc/loongarch_extioi.c +++ b/hw/intc/loongarch_extioi.c @@ -275,8 +275,7 @@ static void loongarch_extioi_instance_init(Object *obj) LoongArchExtIOI *s = LOONGARCH_EXTIOI(obj); int cpu, pin; - sysbus_init_irqs(SYS_BUS_DEVICE(dev), s->irq, EXTIOI_IRQS); - + sysbus_init_irqs(dev, s->irq, EXTIOI_IRQS); qdev_init_gpio_in(DEVICE(obj), extioi_setirq, EXTIOI_IRQS); for (cpu = 0; cpu < EXTIOI_CPUS; cpu++) { diff --git a/hw/intc/omap_intc.c b/hw/intc/omap_intc.c index 647bf324a8..f324b640e3 100644 --- a/hw/intc/omap_intc.c +++ b/hw/intc/omap_intc.c @@ -627,8 +627,7 @@ static void omap2_intc_init(Object *obj) s->level_only = 1; s->nbanks = 3; - sysbus_init_irq(sbd, &s->parent_intr[0]); - sysbus_init_irq(sbd, &s->parent_intr[1]); + sysbus_init_irqs(sbd, s->parent_intr, ARRAY_SIZE(s->parent_intr)); qdev_init_gpio_in(dev, omap_set_intr_noedge, s->nbanks * 32); memory_region_init_io(&s->mmio, obj, &omap2_inth_mem_ops, s, "omap2-intc", 0x1000); diff --git a/hw/pci-host/gpex.c b/hw/pci-host/gpex.c index a6752fac5e..7b46e3e36e 100644 --- a/hw/pci-host/gpex.c +++ b/hw/pci-host/gpex.c @@ -128,8 +128,8 @@ static void gpex_host_realize(DeviceState *dev, Error **errp) sysbus_init_mmio(sbd, &s->io_ioport); } + sysbus_init_irqs(sbd, s->irq, GPEX_NUM_IRQS); for (i = 0; i < GPEX_NUM_IRQS; i++) { - sysbus_init_irq(sbd, &s->irq[i]); s->irq_num[i] = -1; } diff --git a/hw/timer/renesas_tmr.c b/hw/timer/renesas_tmr.c index c15f654738..dd2929d6e7 100644 --- a/hw/timer/renesas_tmr.c +++ b/hw/timer/renesas_tmr.c @@ -428,17 +428,14 @@ static void rtmr_init(Object *obj) { SysBusDevice *d = SYS_BUS_DEVICE(obj); RTMRState *tmr = RTMR(obj); - int i; memory_region_init_io(&tmr->memory, OBJECT(tmr), &tmr_ops, tmr, "renesas-tmr", 0x10); sysbus_init_mmio(d, &tmr->memory); - for (i = 0; i < ARRAY_SIZE(tmr->ovi); i++) { - sysbus_init_irq(d, &tmr->cmia[i]); - sysbus_init_irq(d, &tmr->cmib[i]); - sysbus_init_irq(d, &tmr->ovi[i]); - } + sysbus_init_irqs(d, tmr->cmia, ARRAY_SIZE(tmr->cmia)); + sysbus_init_irqs(d, tmr->cmib, ARRAY_SIZE(tmr->cmib)); + sysbus_init_irqs(d, tmr->ovi, ARRAY_SIZE(tmr->ovi)); timer_init_ns(&tmr->timer[0], QEMU_CLOCK_VIRTUAL, timer_event0, tmr); timer_init_ns(&tmr->timer[1], QEMU_CLOCK_VIRTUAL, timer_event1, tmr); }