From patchwork Fri Jun 14 14:32:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [1/6] nvmem: meson-efuse: update with SPDX Licence identifier X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 166822 Message-Id: <20190614143221.32035-2-srinivas.kandagatla@linaro.org> To: gregkh@linuxfoundation.org Cc: linux-kernel@vger.kernel.org Date: Fri, 14 Jun 2019 15:32:16 +0100 From: Srinivas Kandagatla List-Id: From: Neil Armstrong Signed-off-by: Neil Armstrong Signed-off-by: Srinivas Kandagatla --- drivers/nvmem/meson-efuse.c | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-) -- 2.21.0 diff --git a/drivers/nvmem/meson-efuse.c b/drivers/nvmem/meson-efuse.c index 99372768446b..9f928fa9964f 100644 --- a/drivers/nvmem/meson-efuse.c +++ b/drivers/nvmem/meson-efuse.c @@ -1,17 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Amlogic Meson GX eFuse Driver * * Copyright (c) 2016 Endless Computers, Inc. * Author: Carlo Caione - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. */ #include From patchwork Fri Jun 14 14:32:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [2/6] nvmem: meson-mx-efuse: update with SPDX Licence identifier X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 166823 Message-Id: <20190614143221.32035-3-srinivas.kandagatla@linaro.org> To: gregkh@linuxfoundation.org Cc: linux-kernel@vger.kernel.org Date: Fri, 14 Jun 2019 15:32:17 +0100 From: Srinivas Kandagatla List-Id: From: Neil Armstrong Signed-off-by: Neil Armstrong Reviewed-by: Martin Blumenstingl Signed-off-by: Srinivas Kandagatla --- drivers/nvmem/meson-mx-efuse.c | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-) -- 2.21.0 diff --git a/drivers/nvmem/meson-mx-efuse.c b/drivers/nvmem/meson-mx-efuse.c index a085563e39e3..2976aef87c82 100644 --- a/drivers/nvmem/meson-mx-efuse.c +++ b/drivers/nvmem/meson-mx-efuse.c @@ -1,16 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Amlogic Meson6, Meson8 and Meson8b eFuse Driver * * Copyright (c) 2017 Martin Blumenstingl - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. */ #include From patchwork Fri Jun 14 14:32:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [3/6] dt-bindings: fsl: scu: add ocotp binding X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 166826 Message-Id: <20190614143221.32035-4-srinivas.kandagatla@linaro.org> To: gregkh@linuxfoundation.org Cc: linux-kernel@vger.kernel.org Date: Fri, 14 Jun 2019 15:32:18 +0100 From: Srinivas Kandagatla List-Id: From: Peng Fan NXP i.MX8QXP is an ARMv8 SoC with a Cortex-M4 core inside as system controller(SCU), the ocotp controller is being controlled by the SCU, so Linux need use RPC to SCU for ocotp handling. This patch adds binding doc for i.MX8 SCU OCOTP driver. Cc: Mark Rutland Cc: Shawn Guo Cc: Ulf Hansson Cc: Stephen Boyd Cc: Anson Huang Cc: devicetree@vger.kernel.org Reviewed-by: Rob Herring Reviewed-by: Dong Aisheng Signed-off-by: Peng Fan Signed-off-by: Srinivas Kandagatla --- .../bindings/arm/freescale/fsl,scu.txt | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) -- 2.21.0 diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt index 5d7dbabbb784..f378922906f6 100644 --- a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt +++ b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt @@ -133,6 +133,18 @@ RTC bindings based on SCU Message Protocol Required properties: - compatible: should be "fsl,imx8qxp-sc-rtc"; +OCOTP bindings based on SCU Message Protocol +------------------------------------------------------------ +Required properties: +- compatible: Should be "fsl,imx8qxp-scu-ocotp" +- #address-cells: Must be 1. Contains byte index +- #size-cells: Must be 1. Contains byte length + +Optional Child nodes: + +- Data cells of ocotp: + Detailed bindings are described in bindings/nvmem/nvmem.txt + Example (imx8qxp): ------------- aliases { @@ -177,6 +189,16 @@ firmware { ... }; + ocotp: imx8qx-ocotp { + compatible = "fsl,imx8qxp-scu-ocotp"; + #address-cells = <1>; + #size-cells = <1>; + + fec_mac0: mac@2c4 { + reg = <0x2c4 8>; + }; + }; + pd: imx8qx-pd { compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd"; #power-domain-cells = <1>; From patchwork Fri Jun 14 14:32:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [4/6] nvmem: imx: add i.MX8 nvmem driver X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 166825 Message-Id: <20190614143221.32035-5-srinivas.kandagatla@linaro.org> To: gregkh@linuxfoundation.org Cc: linux-kernel@vger.kernel.org Date: Fri, 14 Jun 2019 15:32:19 +0100 From: Srinivas Kandagatla List-Id: From: Peng Fan This patch adds i.MX8 nvmem ocotp driver to access fuse via RPC to i.MX8 system controller. Cc: Srinivas Kandagatla Cc: Shawn Guo Cc: Sascha Hauer Cc: Pengutronix Kernel Team Cc: Fabio Estevam Cc: NXP Linux Team Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Peng Fan Reviewed-by: Dong Aisheng Signed-off-by: Srinivas Kandagatla --- drivers/nvmem/Kconfig | 7 ++ drivers/nvmem/Makefile | 2 + drivers/nvmem/imx-ocotp-scu.c | 161 ++++++++++++++++++++++++++++++++++ 3 files changed, 170 insertions(+) create mode 100644 drivers/nvmem/imx-ocotp-scu.c -- 2.21.0 diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig index 6b2c4254c2fb..82a07c24e1db 100644 --- a/drivers/nvmem/Kconfig +++ b/drivers/nvmem/Kconfig @@ -46,6 +46,13 @@ config NVMEM_IMX_OCOTP This driver can also be built as a module. If so, the module will be called nvmem-imx-ocotp. +config NVMEM_IMX_OCOTP_SCU + tristate "i.MX8 SCU On-Chip OTP Controller support" + depends on IMX_SCU + help + This is a driver for the SCU On-Chip OTP Controller (OCOTP) + available on i.MX8 SoCs. + config NVMEM_LPC18XX_EEPROM tristate "NXP LPC18XX EEPROM Memory Support" depends on ARCH_LPC18XX || COMPILE_TEST diff --git a/drivers/nvmem/Makefile b/drivers/nvmem/Makefile index c1fe4768dfef..e5c153d99a67 100644 --- a/drivers/nvmem/Makefile +++ b/drivers/nvmem/Makefile @@ -16,6 +16,8 @@ obj-$(CONFIG_NVMEM_IMX_IIM) += nvmem-imx-iim.o nvmem-imx-iim-y := imx-iim.o obj-$(CONFIG_NVMEM_IMX_OCOTP) += nvmem-imx-ocotp.o nvmem-imx-ocotp-y := imx-ocotp.o +obj-$(CONFIG_NVMEM_IMX_OCOTP_SCU) += nvmem-imx-ocotp-scu.o +nvmem-imx-ocotp-scu-y := imx-ocotp-scu.o obj-$(CONFIG_NVMEM_LPC18XX_EEPROM) += nvmem_lpc18xx_eeprom.o nvmem_lpc18xx_eeprom-y := lpc18xx_eeprom.o obj-$(CONFIG_NVMEM_LPC18XX_OTP) += nvmem_lpc18xx_otp.o diff --git a/drivers/nvmem/imx-ocotp-scu.c b/drivers/nvmem/imx-ocotp-scu.c new file mode 100644 index 000000000000..d9dc482ecb2f --- /dev/null +++ b/drivers/nvmem/imx-ocotp-scu.c @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * i.MX8 OCOTP fusebox driver + * + * Copyright 2019 NXP + * + * Peng Fan + */ + +#include +#include +#include +#include +#include +#include + +enum ocotp_devtype { + IMX8QXP, +}; + +struct ocotp_devtype_data { + int devtype; + int nregs; +}; + +struct ocotp_priv { + struct device *dev; + const struct ocotp_devtype_data *data; + struct imx_sc_ipc *nvmem_ipc; +}; + +struct imx_sc_msg_misc_fuse_read { + struct imx_sc_rpc_msg hdr; + u32 word; +} __packed; + +static struct ocotp_devtype_data imx8qxp_data = { + .devtype = IMX8QXP, + .nregs = 800, +}; + +static int imx_sc_misc_otp_fuse_read(struct imx_sc_ipc *ipc, u32 word, + u32 *val) +{ + struct imx_sc_msg_misc_fuse_read msg; + struct imx_sc_rpc_msg *hdr = &msg.hdr; + int ret; + + hdr->ver = IMX_SC_RPC_VERSION; + hdr->svc = IMX_SC_RPC_SVC_MISC; + hdr->func = IMX_SC_MISC_FUNC_OTP_FUSE_READ; + hdr->size = 2; + + msg.word = word; + + ret = imx_scu_call_rpc(ipc, &msg, true); + if (ret) + return ret; + + *val = msg.word; + + return 0; +} + +static int imx_scu_ocotp_read(void *context, unsigned int offset, + void *val, size_t bytes) +{ + struct ocotp_priv *priv = context; + u32 count, index, num_bytes; + u32 *buf; + void *p; + int i, ret; + + index = offset >> 2; + num_bytes = round_up((offset % 4) + bytes, 4); + count = num_bytes >> 2; + + if (count > (priv->data->nregs - index)) + count = priv->data->nregs - index; + + p = kzalloc(num_bytes, GFP_KERNEL); + if (!p) + return -ENOMEM; + + buf = p; + + for (i = index; i < (index + count); i++) { + if (priv->data->devtype == IMX8QXP) { + if ((i > 271) && (i < 544)) { + *buf++ = 0; + continue; + } + } + + ret = imx_sc_misc_otp_fuse_read(priv->nvmem_ipc, i, buf); + if (ret) { + kfree(p); + return ret; + } + buf++; + } + + memcpy(val, (u8 *)p + offset % 4, bytes); + + kfree(p); + + return 0; +} + +static struct nvmem_config imx_scu_ocotp_nvmem_config = { + .name = "imx-scu-ocotp", + .read_only = true, + .word_size = 4, + .stride = 1, + .owner = THIS_MODULE, + .reg_read = imx_scu_ocotp_read, +}; + +static const struct of_device_id imx_scu_ocotp_dt_ids[] = { + { .compatible = "fsl,imx8qxp-scu-ocotp", (void *)&imx8qxp_data }, + { }, +}; +MODULE_DEVICE_TABLE(of, imx_scu_ocotp_dt_ids); + +static int imx_scu_ocotp_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct ocotp_priv *priv; + struct nvmem_device *nvmem; + int ret; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + ret = imx_scu_get_handle(&priv->nvmem_ipc); + if (ret) + return ret; + + priv->data = of_device_get_match_data(dev); + priv->dev = dev; + imx_scu_ocotp_nvmem_config.size = 4 * priv->data->nregs; + imx_scu_ocotp_nvmem_config.dev = dev; + imx_scu_ocotp_nvmem_config.priv = priv; + nvmem = devm_nvmem_register(dev, &imx_scu_ocotp_nvmem_config); + + return PTR_ERR_OR_ZERO(nvmem); +} + +static struct platform_driver imx_scu_ocotp_driver = { + .probe = imx_scu_ocotp_probe, + .driver = { + .name = "imx_scu_ocotp", + .of_match_table = imx_scu_ocotp_dt_ids, + }, +}; +module_platform_driver(imx_scu_ocotp_driver); + +MODULE_AUTHOR("Peng Fan "); +MODULE_DESCRIPTION("i.MX8 SCU OCOTP fuse box driver"); +MODULE_LICENSE("GPL v2"); From patchwork Fri Jun 14 14:32:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [5/6] nvmem: Broaden the selection of NVMEM_SNVS_LPGPR X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 166824 Message-Id: <20190614143221.32035-6-srinivas.kandagatla@linaro.org> To: gregkh@linuxfoundation.org Cc: linux-kernel@vger.kernel.org Date: Fri, 14 Jun 2019 15:32:20 +0100 From: Srinivas Kandagatla List-Id: From: Fabio Estevam The SNVS LPGR IP block is also found on other i.MX SoCs that are not covered by the current SOC_IMX6 || SOC_IMX7D logic. One example is the i.MX7ULP. To avoid keep expanding the SoC logic selection, make it broader by using the more generic ARCH_MXC symbol instead. Signed-off-by: Fabio Estevam Signed-off-by: Srinivas Kandagatla --- drivers/nvmem/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.21.0 diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig index 82a07c24e1db..96a8aedf1a9a 100644 --- a/drivers/nvmem/Kconfig +++ b/drivers/nvmem/Kconfig @@ -194,7 +194,7 @@ config MESON_MX_EFUSE config NVMEM_SNVS_LPGPR tristate "Support for Low Power General Purpose Register" - depends on SOC_IMX6 || SOC_IMX7D || COMPILE_TEST + depends on ARCH_MXC || COMPILE_TEST help This is a driver for Low Power General Purpose Register (LPGPR) available on i.MX6 and i.MX7 SoCs in Secure Non-Volatile Storage (SNVS) of this chip. From patchwork Fri Jun 14 14:32:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [6/6] dt-bindings: nvmem: Convert Allwinner SID to a schema X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 166827 Message-Id: <20190614143221.32035-7-srinivas.kandagatla@linaro.org> To: gregkh@linuxfoundation.org Cc: linux-kernel@vger.kernel.org Date: Fri, 14 Jun 2019 15:32:21 +0100 From: Srinivas Kandagatla List-Id: From: Maxime Ripard The Allwinner SoCs have an efuse supported in Linux, with a matching Device Tree binding. Now that we have the DT validation in place, let's convert the device tree bindings for that controller over to a YAML schemas. Signed-off-by: Maxime Ripard Reviewed-by: Rob Herring Signed-off-by: Srinivas Kandagatla --- .../nvmem/allwinner,sun4i-a10-sid.yaml | 51 +++++++++++++++++++ .../bindings/nvmem/allwinner,sunxi-sid.txt | 29 ----------- 2 files changed, 51 insertions(+), 29 deletions(-) create mode 100644 Documentation/devicetree/bindings/nvmem/allwinner,sun4i-a10-sid.yaml delete mode 100644 Documentation/devicetree/bindings/nvmem/allwinner,sunxi-sid.txt -- 2.21.0 diff --git a/Documentation/devicetree/bindings/nvmem/allwinner,sun4i-a10-sid.yaml b/Documentation/devicetree/bindings/nvmem/allwinner,sun4i-a10-sid.yaml new file mode 100644 index 000000000000..c9efd6e2c134 --- /dev/null +++ b/Documentation/devicetree/bindings/nvmem/allwinner,sun4i-a10-sid.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/nvmem/allwinner,sun4i-a10-sid.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 Security ID Device Tree Bindings + +maintainers: + - Chen-Yu Tsai + - Maxime Ripard + +allOf: + - $ref: "nvmem.yaml#" + +properties: + compatible: + enum: + - allwinner,sun4i-a10-sid + - allwinner,sun7i-a20-sid + - allwinner,sun8i-a83t-sid + - allwinner,sun8i-h3-sid + - allwinner,sun50i-a64-sid + - allwinner,sun50i-h5-sid + - allwinner,sun50i-h6-sid + + reg: + maxItems: 1 + +required: + - compatible + - reg + +# FIXME: We should set it, but it would report all the generic +# properties as additional properties. +# additionalProperties: false + +examples: + - | + sid@1c23800 { + compatible = "allwinner,sun4i-a10-sid"; + reg = <0x01c23800 0x10>; + }; + + - | + sid@1c23800 { + compatible = "allwinner,sun7i-a20-sid"; + reg = <0x01c23800 0x200>; + }; + +... diff --git a/Documentation/devicetree/bindings/nvmem/allwinner,sunxi-sid.txt b/Documentation/devicetree/bindings/nvmem/allwinner,sunxi-sid.txt deleted file mode 100644 index cfb18b4ef8f7..000000000000 --- a/Documentation/devicetree/bindings/nvmem/allwinner,sunxi-sid.txt +++ /dev/null @@ -1,29 +0,0 @@ -Allwinner sunxi-sid - -Required properties: -- compatible: Should be one of the following: - "allwinner,sun4i-a10-sid" - "allwinner,sun7i-a20-sid" - "allwinner,sun8i-a83t-sid" - "allwinner,sun8i-h3-sid" - "allwinner,sun50i-a64-sid" - "allwinner,sun50i-h5-sid" - "allwinner,sun50i-h6-sid" - -- reg: Should contain registers location and length - -= Data cells = -Are child nodes of sunxi-sid, bindings of which as described in -bindings/nvmem/nvmem.txt - -Example for sun4i: - sid@1c23800 { - compatible = "allwinner,sun4i-a10-sid"; - reg = <0x01c23800 0x10> - }; - -Example for sun7i: - sid@1c23800 { - compatible = "allwinner,sun7i-a20-sid"; - reg = <0x01c23800 0x200> - };