From patchwork Mon Jun 17 14:33:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 167060 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp2977392ilk; Mon, 17 Jun 2019 08:05:43 -0700 (PDT) X-Google-Smtp-Source: APXvYqyprHJ816KPRpo/qKL3NCUsAmIqwpxbhx5nDK3XPlT1pWDfcMo5PWdfRT4z8uvhxwXR5xwx X-Received: by 2002:a5d:4b12:: with SMTP id v18mr11979317wrq.123.1560783943739; Mon, 17 Jun 2019 08:05:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560783943; cv=none; d=google.com; s=arc-20160816; b=d4Pwvo9JPb6AawaTuScgqwm/q2r5EC+/jhkB/v4s0EvLWdMIQZ9795KPPoTkgrzRfX Z4TuDSTGcxwlWzotZj/WBCMD8GsNMHmfZsdqmsfnPDYQpq6wtUdpb8OB/NIG9BB4lG9Q QpeWtNOPVRBSi6qFau2a76W9IRRxMbq5a4qi1b+ZJZRMk69X6UfIaQZlfu3CHoO/aXZa jCnyMptB9cqRvGnZYEK6II1k6i9v6430gmU7M7ufk+DwL8CGOei/IRKxkkLEOPOBa90O K8AY+8aQHDkUu+GkpzLx4Hdr42xG0CX7mwmJJ6lG4Yre9sKFWTn9WhZ2uUm5z/nZhnX3 EPJw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=s25YCdPicJAtgC6ByMpACHrwGTStXvqFM1wqHAvS9fE=; b=Amn5tgmSPutQeMXmUTdqFzwTr/KGeOxOWR2ZrL8icjVu3oW87QmDHcKR3pqROfcuZK IEwTLnZbZ75fiaP6PPyT3SQxU0iYVoaPYSfCKkbEDpAQSJF6qqFOHAPtN7e/jgPKFaEp slJhGbfngCSkl9CU6jutNPX3PPu0nH6haMxQa7FzdOxNMzTnD8LmUhRusWOu1uBfH7fw HIx4AvSq8NCBXvVYzNuSmdbOwinvJ7SOo2Y1Qoi0SscoCh9/SKP7TXbz1rOSML+XnOIp xGIPqEBIJe2gY0NqepaQjZM7pMuYDLSTvgArFWSxXDA/Nn/Yfubive4v0ovbFwB2XyMA Fodw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=XCTIXWwF; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id a67sm13819985wmh.40.2019.06.17.07.34.14 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 17 Jun 2019 07:34:14 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 17 Jun 2019 15:33:49 +0100 Message-Id: <20190617143412.5734-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190617143412.5734-1-peter.maydell@linaro.org> References: <20190617143412.5734-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 Subject: [Qemu-devel] [PULL 01/24] hw/arm/boot: Don't assume RAM starts at address zero X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In the Arm kernel/initrd loading code, in some places we make the incorrect assumption that info->ram_size can be treated as the address of the end of RAM, as for instance when we calculate the available space for the initrd using "info->ram_size - info->initrd_start". This is wrong, because many Arm boards (including "virt") specify a non-zero info->loader_start to indicate that their RAM area starts at a non-zero physical address. Correct the places which make this incorrect assumption. Signed-off-by: Peter Maydell Reviewed-by: Alex Bennée Tested-by: Mark Rutland Message-id: 20190516144733.32399-2-peter.maydell@linaro.org --- hw/arm/boot.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) -- 2.20.1 diff --git a/hw/arm/boot.c b/hw/arm/boot.c index 0261fdabab0..bb37a9383f3 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -977,6 +977,7 @@ static void arm_setup_direct_kernel_boot(ARMCPU *cpu, int elf_machine; hwaddr entry; static const ARMInsnFixup *primary_loader; + uint64_t ram_end = info->loader_start + info->ram_size; if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { primary_loader = bootloader_aarch64; @@ -1048,8 +1049,7 @@ static void arm_setup_direct_kernel_boot(ARMCPU *cpu, /* 32-bit ARM */ entry = info->loader_start + KERNEL_LOAD_ADDR; kernel_size = load_image_targphys_as(info->kernel_filename, entry, - info->ram_size - KERNEL_LOAD_ADDR, - as); + ram_end - KERNEL_LOAD_ADDR, as); is_linux = 1; } if (kernel_size < 0) { @@ -1063,12 +1063,11 @@ static void arm_setup_direct_kernel_boot(ARMCPU *cpu, if (info->initrd_filename) { initrd_size = load_ramdisk_as(info->initrd_filename, info->initrd_start, - info->ram_size - info->initrd_start, - as); + ram_end - info->initrd_start, as); if (initrd_size < 0) { initrd_size = load_image_targphys_as(info->initrd_filename, info->initrd_start, - info->ram_size - + ram_end - info->initrd_start, as); } From patchwork Mon Jun 17 14:33:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 167041 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp2949018ilk; Mon, 17 Jun 2019 07:39:10 -0700 (PDT) X-Google-Smtp-Source: APXvYqxyO2L5FeccqXMFa2Grt0XkLWk0PkDT9N9Efjs8eg2llDlGDFcADC+n8Js+juNu1CLy/gdd X-Received: by 2002:a05:6402:6d0:: with SMTP id n16mr56878089edy.168.1560782350751; Mon, 17 Jun 2019 07:39:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560782350; cv=none; d=google.com; s=arc-20160816; b=g6E3GKJn5951ovpsvCfqQnvVDYWu/AmwMcfp5dOjOuguavtNSVVlha9l5IztFJHv/o 1tY1rH8t6gWAYEu+2vIhQ8G31n08LSC9QSxA0v/2M4P0g7pYnH+npn9JXRYtgSp3+m0t NdTDkC/nEEoi28Dwgh9KoFUxeio+gyHEdbMjDgJdWG+vnaLgLIA5Wr72e7RitLv/Pq8o 2gwAV1qbBjvNZYKftO+hdwTagLprXLd+zyeiFdaSC+mXqzVeFyqQbq763TNKh2l0gMq5 tGNhic7WKc8b2sDj+k2U2zOiZFdO+Jn+JwlN1IGxZrYgEeHtarfJuiyN1TVJRVL/mgFo tVcw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=Yes+XPIwYzH/0L/luwos/53c0Vr5A+E/3/iRnhnUMhI=; b=cH8pDl1IzEp0j+UVDDXw26f/fievxmxl5Alf6hV5lwGn8KXsYN7shvoNBg7ZhPXi7E CXTWwn72pGUyx9nv4s9jSwT+NdH+9gOWBIaCUZolVVdpTsbC9+0jSmKq3Bo4ZVkRntVG CQnjfzt6GYtZkbmBy0rqkm+cysLy4Yz0L4QPuw+kogW1yhDkb66/9/YnayMGIqbCzfDE rcRRMG08TUpzLbeCGAaYUus5UcG0mEYX0jB70PxJDnLovUtabDPT/iDaquf7lDXJHGy+ P7willqiO/dGpAYqtEp8wHA9Z9giXVFrAHuS+tG+NHGBWK33eO7mTfJLjIOrSE2cNVbH AEuA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Xy1A1GBB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id a67sm13819985wmh.40.2019.06.17.07.34.15 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 17 Jun 2019 07:34:15 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 17 Jun 2019 15:33:50 +0100 Message-Id: <20190617143412.5734-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190617143412.5734-1-peter.maydell@linaro.org> References: <20190617143412.5734-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 Subject: [Qemu-devel] [PULL 02/24] hw/arm/boot: Diagnose layouts that put initrd or DTB off the end of RAM X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We calculate the locations in memory where we want to put the initrd and the DTB based on the size of the kernel, since they come after it. Add some explicit checks that these aren't off the end of RAM entirely. (At the moment the way we calculate the initrd_start means that it can't ever be off the end of RAM, but that will change with the next commit.) Signed-off-by: Peter Maydell Reviewed-by: Alex Bennée Tested-by: Mark Rutland Message-id: 20190516144733.32399-3-peter.maydell@linaro.org --- hw/arm/boot.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) -- 2.20.1 diff --git a/hw/arm/boot.c b/hw/arm/boot.c index bb37a9383f3..5ddba727d45 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -1056,11 +1056,25 @@ static void arm_setup_direct_kernel_boot(ARMCPU *cpu, error_report("could not load kernel '%s'", info->kernel_filename); exit(1); } + + if (kernel_size > info->ram_size) { + error_report("kernel '%s' is too large to fit in RAM " + "(kernel size %d, RAM size %" PRId64 ")", + info->kernel_filename, kernel_size, info->ram_size); + exit(1); + } + info->entry = entry; if (is_linux) { uint32_t fixupcontext[FIXUP_MAX]; if (info->initrd_filename) { + + if (info->initrd_start >= ram_end) { + error_report("not enough space after kernel to load initrd"); + exit(1); + } + initrd_size = load_ramdisk_as(info->initrd_filename, info->initrd_start, ram_end - info->initrd_start, as); @@ -1076,6 +1090,11 @@ static void arm_setup_direct_kernel_boot(ARMCPU *cpu, info->initrd_filename); exit(1); } + if (info->initrd_start + initrd_size > info->ram_size) { + error_report("could not load initrd '%s': " + "too big to fit into RAM after the kernel", + info->initrd_filename); + } } else { initrd_size = 0; } @@ -1111,6 +1130,10 @@ static void arm_setup_direct_kernel_boot(ARMCPU *cpu, /* Place the DTB after the initrd in memory with alignment. */ info->dtb_start = QEMU_ALIGN_UP(info->initrd_start + initrd_size, align); + if (info->dtb_start >= ram_end) { + error_report("Not enough space for DTB after kernel/initrd"); + exit(1); + } fixupcontext[FIXUP_ARGPTR_LO] = info->dtb_start; fixupcontext[FIXUP_ARGPTR_HI] = info->dtb_start >> 32; } else { From patchwork Mon Jun 17 14:33:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 167063 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp2983525ilk; Mon, 17 Jun 2019 08:10:19 -0700 (PDT) X-Google-Smtp-Source: APXvYqxZgywBS1Q1/yhZRJD8CpjdeNn1xH0QzAk9HwU+Ci2MOfkpYjxXLZuHD+H/bBvZXbbRo66h X-Received: by 2002:a50:ba19:: with SMTP id g25mr36179516edc.123.1560784219018; Mon, 17 Jun 2019 08:10:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560784219; cv=none; d=google.com; s=arc-20160816; b=zOdQvXq0Z04JhD94LAxyDyfV/pEzy8ssOjL+qa0pLIcS3K2sRu+SwMMejNXHcSlY13 saXzHEbrfHhg5Zj8jn9DOKCtz6TNbuJ3CfKKFYf3epFxFZkn9wnMXVHdYZP61u9j9qdh deD/dTJuQ39+IzbquCqpitM+F8Slg5CzBZJCw4BQlkdV4zksX9zhS4wy4yDPDhz14z7V jmMbzwl8vx/FIG7TAPLKExjokiTyKO/zp/wLCgBIvbN2AVgKIp+Cs8WdZzcOknqLIHmW s+C5ESRFwqWmPy8HNSC3HnwzBwL6XofPpYh8mfdbBhT/44bkjzccnFKkdpGzZ80XvKCJ wG5w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=OwEVsvj6AmcZtJrR0oDBzLmj1hc9aGGjVH7CWfs5T2E=; b=imOuP/UNk5udvJt15lC/T94+bAJt0qT75cyIc+JYjPAyJriCO4XIhuCBTxtFxB4UKt D/sH1kt/PsAegTmk8uspbM9XeakiVR4UxpQblgB0dkjko0lYiwDwVgRtuwChIhgxmfiN j1q3zRl4Hqa0edKJte1VrKKusSSnmJwxe0YJ7cizmI9U5QbYcAr2819NvJFP4ybWtF6t 5SF/gswcEtw7OTs8yrsRg/VH3lv6gS2j6AV2Hju/2F2SJOkw2ob8SgRTl0sQQCXM8f86 g7AH4sp6lvlAzRiAASzo2FHc+ko5X60bwC7/vohGLFF6QGaFxnO023Sbj43IF7KooeAl Uosg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=wegP1t44; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id a67sm13819985wmh.40.2019.06.17.07.34.17 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 17 Jun 2019 07:34:17 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 17 Jun 2019 15:33:51 +0100 Message-Id: <20190617143412.5734-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190617143412.5734-1-peter.maydell@linaro.org> References: <20190617143412.5734-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 Subject: [Qemu-devel] [PULL 03/24] hw/arm/boot: Avoid placing the initrd on top of the kernel X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We currently put the initrd at the smaller of: * 128MB into RAM * halfway into the RAM (with the dtb following it). However for large kernels this might mean that the kernel overlaps the initrd. For some kinds of kernel (self-decompressing 32-bit kernels, and ELF images with a BSS section at the end) we don't know the exact size, but even there we have a minimum size. Put the initrd at least further into RAM than that. For image formats that can give us an exact kernel size, this will mean that we definitely avoid overlaying kernel and initrd. Signed-off-by: Peter Maydell Reviewed-by: Alex Bennée Tested-by: Mark Rutland Message-id: 20190516144733.32399-4-peter.maydell@linaro.org --- hw/arm/boot.c | 34 ++++++++++++++++++++-------------- 1 file changed, 20 insertions(+), 14 deletions(-) -- 2.20.1 diff --git a/hw/arm/boot.c b/hw/arm/boot.c index 5ddba727d45..a0e1110719e 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -1000,20 +1000,6 @@ static void arm_setup_direct_kernel_boot(ARMCPU *cpu, if (info->nb_cpus == 0) info->nb_cpus = 1; - /* - * We want to put the initrd far enough into RAM that when the - * kernel is uncompressed it will not clobber the initrd. However - * on boards without much RAM we must ensure that we still leave - * enough room for a decent sized initrd, and on boards with large - * amounts of RAM we must avoid the initrd being so far up in RAM - * that it is outside lowmem and inaccessible to the kernel. - * So for boards with less than 256MB of RAM we put the initrd - * halfway into RAM, and for boards with 256MB of RAM or more we put - * the initrd at 128MB. - */ - info->initrd_start = info->loader_start + - MIN(info->ram_size / 2, 128 * 1024 * 1024); - /* Assume that raw images are linux kernels, and ELF images are not. */ kernel_size = arm_load_elf(info, &elf_entry, &elf_low_addr, &elf_high_addr, elf_machine, as); @@ -1065,6 +1051,26 @@ static void arm_setup_direct_kernel_boot(ARMCPU *cpu, } info->entry = entry; + + /* + * We want to put the initrd far enough into RAM that when the + * kernel is uncompressed it will not clobber the initrd. However + * on boards without much RAM we must ensure that we still leave + * enough room for a decent sized initrd, and on boards with large + * amounts of RAM we must avoid the initrd being so far up in RAM + * that it is outside lowmem and inaccessible to the kernel. + * So for boards with less than 256MB of RAM we put the initrd + * halfway into RAM, and for boards with 256MB of RAM or more we put + * the initrd at 128MB. + * We also refuse to put the initrd somewhere that will definitely + * overlay the kernel we just loaded, though for kernel formats which + * don't tell us their exact size (eg self-decompressing 32-bit kernels) + * we might still make a bad choice here. + */ + info->initrd_start = info->loader_start + + MAX(MIN(info->ram_size / 2, 128 * 1024 * 1024), kernel_size); + info->initrd_start = TARGET_PAGE_ALIGN(info->initrd_start); + if (is_linux) { uint32_t fixupcontext[FIXUP_MAX]; From patchwork Mon Jun 17 14:33:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 167045 Delivered-To: patch@linaro.org Received: by 2002:ac9:6410:0:0:0:0:0 with SMTP id r16csp1094938ock; Mon, 17 Jun 2019 07:48:21 -0700 (PDT) X-Google-Smtp-Source: APXvYqxNVo4mWeyJtHQU4xF0QlQ5IAnD8qsd6KyTr4k6sVGyx1WTkBokPa//UvQfmXodnwMsNftC X-Received: by 2002:a17:906:401a:: with SMTP id v26mr79068480ejj.62.1560782901307; Mon, 17 Jun 2019 07:48:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560782901; cv=none; d=google.com; s=arc-20160816; b=YQKfhowPJb6/JIx2/Q8HTmBqZeijGR8yjIfhAhDJQMjuJZEZU/wia/9oOSLLCOcXJU FcaY+TJfLO4Kj93d6rUezUldVBygvxjxtkTGiVfdIB8Lg0ADElIgkQcmpMXFXYhoi/Ss 4xxDS8KubxUMVxtwKoJiLRQQzPQcBuCe/sR4PeiI9oke4csDmUvsO1CLJ5Qj/pPR7vru hvUY5eZhcwEpFG9OA1NF/SWV6P9W44wUi3YMFjGvtKmiiRxfCdDEPPwoCrtf398PY4CN RbFmcmC8rCisR0FZCHivPgCNw/TlJzkq7MgDyOGD3Od7GEPaE6+PzCn/rZDnR+slboPn DslQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=DxzFr+PxhxGUlwpP3ZW+DROYq2bJOJKyGjaM0kFUnOU=; b=sMVyQQm/mMh1O2gMn9nU9kFRXpxihtHCQecWikSqzcvYI+hsNyrp7OKSu409TKJGNC IddyOP2ywiFFuyD9aonWDIWELcSW7PlufHyC0FsPNSbf2bE4XI8ykRhAvAGDjuXK8ZeW ONjGlcPXHntXBk4EqEtudoeQk2GFD8Bd4MdrTKkvAa/tlQT1pXYs3ARBZ9LHN5gw6J3N uqemHUpEAXU7zdXJU9YlZd2m+quoGUb33Ax08iVqbjfToJa4sXhEwrIxY1vscV2DH7Bd NSWNhZ46SUxMi6+ARz5XpjMo+1kXHlhBRhbbUgXHzQBihBnoW18gRWXLho+orjFzq3E7 UNSg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=aqmm+rB2; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id a67sm13819985wmh.40.2019.06.17.07.34.18 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 17 Jun 2019 07:34:18 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 17 Jun 2019 15:33:52 +0100 Message-Id: <20190617143412.5734-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190617143412.5734-1-peter.maydell@linaro.org> References: <20190617143412.5734-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 Subject: [Qemu-devel] [PULL 04/24] hw/arm/boot: Honour image size field in AArch64 Image format kernels X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Since Linux v3.17, the kernel's Image header includes a field image_size, which gives the total size of the kernel including unpopulated data sections such as the BSS). If this is present, then return it from load_aarch64_image() as the true size of the kernel rather than just using the size of the Image file itself. This allows the code which calculates where to put the initrd to avoid putting it in the kernel's BSS area. This means that we should be able to reliably load kernel images which are larger than 128MB without accidentally putting the initrd or dtb in locations that clash with the kernel itself. Fixes: https://bugs.launchpad.net/qemu/+bug/1823998 Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Alex Bennée Tested-by: Mark Rutland Message-id: 20190516144733.32399-5-peter.maydell@linaro.org --- hw/arm/boot.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) -- 2.20.1 diff --git a/hw/arm/boot.c b/hw/arm/boot.c index a0e1110719e..b2f93f6beff 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -911,6 +911,7 @@ static uint64_t load_aarch64_image(const char *filename, hwaddr mem_base, hwaddr *entry, AddressSpace *as) { hwaddr kernel_load_offset = KERNEL64_LOAD_ADDR; + uint64_t kernel_size = 0; uint8_t *buffer; int size; @@ -938,7 +939,10 @@ static uint64_t load_aarch64_image(const char *filename, hwaddr mem_base, * is only valid if the image_size is non-zero. */ memcpy(&hdrvals, buffer + ARM64_TEXT_OFFSET_OFFSET, sizeof(hdrvals)); - if (hdrvals[1] != 0) { + + kernel_size = le64_to_cpu(hdrvals[1]); + + if (kernel_size != 0) { kernel_load_offset = le64_to_cpu(hdrvals[0]); /* @@ -956,12 +960,21 @@ static uint64_t load_aarch64_image(const char *filename, hwaddr mem_base, } } + /* + * Kernels before v3.17 don't populate the image_size field, and + * raw images have no header. For those our best guess at the size + * is the size of the Image file itself. + */ + if (kernel_size == 0) { + kernel_size = size; + } + *entry = mem_base + kernel_load_offset; rom_add_blob_fixed_as(filename, buffer, size, *entry, as); g_free(buffer); - return size; + return kernel_size; } static void arm_setup_direct_kernel_boot(ARMCPU *cpu, From patchwork Mon Jun 17 14:33:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 167046 Delivered-To: patch@linaro.org Received: by 2002:ac9:6410:0:0:0:0:0 with SMTP id r16csp1096282ock; Mon, 17 Jun 2019 07:49:40 -0700 (PDT) X-Google-Smtp-Source: APXvYqxnJHRC8/D04nyfCwXgsBLDdgwJXhNEAeK8ngRiXoM34BeDCR0G+BIHXp5rxHnIsriBpWUN X-Received: by 2002:a17:906:3948:: with SMTP id g8mr64370939eje.168.1560782980836; Mon, 17 Jun 2019 07:49:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560782980; cv=none; d=google.com; s=arc-20160816; b=JuAMmsXtdGYEDZ4w0F37E+69CeBPXGbgJVKVI2v6K0helfkBxqWsnepV+Md904JMuM s9hyhm+xoGJ8q8xAjw7J/pXCsQ5frumtGyGa7gbyZd06Pq9043rKxSJmT/kJBSIMueD+ 480qa16YOWOchbDNbrNExIjvB4xmMy3MqVoOX30jGhWlk+GVfq/kfq1Y235n/vvOLzA7 mkcj5r93l4P/IVTtyYkLXVZ7O9AYA2XrQuZcIUQ0dq8n+yTHszC6zvuXo1GphvvhpAmH +vVSnTx5PT8PjEw0g3L7tQ00Y2kovxQ5g67mTTYKuluM/hJtkjiqps3x1OEbq0Rhd6GH wyZA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=5kyplZ9y5jGQlctb0ystayBsPFLBex7wmEn4fkno4/4=; b=Kn3yeZQ9013BzZWlUjGTFnObmuYzg5E+WkPmkA9yO/89b/O64w+IpBfthIWbYr0D9G 6Yk+jSZeqHKA1aKTSRRtv/fSElj3anccozxPwIbQRx1biPwvbrO/USnOw01eMWMbHWGW R/Sr59OJrKob7iZuV7dbkk26eddY8JdpGKXlgnOpBosShHCXDzq1bc6hpOvClPkkm4Wu +NcIEmsOaLq0U3ackZ/GHUihz1TnPY6nEwuRAhPT+2UGdNDFt+BALpqfIAPGZSG4qQYX 5of6YeUR6LmvRgORwiYoOxdb94iwyaKrQgVQtRsFJPzmFRYtzkc5Tfus3y5Pec70NilE 1OVQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=x5aGOuOp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id a67sm13819985wmh.40.2019.06.17.07.34.19 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 17 Jun 2019 07:34:19 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 17 Jun 2019 15:33:53 +0100 Message-Id: <20190617143412.5734-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190617143412.5734-1-peter.maydell@linaro.org> References: <20190617143412.5734-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::429 Subject: [Qemu-devel] [PULL 05/24] target/arm: Allow VFP and Neon to be disabled via a CPU property X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Allow VFP and neon to be disabled via a CPU property. As with the "pmu" property, we only allow these features to be removed from CPUs which have it by default, not added to CPUs which don't have it. The primary motivation here is to be able to optionally create Cortex-M33 CPUs with no FPU, but we provide switches for both VFP and Neon because the two interact: * AArch64 can't have one without the other * Some ID register fields only change if both are disabled Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée Message-id: 20190517174046.11146-2-peter.maydell@linaro.org --- target/arm/cpu.h | 4 ++ target/arm/cpu.c | 150 +++++++++++++++++++++++++++++++++++++++++++++-- 2 files changed, 148 insertions(+), 6 deletions(-) -- 2.20.1 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 92298624215..cf2496aeeec 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -786,6 +786,10 @@ struct ARMCPU { bool has_el3; /* CPU has PMU (Performance Monitor Unit) */ bool has_pmu; + /* CPU has VFP */ + bool has_vfp; + /* CPU has Neon */ + bool has_neon; /* CPU has memory protection unit */ bool has_mpu; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 2335659a852..af879d5311e 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -763,6 +763,12 @@ static Property arm_cpu_cfgend_property = static Property arm_cpu_has_pmu_property = DEFINE_PROP_BOOL("pmu", ARMCPU, has_pmu, true); +static Property arm_cpu_has_vfp_property = + DEFINE_PROP_BOOL("vfp", ARMCPU, has_vfp, true); + +static Property arm_cpu_has_neon_property = + DEFINE_PROP_BOOL("neon", ARMCPU, has_neon, true); + static Property arm_cpu_has_mpu_property = DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); @@ -803,6 +809,13 @@ void arm_cpu_post_init(Object *obj) if (arm_feature(&cpu->env, ARM_FEATURE_M)) { set_feature(&cpu->env, ARM_FEATURE_PMSA); } + /* Similarly for the VFP feature bits */ + if (arm_feature(&cpu->env, ARM_FEATURE_VFP4)) { + set_feature(&cpu->env, ARM_FEATURE_VFP3); + } + if (arm_feature(&cpu->env, ARM_FEATURE_VFP3)) { + set_feature(&cpu->env, ARM_FEATURE_VFP); + } if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { @@ -847,6 +860,27 @@ void arm_cpu_post_init(Object *obj) &error_abort); } + /* + * Allow user to turn off VFP and Neon support, but only for TCG -- + * KVM does not currently allow us to lie to the guest about its + * ID/feature registers, so the guest always sees what the host has. + */ + if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + cpu->has_vfp = true; + if (!kvm_enabled()) { + qdev_property_add_static(DEVICE(obj), &arm_cpu_has_vfp_property, + &error_abort); + } + } + + if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) { + cpu->has_neon = true; + if (!kvm_enabled()) { + qdev_property_add_static(DEVICE(obj), &arm_cpu_has_neon_property, + &error_abort); + } + } + if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property, &error_abort); @@ -956,6 +990,116 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) return; } + if (arm_feature(env, ARM_FEATURE_AARCH64) && + cpu->has_vfp != cpu->has_neon) { + /* + * This is an architectural requirement for AArch64; AArch32 is + * more flexible and permits VFP-no-Neon and Neon-no-VFP. + */ + error_setg(errp, + "AArch64 CPUs must have both VFP and Neon or neither"); + return; + } + + if (!cpu->has_vfp) { + uint64_t t; + uint32_t u; + + unset_feature(env, ARM_FEATURE_VFP); + unset_feature(env, ARM_FEATURE_VFP3); + unset_feature(env, ARM_FEATURE_VFP4); + + t = cpu->isar.id_aa64isar1; + t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 0); + cpu->isar.id_aa64isar1 = t; + + t = cpu->isar.id_aa64pfr0; + t = FIELD_DP64(t, ID_AA64PFR0, FP, 0xf); + cpu->isar.id_aa64pfr0 = t; + + u = cpu->isar.id_isar6; + u = FIELD_DP32(u, ID_ISAR6, JSCVT, 0); + cpu->isar.id_isar6 = u; + + u = cpu->isar.mvfr0; + u = FIELD_DP32(u, MVFR0, FPSP, 0); + u = FIELD_DP32(u, MVFR0, FPDP, 0); + u = FIELD_DP32(u, MVFR0, FPTRAP, 0); + u = FIELD_DP32(u, MVFR0, FPDIVIDE, 0); + u = FIELD_DP32(u, MVFR0, FPSQRT, 0); + u = FIELD_DP32(u, MVFR0, FPSHVEC, 0); + u = FIELD_DP32(u, MVFR0, FPROUND, 0); + cpu->isar.mvfr0 = u; + + u = cpu->isar.mvfr1; + u = FIELD_DP32(u, MVFR1, FPFTZ, 0); + u = FIELD_DP32(u, MVFR1, FPDNAN, 0); + u = FIELD_DP32(u, MVFR1, FPHP, 0); + cpu->isar.mvfr1 = u; + + u = cpu->isar.mvfr2; + u = FIELD_DP32(u, MVFR2, FPMISC, 0); + cpu->isar.mvfr2 = u; + } + + if (!cpu->has_neon) { + uint64_t t; + uint32_t u; + + unset_feature(env, ARM_FEATURE_NEON); + + t = cpu->isar.id_aa64isar0; + t = FIELD_DP64(t, ID_AA64ISAR0, DP, 0); + cpu->isar.id_aa64isar0 = t; + + t = cpu->isar.id_aa64isar1; + t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 0); + cpu->isar.id_aa64isar1 = t; + + t = cpu->isar.id_aa64pfr0; + t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 0xf); + cpu->isar.id_aa64pfr0 = t; + + u = cpu->isar.id_isar5; + u = FIELD_DP32(u, ID_ISAR5, RDM, 0); + u = FIELD_DP32(u, ID_ISAR5, VCMA, 0); + cpu->isar.id_isar5 = u; + + u = cpu->isar.id_isar6; + u = FIELD_DP32(u, ID_ISAR6, DP, 0); + u = FIELD_DP32(u, ID_ISAR6, FHM, 0); + cpu->isar.id_isar6 = u; + + u = cpu->isar.mvfr1; + u = FIELD_DP32(u, MVFR1, SIMDLS, 0); + u = FIELD_DP32(u, MVFR1, SIMDINT, 0); + u = FIELD_DP32(u, MVFR1, SIMDSP, 0); + u = FIELD_DP32(u, MVFR1, SIMDHP, 0); + u = FIELD_DP32(u, MVFR1, SIMDFMAC, 0); + cpu->isar.mvfr1 = u; + + u = cpu->isar.mvfr2; + u = FIELD_DP32(u, MVFR2, SIMDMISC, 0); + cpu->isar.mvfr2 = u; + } + + if (!cpu->has_neon && !cpu->has_vfp) { + uint64_t t; + uint32_t u; + + t = cpu->isar.id_aa64isar0; + t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 0); + cpu->isar.id_aa64isar0 = t; + + t = cpu->isar.id_aa64isar1; + t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 0); + cpu->isar.id_aa64isar1 = t; + + u = cpu->isar.mvfr0; + u = FIELD_DP32(u, MVFR0, SIMDREG, 0); + cpu->isar.mvfr0 = u; + } + /* Some features automatically imply others: */ if (arm_feature(env, ARM_FEATURE_V8)) { if (arm_feature(env, ARM_FEATURE_M)) { @@ -1016,12 +1160,6 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) if (arm_feature(env, ARM_FEATURE_V5)) { set_feature(env, ARM_FEATURE_V4T); } - if (arm_feature(env, ARM_FEATURE_VFP4)) { - set_feature(env, ARM_FEATURE_VFP3); - } - if (arm_feature(env, ARM_FEATURE_VFP3)) { - set_feature(env, ARM_FEATURE_VFP); - } if (arm_feature(env, ARM_FEATURE_LPAE)) { set_feature(env, ARM_FEATURE_V7MP); set_feature(env, ARM_FEATURE_PXN); From patchwork Mon Jun 17 14:33:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 167044 Delivered-To: patch@linaro.org Received: by 2002:ac9:6410:0:0:0:0:0 with SMTP id r16csp1091396ock; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id a67sm13819985wmh.40.2019.06.17.07.34.20 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 17 Jun 2019 07:34:20 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 17 Jun 2019 15:33:54 +0100 Message-Id: <20190617143412.5734-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190617143412.5734-1-peter.maydell@linaro.org> References: <20190617143412.5734-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42f Subject: [Qemu-devel] [PULL 06/24] target/arm: Allow M-profile CPUs to disable the DSP extension via CPU property X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Allow the DSP extension to be disabled via a CPU property for M-profile CPUs. (A and R-profile CPUs don't have this extension as a defined separate optional architecture extension, so they don't need the property.) Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée Message-id: 20190517174046.11146-3-peter.maydell@linaro.org --- target/arm/cpu.h | 2 ++ target/arm/cpu.c | 29 +++++++++++++++++++++++++++++ 2 files changed, 31 insertions(+) -- 2.20.1 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index cf2496aeeec..a98c45b1ff0 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -790,6 +790,8 @@ struct ARMCPU { bool has_vfp; /* CPU has Neon */ bool has_neon; + /* CPU has M-profile DSP extension */ + bool has_dsp; /* CPU has memory protection unit */ bool has_mpu; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index af879d5311e..376db154f00 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -769,6 +769,9 @@ static Property arm_cpu_has_vfp_property = static Property arm_cpu_has_neon_property = DEFINE_PROP_BOOL("neon", ARMCPU, has_neon, true); +static Property arm_cpu_has_dsp_property = + DEFINE_PROP_BOOL("dsp", ARMCPU, has_dsp, true); + static Property arm_cpu_has_mpu_property = DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); @@ -881,6 +884,12 @@ void arm_cpu_post_init(Object *obj) } } + if (arm_feature(&cpu->env, ARM_FEATURE_M) && + arm_feature(&cpu->env, ARM_FEATURE_THUMB_DSP)) { + qdev_property_add_static(DEVICE(obj), &arm_cpu_has_dsp_property, + &error_abort); + } + if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property, &error_abort); @@ -1100,6 +1109,26 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) cpu->isar.mvfr0 = u; } + if (arm_feature(env, ARM_FEATURE_M) && !cpu->has_dsp) { + uint32_t u; + + unset_feature(env, ARM_FEATURE_THUMB_DSP); + + u = cpu->isar.id_isar1; + u = FIELD_DP32(u, ID_ISAR1, EXTEND, 1); + cpu->isar.id_isar1 = u; + + u = cpu->isar.id_isar2; + u = FIELD_DP32(u, ID_ISAR2, MULTU, 1); + u = FIELD_DP32(u, ID_ISAR2, MULTS, 1); + cpu->isar.id_isar2 = u; + + u = cpu->isar.id_isar3; + u = FIELD_DP32(u, ID_ISAR3, SIMD, 1); + u = FIELD_DP32(u, ID_ISAR3, SATURATE, 0); + cpu->isar.id_isar3 = u; + } + /* Some features automatically imply others: */ if (arm_feature(env, ARM_FEATURE_V8)) { if (arm_feature(env, ARM_FEATURE_M)) { From patchwork Mon Jun 17 14:33:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 167054 Delivered-To: patch@linaro.org Received: by 2002:ac9:6410:0:0:0:0:0 with SMTP id r16csp1102825ock; Mon, 17 Jun 2019 07:56:56 -0700 (PDT) X-Google-Smtp-Source: APXvYqwfoS56O3plrx0IlHw2TS+4R6/trdB3RFESDBcl0j/xPuhREA+9eW1TFwmt977rvUDbEvZN X-Received: by 2002:a17:906:670f:: with SMTP id a15mr3535513ejp.36.1560783416519; Mon, 17 Jun 2019 07:56:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560783416; cv=none; d=google.com; s=arc-20160816; b=cXqJo16ikv8oWUheOp+747YC+L7jvofbKafWNQM6/oH5wRCiO/t0pSjEuRcDXZgsrz m4T/XDjklLAkJOAawNx2JaMN0749RSVd+1PRObU6z1F5mh3i/wAu3cHkZt1b3svYLZGw 3DaQmLBa8nFYhMaiJxaOPAUZjbF7NxLhteWagVFn8rsQblP4KEypyHzp7d623YDMqjDZ cMSrXxHGKuMHM3ZZYOMP0hcdR5vbYLvGYuGhdlLQGjrdVMJVwNXoa/NYIFTbnQ7TQL1+ NYzEonq50f+M8osuCBTCfx3sDR12a/kDzsSOKmXgsNNJCorED5xeV9eQTfP7hrnu7QFP nGPA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=IZG7m84aDia5PcoPZiLWtdWTRHky1075PYQvx1TM/Ro=; b=KxOvKu9sjq6ItTqg8qP8vYO63OOLHXVmzW/BjvdY85VBSSLPuctjbp3b0ZecgbnWwI kn06K5EJJWbz1tPrleCwA1L7Byc+M/nMpQ7lyQWVMm1B9zYjy5/iSVx5/YXsfg1CGfZb TppWp1dzFwRq8y1FNXcKzLW9hxXCNOpEhJJCBs2hg0aK62YLpnWUM0TXHaeln7VvCz/Z XZoRV02kWcES0BKWPUSGkFYlv5vOQJoPmQQ5BtDUixRWbHKsaquaH/VQUolfn6G09b7e kvVJdVSPaEq+v1bxEYs8xY+l+r1ymHBu0QcZwKqQIqcqKoJbdmGjaFHVUrjJefuFVoYS JvZw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=bx0jjlzY; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id a67sm13819985wmh.40.2019.06.17.07.34.21 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 17 Jun 2019 07:34:21 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 17 Jun 2019 15:33:55 +0100 Message-Id: <20190617143412.5734-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190617143412.5734-1-peter.maydell@linaro.org> References: <20190617143412.5734-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42a Subject: [Qemu-devel] [PULL 07/24] hw/arm/armv7m: Forward "vfp" and "dsp" properties to CPU X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Create "vfp" and "dsp" properties on the armv7m container object which will be forwarded to its CPU object, so that SoCs can configure whether the CPU has these features. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée Message-id: 20190517174046.11146-4-peter.maydell@linaro.org --- include/hw/arm/armv7m.h | 4 ++++ hw/arm/armv7m.c | 18 ++++++++++++++++++ 2 files changed, 22 insertions(+) -- 2.20.1 diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h index e96a98f8093..d2c74d3872a 100644 --- a/include/hw/arm/armv7m.h +++ b/include/hw/arm/armv7m.h @@ -43,6 +43,8 @@ typedef struct { * devices will be automatically layered on top of this view.) * + Property "idau": IDAU interface (forwarded to CPU object) * + Property "init-svtor": secure VTOR reset value (forwarded to CPU object) + * + Property "vfp": enable VFP (forwarded to CPU object) + * + Property "dsp": enable DSP (forwarded to CPU object) * + Property "enable-bitband": expose bitbanded IO */ typedef struct ARMv7MState { @@ -66,6 +68,8 @@ typedef struct ARMv7MState { uint32_t init_svtor; bool enable_bitband; bool start_powered_off; + bool vfp; + bool dsp; } ARMv7MState; #endif diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index 1a8a6c8bf92..b9efad6bac9 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -190,6 +190,22 @@ static void armv7m_realize(DeviceState *dev, Error **errp) return; } } + if (object_property_find(OBJECT(s->cpu), "vfp", NULL)) { + object_property_set_bool(OBJECT(s->cpu), s->vfp, + "vfp", &err); + if (err != NULL) { + error_propagate(errp, err); + return; + } + } + if (object_property_find(OBJECT(s->cpu), "dsp", NULL)) { + object_property_set_bool(OBJECT(s->cpu), s->dsp, + "dsp", &err); + if (err != NULL) { + error_propagate(errp, err); + return; + } + } /* * Tell the CPU where the NVIC is; it will fail realize if it doesn't @@ -260,6 +276,8 @@ static Property armv7m_properties[] = { DEFINE_PROP_BOOL("enable-bitband", ARMv7MState, enable_bitband, false), DEFINE_PROP_BOOL("start-powered-off", ARMv7MState, start_powered_off, false), + DEFINE_PROP_BOOL("vfp", ARMv7MState, vfp, true), + DEFINE_PROP_BOOL("dsp", ARMv7MState, dsp, true), DEFINE_PROP_END_OF_LIST(), }; From patchwork Mon Jun 17 14:33:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 167042 Delivered-To: patch@linaro.org Received: by 2002:ac9:6410:0:0:0:0:0 with SMTP id r16csp1089834ock; Mon, 17 Jun 2019 07:42:59 -0700 (PDT) X-Google-Smtp-Source: APXvYqw05bsGcRiISbw3KkUcZCfgaYJXS2+qyigRrOS6bteUZL0Ip5f9mVRX0/WlgRjtpMSi2bdH X-Received: by 2002:a17:906:76c8:: with SMTP id q8mr92168818ejn.229.1560782579616; Mon, 17 Jun 2019 07:42:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560782579; cv=none; d=google.com; s=arc-20160816; b=nbwjNZeSkUpVpfzCSG+X+BugzYuuxwD5tnj0EyJ5sWxwmipDAfWBqQWrMvAfpKipQC gQXqBO5jiBXxMMxTDnF7N37JpAz0L4M8YLZ5sw694ZKXcVgnK2kEnSD+vBfYnECOw1E9 koPpAb/uoqQagQziM2Dul0FxpoaTT/9jv1h+T7IP+q1uKyY3h2TB25evEQhOSiDeIuxO XTd3QsO2OPaoMpJT8/QXVjsgAuY1SwwqdFO2ByTOvT9o9nOHfweon76cGOlVEP3Qs5LX Wz3AoMd98+c+//HPm9UQzf16kosHsfldUjBPSn0XzxZ7AHi1btSnHQJwDfplDlNm4D0u KraA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=4WOGglriexE6CQruKaZRN4iBHD/0/F+uA+DSiVuMmqg=; b=rK2vX8icCEjGlHGGnm8a1244WQRKKR+P8FO2Q88et4fyqPIGFe8g3Y8Y57iguc4okv 1lP8bLBzLI+vt1OMGYyKzntGc9/prWIxbR2RPmv4vBbV6pb9mth7rvLEAKn32DVahpoI LhZZpG6aki/mBtfMqqkiaYTX4oNUgUwbXdYTXI1A13JL7ArW1lLs+u8O1YGcSxgijOVq CQRPbhuGUaZxz+yZoN+o6JYrunmmQnajKSsvzNkdsoF3p7X8KSQoO7kdMcspenucIlCm iWLZKo3mwhqlykOUbEIncM4J38vy05v4KEHUEa0q4OQPUw0vodF1P98F0xEh/F60zukF rtVw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=JM4xLuSP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id a67sm13819985wmh.40.2019.06.17.07.34.22 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 17 Jun 2019 07:34:22 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 17 Jun 2019 15:33:56 +0100 Message-Id: <20190617143412.5734-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190617143412.5734-1-peter.maydell@linaro.org> References: <20190617143412.5734-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 Subject: [Qemu-devel] [PULL 08/24] hw/arm: Correctly disable FPU/DSP for some ARMSSE-based boards X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The SSE-200 hardware has configurable integration settings which determine whether its two CPUs have the FPU and DSP: * CPU0_FPU (default 0) * CPU0_DSP (default 0) * CPU1_FPU (default 1) * CPU1_DSP (default 1) Similarly, the IoTKit has settings for its single CPU: * CPU0_FPU (default 1) * CPU0_DSP (default 1) Of our four boards that use either the IoTKit or the SSE-200: * mps2-an505, mps2-an521 and musca-a use the default settings * musca-b1 enables FPU and DSP on both CPUs Currently QEMU models all these boards using CPUs with both FPU and DSP enabled. This means that we are incorrect for mps2-an521 and musca-a, which should not have FPU or DSP on CPU0. Create QOM properties on the ARMSSE devices corresponding to the default h/w integration settings, and make the Musca-B1 board enable FPU and DSP on both CPUs. This fixes the mps2-an521 and musca-a behaviour, and leaves the musca-b1 and mps2-an505 behaviour unchanged. Signed-off-by: Peter Maydell Reviewed-by: Alex Bennée Message-id: 20190517174046.11146-5-peter.maydell@linaro.org --- include/hw/arm/armsse.h | 7 +++++ hw/arm/armsse.c | 58 ++++++++++++++++++++++++++++++++--------- hw/arm/musca.c | 8 ++++++ 3 files changed, 61 insertions(+), 12 deletions(-) -- 2.20.1 diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index 81e082cccf8..84080c22993 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -50,6 +50,11 @@ * address of each SRAM bank (and thus the total amount of internal SRAM) * + QOM property "init-svtor" sets the initial value of the CPU SVTOR register * (where it expects to load the PC and SP from the vector table on reset) + * + QOM properties "CPU0_FPU", "CPU0_DSP", "CPU1_FPU" and "CPU1_DSP" which + * set whether the CPUs have the FPU and DSP features present. The default + * (matching the hardware) is that for CPU0 in an IoTKit and CPU1 in an + * SSE-200 both are present; CPU0 in an SSE-200 has neither. + * Since the IoTKit has only one CPU, it does not have the CPU1_* properties. * + Named GPIO inputs "EXP_IRQ" 0..n are the expansion interrupts for CPU 0, * which are wired to its NVIC lines 32 .. n+32 * + Named GPIO inputs "EXP_CPU1_IRQ" 0..n are the expansion interrupts for @@ -208,6 +213,8 @@ typedef struct ARMSSE { uint32_t mainclk_frq; uint32_t sram_addr_width; uint32_t init_svtor; + bool cpu_fpu[SSE_MAX_CPUS]; + bool cpu_dsp[SSE_MAX_CPUS]; } ARMSSE; typedef struct ARMSSEInfo ARMSSEInfo; diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 47d13312dc1..b5c614cc3a1 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -38,6 +38,33 @@ struct ARMSSEInfo { bool has_cachectrl; bool has_cpusecctrl; bool has_cpuid; + Property *props; +}; + +static Property iotkit_properties[] = { + DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION, + MemoryRegion *), + DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64), + DEFINE_PROP_UINT32("MAINCLK", ARMSSE, mainclk_frq, 0), + DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15), + DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000), + DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true), + DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], true), + DEFINE_PROP_END_OF_LIST() +}; + +static Property armsse_properties[] = { + DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION, + MemoryRegion *), + DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64), + DEFINE_PROP_UINT32("MAINCLK", ARMSSE, mainclk_frq, 0), + DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15), + DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000), + DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], false), + DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], false), + DEFINE_PROP_BOOL("CPU1_FPU", ARMSSE, cpu_fpu[1], true), + DEFINE_PROP_BOOL("CPU1_DSP", ARMSSE, cpu_dsp[1], true), + DEFINE_PROP_END_OF_LIST() }; static const ARMSSEInfo armsse_variants[] = { @@ -53,6 +80,7 @@ static const ARMSSEInfo armsse_variants[] = { .has_cachectrl = false, .has_cpusecctrl = false, .has_cpuid = false, + .props = iotkit_properties, }, { .name = TYPE_SSE200, @@ -66,6 +94,7 @@ static const ARMSSEInfo armsse_variants[] = { .has_cachectrl = true, .has_cpusecctrl = true, .has_cpuid = true, + .props = armsse_properties, }, }; @@ -533,6 +562,20 @@ static void armsse_realize(DeviceState *dev, Error **errp) return; } } + if (!s->cpu_fpu[i]) { + object_property_set_bool(cpuobj, false, "vfp", &err); + if (err) { + error_propagate(errp, err); + return; + } + } + if (!s->cpu_dsp[i]) { + object_property_set_bool(cpuobj, false, "dsp", &err); + if (err) { + error_propagate(errp, err); + return; + } + } if (i > 0) { memory_region_add_subregion_overlap(&s->cpu_container[i], 0, @@ -1222,16 +1265,6 @@ static const VMStateDescription armsse_vmstate = { } }; -static Property armsse_properties[] = { - DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION, - MemoryRegion *), - DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64), - DEFINE_PROP_UINT32("MAINCLK", ARMSSE, mainclk_frq, 0), - DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15), - DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000), - DEFINE_PROP_END_OF_LIST() -}; - static void armsse_reset(DeviceState *dev) { ARMSSE *s = ARMSSE(dev); @@ -1244,13 +1277,14 @@ static void armsse_class_init(ObjectClass *klass, void *data) DeviceClass *dc = DEVICE_CLASS(klass); IDAUInterfaceClass *iic = IDAU_INTERFACE_CLASS(klass); ARMSSEClass *asc = ARMSSE_CLASS(klass); + const ARMSSEInfo *info = data; dc->realize = armsse_realize; dc->vmsd = &armsse_vmstate; - dc->props = armsse_properties; + dc->props = info->props; dc->reset = armsse_reset; iic->check = armsse_idau_check; - asc->info = data; + asc->info = info; } static const TypeInfo armsse_info = { diff --git a/hw/arm/musca.c b/hw/arm/musca.c index 825d80e75a4..ddd8842732c 100644 --- a/hw/arm/musca.c +++ b/hw/arm/musca.c @@ -385,6 +385,14 @@ static void musca_init(MachineState *machine) qdev_prop_set_uint32(ssedev, "init-svtor", mmc->init_svtor); qdev_prop_set_uint32(ssedev, "SRAM_ADDR_WIDTH", mmc->sram_addr_width); qdev_prop_set_uint32(ssedev, "MAINCLK", SYSCLK_FRQ); + /* + * Musca-A takes the default SSE-200 FPU/DSP settings (ie no for + * CPU0 and yes for CPU1); Musca-B1 explicitly enables them for CPU0. + */ + if (mmc->type == MUSCA_B1) { + qdev_prop_set_bit(ssedev, "CPU0_FPU", true); + qdev_prop_set_bit(ssedev, "CPU0_DSP", true); + } object_property_set_bool(OBJECT(&mms->sse), true, "realized", &error_fatal); From patchwork Mon Jun 17 14:33:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 167064 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp2997786ilk; Mon, 17 Jun 2019 08:22:50 -0700 (PDT) X-Google-Smtp-Source: APXvYqwruDNmJ549DoS0cA8GeRHXclIs5XLUP2fhk2Zrt7R/5IiIet+iJI8r1UtFOoz3hQCIXW35 X-Received: by 2002:a50:92cd:: with SMTP id l13mr44018076eda.136.1560784969880; Mon, 17 Jun 2019 08:22:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560784969; cv=none; d=google.com; s=arc-20160816; b=XPccOHs4MYLdYi0CM4A5Rx5xL6WLpG3W551mUC11CZEQKox6v0NkhZx/rC1xcNn558 2bBcCf0WOEEWgl5r2tMqIBsOdbsnipgOvrywV2Jw+w3+droee8cqsd5fogZx+qeTZDpH ERS0ZIXLx14gD592YPpdvNBIjNOy7mtif3AicDl/4WAhrAZrWL2gZENaPMy4K0SVcbV6 2SzWsRnovgKhCjWZz8hDPX7zEMVcp6BXmcIwWQHH+c6XdNbXsOAOqnI73IPstpS29oKJ ZmQDFosBCwHHb+KzFSAO2eQf+Y9bbTy0gVVQUvY3Vx82HX01e61ykWX6Q8te4ft7kfDP umrw== ARC-Message-Signature: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id a67sm13819985wmh.40.2019.06.17.07.34.23 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 17 Jun 2019 07:34:23 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 17 Jun 2019 15:33:57 +0100 Message-Id: <20190617143412.5734-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190617143412.5734-1-peter.maydell@linaro.org> References: <20190617143412.5734-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::334 Subject: [Qemu-devel] [PULL 09/24] hw/intc/arm_gicv3: Fix decoding of ID register range X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The GIC ID registers cover an area 0x30 bytes in size (12 registers, 4 bytes each). We were incorrectly decoding only the first 0x20 bytes. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Message-id: 20190524124248.28394-2-peter.maydell@linaro.org --- hw/intc/arm_gicv3_dist.c | 4 ++-- hw/intc/arm_gicv3_redist.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) -- 2.20.1 diff --git a/hw/intc/arm_gicv3_dist.c b/hw/intc/arm_gicv3_dist.c index 53c55c57291..e6fe4905fd3 100644 --- a/hw/intc/arm_gicv3_dist.c +++ b/hw/intc/arm_gicv3_dist.c @@ -533,7 +533,7 @@ static MemTxResult gicd_readl(GICv3State *s, hwaddr offset, } return MEMTX_OK; } - case GICD_IDREGS ... GICD_IDREGS + 0x1f: + case GICD_IDREGS ... GICD_IDREGS + 0x2f: /* ID registers */ *data = gicv3_idreg(offset - GICD_IDREGS); return MEMTX_OK; @@ -744,7 +744,7 @@ static MemTxResult gicd_writel(GICv3State *s, hwaddr offset, gicd_write_irouter(s, attrs, irq, r); return MEMTX_OK; } - case GICD_IDREGS ... GICD_IDREGS + 0x1f: + case GICD_IDREGS ... GICD_IDREGS + 0x2f: case GICD_TYPER: case GICD_IIDR: /* RO registers, ignore the write */ diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c index 3b0ba6de1ab..8645220d618 100644 --- a/hw/intc/arm_gicv3_redist.c +++ b/hw/intc/arm_gicv3_redist.c @@ -233,7 +233,7 @@ static MemTxResult gicr_readl(GICv3CPUState *cs, hwaddr offset, } *data = cs->gicr_nsacr; return MEMTX_OK; - case GICR_IDREGS ... GICR_IDREGS + 0x1f: + case GICR_IDREGS ... GICR_IDREGS + 0x2f: *data = gicv3_idreg(offset - GICR_IDREGS); return MEMTX_OK; default: @@ -363,7 +363,7 @@ static MemTxResult gicr_writel(GICv3CPUState *cs, hwaddr offset, return MEMTX_OK; case GICR_IIDR: case GICR_TYPER: - case GICR_IDREGS ... GICR_IDREGS + 0x1f: + case GICR_IDREGS ... GICR_IDREGS + 0x2f: /* RO registers, ignore the write */ qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid guest write to RO register at offset " From patchwork Mon Jun 17 14:33:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 167066 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp3001367ilk; Mon, 17 Jun 2019 08:26:04 -0700 (PDT) X-Google-Smtp-Source: APXvYqyAfcM718NDWFLir8o4gBGcmhRin6u/TVaRB5bgpiIyeASmIq5WWwB7SzBeAWdwuAL9ohQ/ X-Received: by 2002:a50:90c6:: with SMTP id d6mr97789867eda.19.1560785164186; Mon, 17 Jun 2019 08:26:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560785164; cv=none; d=google.com; s=arc-20160816; b=xFmJ7pksQmQw4QwR6MAZ59FiXQfPaoWK3Q5xt+guHrOKy+QYIwgExvrekODXPY3pxX AqpXcgE3RccIVpk6UJb0o1kTU1WVi8vmVwKADEQJrB+lXpp8CE0QO4RRybfESQ5Z+ya2 oov4C7Ndg2q0YvK3TAcf2t1vuKU27g19sdrUh0imUht5g9xWMYZuPjQBAEOylMw1j1WR ADj7RQSFkDH3WjLMRz5RdgWvf/gM7jrf+BRpWAeyEaAsPq7aqapp1wyJXpWKBDk0/bkr /377VZT2BxNQwIGkpTNJTLjaT1/7323tMfFBetIPyaKQcvLIUCzs9pKCvDrJUrAKsaCd kcvA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=ayi0GkBgLKY3AdrRPsXWIx7VD1COuTHMv3O+HeMPbB0=; b=kYD3vZrxIlbKqQ5QpH28XtGS7GQSqNotvn1VYni2u5l65V6laoHzoZIPDceCVVVAbN 1snTsGCXTN3hFR4T0bebZY/XAjxP/s3pyZ7ZHtVdOvvw/sF9/YvMZBpx3N8nVVjdDhRI 7TKokbRf3MnAk1YmbWes0ygUwLb9FY4RExb9ZAMnLCoqBlqWC8r1RJBV++ZhBNgYyNKb nzxCHLXJmUJYVtErVxgne1Gnk7m/foEQ3sJRxr2c6YPNaOSQdIH7fbQtyhCOHVch2DlX 5lBNTpLSsYZOXKJB26PyvM3PjBVKF6FvbGkJv8XDyBy0hw0zUG10xTCFZjLxQRNhbwTC 1INw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=WfhuD0Pz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id a67sm13819985wmh.40.2019.06.17.07.34.24 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 17 Jun 2019 07:34:24 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 17 Jun 2019 15:33:58 +0100 Message-Id: <20190617143412.5734-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190617143412.5734-1-peter.maydell@linaro.org> References: <20190617143412.5734-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 Subject: [Qemu-devel] [PULL 10/24] hw/intc/arm_gicv3: GICD_TYPER.SecurityExtn is RAZ if GICD_CTLR.DS == 1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The GICv3 specification says that the GICD_TYPER.SecurityExtn bit is RAZ if GICD_CTLR.DS is 1. We were incorrectly making it RAZ if the security extension is unsupported. "Security extension unsupported" always implies GICD_CTLR.DS == 1, but the guest can also set DS on a GIC which does support the security extension. Fix the condition to correctly check the GICD_CTLR.DS bit. Signed-off-by: Peter Maydell Message-id: 20190524124248.28394-3-peter.maydell@linaro.org --- hw/intc/arm_gicv3_dist.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) -- 2.20.1 diff --git a/hw/intc/arm_gicv3_dist.c b/hw/intc/arm_gicv3_dist.c index e6fe4905fd3..b65f56f9035 100644 --- a/hw/intc/arm_gicv3_dist.c +++ b/hw/intc/arm_gicv3_dist.c @@ -378,8 +378,14 @@ static MemTxResult gicd_readl(GICv3State *s, hwaddr offset, * ITLinesNumber == (num external irqs / 32) - 1 */ int itlinesnumber = ((s->num_irq - GIC_INTERNAL) / 32) - 1; + /* + * SecurityExtn must be RAZ if GICD_CTLR.DS == 1, and + * "security extensions not supported" always implies DS == 1, + * so we only need to check the DS bit. + */ + bool sec_extn = !(s->gicd_ctlr & GICD_CTLR_DS); - *data = (1 << 25) | (1 << 24) | (s->security_extn << 10) | + *data = (1 << 25) | (1 << 24) | (sec_extn << 10) | (0xf << 19) | itlinesnumber; return MEMTX_OK; } From patchwork Mon Jun 17 14:33:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 167067 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp3005803ilk; Mon, 17 Jun 2019 08:30:17 -0700 (PDT) X-Google-Smtp-Source: APXvYqxgY4OYZ7TxEM0m7tjAY2z9tWSGBY6DedvZ2174zpo3YdjAxXW04B+RiMYJOUVB+AgARXek X-Received: by 2002:a50:a53a:: with SMTP id y55mr102223957edb.147.1560785415837; Mon, 17 Jun 2019 08:30:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560785415; cv=none; d=google.com; s=arc-20160816; b=qmlJ/aVEu7bAMJt5avRd/5eGUUZiRZHFrp/l5EOT02i/F/7OmJGa78LPZMKB55mYPF hzxL+WWeLPwzrRNIg1n6L0SxcTr/YxoV4FuJGrEBZWHVFBIX9Ep9+d7xRpRNV324OgbK ilthP2dhfEWUEbs3I4zPrbtP0zRQCq+Na0b+vR8EpKjl0jZbw+gGkbA0ESMsLA5d41Fa 4p2GTBmR9LLBdU9knX/VDWuBhi2H7zgO0b677LA5KxLGruRRPDGXIqjSfwOU0PC1TiHs iL6xmaHLTKVxPB4EhpbmjVhgs42bsCQt+KxSCoxxDIvP9K8QlI+HU9nOs4Qfxb94zqaz Cxqw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=fkduvo7H+Mb+0yWACJmN2aG39JYYGYZGB+AH2iBoI9s=; b=s6lyu/HAp5EhqrRAMOh37PCtLQFKVcgk8mc+6w3kxft0+e31HMXUxCafnpqST9Ccwh reKJfJBVCRlSZ2a79W4IxPrqlyVAmhbIP8Kmswu3WPkqbdfuwbQgI58NOfWul29Ld22j kujSmM+FDodyCjrIw9vqKScj78e8pgz7Qcf8r6R9MWJVTVsVc5OAV4Bp7WxeLz+IImN/ 4BJIOQg4OM6TJ7w8pQEUpOS3nLY4cyKgPCh9AgPFL9SDd8gU30kobaw9A7VLq0nn/XVQ eo36M32FRjdratRg30gEbeyRmNSngoIKUowXvFV8zA/MkNKRdKoPAV6TjT30alfjLkG+ DHoA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=gqfnA1wX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id a67sm13819985wmh.40.2019.06.17.07.34.25 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 17 Jun 2019 07:34:26 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 17 Jun 2019 15:33:59 +0100 Message-Id: <20190617143412.5734-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190617143412.5734-1-peter.maydell@linaro.org> References: <20190617143412.5734-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 Subject: [Qemu-devel] [PULL 11/24] target/arm: Move vfp_expand_imm() to translate.[ch] X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We want to use vfp_expand_imm() in the AArch32 VFP decode; move it from the a64-only header/source file to the AArch32 one (which is always compiled even for AArch64). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daudé Message-id: 20190613163917.28589-2-peter.maydell@linaro.org --- target/arm/translate-a64.h | 1 - target/arm/translate.h | 7 +++++++ target/arm/translate-a64.c | 32 -------------------------------- target/arm/translate-vfp.inc.c | 33 +++++++++++++++++++++++++++++++++ 4 files changed, 40 insertions(+), 33 deletions(-) -- 2.20.1 diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h index 9569bc5963d..9ab40872d85 100644 --- a/target/arm/translate-a64.h +++ b/target/arm/translate-a64.h @@ -39,7 +39,6 @@ void write_fp_dreg(DisasContext *s, int reg, TCGv_i64 v); TCGv_ptr get_fpstatus_ptr(bool); bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn, unsigned int imms, unsigned int immr); -uint64_t vfp_expand_imm(int size, uint8_t imm8); bool sve_access_check(DisasContext *s); /* We should have at some point before trying to access an FP register diff --git a/target/arm/translate.h b/target/arm/translate.h index dc06dce7675..bc1617809da 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -237,6 +237,13 @@ static inline void gen_ss_advance(DisasContext *s) } } +/* + * Given a VFP floating point constant encoded into an 8 bit immediate in an + * instruction, expand it to the actual constant value of the specified + * size, as per the VFPExpandImm() pseudocode in the Arm ARM. + */ +uint64_t vfp_expand_imm(int size, uint8_t imm8); + /* Vector operations shared between ARM and AArch64. */ extern const GVecGen3 mla_op[4]; extern const GVecGen3 mls_op[4]; diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index ae739f65756..97f4164fbbc 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -6380,38 +6380,6 @@ static void disas_fp_3src(DisasContext *s, uint32_t insn) } } -/* The imm8 encodes the sign bit, enough bits to represent an exponent in - * the range 01....1xx to 10....0xx, and the most significant 4 bits of - * the mantissa; see VFPExpandImm() in the v8 ARM ARM. - */ -uint64_t vfp_expand_imm(int size, uint8_t imm8) -{ - uint64_t imm; - - switch (size) { - case MO_64: - imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) | - (extract32(imm8, 6, 1) ? 0x3fc0 : 0x4000) | - extract32(imm8, 0, 6); - imm <<= 48; - break; - case MO_32: - imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) | - (extract32(imm8, 6, 1) ? 0x3e00 : 0x4000) | - (extract32(imm8, 0, 6) << 3); - imm <<= 16; - break; - case MO_16: - imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) | - (extract32(imm8, 6, 1) ? 0x3000 : 0x4000) | - (extract32(imm8, 0, 6) << 6); - break; - default: - g_assert_not_reached(); - } - return imm; -} - /* Floating point immediate * 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0 * +---+---+---+-----------+------+---+------------+-------+------+------+ diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index 709fc65374d..a66084f6e36 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -30,6 +30,39 @@ #include "decode-vfp.inc.c" #include "decode-vfp-uncond.inc.c" +/* + * The imm8 encodes the sign bit, enough bits to represent an exponent in + * the range 01....1xx to 10....0xx, and the most significant 4 bits of + * the mantissa; see VFPExpandImm() in the v8 ARM ARM. + */ +uint64_t vfp_expand_imm(int size, uint8_t imm8) +{ + uint64_t imm; + + switch (size) { + case MO_64: + imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) | + (extract32(imm8, 6, 1) ? 0x3fc0 : 0x4000) | + extract32(imm8, 0, 6); + imm <<= 48; + break; + case MO_32: + imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) | + (extract32(imm8, 6, 1) ? 0x3e00 : 0x4000) | + (extract32(imm8, 0, 6) << 3); + imm <<= 16; + break; + case MO_16: + imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) | + (extract32(imm8, 6, 1) ? 0x3000 : 0x4000) | + (extract32(imm8, 0, 6) << 6); + break; + default: + g_assert_not_reached(); + } + return imm; +} + /* * Return the offset of a 16-bit half of the specified VFP single-precision * register. If top is true, returns the top 16 bits; otherwise the bottom From patchwork Mon Jun 17 14:34:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 167050 Delivered-To: patch@linaro.org Received: by 2002:ac9:6410:0:0:0:0:0 with SMTP id r16csp1100850ock; Mon, 17 Jun 2019 07:54:34 -0700 (PDT) X-Google-Smtp-Source: APXvYqwpA2yRlxdYQQ4xI9mH7GOnIs0BjN9ux+xjs++qVe8YV2AGhA77bTfFMNX3WeTCAJVmPkcx X-Received: by 2002:aa7:c999:: with SMTP id c25mr55381919edt.134.1560783274557; Mon, 17 Jun 2019 07:54:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560783274; cv=none; d=google.com; s=arc-20160816; b=a/Zbd85/+zzwgCLFetKOWAa3dLS3X+1zDttgn1pPBQK5zm4vA1Vql8AmftOsEitfOd Xq2E8+JD4ErxfEuvynVDIrV10R82+2qiShBwq6Kiv1P35i9LNtiTLHBM0wHxRU9O/H2W YI7s33bu0B7q29H+Jwle6LS15DUv9JsuLPV4D1W1l+gGRUsOXm/WHdSA6l3xvgRGrDRo aTqdo0EwCL5Ps2nacSHikIiyzUbf+O/mHTZ7Z6fQeaotVTP5SDrbFetV8H2g2OMZ5kzl qodEapd0PgFznMsCr8dVx+O2H5hL8YgYnEDqGFxGCbhtQXp+Z7GR3/W8wCeXmgO1RwiK hoLA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=/O59M+oyu5/R7Sber67X9/QD01sBNxWM7GHNOMmzU2g=; b=KBIQuFSNmGkF84S/PkvVbgAaJ/Pvm+9JBgjMbVT6M2YMlyllG1dMf4qnSOWurc3wip MT+xYVMVQsU5M6rkAbynTxdMAFEgQ40Cz0ttmxlFRPrXtju6iqVABbaqntewpSjD+Wnv FHks6C0LXefTS9MwTZGLT4QOdt7n6D65bBCPFiHt6Mwqct7AKe/xD48T3nAnVrEFPlVP 0jsWaid+ZMI0yax2jl8UKaMtEQwgbVBpv8mQ4lubg7SXkz96lZKxtfJIocgqYqVznTXj ctLkBRDbYc3T3bb/kkWXoQ55lfU4RYuwkVV91XKax7+7Ls4CVNLwE+5S9Aop7Xc+rwNi 2AmA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=EDTfAyrD; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id a67sm13819985wmh.40.2019.06.17.07.34.27 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 17 Jun 2019 07:34:27 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 17 Jun 2019 15:34:00 +0100 Message-Id: <20190617143412.5734-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190617143412.5734-1-peter.maydell@linaro.org> References: <20190617143412.5734-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 Subject: [Qemu-devel] [PULL 12/24] target/arm: Use vfp_expand_imm() for AArch32 VFP VMOV_imm X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The AArch32 VMOV (immediate) instruction uses the same VFP encoded immediate format we already handle in vfp_expand_imm(). Use that function rather than hand-decoding it. Suggested-by: Richard Henderson Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daudé Message-id: 20190613163917.28589-3-peter.maydell@linaro.org --- target/arm/translate-vfp.inc.c | 28 ++++------------------------ target/arm/vfp.decode | 10 ++++++---- 2 files changed, 10 insertions(+), 28 deletions(-) -- 2.20.1 diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index a66084f6e36..8b732761f26 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -1842,7 +1842,7 @@ static bool trans_VMOV_imm_sp(DisasContext *s, arg_VMOV_imm_sp *a) uint32_t delta_d = 0; int veclen = s->vec_len; TCGv_i32 fd; - uint32_t n, i, vd; + uint32_t vd; vd = a->vd; @@ -1869,17 +1869,7 @@ static bool trans_VMOV_imm_sp(DisasContext *s, arg_VMOV_imm_sp *a) } } - n = (a->imm4h << 28) & 0x80000000; - i = ((a->imm4h << 4) & 0x70) | a->imm4l; - if (i & 0x40) { - i |= 0x780; - } else { - i |= 0x800; - } - n |= i << 19; - - fd = tcg_temp_new_i32(); - tcg_gen_movi_i32(fd, n); + fd = tcg_const_i32(vfp_expand_imm(MO_32, a->imm)); for (;;) { neon_store_reg32(fd, vd); @@ -1902,7 +1892,7 @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_VMOV_imm_dp *a) uint32_t delta_d = 0; int veclen = s->vec_len; TCGv_i64 fd; - uint32_t n, i, vd; + uint32_t vd; vd = a->vd; @@ -1934,17 +1924,7 @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_VMOV_imm_dp *a) } } - n = (a->imm4h << 28) & 0x80000000; - i = ((a->imm4h << 4) & 0x70) | a->imm4l; - if (i & 0x40) { - i |= 0x3f80; - } else { - i |= 0x4000; - } - n |= i << 16; - - fd = tcg_temp_new_i64(); - tcg_gen_movi_i64(fd, ((uint64_t)n) << 32); + fd = tcg_const_i64(vfp_expand_imm(MO_64, a->imm)); for (;;) { neon_store_reg64(fd, vd); diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode index ea24365bb4c..a67b3f29ee5 100644 --- a/target/arm/vfp.decode +++ b/target/arm/vfp.decode @@ -44,6 +44,8 @@ %vmov_idx_b 21:1 5:2 %vmov_idx_h 21:1 6:1 +%vmov_imm 16:4 0:4 + # VMOV scalar to general-purpose register; note that this does # include some Neon cases. VMOV_to_gp ---- 1110 u:1 1. 1 .... rt:4 1011 ... 1 0000 \ @@ -152,10 +154,10 @@ VFM_sp ---- 1110 1.10 .... .... 1010 . o2:1 . 0 .... \ VFM_dp ---- 1110 1.10 .... .... 1011 . o2:1 . 0 .... \ vm=%vm_dp vn=%vn_dp vd=%vd_dp o1=2 -VMOV_imm_sp ---- 1110 1.11 imm4h:4 .... 1010 0000 imm4l:4 \ - vd=%vd_sp -VMOV_imm_dp ---- 1110 1.11 imm4h:4 .... 1011 0000 imm4l:4 \ - vd=%vd_dp +VMOV_imm_sp ---- 1110 1.11 .... .... 1010 0000 .... \ + vd=%vd_sp imm=%vmov_imm +VMOV_imm_dp ---- 1110 1.11 .... .... 1011 0000 .... \ + vd=%vd_dp imm=%vmov_imm VMOV_reg_sp ---- 1110 1.11 0000 .... 1010 01.0 .... \ vd=%vd_sp vm=%vm_sp From patchwork Mon Jun 17 14:34:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 167068 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp3006810ilk; Mon, 17 Jun 2019 08:31:09 -0700 (PDT) X-Google-Smtp-Source: APXvYqwNUfysBmHp3+P4na1N9H46/WaBbIdzCwTMRe9yXY9qv4UJckWkmS2CReeN8/4w6Fmv2fKz X-Received: by 2002:a17:906:f10d:: with SMTP id gv13mr60975104ejb.151.1560785469707; Mon, 17 Jun 2019 08:31:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560785469; cv=none; d=google.com; s=arc-20160816; b=f5cN9LzJ2dpCgRyiRYS9OwuR3yYCQiiQu3ejFIcvZjlNSuh+GFGprDBFrOkgi7FQKi vbzG3XeVtzl2QVR9dcxsFU4Nck4LCMr/Bo9b16frjUx8OHe4/d+432/VaAeUeTH9/01E dl/D7ZTSoWjdNLRhP6D0lx4nwnxHwu2Dhe/mCQn6sDrmnyKcLyHbxdFnCBsU7ZKTdy2X i70LJir3lZLOF2vfIbKXDKJCbnIpLY1P/e5p9aDrjhsdsG1ZPzMTAnqMM/WaSSA3jtKg p0y1ySjd1cYvExI/KEaJiLrmbpCLl70bv/3pxJfEIieSX5m4kSbAG7AuZzhOfF9aNJLj ztDA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=Ul7s+t7hXiN2ylOfOOWOvIZY61Jzqwc15l5S4ChbjBk=; b=vkztTpMqefKLHhT5FDCy7jhEgwnC4N/QMnizJfkI9e22M6Xg/yh3Og0KVSVdprqvD7 t5svvbIJT2MUxZWu0H9gCWOBerLBhG2pU18GsP5NiZqcqZZkzxaHytY2YWTARP1zxt9m kVIxqdQ0HcdoqlSqJDnBYk+TjVNBWUWSsYCAbwfz8MTb9M4QgwpaA8dA04D2tTiTeMWI J67anD+6nIm6j06F5WbtLnAcjxeT8SZcEpA0UDoMBgrWHU5/ucHzWCS4NIWvbhiSWalV RRnBCcZAk5GVksEzrzBDfDzd7ihOCMBW1Sxbu7LhUPstYR5461ApW5jGC2JDJ+cPL2Ry LS9Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=CvFMte1e; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id a67sm13819985wmh.40.2019.06.17.07.34.27 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 17 Jun 2019 07:34:28 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 17 Jun 2019 15:34:01 +0100 Message-Id: <20190617143412.5734-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190617143412.5734-1-peter.maydell@linaro.org> References: <20190617143412.5734-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42c Subject: [Qemu-devel] [PULL 13/24] target/arm: Stop using cpu_F0s for NEON_2RM_VABS_F X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Where Neon instructions are floating point operations, we mostly use the old VFP utility functions like gen_vfp_abs() which work on the TCG globals cpu_F0s and cpu_F1s. The Neon for-each-element loop conditionally loads the inputs into either a plain old TCG temporary for most operations or into cpu_F0s for float operations, and similarly stores back either cpu_F0s or the temporary. Switch NEON_2RM_VABS_F away from using cpu_F0s, and update neon_2rm_is_float_op() accordingly. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daudé Message-id: 20190613163917.28589-4-peter.maydell@linaro.org --- target/arm/translate.c | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-) -- 2.20.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index c274c8b4602..a10fded1f39 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1374,14 +1374,6 @@ static TCGv_ptr get_fpstatus_ptr(int neon) return statusptr; } -static inline void gen_vfp_abs(int dp) -{ - if (dp) - gen_helper_vfp_absd(cpu_F0d, cpu_F0d); - else - gen_helper_vfp_abss(cpu_F0s, cpu_F0s); -} - static inline void gen_vfp_neg(int dp) { if (dp) @@ -4191,8 +4183,13 @@ static const uint8_t neon_3r_sizes[] = { static int neon_2rm_is_float_op(int op) { - /* Return true if this neon 2reg-misc op is float-to-float */ - return (op == NEON_2RM_VABS_F || op == NEON_2RM_VNEG_F || + /* + * Return true if this neon 2reg-misc op is float-to-float. + * This is not a property of the operation but of our code -- + * what we are asking here is "does the code for this case in + * the Neon for-each-pass loop use cpu_F0s?". + */ + return (op == NEON_2RM_VNEG_F || (op >= NEON_2RM_VRINTN && op <= NEON_2RM_VRINTZ) || op == NEON_2RM_VRINTM || (op >= NEON_2RM_VRINTP && op <= NEON_2RM_VCVTMS) || @@ -6761,7 +6758,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) break; } case NEON_2RM_VABS_F: - gen_vfp_abs(0); + gen_helper_vfp_abss(tmp, tmp); break; case NEON_2RM_VNEG_F: gen_vfp_neg(0); From patchwork Mon Jun 17 14:34:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 167069 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp3012092ilk; Mon, 17 Jun 2019 08:36:02 -0700 (PDT) X-Google-Smtp-Source: APXvYqy2sEr3N/j5Cz2M+hhTMH4dq9LPR8Z0ZlN+jcIBWMFcoVxPwOfz57UbnWvSxeSdGwg37r+F X-Received: by 2002:a17:906:838a:: with SMTP id p10mr4451902ejx.237.1560785762447; Mon, 17 Jun 2019 08:36:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560785762; cv=none; d=google.com; s=arc-20160816; b=N4JaXEe7PsdUBIc8SPIpudYbPV46tm+zhBmb90ByJnbbr8SybHO/qAoFhvDBwUFEDr T62tQcO38LgQrAo41mDIH8zqO3KmCAcJFO3+z+4pmdrkkX0+4lw/CIqp6WehOo3HvTrK sekV8KYOGDD+lx/zRlwb+xK8dp+QUp5nJFoRgoBAxntfCWYKrs6hYPWDpG8/QwvRfwhL VLsrt8nq+SdVWARVjX9AYlHCJJWbXER2kxajQAa7H0tVT8I4J04zPLczPBROSXBU7jH7 Ej4vJCl+zHb2Qp98bWPXMS6Yv/OwNTlSrSbybaKmRDDRHgqw5qzX7FJ1N2xSk6PrHifm 7Cpg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=L1QAxhdOtIdBK1xtHMazBBt8aewsGSxHd8eF0bvtE2w=; b=Vy0RnOUquQ/WJL7Z5RpopNXUXlbq9DcZYpKTLQBmJCy8J4bQqu/JuZTIlPJSDQpnTb xRDpZ8rCMCxzTEPBRq9S0InQp5mNaH0UyUeYJlD6KzRjCvCA1wp4ksW8V8IMPEg4+b/3 XmVu0AuT8YFNohNsG5DRJx7UIc+pZDlf7oNcuPbMJ3UHtoS7lww+AIMkTGp22jtpP9ai Sv3ldoSPjHWQLdXA3U5WbUfq3X4yJg6CSYDqCo/Ixga4BcNs8hePFsg2TnM4uDETaN4Z 9N0KvjjMCQ/o5SsS8rO7ezYxODHsaRwVmjQRnRwQowjK+67lVu4BR0pVrAazOT4ewH/h yaSw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=gLi27PxJ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:4864:20::341 Subject: [Qemu-devel] [PULL 14/24] target/arm: Stop using cpu_F0s for NEON_2RM_VNEG_F X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Switch NEON_2RM_VABS_F away from using cpu_F0s. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daudé Message-id: 20190613163917.28589-5-peter.maydell@linaro.org --- target/arm/translate.c | 13 ++----------- 1 file changed, 2 insertions(+), 11 deletions(-) -- 2.20.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index a10fded1f39..a006ab498e7 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1374,14 +1374,6 @@ static TCGv_ptr get_fpstatus_ptr(int neon) return statusptr; } -static inline void gen_vfp_neg(int dp) -{ - if (dp) - gen_helper_vfp_negd(cpu_F0d, cpu_F0d); - else - gen_helper_vfp_negs(cpu_F0s, cpu_F0s); -} - #define VFP_GEN_ITOF(name) \ static inline void gen_vfp_##name(int dp, int neon) \ { \ @@ -4189,8 +4181,7 @@ static int neon_2rm_is_float_op(int op) * what we are asking here is "does the code for this case in * the Neon for-each-pass loop use cpu_F0s?". */ - return (op == NEON_2RM_VNEG_F || - (op >= NEON_2RM_VRINTN && op <= NEON_2RM_VRINTZ) || + return ((op >= NEON_2RM_VRINTN && op <= NEON_2RM_VRINTZ) || op == NEON_2RM_VRINTM || (op >= NEON_2RM_VRINTP && op <= NEON_2RM_VCVTMS) || op >= NEON_2RM_VRECPE_F); @@ -6761,7 +6752,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) gen_helper_vfp_abss(tmp, tmp); break; case NEON_2RM_VNEG_F: - gen_vfp_neg(0); + gen_helper_vfp_negs(tmp, tmp); break; case NEON_2RM_VSWP: tmp2 = neon_load_reg(rd, pass); From patchwork Mon Jun 17 14:34:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 167047 Delivered-To: patch@linaro.org Received: by 2002:ac9:6410:0:0:0:0:0 with SMTP id r16csp1098540ock; Mon, 17 Jun 2019 07:52:05 -0700 (PDT) X-Google-Smtp-Source: APXvYqxqjhXHdCvULAz2Sgl1fL2uTXarG32F5y0kNyusFMG/wZvVDzAZ8MuRmSWymcqySb9tiIXY X-Received: by 2002:ac8:431e:: with SMTP id z30mr94451934qtm.291.1560783125024; Mon, 17 Jun 2019 07:52:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560783125; cv=none; d=google.com; s=arc-20160816; b=UBgMFC+SkAEUg1k+4gelFj/mssJF6BHhf4qBgutvfRHDNdqIuZfVZVYr92EZfwcrCC fWsLk+v42O85LOtqZhYnRq8q/1gO2FYVvQcnCWwgpOlqEvKCza76lYSS4vC6TCYMKtNj X6C8nc5w8Apth6kxeCrrxpHgsoI37Kx32+5mrkfaG5CBuK4ycBxp4aj32wH0aeD43uxB fYQ8vDncUD7WYCThm/iluAPhSWei3LB3Oi/n+RSQpDjGVq+F+AdK8W/lFU5wR1LGMwsS jRElWk08P/7IvzxvMpjh6xK2Xej+on9DGpGKaxj+WCEgLSBa1R6l/l9xx6wihUuObRIH mD9Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=YQocH3JzOwJkJhKLmOCIia7aopw+9WsCQO9KTDk9Jlk=; b=dJ28m3LuCDijSGrBir1Q5haGGrVPh1+Hn58iIWZ4xr2yPbVXB0zArTniZwhBzM1Ni8 Cm4ZOKajt/WGQkLFMwPt+iiG96tg15Eb3wiK2dkGItN9q99A00brUgBzudmjxMKm05gW yX3etDMRlDzmv1KAAA3+JEkMcD9IT6+5OZZacBOtKTeWTcrUN3EMTdis7AuyQbCSNB0s XaXfjm22B3QiND5tMb85wB1AzjGYtv5QrzdsQVtCjTADziDJ7nN8PPy7hOUsE9biCRKx HZ8Nuqju91jb1O9IWU/9n920u1cwpBpFpGH7vv83BXJW7/y/ldLV/j1QpYRbbMSBMBOW hBaw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=aI4xjgkO; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id a67sm13819985wmh.40.2019.06.17.07.34.30 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 17 Jun 2019 07:34:30 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 17 Jun 2019 15:34:03 +0100 Message-Id: <20190617143412.5734-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190617143412.5734-1-peter.maydell@linaro.org> References: <20190617143412.5734-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::435 Subject: [Qemu-devel] [PULL 15/24] target/arm: Stop using cpu_F0s for NEON_2RM_VRINT* X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Switch NEON_2RM_VRINT* away from using cpu_F0s. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daudé Message-id: 20190613163917.28589-6-peter.maydell@linaro.org --- target/arm/translate.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) -- 2.20.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index a006ab498e7..243dbee8357 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -4181,9 +4181,7 @@ static int neon_2rm_is_float_op(int op) * what we are asking here is "does the code for this case in * the Neon for-each-pass loop use cpu_F0s?". */ - return ((op >= NEON_2RM_VRINTN && op <= NEON_2RM_VRINTZ) || - op == NEON_2RM_VRINTM || - (op >= NEON_2RM_VRINTP && op <= NEON_2RM_VCVTMS) || + return ((op >= NEON_2RM_VCVTAU && op <= NEON_2RM_VCVTMS) || op >= NEON_2RM_VRECPE_F); } @@ -6786,7 +6784,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode)); gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode, cpu_env); - gen_helper_rints(cpu_F0s, cpu_F0s, fpstatus); + gen_helper_rints(tmp, tmp, fpstatus); gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode, cpu_env); tcg_temp_free_ptr(fpstatus); @@ -6796,7 +6794,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) case NEON_2RM_VRINTX: { TCGv_ptr fpstatus = get_fpstatus_ptr(1); - gen_helper_rints_exact(cpu_F0s, cpu_F0s, fpstatus); + gen_helper_rints_exact(tmp, tmp, fpstatus); tcg_temp_free_ptr(fpstatus); break; } From patchwork Mon Jun 17 14:34:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 167071 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp3019347ilk; Mon, 17 Jun 2019 08:43:09 -0700 (PDT) X-Google-Smtp-Source: APXvYqwlwp37dsldTojtYNgxWbyvNrI661a23X0bvEKKXhVAwAovH0PX7sZRsXl7cFO6Eb8kUDCc X-Received: by 2002:a17:906:58cf:: with SMTP id e15mr45825741ejs.240.1560786189696; Mon, 17 Jun 2019 08:43:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560786189; cv=none; d=google.com; s=arc-20160816; b=MVOFWKbFzlTW5hiq2sdtK5dryQP+GSkmNQyCz2sr599xIPV3buBgBbRNiv60qi69lZ zpWcvt9fx71LM/UNzjXpve/wtMvCAhp6F6nVLlYWEM/6M7W+lCEdNHQWIfsa2rB/vAqA NGQpetPnwhDc4/hJhMI8zMsCaGQjnzNseV0AH3jzMFZZeBbWlOu5MyobwRnGhMXf6/LD 4/8eQmqcXDgwtJpp6VSfirN2NQTE4MxRD1OZ+BzH0IgUeQ85RhhAOIq3qEpP0E6fWcDz LIkyq9AMIDBESQ7Z7+C52DVOs26BuHbvvdLl6awE91GCjSz58EjrRtnWHeMpEHbIRYwC h78A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=WgJ3ME0OmnuR5vXoFEmNb/znccvEB85oUYK/SkfReNM=; b=A8H7XJr6yz/+KCXnhbPtICGpghXpGiYaE3IF2QDmeaeVA/VNZM5RjMJtASVJEpWC4E OGuQn+SGYpsyqfg80lmVGDJy/hLmx5pe9xLZB6ybcbUV0ravvEX7GZRbJ9Dl3gbZM9RM K9/G3yPn4GLdHU7kigob1S6dEoUAqn28F1GmJkJQa26/geak8E6nFQMZpwrt2QHINHeD EHyXrkTDNa5bTYP3CaLIuyxXXkWB7FJ9coVs6FYEXeT3KHbaHujWtZjIO0aZbvFvMH3S UarjPjEk9A/1p+B3YyJSVJUka+8XvVchTaUHDMAk6T/337QGB4X4eYHIZ0UIxxWLcRiI DVBQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=JDGyteuB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id a67sm13819985wmh.40.2019.06.17.07.34.31 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 17 Jun 2019 07:34:31 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 17 Jun 2019 15:34:04 +0100 Message-Id: <20190617143412.5734-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190617143412.5734-1-peter.maydell@linaro.org> References: <20190617143412.5734-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::431 Subject: [Qemu-devel] [PULL 16/24] target/arm: Stop using cpu_F0s for NEON_2RM_VCVT[ANPM][US] X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Stop using cpu_F0s for the NEON_2RM_VCVT[ANPM][US] ops. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daudé Message-id: 20190613163917.28589-7-peter.maydell@linaro.org --- target/arm/translate.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) -- 2.20.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 243dbee8357..124045a9ef6 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -4181,8 +4181,7 @@ static int neon_2rm_is_float_op(int op) * what we are asking here is "does the code for this case in * the Neon for-each-pass loop use cpu_F0s?". */ - return ((op >= NEON_2RM_VCVTAU && op <= NEON_2RM_VCVTMS) || - op >= NEON_2RM_VRECPE_F); + return op >= NEON_2RM_VRECPE_F; } static bool neon_2rm_is_v8_op(int op) @@ -6818,10 +6817,10 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) cpu_env); if (is_signed) { - gen_helper_vfp_tosls(cpu_F0s, cpu_F0s, + gen_helper_vfp_tosls(tmp, tmp, tcg_shift, fpst); } else { - gen_helper_vfp_touls(cpu_F0s, cpu_F0s, + gen_helper_vfp_touls(tmp, tmp, tcg_shift, fpst); } From patchwork Mon Jun 17 14:34:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 167051 Delivered-To: patch@linaro.org Received: by 2002:ac9:6410:0:0:0:0:0 with SMTP id r16csp1101831ock; Mon, 17 Jun 2019 07:55:41 -0700 (PDT) X-Google-Smtp-Source: APXvYqzAG5eGKxv4TLNOgAskjUY/PnvuT3tTBitJYW2r6oWuwmQFPpSRvLEkNhbp4WZmuCLexGR0 X-Received: by 2002:a50:b48f:: with SMTP id w15mr73078913edd.260.1560783341622; Mon, 17 Jun 2019 07:55:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560783341; cv=none; d=google.com; s=arc-20160816; b=lEUBhccOQA/cmsP1IsgQ3ZTRb1c1F4LZca2WH/YACfyKDsN9kUpQfqGDEX0HKbg+zX rn5mVb4KS2JR3YtyWdleUJMRFtMQji9iLQhOXU9349ThCN34x7NZsxGkYAPy+J0eO/5q BhKuIiMXA9Mz0psZdnjNx104HRkoiTSIX4bHLb5J5Vmpq2LweY/+ekon5CptwgBapgYo GOeMMnO+h5U6d4HswNcd2NNhnMJJn5h4mSdUWrv7rqwAgWOVZL9mnzCqzYQ49UeCEote THTP0PmZIEWfah5ShG8GpQJso8xTRMgAq+0z4PrV7/bjt3iNM6k4O1zQ2f933aah2zKr eC6g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=4QBUk4yePtKTDco8yX0s+6IInVsDCxdEuCWVUvL2BwI=; b=xadi58Q/lZhmms5qTywlsuqbWMV7D0MjuicJFCz6xUs7LIjYAwZWJXF7xcJzGmP5bd xMmRRNB9IWrg+aN2bVFAm5eXAKBnexmj7nlG8mMkTEBUjQjBPv1zP/8rh5pIjx2suU21 KMotODJ6ry/qfVbjwe7EAsyIHoKyUdLOtvO4JX3GEGzEnhocoSeuseoaSso2X4IVf9rZ Ap3SxH4OX0eYDSylkJZrJrCE5zBqqT3u0ukGn9wwd5LvIVtnIdURt9PwhUaAqELzMsRm Y7xEFR1McGk1s40JepstAWlRGNLahDyxsA/zW1dkGFMKyHYzDh03ttbil3z8rbh2rmk7 7CcA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="V9/OtmYx"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id a67sm13819985wmh.40.2019.06.17.07.34.32 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 17 Jun 2019 07:34:32 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 17 Jun 2019 15:34:05 +0100 Message-Id: <20190617143412.5734-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190617143412.5734-1-peter.maydell@linaro.org> References: <20190617143412.5734-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 Subject: [Qemu-devel] [PULL 17/24] target/arm: Stop using cpu_F0s for NEON_2RM_VRECPE_F and NEON_2RM_VRSQRTE_F X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Stop using cpu_F0s for NEON_2RM_VRECPE_F and NEON_2RM_VRSQRTE_F. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daudé Message-id: 20190613163917.28589-8-peter.maydell@linaro.org --- target/arm/translate.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) -- 2.20.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 124045a9ef6..75ed7cc7cb0 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -4181,7 +4181,7 @@ static int neon_2rm_is_float_op(int op) * what we are asking here is "does the code for this case in * the Neon for-each-pass loop use cpu_F0s?". */ - return op >= NEON_2RM_VRECPE_F; + return op >= NEON_2RM_VCVT_FS; } static bool neon_2rm_is_v8_op(int op) @@ -6848,14 +6848,14 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) case NEON_2RM_VRECPE_F: { TCGv_ptr fpstatus = get_fpstatus_ptr(1); - gen_helper_recpe_f32(cpu_F0s, cpu_F0s, fpstatus); + gen_helper_recpe_f32(tmp, tmp, fpstatus); tcg_temp_free_ptr(fpstatus); break; } case NEON_2RM_VRSQRTE_F: { TCGv_ptr fpstatus = get_fpstatus_ptr(1); - gen_helper_rsqrte_f32(cpu_F0s, cpu_F0s, fpstatus); + gen_helper_rsqrte_f32(tmp, tmp, fpstatus); tcg_temp_free_ptr(fpstatus); break; } From patchwork Mon Jun 17 14:34:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 167055 Delivered-To: patch@linaro.org Received: by 2002:ac9:6410:0:0:0:0:0 with SMTP id r16csp1103089ock; Mon, 17 Jun 2019 07:57:14 -0700 (PDT) X-Google-Smtp-Source: APXvYqyJnqTCSCtQGPpCbfGUEmP4MKw6sUEG99YbZS3qtxBEA9swSl4vxvzlkPxz1vHiZlY3xioN X-Received: by 2002:a05:6402:652:: with SMTP id u18mr26662508edx.85.1560783434710; Mon, 17 Jun 2019 07:57:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560783434; cv=none; d=google.com; s=arc-20160816; b=uOrBaec+92FRs2sapbLUWXnro9tb8k45+PzIppRzvjKKJZvoEEssGBde5ZALYqZrDA sbuwnR0Nh/rDQgbiAhhKVGkzYyGkDCQz1ztHsY+FElK47277u6Tnd7wUxOtvVlyOTYd8 gRwK+rldTtehHghdoV3ovmT6W0CBVfSXhdElfxxBAMfvREnGTeK9xjOA1LT3AFNAuYO9 b2p4nl4nM8w1l7jv/BFVuguxFncGJPzlXjwrYvIzaw3qWcKrAU26dahF9nCltWBg1Xdi AD6QZFzyDM6inZE5i+X6EEh2OQ/e8fRDgjZt/7jm+ghiahzW1b7ygwgi6wOwG3v9NFJb 30+g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=QH/DDBGbAAKw5E22C6nxXcLX4pRMuc/olgVu3SfYiz4=; b=GkmNK+e3HEBHIJegINvlACIdyrq3NJ7xKaZyN/5o9RsnT1hW6QtUgrIeyL6Q+E+yKw Sxg1zYwPhu12VZ7o1WjKyPgJU+iQcnu1d1umP/apR8a8Msqa2sikEjBlR9FIOxH8wF7+ vRfj+JOX+FNlPzKSGMOj/HqKKe0D+5jm9GtmatNfgfNLQuR/16vh+La0ECHK90IXtYp4 30pdmSI/P6JUXmxb6F+iRZGgWVuFeFFWPI94O28eMGqviJr1QzuZVn1l8LwlyW1Pqrla ZBGm16aKzTZ1hwmHqLFA/fH85Vz2GUIHnYVg2ZOPT5wLLgQori+o6/oOYGe4kQEkevSv pnxg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ypAYlGCU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id a67sm13819985wmh.40.2019.06.17.07.34.33 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 17 Jun 2019 07:34:33 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 17 Jun 2019 15:34:06 +0100 Message-Id: <20190617143412.5734-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190617143412.5734-1-peter.maydell@linaro.org> References: <20190617143412.5734-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::429 Subject: [Qemu-devel] [PULL 18/24] target/arm: Stop using cpu_F0s for Neon f32/s32 VCVT X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Stop using cpu_F0s for the Neon f32/s32 VCVT operations. Since this is the last user of cpu_F0s in the Neon 2rm-op loop, we can remove the handling code for it too. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daudé Message-id: 20190613163917.28589-9-peter.maydell@linaro.org --- target/arm/translate.c | 82 ++++++++++++------------------------------ 1 file changed, 22 insertions(+), 60 deletions(-) -- 2.20.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 75ed7cc7cb0..0fb94b777bf 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1374,38 +1374,6 @@ static TCGv_ptr get_fpstatus_ptr(int neon) return statusptr; } -#define VFP_GEN_ITOF(name) \ -static inline void gen_vfp_##name(int dp, int neon) \ -{ \ - TCGv_ptr statusptr = get_fpstatus_ptr(neon); \ - if (dp) { \ - gen_helper_vfp_##name##d(cpu_F0d, cpu_F0s, statusptr); \ - } else { \ - gen_helper_vfp_##name##s(cpu_F0s, cpu_F0s, statusptr); \ - } \ - tcg_temp_free_ptr(statusptr); \ -} - -VFP_GEN_ITOF(uito) -VFP_GEN_ITOF(sito) -#undef VFP_GEN_ITOF - -#define VFP_GEN_FTOI(name) \ -static inline void gen_vfp_##name(int dp, int neon) \ -{ \ - TCGv_ptr statusptr = get_fpstatus_ptr(neon); \ - if (dp) { \ - gen_helper_vfp_##name##d(cpu_F0s, cpu_F0d, statusptr); \ - } else { \ - gen_helper_vfp_##name##s(cpu_F0s, cpu_F0s, statusptr); \ - } \ - tcg_temp_free_ptr(statusptr); \ -} - -VFP_GEN_FTOI(touiz) -VFP_GEN_FTOI(tosiz) -#undef VFP_GEN_FTOI - #define VFP_GEN_FIX(name, round) \ static inline void gen_vfp_##name(int dp, int shift, int neon) \ { \ @@ -4173,17 +4141,6 @@ static const uint8_t neon_3r_sizes[] = { #define NEON_2RM_VCVT_SF 62 #define NEON_2RM_VCVT_UF 63 -static int neon_2rm_is_float_op(int op) -{ - /* - * Return true if this neon 2reg-misc op is float-to-float. - * This is not a property of the operation but of our code -- - * what we are asking here is "does the code for this case in - * the Neon for-each-pass loop use cpu_F0s?". - */ - return op >= NEON_2RM_VCVT_FS; -} - static bool neon_2rm_is_v8_op(int op) { /* Return true if this neon 2reg-misc op is ARMv8 and up */ @@ -6599,13 +6556,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) default: elementwise: for (pass = 0; pass < (q ? 4 : 2); pass++) { - if (neon_2rm_is_float_op(op)) { - tcg_gen_ld_f32(cpu_F0s, cpu_env, - neon_reg_offset(rm, pass)); - tmp = NULL; - } else { - tmp = neon_load_reg(rm, pass); - } + tmp = neon_load_reg(rm, pass); switch (op) { case NEON_2RM_VREV32: switch (size) { @@ -6860,29 +6811,40 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) break; } case NEON_2RM_VCVT_FS: /* VCVT.F32.S32 */ - gen_vfp_sito(0, 1); + { + TCGv_ptr fpstatus = get_fpstatus_ptr(1); + gen_helper_vfp_sitos(tmp, tmp, fpstatus); + tcg_temp_free_ptr(fpstatus); break; + } case NEON_2RM_VCVT_FU: /* VCVT.F32.U32 */ - gen_vfp_uito(0, 1); + { + TCGv_ptr fpstatus = get_fpstatus_ptr(1); + gen_helper_vfp_uitos(tmp, tmp, fpstatus); + tcg_temp_free_ptr(fpstatus); break; + } case NEON_2RM_VCVT_SF: /* VCVT.S32.F32 */ - gen_vfp_tosiz(0, 1); + { + TCGv_ptr fpstatus = get_fpstatus_ptr(1); + gen_helper_vfp_tosizs(tmp, tmp, fpstatus); + tcg_temp_free_ptr(fpstatus); break; + } case NEON_2RM_VCVT_UF: /* VCVT.U32.F32 */ - gen_vfp_touiz(0, 1); + { + TCGv_ptr fpstatus = get_fpstatus_ptr(1); + gen_helper_vfp_touizs(tmp, tmp, fpstatus); + tcg_temp_free_ptr(fpstatus); break; + } default: /* Reserved op values were caught by the * neon_2rm_sizes[] check earlier. */ abort(); } - if (neon_2rm_is_float_op(op)) { - tcg_gen_st_f32(cpu_F0s, cpu_env, - neon_reg_offset(rd, pass)); - } else { - neon_store_reg(rd, pass, tmp); - } + neon_store_reg(rd, pass, tmp); } break; } From patchwork Mon Jun 17 14:34:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 167053 Delivered-To: patch@linaro.org Received: by 2002:ac9:6410:0:0:0:0:0 with SMTP id r16csp1102572ock; Mon, 17 Jun 2019 07:56:37 -0700 (PDT) X-Google-Smtp-Source: APXvYqwQw6ee9SwSbWL0eUwwKQTSn3kYXjnBJl+P1RWw5h+5GyS+DE+aRqM3HMJsgeiJRV7Bduvn X-Received: by 2002:a17:906:4482:: with SMTP id y2mr36353263ejo.201.1560783397455; Mon, 17 Jun 2019 07:56:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560783397; cv=none; d=google.com; s=arc-20160816; b=P4Q4wYhhnkyb4Ogx1vLTkLBm8Ffc6W3CfNn4orUY0Hzpd53Z7MQ9jI1HpHlTi8InxD U0Ezo4AxDMHUmAwiJZWF8VNfkuIQP5GJ0ZuUcg+OGbUJXKajgPIt28XksrgRmnFxNFXq GJgzCMfczx+Sj9jAZ0qGbiojubhCbsRG34JvY2CACfCA7rpPqKc6MruUuyR7fvydEtQ9 L6We6Zg9DHn1ENrjJRorQPaYSv6ZVfjcTV5+rxm+B0ep63Vl0T7miHfzgr+O1dJNm/rU 0FX3wB1vbd6jVdcsVQTIEo4RG4IGekGUYU0ElYHRNfnz47Mf791G1CzvoWhXd/PuC0W5 EhzA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=58okBtFY53UueZQheoG6tvyEr1auSHKr4SvkRALekYU=; b=WbM0VgG9Pdcs8RZ3VKcIjRfnCrH8l6ysvaUOnobbFEXOkI6iI4TSmPrH5aiUNzr7x+ 0W8OGhMnv86Xtb3m/Cq3XmrtPmUHtGkY+eqwrSR4iqUtTpkTf4lEBK1gNlJFhu7ZN+Lb 2jNyWDY/cKbKkEnBLodUiCQD5uDKtJBrIb9hP2QrFLid13ePrHcBeZmoR1t1wgQpnoWH zYzzMrjWe0Bo8jwJZor24A5TC+0KYk3uFOiexY9j9yHHL6TO6Mh6iDfNKBMzwhoJTelA 5r9TmFS1LP4oWnH1GIphJFcbkXD9mp/lqv1iX3VM5rgVeI578msOEh3nVIrXPepHwRaT LfVA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=HcmL0DVH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id a67sm13819985wmh.40.2019.06.17.07.34.34 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 17 Jun 2019 07:34:34 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 17 Jun 2019 15:34:07 +0100 Message-Id: <20190617143412.5734-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190617143412.5734-1-peter.maydell@linaro.org> References: <20190617143412.5734-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 Subject: [Qemu-devel] [PULL 19/24] target/arm: Stop using cpu_F0s in Neon VCVT fixed-point ops X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Stop using cpu_F0s in the Neon VCVT fixed-point operations. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daudé Message-id: 20190613163917.28589-10-peter.maydell@linaro.org --- target/arm/translate.c | 62 +++++++++++++++++++----------------------- 1 file changed, 28 insertions(+), 34 deletions(-) -- 2.20.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 0fb94b777bf..d8b46130d42 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -80,6 +80,8 @@ static const char * const regnames[] = /* Function prototypes for gen_ functions calling Neon helpers. */ typedef void NeonGenThreeOpEnvFn(TCGv_i32, TCGv_env, TCGv_i32, TCGv_i32, TCGv_i32); +/* Function prototypes for gen_ functions for fix point conversions */ +typedef void VFPGenFixPointFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr); /* initialize TCG globals. */ void arm_translate_init(void) @@ -1374,27 +1376,6 @@ static TCGv_ptr get_fpstatus_ptr(int neon) return statusptr; } -#define VFP_GEN_FIX(name, round) \ -static inline void gen_vfp_##name(int dp, int shift, int neon) \ -{ \ - TCGv_i32 tmp_shift = tcg_const_i32(shift); \ - TCGv_ptr statusptr = get_fpstatus_ptr(neon); \ - if (dp) { \ - gen_helper_vfp_##name##d##round(cpu_F0d, cpu_F0d, tmp_shift, \ - statusptr); \ - } else { \ - gen_helper_vfp_##name##s##round(cpu_F0s, cpu_F0s, tmp_shift, \ - statusptr); \ - } \ - tcg_temp_free_i32(tmp_shift); \ - tcg_temp_free_ptr(statusptr); \ -} -VFP_GEN_FIX(tosl, _round_to_zero) -VFP_GEN_FIX(toul, _round_to_zero) -VFP_GEN_FIX(slto, ) -VFP_GEN_FIX(ulto, ) -#undef VFP_GEN_FIX - static inline long vfp_reg_offset(bool dp, unsigned reg) { if (dp) { @@ -5721,28 +5702,41 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) } } else if (op >= 14) { /* VCVT fixed-point. */ + TCGv_ptr fpst; + TCGv_i32 shiftv; + VFPGenFixPointFn *fn; + if (!(insn & (1 << 21)) || (q && ((rd | rm) & 1))) { return 1; } + + if (!(op & 1)) { + if (u) { + fn = gen_helper_vfp_ultos; + } else { + fn = gen_helper_vfp_sltos; + } + } else { + if (u) { + fn = gen_helper_vfp_touls_round_to_zero; + } else { + fn = gen_helper_vfp_tosls_round_to_zero; + } + } + /* We have already masked out the must-be-1 top bit of imm6, * hence this 32-shift where the ARM ARM has 64-imm6. */ shift = 32 - shift; + fpst = get_fpstatus_ptr(1); + shiftv = tcg_const_i32(shift); for (pass = 0; pass < (q ? 4 : 2); pass++) { - tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, pass)); - if (!(op & 1)) { - if (u) - gen_vfp_ulto(0, shift, 1); - else - gen_vfp_slto(0, shift, 1); - } else { - if (u) - gen_vfp_toul(0, shift, 1); - else - gen_vfp_tosl(0, shift, 1); - } - tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, pass)); + TCGv_i32 tmpf = neon_load_reg(rm, pass); + fn(tmpf, tmpf, shiftv, fpst); + neon_store_reg(rd, pass, tmpf); } + tcg_temp_free_ptr(fpst); + tcg_temp_free_i32(shiftv); } else { return 1; } From patchwork Mon Jun 17 14:34:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 167059 Delivered-To: patch@linaro.org Received: by 2002:ac9:6410:0:0:0:0:0 with SMTP id r16csp1109258ock; Mon, 17 Jun 2019 08:02:49 -0700 (PDT) X-Google-Smtp-Source: APXvYqyHCE9ZUihxzNgFpyn5Fx/Sc74dZkMU7MZvQ3QBLC4mO6YAl1Xs+TgojZMdlN+8v6kAlN5e X-Received: by 2002:a1c:9a46:: with SMTP id c67mr16890177wme.11.1560783769179; Mon, 17 Jun 2019 08:02:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560783769; cv=none; d=google.com; s=arc-20160816; b=O0Hyt7JuPxVWAsCqTYngCrn88mKydHsvHBxtSIhcKxuvh8oDNkrPzGDpukeZTGy881 6EQhG6UqlK5+bGrSztFvkK8Xsx6L/XotLvKymtKQ3fCa6CHXt+O8xAZmOJz+X1Ax4Iu8 uYHtbhrtnYhth7jTMkBZaQx3f1tvMPKz9oBoBejfhL7hMvRd8JfFszU++M2rmKttNHUp qY5WT1b2jECMUAgqwjhfeJ4lnzDxoImT6EiThOVG/Kw60N6p7Mupk1I3fIg7oatKMdF8 tvGOkjszxZ2BjvemefoAFuamBoPf6TW2vADeato9LuqpjYMSJfovr/nrRy6XlH1xmblT z3tQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=I+75XYVbaOE0Z2VDKw9wMsw3L7xan4AZtISiVXygjxo=; b=mRN7vl/PTwcyI7M3d5KY9SWBGHnh8kgS53WwriJs1TbUoeVL0ZWmi81naRNX+smhjK chFzlJe8f1JpFIglmgUIRGoeq94AVAu4W0SIeMBQBq/6NqERmfrMWClZmTHpWfGgGMH+ 58SZRM0GGw+1o5do3tgfBi+fUUgJXFZ5Ve33BUCBH+lqsv6PthQ8NshIEkGnOFIaxGua m1FoWnCM1a3mVQsYhZh73DLh3cEET8bLdelDQevuRUnoeLiY3htnOFR1o41FflWRpFXC x1ikbnO31dcV448kfvsODe3tIowqR5ob3MDfagqVAafAJT0GzFDlm0Ql5K+iOy0VH7iz vWxw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=n31Y7vMm; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id a67sm13819985wmh.40.2019.06.17.07.34.35 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 17 Jun 2019 07:34:35 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 17 Jun 2019 15:34:08 +0100 Message-Id: <20190617143412.5734-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190617143412.5734-1-peter.maydell@linaro.org> References: <20190617143412.5734-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 Subject: [Qemu-devel] [PULL 20/24] target/arm: stop using deprecated functions in NEON_2RM_VCVT_F16_F32 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Remove some old constructs from NEON_2RM_VCVT_F16_F32 code: * don't use cpu_F0s * don't use tcg_gen_ld_f32 Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daudé Message-id: 20190613163917.28589-11-peter.maydell@linaro.org --- target/arm/translate.c | 27 ++++++++++++--------------- 1 file changed, 12 insertions(+), 15 deletions(-) -- 2.20.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index d8b46130d42..2ba620ac1e1 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1542,7 +1542,6 @@ static TCGv_ptr vfp_reg_ptr(bool dp, int reg) return ret; } -#define tcg_gen_ld_f32 tcg_gen_ld_i32 #define tcg_gen_st_f32 tcg_gen_st_i32 #define ARM_CP_RW_BIT (1 << 20) @@ -6425,25 +6424,23 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) q || (rm & 1)) { return 1; } - tmp = tcg_temp_new_i32(); - tmp2 = tcg_temp_new_i32(); fpst = get_fpstatus_ptr(true); ahp = get_ahp_flag(); - tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 0)); - gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, fpst, ahp); - tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 1)); - gen_helper_vfp_fcvt_f32_to_f16(tmp2, cpu_F0s, fpst, ahp); + tmp = neon_load_reg(rm, 0); + gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp); + tmp2 = neon_load_reg(rm, 1); + gen_helper_vfp_fcvt_f32_to_f16(tmp2, tmp2, fpst, ahp); tcg_gen_shli_i32(tmp2, tmp2, 16); tcg_gen_or_i32(tmp2, tmp2, tmp); - tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 2)); - gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, fpst, ahp); - tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 3)); + tcg_temp_free_i32(tmp); + tmp = neon_load_reg(rm, 2); + gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp); + tmp3 = neon_load_reg(rm, 3); neon_store_reg(rd, 0, tmp2); - tmp2 = tcg_temp_new_i32(); - gen_helper_vfp_fcvt_f32_to_f16(tmp2, cpu_F0s, fpst, ahp); - tcg_gen_shli_i32(tmp2, tmp2, 16); - tcg_gen_or_i32(tmp2, tmp2, tmp); - neon_store_reg(rd, 1, tmp2); + gen_helper_vfp_fcvt_f32_to_f16(tmp3, tmp3, fpst, ahp); + tcg_gen_shli_i32(tmp3, tmp3, 16); + tcg_gen_or_i32(tmp3, tmp3, tmp); + neon_store_reg(rd, 1, tmp3); tcg_temp_free_i32(tmp); tcg_temp_free_i32(ahp); tcg_temp_free_ptr(fpst); From patchwork Mon Jun 17 14:34:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 167072 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp3023949ilk; Mon, 17 Jun 2019 08:47:28 -0700 (PDT) X-Google-Smtp-Source: APXvYqxpwP4xmyLj9cnAqvTR1L3JtfNCcaC4JCITxCfEhSvmqSPYzINBldpvQo+rNQDhXBL1ig/F X-Received: by 2002:a50:9456:: with SMTP id q22mr100979948eda.28.1560786448219; Mon, 17 Jun 2019 08:47:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560786448; cv=none; d=google.com; s=arc-20160816; b=x7biNFO8C4ggV1mlJM8U7SiADI87+c9DiRQsCSsY+0cxQDVJ5btveH8ow0CIIEhB1J oyMsnsRBlO9vW+YiqfqAwN+HEJbZIBHJk2yKv5lITY4HqdIZyJXTp5OmzrC5VJQveTWH grdEWrpRE6dtl4cjfXL0XjuDP3AmlJ4Tv7M/ISjlfjrnnzHiUGt2Rtu31pXP1pv/byop nfliSXRdlfxoD2YWLaMZh05AsjyOrTFSXs1NLrbDA0qvjL5cyV6ZE8CAtecdelhlHG4q 9xqXs0e4BZy0Bqa5TjsUhX8MczTZORnuFpMNfH4oyBh5q1qZZtIrl2DgGVWJuPMvek5b jkfw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=XTL6vXsjTHflOLJ+e9+ddR0nb34AKoiPztLrrZicDQo=; b=PPTcYoYlhPwmeMICXgswmNoVT4iTCN6JTptDdxry5681drSyxwosmyDr17DX0JUsVN CSm2rW1yeCCzdODx8GXM5D8xX9sii5rmnusd0KCXrq0e9ilLej2NNhtuqOXTSoDYZraK Cpa2xWT0agx/lN4GO5PEPyFcq2CimqcKVAlC0U+yC2+NKkqFHNmL7cEgCuqZNKm3D6+c FqHFFWCgae6gPeX9CJVXiWfmk/oX3D2+/NF3W4OCZeMX3knFz9m2lA4/nrTOW5fVWnzE +N9KQeW25/0JNTsyITlbc+CSii7SSj4kzuesw0+kq5mUzAyRZLd/jzrl8vXjBpOgWLiE 3YTA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=jBRTNCWh; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id a67sm13819985wmh.40.2019.06.17.07.34.36 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 17 Jun 2019 07:34:36 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 17 Jun 2019 15:34:09 +0100 Message-Id: <20190617143412.5734-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190617143412.5734-1-peter.maydell@linaro.org> References: <20190617143412.5734-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 Subject: [Qemu-devel] [PULL 21/24] target/arm: Stop using deprecated functions in NEON_2RM_VCVT_F32_F16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Remove some old constructns from NEON_2RM_VCVT_F16_F32 code: * don't use CPU_F0s * don't use tcg_gen_st_f32 Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daudé Message-id: 20190613163917.28589-12-peter.maydell@linaro.org --- target/arm/translate.c | 26 +++++++++++--------------- 1 file changed, 11 insertions(+), 15 deletions(-) -- 2.20.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 2ba620ac1e1..8f124a953b6 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1542,8 +1542,6 @@ static TCGv_ptr vfp_reg_ptr(bool dp, int reg) return ret; } -#define tcg_gen_st_f32 tcg_gen_st_i32 - #define ARM_CP_RW_BIT (1 << 20) /* Include the VFP decoder */ @@ -6460,20 +6458,18 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) tmp = neon_load_reg(rm, 0); tmp2 = neon_load_reg(rm, 1); tcg_gen_ext16u_i32(tmp3, tmp); - gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp3, fpst, ahp); - tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 0)); - tcg_gen_shri_i32(tmp3, tmp, 16); - gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp3, fpst, ahp); - tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 1)); - tcg_temp_free_i32(tmp); + gen_helper_vfp_fcvt_f16_to_f32(tmp3, tmp3, fpst, ahp); + neon_store_reg(rd, 0, tmp3); + tcg_gen_shri_i32(tmp, tmp, 16); + gen_helper_vfp_fcvt_f16_to_f32(tmp, tmp, fpst, ahp); + neon_store_reg(rd, 1, tmp); + tmp3 = tcg_temp_new_i32(); tcg_gen_ext16u_i32(tmp3, tmp2); - gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp3, fpst, ahp); - tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 2)); - tcg_gen_shri_i32(tmp3, tmp2, 16); - gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp3, fpst, ahp); - tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 3)); - tcg_temp_free_i32(tmp2); - tcg_temp_free_i32(tmp3); + gen_helper_vfp_fcvt_f16_to_f32(tmp3, tmp3, fpst, ahp); + neon_store_reg(rd, 2, tmp3); + tcg_gen_shri_i32(tmp2, tmp2, 16); + gen_helper_vfp_fcvt_f16_to_f32(tmp2, tmp2, fpst, ahp); + neon_store_reg(rd, 3, tmp2); tcg_temp_free_i32(ahp); tcg_temp_free_ptr(fpst); break; From patchwork Mon Jun 17 14:34:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 167061 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp2978297ilk; Mon, 17 Jun 2019 08:06:26 -0700 (PDT) X-Google-Smtp-Source: APXvYqzOAUtyxg48dFEDwtpf5K+72wVInmi/tJyurEKWct5YxcTnAF7ZJaKfH3Yk1euW8bE+Q4Zg X-Received: by 2002:a17:906:3953:: with SMTP id g19mr44171125eje.242.1560783986482; Mon, 17 Jun 2019 08:06:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560783986; cv=none; d=google.com; s=arc-20160816; b=rPUNyvrcPNKwmZsfBVa9KZaoj8+041g/k4cV619pqJLf7+FsK/qjOF/OWerDATEOr0 QiqXwJbHcqU1BphlwSQ4wUeNTIkp7vCTwREOoGb0NkhDiD5veaY2G0UHKLgvSZstFaRe 1DFONbmW1ZtTgTn2UmL23aQulD1qT90MEXSmaG6iewxGz2qjYkJFDJ5ce6C1XAaJK5xK dQW+KKoyPVnKKYNsR/8YYZ4w0WZ97avUWKre2FDrEMeQWAPZegxe0ytDFMQpC4HzVb/2 VJ6xOMPud3Rd0M73txmn+j+JD7i7jcThev1LaHqN1WbLlu4deeNqa8/xCTS8R58Xlhd3 ZjGQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=LDkGhdEmd/3w+lVgH7xwzSp5iBC3yN2clKihNtTszW0=; b=0KgnySGwbeOdOZr2EM0biegk46Z4J95CvLJ1Bdkix7rmiURy9WBUInrHejbCVGPz3g HgWSP9QN64GPgzVvTLdLTngK9Jm6lrcFfUcjPAQphagW4OBvepCyvOv/XnongWyymBjl +oKfdvvsKLytUd6pjLm9KivnXIN4ZJd1AoGgdH+5rnDokBOMDGHYfCoo0qSy0RW1fJ/v ZjVGsISq3r2eHvZFXXY7rYcnQ2pwfvomprsnW+q2eImorswmQAfUqbEDSpXCn/8riceE 47a36QLsTmv6F3zMkbg8XLpIVGuVyUgeOdSNcEBJvpgU5+zc1TdbTzpkQgWkF62VyZSD 8pyw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=FRcDRMwF; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id a67sm13819985wmh.40.2019.06.17.07.34.37 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 17 Jun 2019 07:34:37 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 17 Jun 2019 15:34:10 +0100 Message-Id: <20190617143412.5734-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190617143412.5734-1-peter.maydell@linaro.org> References: <20190617143412.5734-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 Subject: [Qemu-devel] [PULL 22/24] target/arm: Remove unused cpu_F0s, cpu_F0d, cpu_F1s, cpu_F1d X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Remove the now unused TCG globals cpu_F0s, cpu_F0d, cpu_F1s, cpu_F1d. cpu_M0 is still used by the iwmmxt code, and cpu_V0 and cpu_V1 are used by both iwmmxt and Neon. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daudé Message-id: 20190613163917.28589-13-peter.maydell@linaro.org --- target/arm/translate.c | 12 ++---------- 1 file changed, 2 insertions(+), 10 deletions(-) -- 2.20.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 8f124a953b6..4750b9fa1bb 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -67,10 +67,6 @@ TCGv_i32 cpu_CF, cpu_NF, cpu_VF, cpu_ZF; TCGv_i64 cpu_exclusive_addr; TCGv_i64 cpu_exclusive_val; -/* FIXME: These should be removed. */ -static TCGv_i32 cpu_F0s, cpu_F1s; -static TCGv_i64 cpu_F0d, cpu_F1d; - #include "exec/gen-icount.h" static const char * const regnames[] = @@ -11911,12 +11907,8 @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) dc->base.max_insns = MIN(dc->base.max_insns, bound); } - cpu_F0s = tcg_temp_new_i32(); - cpu_F1s = tcg_temp_new_i32(); - cpu_F0d = tcg_temp_new_i64(); - cpu_F1d = tcg_temp_new_i64(); - cpu_V0 = cpu_F0d; - cpu_V1 = cpu_F1d; + cpu_V0 = tcg_temp_new_i64(); + cpu_V1 = tcg_temp_new_i64(); /* FIXME: cpu_M0 can probably be the same as cpu_V0. */ cpu_M0 = tcg_temp_new_i64(); } From patchwork Mon Jun 17 14:34:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 167062 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp2980929ilk; Mon, 17 Jun 2019 08:08:24 -0700 (PDT) X-Google-Smtp-Source: APXvYqxi8zB1t+bo1GvgKIXzq1jyeBV74XYaPiCtohAtq8OaRrLZ6YtOiQ1UYDIUyTX+36c/RuFO X-Received: by 2002:a17:906:708d:: with SMTP id b13mr15937927ejk.89.1560784103914; Mon, 17 Jun 2019 08:08:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560784103; cv=none; d=google.com; s=arc-20160816; b=1ABnfsY40fcBmNLEjs23JbA4mBAXLgs0iU9kgcqbysv40eMxluDtZt3vJd0jau0SDW yYRDsCY8zFQ9YJb0dtvyxnRBJ9ADEYtfghoR+SxqojL3yFcaMVUnYSXTQEbfCUx8q8on SL1Kh/LQWRDRbgq4/o2R/h1cXF0y0jOdLu8gYJpyXzkuYFGkGc4RPPDiX3w9NvnkffNL 8XBuj8XF0fG3kzQ+TzEounjOhNU57dVl08vzijz1bcZ/JwPSzQfK7zLCM+0Y/hG112zh DwSXan7P+DHgy5soLVAPNecqdxbi2Wh8XjK0QmZk+CKgQoGDUn52cF9Kl1q/7nSojMC2 77zA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=HRNOi6ICfUn/2quaFaB6uVzcnt5OTh3SvAEE3S908PQ=; b=VmCzsBc20MonuhFg9J4AwGfQlQzpOYgaZ5VrtMD9+fAmDV3Cmpsq4PTVWTEIxhQQIX 8ynjv8ghgfpLusB+xdv479owlLADCNlS1FnVQrWFSGTeLd+u4E45D2OHgqQSsNN1gJPK ZJmX8oHpwfoRwSv0OIBZkv1TzphOy1Aqt/tgJEVAElslubyk9cPceFtPIUxqNfK9p24W YGwFYZEiECFJhUnxzqvOcXBp/yworzj8LhqfOeNuUt5V8rZTfse7lgHinfVrSi10LclY TOP6HmfWjsaHedmozsdXT1EVExlIIDbZe87sN3lvXZZWyHSMONChfXHmANjs1Byv8cAy OLhg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=rVHp5i6m; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id a67sm13819985wmh.40.2019.06.17.07.34.38 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 17 Jun 2019 07:34:38 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 17 Jun 2019 15:34:11 +0100 Message-Id: <20190617143412.5734-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190617143412.5734-1-peter.maydell@linaro.org> References: <20190617143412.5734-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::429 Subject: [Qemu-devel] [PULL 23/24] target/arm: Fix typos in trans function prototypes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In several places cut and paste errors meant we were using the wrong type for the 'arg' struct in trans_ functions called by the decodetree decoder, because we were using the _sp version of the struct in the _dp function. These were harmless, because the two structs were identical and so decodetree made them typedefs of the same underlying structure (and we'd have had a compile error if they were not harmless), but we should clean them up anyway. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Message-id: 20190614104457.24703-2-peter.maydell@linaro.org --- target/arm/translate-vfp.inc.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) -- 2.20.1 diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index 8b732761f26..390441a1104 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -868,7 +868,7 @@ static bool trans_VMOV_64_sp(DisasContext *s, arg_VMOV_64_sp *a) return true; } -static bool trans_VMOV_64_dp(DisasContext *s, arg_VMOV_64_sp *a) +static bool trans_VMOV_64_dp(DisasContext *s, arg_VMOV_64_dp *a) { TCGv_i32 tmp; @@ -943,7 +943,7 @@ static bool trans_VLDR_VSTR_sp(DisasContext *s, arg_VLDR_VSTR_sp *a) return true; } -static bool trans_VLDR_VSTR_dp(DisasContext *s, arg_VLDR_VSTR_sp *a) +static bool trans_VLDR_VSTR_dp(DisasContext *s, arg_VLDR_VSTR_dp *a) { uint32_t offset; TCGv_i32 addr; @@ -1533,7 +1533,7 @@ static void gen_VMLA_dp(TCGv_i64 vd, TCGv_i64 vn, TCGv_i64 vm, TCGv_ptr fpst) tcg_temp_free_i64(tmp); } -static bool trans_VMLA_dp(DisasContext *s, arg_VMLA_sp *a) +static bool trans_VMLA_dp(DisasContext *s, arg_VMLA_dp *a) { return do_vfp_3op_dp(s, gen_VMLA_dp, a->vd, a->vn, a->vm, true); } @@ -1571,7 +1571,7 @@ static void gen_VMLS_dp(TCGv_i64 vd, TCGv_i64 vn, TCGv_i64 vm, TCGv_ptr fpst) tcg_temp_free_i64(tmp); } -static bool trans_VMLS_dp(DisasContext *s, arg_VMLS_sp *a) +static bool trans_VMLS_dp(DisasContext *s, arg_VMLS_dp *a) { return do_vfp_3op_dp(s, gen_VMLS_dp, a->vd, a->vn, a->vm, true); } @@ -1613,7 +1613,7 @@ static void gen_VNMLS_dp(TCGv_i64 vd, TCGv_i64 vn, TCGv_i64 vm, TCGv_ptr fpst) tcg_temp_free_i64(tmp); } -static bool trans_VNMLS_dp(DisasContext *s, arg_VNMLS_sp *a) +static bool trans_VNMLS_dp(DisasContext *s, arg_VNMLS_dp *a) { return do_vfp_3op_dp(s, gen_VNMLS_dp, a->vd, a->vn, a->vm, true); } @@ -1647,7 +1647,7 @@ static void gen_VNMLA_dp(TCGv_i64 vd, TCGv_i64 vn, TCGv_i64 vm, TCGv_ptr fpst) tcg_temp_free_i64(tmp); } -static bool trans_VNMLA_dp(DisasContext *s, arg_VNMLA_sp *a) +static bool trans_VNMLA_dp(DisasContext *s, arg_VNMLA_dp *a) { return do_vfp_3op_dp(s, gen_VNMLA_dp, a->vd, a->vn, a->vm, true); } @@ -1657,7 +1657,7 @@ static bool trans_VMUL_sp(DisasContext *s, arg_VMUL_sp *a) return do_vfp_3op_sp(s, gen_helper_vfp_muls, a->vd, a->vn, a->vm, false); } -static bool trans_VMUL_dp(DisasContext *s, arg_VMUL_sp *a) +static bool trans_VMUL_dp(DisasContext *s, arg_VMUL_dp *a) { return do_vfp_3op_dp(s, gen_helper_vfp_muld, a->vd, a->vn, a->vm, false); } @@ -1681,7 +1681,7 @@ static void gen_VNMUL_dp(TCGv_i64 vd, TCGv_i64 vn, TCGv_i64 vm, TCGv_ptr fpst) gen_helper_vfp_negd(vd, vd); } -static bool trans_VNMUL_dp(DisasContext *s, arg_VNMUL_sp *a) +static bool trans_VNMUL_dp(DisasContext *s, arg_VNMUL_dp *a) { return do_vfp_3op_dp(s, gen_VNMUL_dp, a->vd, a->vn, a->vm, false); } @@ -1691,7 +1691,7 @@ static bool trans_VADD_sp(DisasContext *s, arg_VADD_sp *a) return do_vfp_3op_sp(s, gen_helper_vfp_adds, a->vd, a->vn, a->vm, false); } -static bool trans_VADD_dp(DisasContext *s, arg_VADD_sp *a) +static bool trans_VADD_dp(DisasContext *s, arg_VADD_dp *a) { return do_vfp_3op_dp(s, gen_helper_vfp_addd, a->vd, a->vn, a->vm, false); } @@ -1701,7 +1701,7 @@ static bool trans_VSUB_sp(DisasContext *s, arg_VSUB_sp *a) return do_vfp_3op_sp(s, gen_helper_vfp_subs, a->vd, a->vn, a->vm, false); } -static bool trans_VSUB_dp(DisasContext *s, arg_VSUB_sp *a) +static bool trans_VSUB_dp(DisasContext *s, arg_VSUB_dp *a) { return do_vfp_3op_dp(s, gen_helper_vfp_subd, a->vd, a->vn, a->vm, false); } @@ -1711,7 +1711,7 @@ static bool trans_VDIV_sp(DisasContext *s, arg_VDIV_sp *a) return do_vfp_3op_sp(s, gen_helper_vfp_divs, a->vd, a->vn, a->vm, false); } -static bool trans_VDIV_dp(DisasContext *s, arg_VDIV_sp *a) +static bool trans_VDIV_dp(DisasContext *s, arg_VDIV_dp *a) { return do_vfp_3op_dp(s, gen_helper_vfp_divd, a->vd, a->vn, a->vm, false); } @@ -1774,7 +1774,7 @@ static bool trans_VFM_sp(DisasContext *s, arg_VFM_sp *a) return true; } -static bool trans_VFM_dp(DisasContext *s, arg_VFM_sp *a) +static bool trans_VFM_dp(DisasContext *s, arg_VFM_dp *a) { /* * VFNMA : fd = muladd(-fd, fn, fm) @@ -2214,7 +2214,7 @@ static bool trans_VRINTR_sp(DisasContext *s, arg_VRINTR_sp *a) return true; } -static bool trans_VRINTR_dp(DisasContext *s, arg_VRINTR_sp *a) +static bool trans_VRINTR_dp(DisasContext *s, arg_VRINTR_dp *a) { TCGv_ptr fpst; TCGv_i64 tmp; @@ -2270,7 +2270,7 @@ static bool trans_VRINTZ_sp(DisasContext *s, arg_VRINTZ_sp *a) return true; } -static bool trans_VRINTZ_dp(DisasContext *s, arg_VRINTZ_sp *a) +static bool trans_VRINTZ_dp(DisasContext *s, arg_VRINTZ_dp *a) { TCGv_ptr fpst; TCGv_i64 tmp; From patchwork Mon Jun 17 14:34:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 167056 Delivered-To: patch@linaro.org Received: by 2002:ac9:6410:0:0:0:0:0 with SMTP id r16csp1103907ock; Mon, 17 Jun 2019 07:58:11 -0700 (PDT) X-Google-Smtp-Source: APXvYqzVH8Zgmp7MR5B+/i9zejDVMIq4j857GyAMxSPleDo6gr3vSxnriklNtwHQosf3sIv9qK82 X-Received: by 2002:a50:a5e7:: with SMTP id b36mr92973150edc.301.1560783491700; Mon, 17 Jun 2019 07:58:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560783491; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id a67sm13819985wmh.40.2019.06.17.07.34.39 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 17 Jun 2019 07:34:39 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 17 Jun 2019 15:34:12 +0100 Message-Id: <20190617143412.5734-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190617143412.5734-1-peter.maydell@linaro.org> References: <20190617143412.5734-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 Subject: [Qemu-devel] [PULL 24/24] target/arm: Only implement doubles if the FPU supports them X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The architecture permits FPUs which have only single-precision support, not double-precision; Cortex-M4 and Cortex-M33 are both like that. Add the necessary checks on the MVFR0 FPDP field so that we UNDEF any double-precision instructions on CPUs like this. Note that even if FPDP==0 the insns like VMOV-to/from-gpreg, VLDM/VSTM, VLDR/VSTR which take double precision registers still exist. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20190614104457.24703-3-peter.maydell@linaro.org --- target/arm/cpu.h | 6 +++ target/arm/translate-vfp.inc.c | 84 ++++++++++++++++++++++++++++++++++ 2 files changed, 90 insertions(+) -- 2.20.1 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index a98c45b1ff0..f9da672be57 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3388,6 +3388,12 @@ static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id) return FIELD_EX64(id->mvfr0, MVFR0, FPSHVEC) > 0; } +static inline bool isar_feature_aa32_fpdp(const ARMISARegisters *id) +{ + /* Return true if CPU supports double precision floating point */ + return FIELD_EX64(id->mvfr0, MVFR0, FPDP) > 0; +} + /* * We always set the FP and SIMD FP16 fields to indicate identical * levels of support (assuming SIMD is implemented at all), so diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index 390441a1104..348173d6026 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -206,6 +206,11 @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a) ((a->vm | a->vn | a->vd) & 0x10)) { return false; } + + if (dp && !dc_isar_feature(aa32_fpdp, s)) { + return false; + } + rd = a->vd; rn = a->vn; rm = a->vm; @@ -334,6 +339,11 @@ static bool trans_VMINMAXNM(DisasContext *s, arg_VMINMAXNM *a) ((a->vm | a->vn | a->vd) & 0x10)) { return false; } + + if (dp && !dc_isar_feature(aa32_fpdp, s)) { + return false; + } + rd = a->vd; rn = a->vn; rm = a->vm; @@ -415,6 +425,11 @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a) ((a->vm | a->vd) & 0x10)) { return false; } + + if (dp && !dc_isar_feature(aa32_fpdp, s)) { + return false; + } + rd = a->vd; rm = a->vm; @@ -473,6 +488,11 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a) if (dp && !dc_isar_feature(aa32_fp_d32, s) && (a->vm & 0x10)) { return false; } + + if (dp && !dc_isar_feature(aa32_fpdp, s)) { + return false; + } + rd = a->vd; rm = a->vm; @@ -1301,6 +1321,10 @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3OpDPFn *fn, return false; } + if (!dc_isar_feature(aa32_fpdp, s)) { + return false; + } + if (!dc_isar_feature(aa32_fpshvec, s) && (veclen != 0 || s->vec_stride != 0)) { return false; @@ -1446,6 +1470,10 @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpDPFn *fn, int vd, int vm) return false; } + if (!dc_isar_feature(aa32_fpdp, s)) { + return false; + } + if (!dc_isar_feature(aa32_fpshvec, s) && (veclen != 0 || s->vec_stride != 0)) { return false; @@ -1743,6 +1771,10 @@ static bool trans_VFM_sp(DisasContext *s, arg_VFM_sp *a) return false; } + if (!dc_isar_feature(aa32_fpdp, s)) { + return false; + } + if (!vfp_access_check(s)) { return true; } @@ -1901,6 +1933,10 @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_VMOV_imm_dp *a) return false; } + if (!dc_isar_feature(aa32_fpdp, s)) { + return false; + } + if (!dc_isar_feature(aa32_fpshvec, s) && (veclen != 0 || s->vec_stride != 0)) { return false; @@ -2041,6 +2077,10 @@ static bool trans_VCMP_dp(DisasContext *s, arg_VCMP_dp *a) return false; } + if (!dc_isar_feature(aa32_fpdp, s)) { + return false; + } + if (!vfp_access_check(s)) { return true; } @@ -2110,6 +2150,10 @@ static bool trans_VCVT_f64_f16(DisasContext *s, arg_VCVT_f64_f16 *a) return false; } + if (!dc_isar_feature(aa32_fpdp, s)) { + return false; + } + if (!vfp_access_check(s)) { return true; } @@ -2172,6 +2216,10 @@ static bool trans_VCVT_f16_f64(DisasContext *s, arg_VCVT_f16_f64 *a) return false; } + if (!dc_isar_feature(aa32_fpdp, s)) { + return false; + } + if (!vfp_access_check(s)) { return true; } @@ -2228,6 +2276,10 @@ static bool trans_VRINTR_dp(DisasContext *s, arg_VRINTR_dp *a) return false; } + if (!dc_isar_feature(aa32_fpdp, s)) { + return false; + } + if (!vfp_access_check(s)) { return true; } @@ -2285,6 +2337,10 @@ static bool trans_VRINTZ_dp(DisasContext *s, arg_VRINTZ_dp *a) return false; } + if (!dc_isar_feature(aa32_fpdp, s)) { + return false; + } + if (!vfp_access_check(s)) { return true; } @@ -2340,6 +2396,10 @@ static bool trans_VRINTX_dp(DisasContext *s, arg_VRINTX_dp *a) return false; } + if (!dc_isar_feature(aa32_fpdp, s)) { + return false; + } + if (!vfp_access_check(s)) { return true; } @@ -2364,6 +2424,10 @@ static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_sp *a) return false; } + if (!dc_isar_feature(aa32_fpdp, s)) { + return false; + } + if (!vfp_access_check(s)) { return true; } @@ -2388,6 +2452,10 @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_dp *a) return false; } + if (!dc_isar_feature(aa32_fpdp, s)) { + return false; + } + if (!vfp_access_check(s)) { return true; } @@ -2438,6 +2506,10 @@ static bool trans_VCVT_int_dp(DisasContext *s, arg_VCVT_int_dp *a) return false; } + if (!dc_isar_feature(aa32_fpdp, s)) { + return false; + } + if (!vfp_access_check(s)) { return true; } @@ -2474,6 +2546,10 @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a) return false; } + if (!dc_isar_feature(aa32_fpdp, s)) { + return false; + } + if (!vfp_access_check(s)) { return true; } @@ -2563,6 +2639,10 @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_VCVT_fix_dp *a) return false; } + if (!dc_isar_feature(aa32_fpdp, s)) { + return false; + } + if (!vfp_access_check(s)) { return true; } @@ -2655,6 +2735,10 @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_VCVT_dp_int *a) return false; } + if (!dc_isar_feature(aa32_fpdp, s)) { + return false; + } + if (!vfp_access_check(s)) { return true; }