From patchwork Tue Jun 13 12:58:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xingyu Wu X-Patchwork-Id: 692237 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 86830EB64D9 for ; Tue, 13 Jun 2023 13:28:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242586AbjFMNgZ convert rfc822-to-8bit (ORCPT ); Tue, 13 Jun 2023 09:36:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42414 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242575AbjFMNgX (ORCPT ); Tue, 13 Jun 2023 09:36:23 -0400 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DACCB1715; Tue, 13 Jun 2023 06:36:20 -0700 (PDT) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id D58CB24DCF1; Tue, 13 Jun 2023 21:36:11 +0800 (CST) Received: from EXMBX061.cuchost.com (172.16.6.61) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 13 Jun 2023 20:58:55 +0800 Received: from localhost.localdomain (113.72.145.34) by EXMBX061.cuchost.com (172.16.6.61) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 13 Jun 2023 20:58:54 +0800 From: Xingyu Wu To: , , "Michael Turquette" , Stephen Boyd , "Rob Herring" , Krzysztof Kozlowski , Philipp Zabel , Conor Dooley , Emil Renner Berthing CC: Paul Walmsley , Palmer Dabbelt , Albert Ou , Hal Feng , Xingyu Wu , "William Qiu" , , Subject: [PATCH v5 2/7] dt-bindings: soc: starfive: Add StarFive syscon module Date: Tue, 13 Jun 2023 20:58:47 +0800 Message-ID: <20230613125852.211636-3-xingyu.wu@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230613125852.211636-1-xingyu.wu@starfivetech.com> References: <20230613125852.211636-1-xingyu.wu@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [113.72.145.34] X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX061.cuchost.com (172.16.6.61) X-YovoleRuleAgent: yovoleflag Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: William Qiu Add documentation to describe StarFive System Controller Registers. Co-developed-by: Xingyu Wu Signed-off-by: Xingyu Wu Signed-off-by: William Qiu --- .../soc/starfive/starfive,jh7110-syscon.yaml | 62 +++++++++++++++++++ MAINTAINERS | 7 +++ 2 files changed, 69 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml diff --git a/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml new file mode 100644 index 000000000000..a81190f8a54d --- /dev/null +++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/starfive/starfive,jh7110-syscon.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7110 SoC system controller + +maintainers: + - William Qiu + +description: | + The StarFive JH7110 SoC system controller provides register information such + as offset, mask and shift to configure related modules such as MMC and PCIe. + +properties: + compatible: + oneOf: + - items: + - const: starfive,jh7110-sys-syscon + - const: syscon + - const: simple-mfd + - items: + - enum: + - starfive,jh7110-aon-syscon + - starfive,jh7110-stg-syscon + - const: syscon + + reg: + maxItems: 1 + + clock-controller: + $ref: /schemas/clock/starfive,jh7110-pll.yaml# + type: object + + "#power-domain-cells": + const: 1 + +required: + - compatible + - reg + +allOf: + - if: + properties: + compatible: + contains: + const: starfive,jh7110-aon-syscon + then: + required: + - "#power-domain-cells" + +additionalProperties: false + +examples: + - | + syscon@10240000 { + compatible = "starfive,jh7110-stg-syscon", "syscon"; + reg = <0x10240000 0x1000>; + }; + +... diff --git a/MAINTAINERS b/MAINTAINERS index f794002a192e..ae037ba7fc47 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20122,6 +20122,12 @@ S: Supported F: Documentation/devicetree/bindings/mmc/starfive* F: drivers/mmc/host/dw_mmc-starfive.c +STARFIVE JH7110 SYSCON +M: William Qiu +M: Xingyu Wu +S: Supported +F: Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml + STARFIVE JH71X0 CLOCK DRIVERS M: Emil Renner Berthing M: Hal Feng @@ -20159,6 +20165,7 @@ STARFIVE SOC DRIVERS M: Conor Dooley S: Maintained T: git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ +F: Documentation/devicetree/bindings/soc/starfive/ F: drivers/soc/starfive/ STARFIVE TRNG DRIVER From patchwork Tue Jun 13 12:58:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xingyu Wu X-Patchwork-Id: 692238 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B4B80C04A94 for ; Tue, 13 Jun 2023 13:28:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239579AbjFMNgT convert rfc822-to-8bit (ORCPT ); Tue, 13 Jun 2023 09:36:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42386 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241006AbjFMNgS (ORCPT ); Tue, 13 Jun 2023 09:36:18 -0400 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 61C1110DF; Tue, 13 Jun 2023 06:36:14 -0700 (PDT) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id ECF627FF9; Tue, 13 Jun 2023 21:36:11 +0800 (CST) Received: from EXMBX061.cuchost.com (172.16.6.61) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 13 Jun 2023 20:58:58 +0800 Received: from localhost.localdomain (113.72.145.34) by EXMBX061.cuchost.com (172.16.6.61) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 13 Jun 2023 20:58:57 +0800 From: Xingyu Wu To: , , "Michael Turquette" , Stephen Boyd , "Rob Herring" , Krzysztof Kozlowski , Philipp Zabel , Conor Dooley , Emil Renner Berthing CC: Paul Walmsley , Palmer Dabbelt , Albert Ou , Hal Feng , Xingyu Wu , "William Qiu" , , Subject: [PATCH v5 6/7] riscv: dts: starfive: jh7110: Add syscon nodes Date: Tue, 13 Jun 2023 20:58:51 +0800 Message-ID: <20230613125852.211636-7-xingyu.wu@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230613125852.211636-1-xingyu.wu@starfivetech.com> References: <20230613125852.211636-1-xingyu.wu@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [113.72.145.34] X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX061.cuchost.com (172.16.6.61) X-YovoleRuleAgent: yovoleflag Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: William Qiu Add stg_syscon/sys_syscon/aon_syscon/PLL nodes for JH7110 Soc. Co-developed-by: Xingyu Wu Signed-off-by: Xingyu Wu Signed-off-by: William Qiu --- arch/riscv/boot/dts/starfive/jh7110.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index 4c5fdb905da8..11dd4c9d64b0 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -353,6 +353,11 @@ i2c2: i2c@10050000 { status = "disabled"; }; + stg_syscon: syscon@10240000 { + compatible = "starfive,jh7110-stg-syscon", "syscon"; + reg = <0x0 0x10240000 0x0 0x1000>; + }; + uart3: serial@12000000 { compatible = "snps,dw-apb-uart"; reg = <0x0 0x12000000 0x0 0x10000>; @@ -457,6 +462,17 @@ syscrg: clock-controller@13020000 { #reset-cells = <1>; }; + sys_syscon: syscon@13030000 { + compatible = "starfive,jh7110-sys-syscon", "syscon", "simple-mfd"; + reg = <0x0 0x13030000 0x0 0x1000>; + + pllclk: clock-controller { + compatible = "starfive,jh7110-pll"; + clocks = <&osc>; + #clock-cells = <1>; + }; + }; + sysgpio: pinctrl@13040000 { compatible = "starfive,jh7110-sys-pinctrl"; reg = <0x0 0x13040000 0x0 0x10000>; @@ -486,6 +502,12 @@ aoncrg: clock-controller@17000000 { #reset-cells = <1>; }; + aon_syscon: syscon@17010000 { + compatible = "starfive,jh7110-aon-syscon", "syscon"; + reg = <0x0 0x17010000 0x0 0x1000>; + #power-domain-cells = <1>; + }; + aongpio: pinctrl@17020000 { compatible = "starfive,jh7110-aon-pinctrl"; reg = <0x0 0x17020000 0x0 0x10000>; From patchwork Tue Jun 13 12:58:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xingyu Wu X-Patchwork-Id: 692216 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 585A8EB64D0 for ; Tue, 13 Jun 2023 16:29:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231201AbjFMQ33 convert rfc822-to-8bit (ORCPT ); Tue, 13 Jun 2023 12:29:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55180 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229576AbjFMQ32 (ORCPT ); Tue, 13 Jun 2023 12:29:28 -0400 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3E2C4A6; Tue, 13 Jun 2023 09:29:26 -0700 (PDT) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id 81C507FEF; Wed, 14 Jun 2023 00:29:22 +0800 (CST) Received: from EXMBX061.cuchost.com (172.16.6.61) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 13 Jun 2023 20:58:59 +0800 Received: from localhost.localdomain (113.72.145.34) by EXMBX061.cuchost.com (172.16.6.61) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 13 Jun 2023 20:58:58 +0800 From: Xingyu Wu To: , , "Michael Turquette" , Stephen Boyd , "Rob Herring" , Krzysztof Kozlowski , Philipp Zabel , Conor Dooley , Emil Renner Berthing CC: Paul Walmsley , Palmer Dabbelt , Albert Ou , Hal Feng , Xingyu Wu , "William Qiu" , , Subject: [PATCH v5 7/7] riscv: dts: starfive: jh7110: Add PLL clock source in SYSCRG node Date: Tue, 13 Jun 2023 20:58:52 +0800 Message-ID: <20230613125852.211636-8-xingyu.wu@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230613125852.211636-1-xingyu.wu@starfivetech.com> References: <20230613125852.211636-1-xingyu.wu@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [113.72.145.34] X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX061.cuchost.com (172.16.6.61) X-YovoleRuleAgent: yovoleflag Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Modify the SYSCRG node to add PLL clocks input from PLL clocks driver. Signed-off-by: Xingyu Wu --- arch/riscv/boot/dts/starfive/jh7110.dtsi | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index 11dd4c9d64b0..cdfd036a0e6c 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -452,12 +452,16 @@ syscrg: clock-controller@13020000 { <&gmac1_rgmii_rxin>, <&i2stx_bclk_ext>, <&i2stx_lrck_ext>, <&i2srx_bclk_ext>, <&i2srx_lrck_ext>, - <&tdm_ext>, <&mclk_ext>; + <&tdm_ext>, <&mclk_ext>, + <&pllclk JH7110_CLK_PLL0_OUT>, + <&pllclk JH7110_CLK_PLL1_OUT>, + <&pllclk JH7110_CLK_PLL2_OUT>; clock-names = "osc", "gmac1_rmii_refin", "gmac1_rgmii_rxin", "i2stx_bclk_ext", "i2stx_lrck_ext", "i2srx_bclk_ext", "i2srx_lrck_ext", - "tdm_ext", "mclk_ext"; + "tdm_ext", "mclk_ext", + "pll0_out", "pll1_out", "pll2_out"; #clock-cells = <1>; #reset-cells = <1>; };