From patchwork Wed Jun 14 19:23:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hans de Goede X-Patchwork-Id: 692839 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0C82DEB64D9 for ; Wed, 14 Jun 2023 19:26:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236748AbjFNT0u (ORCPT ); Wed, 14 Jun 2023 15:26:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50448 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236568AbjFNTY7 (ORCPT ); Wed, 14 Jun 2023 15:24:59 -0400 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 14932268C for ; Wed, 14 Jun 2023 12:24:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1686770639; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=3fzMcpPVOoj/9SIelWx/6JRrDaDJayaKHsLDws1dMwk=; b=ZNdUifv990hxj2pgLDAJDr9kcCMm4MBlrwc9zQrjmEfv1PPJerVsKqTLDZpPIPof7XNQmm Yxw1NvcmtKnQF02QHxXU0bhKpwzeuPbPCLvGqMeeqIqorp/SaKDkRcqYylNjXj64Law8iV Ox8XaCU7vOc2rGqC34CircDqGrpuKo0= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-347-_Xn8SDm2O8uXOc1_b_2wjA-1; Wed, 14 Jun 2023 15:23:52 -0400 X-MC-Unique: _Xn8SDm2O8uXOc1_b_2wjA-1 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.rdu2.redhat.com [10.11.54.7]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id C2BE085A5BB; Wed, 14 Jun 2023 19:23:51 +0000 (UTC) Received: from localhost.localdomain (unknown [10.39.192.46]) by smtp.corp.redhat.com (Postfix) with ESMTP id AC5AD140EBB8; Wed, 14 Jun 2023 19:23:50 +0000 (UTC) From: Hans de Goede To: Sakari Ailus , Laurent Pinchart Cc: Hans de Goede , Mauro Carvalho Chehab , Andy Shevchenko , Kate Hsuan , linux-media@vger.kernel.org Subject: [PATCH v2 1/5] media: Add MIPI CCI register access helper functions Date: Wed, 14 Jun 2023 21:23:39 +0200 Message-Id: <20230614192343.57280-2-hdegoede@redhat.com> In-Reply-To: <20230614192343.57280-1-hdegoede@redhat.com> References: <20230614192343.57280-1-hdegoede@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.1 on 10.11.54.7 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org The CSI2 specification specifies a standard method to access camera sensor registers called "Camera Control Interface (CCI)". This uses either 8 or 16 bit (big-endian wire order) register addresses and supports 8, 16, 24 or 32 bit (big-endian wire order) register widths. Currently a lot of Linux camera sensor drivers all have their own custom helpers for this, often copy and pasted from other drivers. Add a set of generic helpers for this so that all sensor drivers can switch to a single common implementation. These helpers take an extra optional "int *err" function parameter, this can be used to chain a bunch of register accesses together with only a single error check at the end, rather then needing to error check each individual register access. The first failing call will set the contents of err to a non 0 value and all other calls will then become no-ops. Link: https://lore.kernel.org/linux-media/59aefa7f-7bf9-6736-6040-39551329cd0a@redhat.com/ Signed-off-by: Hans de Goede --- Changes in v2: - Drop cci_reg_type enum - Make having an encoded reg-width mandatory rather then using 0 to encode 8 bit width making reg-addresses without an encoded width default to a width of 8 - Add support for 64 bit wide registers - Introduce a new cci_reg_sequence struct with 64 bit reg values for 64 bit support and without the delay_us field - Various kerneldoc updates - Stop supporting delays in cci_multi_reg_write() - Some includes cleanups - Disable regmap locking --- Documentation/driver-api/media/v4l2-cci.rst | 5 + Documentation/driver-api/media/v4l2-core.rst | 1 + drivers/media/v4l2-core/Kconfig | 5 + drivers/media/v4l2-core/Makefile | 1 + drivers/media/v4l2-core/v4l2-cci.c | 157 +++++++++++++++++++ include/media/v4l2-cci.h | 121 ++++++++++++++ 6 files changed, 290 insertions(+) create mode 100644 Documentation/driver-api/media/v4l2-cci.rst create mode 100644 drivers/media/v4l2-core/v4l2-cci.c create mode 100644 include/media/v4l2-cci.h diff --git a/Documentation/driver-api/media/v4l2-cci.rst b/Documentation/driver-api/media/v4l2-cci.rst new file mode 100644 index 000000000000..dd297a40ed20 --- /dev/null +++ b/Documentation/driver-api/media/v4l2-cci.rst @@ -0,0 +1,5 @@ +.. SPDX-License-Identifier: GPL-2.0 + +V4L2 CCI kAPI +^^^^^^^^^^^^^ +.. kernel-doc:: include/media/v4l2-cci.h diff --git a/Documentation/driver-api/media/v4l2-core.rst b/Documentation/driver-api/media/v4l2-core.rst index 1a8c4a5f256b..239045ecc8f4 100644 --- a/Documentation/driver-api/media/v4l2-core.rst +++ b/Documentation/driver-api/media/v4l2-core.rst @@ -22,6 +22,7 @@ Video4Linux devices v4l2-mem2mem v4l2-async v4l2-fwnode + v4l2-cci v4l2-rect v4l2-tuner v4l2-common diff --git a/drivers/media/v4l2-core/Kconfig b/drivers/media/v4l2-core/Kconfig index 348559bc2468..523ba243261d 100644 --- a/drivers/media/v4l2-core/Kconfig +++ b/drivers/media/v4l2-core/Kconfig @@ -74,6 +74,11 @@ config V4L2_FWNODE config V4L2_ASYNC tristate +config V4L2_CCI + tristate + depends on I2C + select REGMAP_I2C + # Used by drivers that need Videobuf modules config VIDEOBUF_GEN tristate diff --git a/drivers/media/v4l2-core/Makefile b/drivers/media/v4l2-core/Makefile index 41d91bd10cf2..be2551705755 100644 --- a/drivers/media/v4l2-core/Makefile +++ b/drivers/media/v4l2-core/Makefile @@ -25,6 +25,7 @@ videodev-$(CONFIG_VIDEO_V4L2_I2C) += v4l2-i2c.o # (e. g. LC_ALL=C sort Makefile) obj-$(CONFIG_V4L2_ASYNC) += v4l2-async.o +obj-$(CONFIG_V4L2_CCI) += v4l2-cci.o obj-$(CONFIG_V4L2_FLASH_LED_CLASS) += v4l2-flash-led-class.o obj-$(CONFIG_V4L2_FWNODE) += v4l2-fwnode.o obj-$(CONFIG_V4L2_H264) += v4l2-h264.o diff --git a/drivers/media/v4l2-core/v4l2-cci.c b/drivers/media/v4l2-core/v4l2-cci.c new file mode 100644 index 000000000000..94764f3ebc6c --- /dev/null +++ b/drivers/media/v4l2-core/v4l2-cci.c @@ -0,0 +1,157 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * MIPI Camera Control Interface (CCI) register access helpers. + * + * Copyright (C) 2023 Hans de Goede + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include + +int cci_read(struct regmap *map, u32 reg, u64 *val, int *err) +{ + int len, ret; + u8 buf[8]; + + if (err && *err) + return *err; + + len = FIELD_GET(CCI_REG_WIDTH_MASK, reg); + reg = FIELD_GET(CCI_REG_ADDR_MASK, reg); + + ret = regmap_bulk_read(map, reg, buf, len); + if (ret) { + dev_err(regmap_get_device(map), "Error reading reg 0x%4x: %d\n", reg, ret); + goto out; + } + + switch (len) { + case 1: + *val = buf[0]; + break; + case 2: + *val = get_unaligned_be16(buf); + break; + case 3: + *val = get_unaligned_be24(buf); + break; + case 4: + *val = get_unaligned_be32(buf); + break; + case 8: + *val = get_unaligned_be64(buf); + break; + default: + dev_err(regmap_get_device(map), "Error invalid reg-width %d for reg 0x%04x\n", + len, reg); + ret = -EINVAL; + break; + } + +out: + if (ret && err) + *err = ret; + + return ret; +} +EXPORT_SYMBOL_GPL(cci_read); + +int cci_write(struct regmap *map, u32 reg, u64 val, int *err) +{ + int len, ret; + u8 buf[8]; + + if (err && *err) + return *err; + + len = FIELD_GET(CCI_REG_WIDTH_MASK, reg); + reg = FIELD_GET(CCI_REG_ADDR_MASK, reg); + + switch (len) { + case 1: + buf[0] = val; + break; + case 2: + put_unaligned_be16(val, buf); + break; + case 3: + put_unaligned_be24(val, buf); + break; + case 4: + put_unaligned_be32(val, buf); + break; + case 8: + put_unaligned_be64(val, buf); + break; + default: + dev_err(regmap_get_device(map), "Error invalid reg-width %d for reg 0x%04x\n", + len, reg); + ret = -EINVAL; + goto out; + } + + ret = regmap_bulk_write(map, reg, buf, len); + if (ret) + dev_err(regmap_get_device(map), "Error writing reg 0x%4x: %d\n", reg, ret); + +out: + if (ret && err) + *err = ret; + + return ret; +} +EXPORT_SYMBOL_GPL(cci_write); + +int cci_update_bits(struct regmap *map, u32 reg, u64 mask, u64 val, int *err) +{ + u64 readval; + int ret; + + ret = cci_read(map, reg, &readval, err); + if (ret) + return ret; + + val = (readval & ~mask) | (val & mask); + + return cci_write(map, reg, val, err); +} +EXPORT_SYMBOL_GPL(cci_update_bits); + +int cci_multi_reg_write(struct regmap *map, const struct cci_reg_sequence *regs, + int num_regs, int *err) +{ + int i, ret; + + for (i = 0; i < num_regs; i++) { + ret = cci_write(map, regs[i].reg, regs[i].val, err); + if (ret) + return ret; + } + + return 0; +} +EXPORT_SYMBOL_GPL(cci_multi_reg_write); + +struct regmap *cci_regmap_init_i2c(struct i2c_client *client, int reg_addr_bits) +{ + struct regmap_config config = { + .reg_bits = reg_addr_bits, + .val_bits = 8, + .reg_format_endian = REGMAP_ENDIAN_BIG, + .disable_locking = true, + }; + + return devm_regmap_init_i2c(client, &config); +} +EXPORT_SYMBOL_GPL(cci_regmap_init_i2c); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Hans de Goede "); diff --git a/include/media/v4l2-cci.h b/include/media/v4l2-cci.h new file mode 100644 index 000000000000..5d8fdff086db --- /dev/null +++ b/include/media/v4l2-cci.h @@ -0,0 +1,121 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * MIPI Camera Control Interface (CCI) register access helpers. + * + * Copyright (C) 2023 Hans de Goede + */ +#ifndef _V4L2_CCI_H +#define _V4L2_CCI_H + +#include + +struct i2c_client; +struct reg_sequence; +struct regmap; + +/** + * struct cci_reg_sequence - An individual write from a sequence of CCI writes + * + * @reg: Register address, use CCI_REG#() macros to encode reg width + * @val: Register value + * + * Register/value pairs for sequences of writes. + */ +struct cci_reg_sequence { + u32 reg; + u64 val; +}; + +/* + * Macros to define register address with the register width encoded + * into the higher bits. + */ +#define CCI_REG_ADDR_MASK GENMASK(15, 0) +#define CCI_REG_WIDTH_SHIFT 16 +#define CCI_REG_WIDTH_MASK GENMASK(19, 16) + +#define CCI_REG8(x) ((1 << CCI_REG_WIDTH_SHIFT) | (x)) +#define CCI_REG16(x) ((2 << CCI_REG_WIDTH_SHIFT) | (x)) +#define CCI_REG24(x) ((3 << CCI_REG_WIDTH_SHIFT) | (x)) +#define CCI_REG32(x) ((4 << CCI_REG_WIDTH_SHIFT) | (x)) +#define CCI_REG64(x) ((8 << CCI_REG_WIDTH_SHIFT) | (x)) + +/** + * cci_read() - Read a value from a single CCI register + * + * @map: Register map to read from + * @reg: Register address to read, use CCI_REG#() macros to encode reg width + * @val: Pointer to store read value + * @err: optional pointer to store errors, if a previous error is set + * then the read will be skipped + * + * Return: %0 on success or a negative error code on failure. + */ +int cci_read(struct regmap *map, u32 reg, u64 *val, int *err); + +/** + * cci_write() - Write a value to a single CCI register + * + * @map: Register map to write to + * @reg: Register address to write, use CCI_REG#() macros to encode reg width + * @val: Value to be written + * @err: optional pointer to store errors, if a previous error is set + * then the write will be skipped + * + * Return: %0 on success or a negative error code on failure. + */ +int cci_write(struct regmap *map, u32 reg, u64 val, int *err); + +/** + * cci_update_bits() - Perform a read/modify/write cycle on a single CCI register + * + * @map: Register map to update + * @reg: Register address to update, use CCI_REG#() macros to encode reg width + * @mask: Bitmask to change + * @val: New value for bitmask + * @err: optional pointer to store errors, if a previous error is set + * then the update will be skipped + * + * Note this uses read-modify-write to update the bits, atomicity wrt other + * cci_*() register access functions is NOT guaranteed. + * + * Return: %0 on success or a negative error code on failure. + */ +int cci_update_bits(struct regmap *map, u32 reg, u64 mask, u64 val, int *err); + +/** + * cci_multi_reg_write() - Write multiple registers to the device + * + * @map: Register map to write to + * @regs: Array of structures containing register-address, value pairs to be written + * register-addresses use CCI_REG#() macros to encode reg width + * @num_regs: Number of registers to write + * @err: optional pointer to store errors, if a previous error is set + * then the write will be skipped + * + * Write multiple registers to the device where the set of register, value + * pairs are supplied in any order, possibly not all in a single range. + * + * Use of the CCI_REG#() macros to encode reg width is mandatory. + * + * For raw lists of register-address, -value pairs with only 8 bit + * wide writes regmap_multi_reg_write() can be used instead. + * + * Return: %0 on success or a negative error code on failure. + */ +int cci_multi_reg_write(struct regmap *map, const struct cci_reg_sequence *regs, + int num_regs, int *err); + +/** + * cci_regmap_init_i2c() - Create regmap to use with cci_*() register access functions + * + * @client: i2c_client to create the regmap for + * @reg_addr_bits: register address width to use (8 or 16) + * + * Note the memory for the created regmap is devm() managed, tied to the client. + * + * Return: %0 on success or a negative error code on failure. + */ +struct regmap *cci_regmap_init_i2c(struct i2c_client *client, int reg_addr_bits); + +#endif From patchwork Wed Jun 14 19:23:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hans de Goede X-Patchwork-Id: 692840 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 520D4EB64DB for ; Wed, 14 Jun 2023 19:26:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236422AbjFNT0p (ORCPT ); Wed, 14 Jun 2023 15:26:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50424 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236593AbjFNTZA (ORCPT ); Wed, 14 Jun 2023 15:25:00 -0400 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 557EE2683 for ; Wed, 14 Jun 2023 12:23:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1686770637; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=F6Km22jKD6sF4GMl4bTvLULRzhMvvlHcdtBVPWEwHWc=; b=d9tLU7RpM2MzlmTxd2HFreurm65bDRPgoncrmOAqrEACGlnsLT8ID9NpTtS7QuBx8EKrSE d2ucuphlMlOcbMC5sD1+82ObCaBMFlARcnMxcmzutYMM1P+3fm8o40gV4w3L4v0SEr6t6b 4FAnWWcnMQJbZ13ekf745YPX2qhUIZ4= Received: from mimecast-mx02.redhat.com (mx3-rdu2.redhat.com [66.187.233.73]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-517-gyJGj6jXMcK6ZyXv-sdSDg-1; Wed, 14 Jun 2023 15:23:54 -0400 X-MC-Unique: gyJGj6jXMcK6ZyXv-sdSDg-1 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.rdu2.redhat.com [10.11.54.7]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 18E4F384952E; Wed, 14 Jun 2023 19:23:53 +0000 (UTC) Received: from localhost.localdomain (unknown [10.39.192.46]) by smtp.corp.redhat.com (Postfix) with ESMTP id 01B891415102; Wed, 14 Jun 2023 19:23:51 +0000 (UTC) From: Hans de Goede To: Sakari Ailus , Laurent Pinchart Cc: Hans de Goede , Mauro Carvalho Chehab , Andy Shevchenko , Kate Hsuan , linux-media@vger.kernel.org Subject: [PATCH v2 2/5] media: ov5693: Convert to new CCI register access helpers Date: Wed, 14 Jun 2023 21:23:40 +0200 Message-Id: <20230614192343.57280-3-hdegoede@redhat.com> In-Reply-To: <20230614192343.57280-1-hdegoede@redhat.com> References: <20230614192343.57280-1-hdegoede@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.1 on 10.11.54.7 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Use the new comon CCI register access helpers to replace the private register access helpers in the ov5693 driver. Signed-off-by: Hans de Goede --- Note for reviewers all the OV5693_REG_?BIT defines in both the register address defines as well as in ov5693_global_regs[] were automatically changed using search replace. --- drivers/media/i2c/Kconfig | 1 + drivers/media/i2c/ov5693.c | 574 ++++++++++++++----------------------- 2 files changed, 220 insertions(+), 355 deletions(-) diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig index 11e503129085..298884a09196 100644 --- a/drivers/media/i2c/Kconfig +++ b/drivers/media/i2c/Kconfig @@ -591,6 +591,7 @@ config VIDEO_OV5693 tristate "OmniVision OV5693 sensor support" depends on I2C && VIDEO_DEV select V4L2_FWNODE + select V4L2_CCI help This is a Video4Linux2 sensor driver for the OmniVision OV5693 camera. diff --git a/drivers/media/i2c/ov5693.c b/drivers/media/i2c/ov5693.c index 7f9212cce239..349124e422bd 100644 --- a/drivers/media/i2c/ov5693.c +++ b/drivers/media/i2c/ov5693.c @@ -12,7 +12,6 @@ * Jake Day */ -#include #include #include #include @@ -23,36 +22,32 @@ #include #include #include + +#include #include #include #include -#define OV5693_REG_8BIT(n) ((1 << 16) | (n)) -#define OV5693_REG_16BIT(n) ((2 << 16) | (n)) -#define OV5693_REG_24BIT(n) ((3 << 16) | (n)) -#define OV5693_REG_SIZE_SHIFT 16 -#define OV5693_REG_ADDR_MASK 0xffff - /* System Control */ -#define OV5693_SW_RESET_REG OV5693_REG_8BIT(0x0103) -#define OV5693_SW_STREAM_REG OV5693_REG_8BIT(0x0100) +#define OV5693_SW_RESET_REG CCI_REG8(0x0103) +#define OV5693_SW_STREAM_REG CCI_REG8(0x0100) #define OV5693_START_STREAMING 0x01 #define OV5693_STOP_STREAMING 0x00 #define OV5693_SW_RESET 0x01 -#define OV5693_REG_CHIP_ID OV5693_REG_16BIT(0x300a) +#define OV5693_REG_CHIP_ID CCI_REG16(0x300a) /* Yes, this is right. The datasheet for the OV5693 gives its ID as 0x5690 */ #define OV5693_CHIP_ID 0x5690 /* Exposure */ -#define OV5693_EXPOSURE_CTRL_REG OV5693_REG_24BIT(0x3500) +#define OV5693_EXPOSURE_CTRL_REG CCI_REG24(0x3500) #define OV5693_EXPOSURE_CTRL_MASK GENMASK(19, 4) #define OV5693_INTEGRATION_TIME_MARGIN 8 #define OV5693_EXPOSURE_MIN 1 #define OV5693_EXPOSURE_STEP 1 /* Analogue Gain */ -#define OV5693_GAIN_CTRL_REG OV5693_REG_16BIT(0x350a) +#define OV5693_GAIN_CTRL_REG CCI_REG16(0x350a) #define OV5693_GAIN_CTRL_MASK GENMASK(10, 4) #define OV5693_GAIN_MIN 1 #define OV5693_GAIN_MAX 127 @@ -60,9 +55,9 @@ #define OV5693_GAIN_STEP 1 /* Digital Gain */ -#define OV5693_MWB_RED_GAIN_REG OV5693_REG_16BIT(0x3400) -#define OV5693_MWB_GREEN_GAIN_REG OV5693_REG_16BIT(0x3402) -#define OV5693_MWB_BLUE_GAIN_REG OV5693_REG_16BIT(0x3404) +#define OV5693_MWB_RED_GAIN_REG CCI_REG16(0x3400) +#define OV5693_MWB_GREEN_GAIN_REG CCI_REG16(0x3402) +#define OV5693_MWB_BLUE_GAIN_REG CCI_REG16(0x3404) #define OV5693_MWB_GAIN_MASK GENMASK(11, 0) #define OV5693_MWB_GAIN_MAX 0x0fff #define OV5693_DIGITAL_GAIN_MIN 1 @@ -71,36 +66,36 @@ #define OV5693_DIGITAL_GAIN_STEP 1 /* Timing and Format */ -#define OV5693_CROP_START_X_REG OV5693_REG_16BIT(0x3800) -#define OV5693_CROP_START_Y_REG OV5693_REG_16BIT(0x3802) -#define OV5693_CROP_END_X_REG OV5693_REG_16BIT(0x3804) -#define OV5693_CROP_END_Y_REG OV5693_REG_16BIT(0x3806) -#define OV5693_OUTPUT_SIZE_X_REG OV5693_REG_16BIT(0x3808) -#define OV5693_OUTPUT_SIZE_Y_REG OV5693_REG_16BIT(0x380a) +#define OV5693_CROP_START_X_REG CCI_REG16(0x3800) +#define OV5693_CROP_START_Y_REG CCI_REG16(0x3802) +#define OV5693_CROP_END_X_REG CCI_REG16(0x3804) +#define OV5693_CROP_END_Y_REG CCI_REG16(0x3806) +#define OV5693_OUTPUT_SIZE_X_REG CCI_REG16(0x3808) +#define OV5693_OUTPUT_SIZE_Y_REG CCI_REG16(0x380a) -#define OV5693_TIMING_HTS_REG OV5693_REG_16BIT(0x380c) +#define OV5693_TIMING_HTS_REG CCI_REG16(0x380c) #define OV5693_FIXED_PPL 2688U -#define OV5693_TIMING_VTS_REG OV5693_REG_16BIT(0x380e) +#define OV5693_TIMING_VTS_REG CCI_REG16(0x380e) #define OV5693_TIMING_MAX_VTS 0xffff #define OV5693_TIMING_MIN_VTS 0x04 -#define OV5693_OFFSET_START_X_REG OV5693_REG_16BIT(0x3810) -#define OV5693_OFFSET_START_Y_REG OV5693_REG_16BIT(0x3812) +#define OV5693_OFFSET_START_X_REG CCI_REG16(0x3810) +#define OV5693_OFFSET_START_Y_REG CCI_REG16(0x3812) -#define OV5693_SUB_INC_X_REG OV5693_REG_8BIT(0x3814) -#define OV5693_SUB_INC_Y_REG OV5693_REG_8BIT(0x3815) +#define OV5693_SUB_INC_X_REG CCI_REG8(0x3814) +#define OV5693_SUB_INC_Y_REG CCI_REG8(0x3815) -#define OV5693_FORMAT1_REG OV5693_REG_8BIT(0x3820) +#define OV5693_FORMAT1_REG CCI_REG8(0x3820) #define OV5693_FORMAT1_FLIP_VERT_ISP_EN BIT(6) #define OV5693_FORMAT1_FLIP_VERT_SENSOR_EN BIT(1) #define OV5693_FORMAT1_VBIN_EN BIT(0) -#define OV5693_FORMAT2_REG OV5693_REG_8BIT(0x3821) +#define OV5693_FORMAT2_REG CCI_REG8(0x3821) #define OV5693_FORMAT2_HDR_EN BIT(7) #define OV5693_FORMAT2_FLIP_HORZ_ISP_EN BIT(2) #define OV5693_FORMAT2_FLIP_HORZ_SENSOR_EN BIT(1) #define OV5693_FORMAT2_HBIN_EN BIT(0) -#define OV5693_ISP_CTRL2_REG OV5693_REG_8BIT(0x5002) +#define OV5693_ISP_CTRL2_REG CCI_REG8(0x5002) #define OV5693_ISP_SCALE_ENABLE BIT(7) /* Pixel Array */ @@ -116,7 +111,7 @@ #define OV5693_MIN_CROP_HEIGHT 2 /* Test Pattern */ -#define OV5693_TEST_PATTERN_REG OV5693_REG_8BIT(0x5e00) +#define OV5693_TEST_PATTERN_REG CCI_REG8(0x5e00) #define OV5693_TEST_PATTERN_ENABLE BIT(7) #define OV5693_TEST_PATTERN_ROLLING BIT(6) #define OV5693_TEST_PATTERN_RANDOM 0x01 @@ -137,19 +132,10 @@ static const char * const ov5693_supply_names[] = { #define OV5693_NUM_SUPPLIES ARRAY_SIZE(ov5693_supply_names) -struct ov5693_reg { - u32 reg; - u8 val; -}; - -struct ov5693_reg_list { - u32 num_regs; - const struct ov5693_reg *regs; -}; - struct ov5693_device { struct i2c_client *client; struct device *dev; + struct regmap *regmap; /* Protect against concurrent changes to controls */ struct mutex lock; @@ -189,156 +175,151 @@ struct ov5693_device { } ctrls; }; -static const struct ov5693_reg ov5693_global_regs[] = { - {OV5693_REG_8BIT(0x3016), 0xf0}, - {OV5693_REG_8BIT(0x3017), 0xf0}, - {OV5693_REG_8BIT(0x3018), 0xf0}, - {OV5693_REG_8BIT(0x3022), 0x01}, - {OV5693_REG_8BIT(0x3028), 0x44}, - {OV5693_REG_8BIT(0x3098), 0x02}, - {OV5693_REG_8BIT(0x3099), 0x19}, - {OV5693_REG_8BIT(0x309a), 0x02}, - {OV5693_REG_8BIT(0x309b), 0x01}, - {OV5693_REG_8BIT(0x309c), 0x00}, - {OV5693_REG_8BIT(0x30a0), 0xd2}, - {OV5693_REG_8BIT(0x30a2), 0x01}, - {OV5693_REG_8BIT(0x30b2), 0x00}, - {OV5693_REG_8BIT(0x30b3), 0x83}, - {OV5693_REG_8BIT(0x30b4), 0x03}, - {OV5693_REG_8BIT(0x30b5), 0x04}, - {OV5693_REG_8BIT(0x30b6), 0x01}, - {OV5693_REG_8BIT(0x3080), 0x01}, - {OV5693_REG_8BIT(0x3104), 0x21}, - {OV5693_REG_8BIT(0x3106), 0x00}, - {OV5693_REG_8BIT(0x3406), 0x01}, - {OV5693_REG_8BIT(0x3503), 0x07}, - {OV5693_REG_8BIT(0x350b), 0x40}, - {OV5693_REG_8BIT(0x3601), 0x0a}, - {OV5693_REG_8BIT(0x3602), 0x38}, - {OV5693_REG_8BIT(0x3612), 0x80}, - {OV5693_REG_8BIT(0x3620), 0x54}, - {OV5693_REG_8BIT(0x3621), 0xc7}, - {OV5693_REG_8BIT(0x3622), 0x0f}, - {OV5693_REG_8BIT(0x3625), 0x10}, - {OV5693_REG_8BIT(0x3630), 0x55}, - {OV5693_REG_8BIT(0x3631), 0xf4}, - {OV5693_REG_8BIT(0x3632), 0x00}, - {OV5693_REG_8BIT(0x3633), 0x34}, - {OV5693_REG_8BIT(0x3634), 0x02}, - {OV5693_REG_8BIT(0x364d), 0x0d}, - {OV5693_REG_8BIT(0x364f), 0xdd}, - {OV5693_REG_8BIT(0x3660), 0x04}, - {OV5693_REG_8BIT(0x3662), 0x10}, - {OV5693_REG_8BIT(0x3663), 0xf1}, - {OV5693_REG_8BIT(0x3665), 0x00}, - {OV5693_REG_8BIT(0x3666), 0x20}, - {OV5693_REG_8BIT(0x3667), 0x00}, - {OV5693_REG_8BIT(0x366a), 0x80}, - {OV5693_REG_8BIT(0x3680), 0xe0}, - {OV5693_REG_8BIT(0x3681), 0x00}, - {OV5693_REG_8BIT(0x3700), 0x42}, - {OV5693_REG_8BIT(0x3701), 0x14}, - {OV5693_REG_8BIT(0x3702), 0xa0}, - {OV5693_REG_8BIT(0x3703), 0xd8}, - {OV5693_REG_8BIT(0x3704), 0x78}, - {OV5693_REG_8BIT(0x3705), 0x02}, - {OV5693_REG_8BIT(0x370a), 0x00}, - {OV5693_REG_8BIT(0x370b), 0x20}, - {OV5693_REG_8BIT(0x370c), 0x0c}, - {OV5693_REG_8BIT(0x370d), 0x11}, - {OV5693_REG_8BIT(0x370e), 0x00}, - {OV5693_REG_8BIT(0x370f), 0x40}, - {OV5693_REG_8BIT(0x3710), 0x00}, - {OV5693_REG_8BIT(0x371a), 0x1c}, - {OV5693_REG_8BIT(0x371b), 0x05}, - {OV5693_REG_8BIT(0x371c), 0x01}, - {OV5693_REG_8BIT(0x371e), 0xa1}, - {OV5693_REG_8BIT(0x371f), 0x0c}, - {OV5693_REG_8BIT(0x3721), 0x00}, - {OV5693_REG_8BIT(0x3724), 0x10}, - {OV5693_REG_8BIT(0x3726), 0x00}, - {OV5693_REG_8BIT(0x372a), 0x01}, - {OV5693_REG_8BIT(0x3730), 0x10}, - {OV5693_REG_8BIT(0x3738), 0x22}, - {OV5693_REG_8BIT(0x3739), 0xe5}, - {OV5693_REG_8BIT(0x373a), 0x50}, - {OV5693_REG_8BIT(0x373b), 0x02}, - {OV5693_REG_8BIT(0x373c), 0x41}, - {OV5693_REG_8BIT(0x373f), 0x02}, - {OV5693_REG_8BIT(0x3740), 0x42}, - {OV5693_REG_8BIT(0x3741), 0x02}, - {OV5693_REG_8BIT(0x3742), 0x18}, - {OV5693_REG_8BIT(0x3743), 0x01}, - {OV5693_REG_8BIT(0x3744), 0x02}, - {OV5693_REG_8BIT(0x3747), 0x10}, - {OV5693_REG_8BIT(0x374c), 0x04}, - {OV5693_REG_8BIT(0x3751), 0xf0}, - {OV5693_REG_8BIT(0x3752), 0x00}, - {OV5693_REG_8BIT(0x3753), 0x00}, - {OV5693_REG_8BIT(0x3754), 0xc0}, - {OV5693_REG_8BIT(0x3755), 0x00}, - {OV5693_REG_8BIT(0x3756), 0x1a}, - {OV5693_REG_8BIT(0x3758), 0x00}, - {OV5693_REG_8BIT(0x3759), 0x0f}, - {OV5693_REG_8BIT(0x376b), 0x44}, - {OV5693_REG_8BIT(0x375c), 0x04}, - {OV5693_REG_8BIT(0x3774), 0x10}, - {OV5693_REG_8BIT(0x3776), 0x00}, - {OV5693_REG_8BIT(0x377f), 0x08}, - {OV5693_REG_8BIT(0x3780), 0x22}, - {OV5693_REG_8BIT(0x3781), 0x0c}, - {OV5693_REG_8BIT(0x3784), 0x2c}, - {OV5693_REG_8BIT(0x3785), 0x1e}, - {OV5693_REG_8BIT(0x378f), 0xf5}, - {OV5693_REG_8BIT(0x3791), 0xb0}, - {OV5693_REG_8BIT(0x3795), 0x00}, - {OV5693_REG_8BIT(0x3796), 0x64}, - {OV5693_REG_8BIT(0x3797), 0x11}, - {OV5693_REG_8BIT(0x3798), 0x30}, - {OV5693_REG_8BIT(0x3799), 0x41}, - {OV5693_REG_8BIT(0x379a), 0x07}, - {OV5693_REG_8BIT(0x379b), 0xb0}, - {OV5693_REG_8BIT(0x379c), 0x0c}, - {OV5693_REG_8BIT(0x3a04), 0x06}, - {OV5693_REG_8BIT(0x3a05), 0x14}, - {OV5693_REG_8BIT(0x3e07), 0x20}, - {OV5693_REG_8BIT(0x4000), 0x08}, - {OV5693_REG_8BIT(0x4001), 0x04}, - {OV5693_REG_8BIT(0x4004), 0x08}, - {OV5693_REG_8BIT(0x4006), 0x20}, - {OV5693_REG_8BIT(0x4008), 0x24}, - {OV5693_REG_8BIT(0x4009), 0x10}, - {OV5693_REG_8BIT(0x4058), 0x00}, - {OV5693_REG_8BIT(0x4101), 0xb2}, - {OV5693_REG_8BIT(0x4307), 0x31}, - {OV5693_REG_8BIT(0x4511), 0x05}, - {OV5693_REG_8BIT(0x4512), 0x01}, - {OV5693_REG_8BIT(0x481f), 0x30}, - {OV5693_REG_8BIT(0x4826), 0x2c}, - {OV5693_REG_8BIT(0x4d02), 0xfd}, - {OV5693_REG_8BIT(0x4d03), 0xf5}, - {OV5693_REG_8BIT(0x4d04), 0x0c}, - {OV5693_REG_8BIT(0x4d05), 0xcc}, - {OV5693_REG_8BIT(0x4837), 0x0a}, - {OV5693_REG_8BIT(0x5003), 0x20}, - {OV5693_REG_8BIT(0x5013), 0x00}, - {OV5693_REG_8BIT(0x5842), 0x01}, - {OV5693_REG_8BIT(0x5843), 0x2b}, - {OV5693_REG_8BIT(0x5844), 0x01}, - {OV5693_REG_8BIT(0x5845), 0x92}, - {OV5693_REG_8BIT(0x5846), 0x01}, - {OV5693_REG_8BIT(0x5847), 0x8f}, - {OV5693_REG_8BIT(0x5848), 0x01}, - {OV5693_REG_8BIT(0x5849), 0x0c}, - {OV5693_REG_8BIT(0x5e10), 0x0c}, - {OV5693_REG_8BIT(0x3820), 0x00}, - {OV5693_REG_8BIT(0x3821), 0x1e}, - {OV5693_REG_8BIT(0x5041), 0x14} -}; - -static const struct ov5693_reg_list ov5693_global_setting = { - .num_regs = ARRAY_SIZE(ov5693_global_regs), - .regs = ov5693_global_regs, +static const struct cci_reg_sequence ov5693_global_regs[] = { + {CCI_REG8(0x3016), 0xf0}, + {CCI_REG8(0x3017), 0xf0}, + {CCI_REG8(0x3018), 0xf0}, + {CCI_REG8(0x3022), 0x01}, + {CCI_REG8(0x3028), 0x44}, + {CCI_REG8(0x3098), 0x02}, + {CCI_REG8(0x3099), 0x19}, + {CCI_REG8(0x309a), 0x02}, + {CCI_REG8(0x309b), 0x01}, + {CCI_REG8(0x309c), 0x00}, + {CCI_REG8(0x30a0), 0xd2}, + {CCI_REG8(0x30a2), 0x01}, + {CCI_REG8(0x30b2), 0x00}, + {CCI_REG8(0x30b3), 0x83}, + {CCI_REG8(0x30b4), 0x03}, + {CCI_REG8(0x30b5), 0x04}, + {CCI_REG8(0x30b6), 0x01}, + {CCI_REG8(0x3080), 0x01}, + {CCI_REG8(0x3104), 0x21}, + {CCI_REG8(0x3106), 0x00}, + {CCI_REG8(0x3406), 0x01}, + {CCI_REG8(0x3503), 0x07}, + {CCI_REG8(0x350b), 0x40}, + {CCI_REG8(0x3601), 0x0a}, + {CCI_REG8(0x3602), 0x38}, + {CCI_REG8(0x3612), 0x80}, + {CCI_REG8(0x3620), 0x54}, + {CCI_REG8(0x3621), 0xc7}, + {CCI_REG8(0x3622), 0x0f}, + {CCI_REG8(0x3625), 0x10}, + {CCI_REG8(0x3630), 0x55}, + {CCI_REG8(0x3631), 0xf4}, + {CCI_REG8(0x3632), 0x00}, + {CCI_REG8(0x3633), 0x34}, + {CCI_REG8(0x3634), 0x02}, + {CCI_REG8(0x364d), 0x0d}, + {CCI_REG8(0x364f), 0xdd}, + {CCI_REG8(0x3660), 0x04}, + {CCI_REG8(0x3662), 0x10}, + {CCI_REG8(0x3663), 0xf1}, + {CCI_REG8(0x3665), 0x00}, + {CCI_REG8(0x3666), 0x20}, + {CCI_REG8(0x3667), 0x00}, + {CCI_REG8(0x366a), 0x80}, + {CCI_REG8(0x3680), 0xe0}, + {CCI_REG8(0x3681), 0x00}, + {CCI_REG8(0x3700), 0x42}, + {CCI_REG8(0x3701), 0x14}, + {CCI_REG8(0x3702), 0xa0}, + {CCI_REG8(0x3703), 0xd8}, + {CCI_REG8(0x3704), 0x78}, + {CCI_REG8(0x3705), 0x02}, + {CCI_REG8(0x370a), 0x00}, + {CCI_REG8(0x370b), 0x20}, + {CCI_REG8(0x370c), 0x0c}, + {CCI_REG8(0x370d), 0x11}, + {CCI_REG8(0x370e), 0x00}, + {CCI_REG8(0x370f), 0x40}, + {CCI_REG8(0x3710), 0x00}, + {CCI_REG8(0x371a), 0x1c}, + {CCI_REG8(0x371b), 0x05}, + {CCI_REG8(0x371c), 0x01}, + {CCI_REG8(0x371e), 0xa1}, + {CCI_REG8(0x371f), 0x0c}, + {CCI_REG8(0x3721), 0x00}, + {CCI_REG8(0x3724), 0x10}, + {CCI_REG8(0x3726), 0x00}, + {CCI_REG8(0x372a), 0x01}, + {CCI_REG8(0x3730), 0x10}, + {CCI_REG8(0x3738), 0x22}, + {CCI_REG8(0x3739), 0xe5}, + {CCI_REG8(0x373a), 0x50}, + {CCI_REG8(0x373b), 0x02}, + {CCI_REG8(0x373c), 0x41}, + {CCI_REG8(0x373f), 0x02}, + {CCI_REG8(0x3740), 0x42}, + {CCI_REG8(0x3741), 0x02}, + {CCI_REG8(0x3742), 0x18}, + {CCI_REG8(0x3743), 0x01}, + {CCI_REG8(0x3744), 0x02}, + {CCI_REG8(0x3747), 0x10}, + {CCI_REG8(0x374c), 0x04}, + {CCI_REG8(0x3751), 0xf0}, + {CCI_REG8(0x3752), 0x00}, + {CCI_REG8(0x3753), 0x00}, + {CCI_REG8(0x3754), 0xc0}, + {CCI_REG8(0x3755), 0x00}, + {CCI_REG8(0x3756), 0x1a}, + {CCI_REG8(0x3758), 0x00}, + {CCI_REG8(0x3759), 0x0f}, + {CCI_REG8(0x376b), 0x44}, + {CCI_REG8(0x375c), 0x04}, + {CCI_REG8(0x3774), 0x10}, + {CCI_REG8(0x3776), 0x00}, + {CCI_REG8(0x377f), 0x08}, + {CCI_REG8(0x3780), 0x22}, + {CCI_REG8(0x3781), 0x0c}, + {CCI_REG8(0x3784), 0x2c}, + {CCI_REG8(0x3785), 0x1e}, + {CCI_REG8(0x378f), 0xf5}, + {CCI_REG8(0x3791), 0xb0}, + {CCI_REG8(0x3795), 0x00}, + {CCI_REG8(0x3796), 0x64}, + {CCI_REG8(0x3797), 0x11}, + {CCI_REG8(0x3798), 0x30}, + {CCI_REG8(0x3799), 0x41}, + {CCI_REG8(0x379a), 0x07}, + {CCI_REG8(0x379b), 0xb0}, + {CCI_REG8(0x379c), 0x0c}, + {CCI_REG8(0x3a04), 0x06}, + {CCI_REG8(0x3a05), 0x14}, + {CCI_REG8(0x3e07), 0x20}, + {CCI_REG8(0x4000), 0x08}, + {CCI_REG8(0x4001), 0x04}, + {CCI_REG8(0x4004), 0x08}, + {CCI_REG8(0x4006), 0x20}, + {CCI_REG8(0x4008), 0x24}, + {CCI_REG8(0x4009), 0x10}, + {CCI_REG8(0x4058), 0x00}, + {CCI_REG8(0x4101), 0xb2}, + {CCI_REG8(0x4307), 0x31}, + {CCI_REG8(0x4511), 0x05}, + {CCI_REG8(0x4512), 0x01}, + {CCI_REG8(0x481f), 0x30}, + {CCI_REG8(0x4826), 0x2c}, + {CCI_REG8(0x4d02), 0xfd}, + {CCI_REG8(0x4d03), 0xf5}, + {CCI_REG8(0x4d04), 0x0c}, + {CCI_REG8(0x4d05), 0xcc}, + {CCI_REG8(0x4837), 0x0a}, + {CCI_REG8(0x5003), 0x20}, + {CCI_REG8(0x5013), 0x00}, + {CCI_REG8(0x5842), 0x01}, + {CCI_REG8(0x5843), 0x2b}, + {CCI_REG8(0x5844), 0x01}, + {CCI_REG8(0x5845), 0x92}, + {CCI_REG8(0x5846), 0x01}, + {CCI_REG8(0x5847), 0x8f}, + {CCI_REG8(0x5848), 0x01}, + {CCI_REG8(0x5849), 0x0c}, + {CCI_REG8(0x5e10), 0x0c}, + {CCI_REG8(0x3820), 0x00}, + {CCI_REG8(0x3821), 0x1e}, + {CCI_REG8(0x5041), 0x14} }; static const struct v4l2_rect ov5693_default_crop = { @@ -373,115 +354,6 @@ static const u8 ov5693_test_pattern_bits[] = { OV5693_TEST_PATTERN_ROLLING, }; -/* I2C I/O Operations */ - -static int ov5693_read_reg(struct ov5693_device *ov5693, u32 addr, u32 *value) -{ - struct i2c_client *client = ov5693->client; - __be16 reg; - u8 val[4]; - struct i2c_msg msg[] = { - { - .addr = client->addr, - .flags = 0, - .len = 2, - .buf = (u8 *)®, - }, - { - .addr = client->addr, - .flags = I2C_M_RD, - .buf = (u8 *)&val, - }, - }; - unsigned int len = ((addr >> OV5693_REG_SIZE_SHIFT) & 3); - unsigned int i; - int ret; - - reg = cpu_to_be16(addr & OV5693_REG_ADDR_MASK); - - msg[1].len = len; - - ret = i2c_transfer(client->adapter, msg, 2); - if (ret < 0) - return dev_err_probe(&client->dev, ret, - "Failed to read register 0x%04x\n", - addr & OV5693_REG_ADDR_MASK); - - *value = 0; - for (i = 0; i < len; ++i) { - *value <<= 8; - *value |= val[i]; - } - - return 0; -} - -static void ov5693_write_reg(struct ov5693_device *ov5693, u32 addr, u32 value, - int *error) -{ - struct i2c_client *client = ov5693->client; - struct { - __be16 reg; - u8 val[4]; - } __packed buf; - struct i2c_msg msg = { - .addr = client->addr, - .buf = (u8 *)&buf, - }; - unsigned int len = ((addr >> OV5693_REG_SIZE_SHIFT) & 3); - unsigned int i; - int ret; - - if (*error < 0) - return; - - buf.reg = cpu_to_be16(addr & OV5693_REG_ADDR_MASK); - for (i = 0; i < len; ++i) { - buf.val[len - i - 1] = value & 0xff; - value >>= 8; - } - - msg.len = len + 2; - - ret = i2c_transfer(client->adapter, &msg, 1); - if (ret < 0) { - dev_err(&client->dev, "Failed to write register 0x%04x: %d\n", - addr & OV5693_REG_ADDR_MASK, ret); - *error = ret; - } -} - -static int ov5693_write_reg_array(struct ov5693_device *ov5693, - const struct ov5693_reg_list *reglist) -{ - unsigned int i; - int ret = 0; - - for (i = 0; i < reglist->num_regs; i++) - ov5693_write_reg(ov5693, reglist->regs[i].reg, - reglist->regs[i].val, &ret); - - return ret; -} - -static int ov5693_update_bits(struct ov5693_device *ov5693, u32 address, - u32 mask, u32 bits) -{ - u32 value = 0; - int ret; - - ret = ov5693_read_reg(ov5693, address, &value); - if (ret) - return ret; - - value &= ~mask; - value |= bits; - - ov5693_write_reg(ov5693, address, value, &ret); - - return ret; -} - /* V4L2 Controls Functions */ static int ov5693_flip_vert_configure(struct ov5693_device *ov5693, @@ -491,8 +363,8 @@ static int ov5693_flip_vert_configure(struct ov5693_device *ov5693, OV5693_FORMAT1_FLIP_VERT_SENSOR_EN; int ret; - ret = ov5693_update_bits(ov5693, OV5693_FORMAT1_REG, bits, - enable ? bits : 0); + ret = cci_update_bits(ov5693->regmap, OV5693_FORMAT1_REG, bits, + enable ? bits : 0, NULL); if (ret) return ret; @@ -506,8 +378,8 @@ static int ov5693_flip_horz_configure(struct ov5693_device *ov5693, OV5693_FORMAT2_FLIP_HORZ_SENSOR_EN; int ret; - ret = ov5693_update_bits(ov5693, OV5693_FORMAT2_REG, bits, - enable ? bits : 0); + ret = cci_update_bits(ov5693->regmap, OV5693_FORMAT2_REG, bits, + enable ? bits : 0, NULL); if (ret) return ret; @@ -516,10 +388,10 @@ static int ov5693_flip_horz_configure(struct ov5693_device *ov5693, static int ov5693_get_exposure(struct ov5693_device *ov5693, s32 *value) { - u32 exposure; + u64 exposure; int ret; - ret = ov5693_read_reg(ov5693, OV5693_EXPOSURE_CTRL_REG, &exposure); + ret = cci_read(ov5693->regmap, OV5693_EXPOSURE_CTRL_REG, &exposure, NULL); if (ret) return ret; @@ -536,17 +408,17 @@ static int ov5693_exposure_configure(struct ov5693_device *ov5693, exposure = (exposure << 4) & OV5693_EXPOSURE_CTRL_MASK; - ov5693_write_reg(ov5693, OV5693_EXPOSURE_CTRL_REG, exposure, &ret); + cci_write(ov5693->regmap, OV5693_EXPOSURE_CTRL_REG, exposure, &ret); return ret; } static int ov5693_get_gain(struct ov5693_device *ov5693, u32 *gain) { - u32 value; + u64 value; int ret; - ret = ov5693_read_reg(ov5693, OV5693_GAIN_CTRL_REG, &value); + ret = cci_read(ov5693->regmap, OV5693_GAIN_CTRL_REG, &value, NULL); if (ret) return ret; @@ -563,9 +435,9 @@ static int ov5693_digital_gain_configure(struct ov5693_device *ov5693, gain &= OV5693_MWB_GAIN_MASK; - ov5693_write_reg(ov5693, OV5693_MWB_RED_GAIN_REG, gain, &ret); - ov5693_write_reg(ov5693, OV5693_MWB_GREEN_GAIN_REG, gain, &ret); - ov5693_write_reg(ov5693, OV5693_MWB_BLUE_GAIN_REG, gain, &ret); + cci_write(ov5693->regmap, OV5693_MWB_RED_GAIN_REG, gain, &ret); + cci_write(ov5693->regmap, OV5693_MWB_GREEN_GAIN_REG, gain, &ret); + cci_write(ov5693->regmap, OV5693_MWB_BLUE_GAIN_REG, gain, &ret); return ret; } @@ -576,7 +448,7 @@ static int ov5693_analog_gain_configure(struct ov5693_device *ov5693, u32 gain) gain = (gain << 4) & OV5693_GAIN_CTRL_MASK; - ov5693_write_reg(ov5693, OV5693_GAIN_CTRL_REG, gain, &ret); + cci_write(ov5693->regmap, OV5693_GAIN_CTRL_REG, gain, &ret); return ret; } @@ -586,7 +458,7 @@ static int ov5693_vts_configure(struct ov5693_device *ov5693, u32 vblank) u16 vts = ov5693->mode.format.height + vblank; int ret = 0; - ov5693_write_reg(ov5693, OV5693_TIMING_VTS_REG, vts, &ret); + cci_write(ov5693->regmap, OV5693_TIMING_VTS_REG, vts, &ret); return ret; } @@ -595,8 +467,8 @@ static int ov5693_test_pattern_configure(struct ov5693_device *ov5693, u32 idx) { int ret = 0; - ov5693_write_reg(ov5693, OV5693_TEST_PATTERN_REG, - ov5693_test_pattern_bits[idx], &ret); + cci_write(ov5693->regmap, OV5693_TEST_PATTERN_REG, + ov5693_test_pattern_bits[idx], &ret); return ret; } @@ -685,59 +557,47 @@ static int ov5693_mode_configure(struct ov5693_device *ov5693) int ret = 0; /* Crop Start X */ - ov5693_write_reg(ov5693, OV5693_CROP_START_X_REG, mode->crop.left, - &ret); + cci_write(ov5693->regmap, OV5693_CROP_START_X_REG, mode->crop.left, &ret); /* Offset X */ - ov5693_write_reg(ov5693, OV5693_OFFSET_START_X_REG, 0, &ret); + cci_write(ov5693->regmap, OV5693_OFFSET_START_X_REG, 0, &ret); /* Output Size X */ - ov5693_write_reg(ov5693, OV5693_OUTPUT_SIZE_X_REG, mode->format.width, - &ret); + cci_write(ov5693->regmap, OV5693_OUTPUT_SIZE_X_REG, mode->format.width, &ret); /* Crop End X */ - ov5693_write_reg(ov5693, OV5693_CROP_END_X_REG, - mode->crop.left + mode->crop.width, &ret); + cci_write(ov5693->regmap, OV5693_CROP_END_X_REG, + mode->crop.left + mode->crop.width, &ret); /* Horizontal Total Size */ - ov5693_write_reg(ov5693, OV5693_TIMING_HTS_REG, OV5693_FIXED_PPL, - &ret); + cci_write(ov5693->regmap, OV5693_TIMING_HTS_REG, OV5693_FIXED_PPL, &ret); /* Crop Start Y */ - ov5693_write_reg(ov5693, OV5693_CROP_START_Y_REG, mode->crop.top, - &ret); + cci_write(ov5693->regmap, OV5693_CROP_START_Y_REG, mode->crop.top, &ret); /* Offset Y */ - ov5693_write_reg(ov5693, OV5693_OFFSET_START_Y_REG, 0, &ret); + cci_write(ov5693->regmap, OV5693_OFFSET_START_Y_REG, 0, &ret); /* Output Size Y */ - ov5693_write_reg(ov5693, OV5693_OUTPUT_SIZE_Y_REG, mode->format.height, - &ret); + cci_write(ov5693->regmap, OV5693_OUTPUT_SIZE_Y_REG, mode->format.height, &ret); /* Crop End Y */ - ov5693_write_reg(ov5693, OV5693_CROP_END_Y_REG, - mode->crop.top + mode->crop.height, &ret); + cci_write(ov5693->regmap, OV5693_CROP_END_Y_REG, + mode->crop.top + mode->crop.height, &ret); /* Subsample X increase */ - ov5693_write_reg(ov5693, OV5693_SUB_INC_X_REG, - ((mode->inc_x_odd << 4) & 0xf0) | 0x01, &ret); + cci_write(ov5693->regmap, OV5693_SUB_INC_X_REG, + ((mode->inc_x_odd << 4) & 0xf0) | 0x01, &ret); /* Subsample Y increase */ - ov5693_write_reg(ov5693, OV5693_SUB_INC_Y_REG, - ((mode->inc_y_odd << 4) & 0xf0) | 0x01, &ret); - - if (ret) - return ret; + cci_write(ov5693->regmap, OV5693_SUB_INC_Y_REG, + ((mode->inc_y_odd << 4) & 0xf0) | 0x01, &ret); /* Binning */ - ret = ov5693_update_bits(ov5693, OV5693_FORMAT1_REG, - OV5693_FORMAT1_VBIN_EN, - mode->binning_y ? OV5693_FORMAT1_VBIN_EN : 0); - if (ret) - return ret; + ret = cci_update_bits(ov5693->regmap, OV5693_FORMAT1_REG, OV5693_FORMAT1_VBIN_EN, + mode->binning_y ? OV5693_FORMAT1_VBIN_EN : 0, &ret); - ret = ov5693_update_bits(ov5693, OV5693_FORMAT2_REG, - OV5693_FORMAT2_HBIN_EN, - mode->binning_x ? OV5693_FORMAT2_HBIN_EN : 0); + ret = cci_update_bits(ov5693->regmap, OV5693_FORMAT2_REG, OV5693_FORMAT2_HBIN_EN, + mode->binning_x ? OV5693_FORMAT2_HBIN_EN : 0, &ret); return ret; } @@ -746,9 +606,8 @@ static int ov5693_enable_streaming(struct ov5693_device *ov5693, bool enable) { int ret = 0; - ov5693_write_reg(ov5693, OV5693_SW_STREAM_REG, - enable ? OV5693_START_STREAMING : - OV5693_STOP_STREAMING, &ret); + cci_write(ov5693->regmap, OV5693_SW_STREAM_REG, + enable ? OV5693_START_STREAMING : OV5693_STOP_STREAMING, &ret); return ret; } @@ -757,7 +616,7 @@ static int ov5693_sw_reset(struct ov5693_device *ov5693) { int ret = 0; - ov5693_write_reg(ov5693, OV5693_SW_RESET_REG, OV5693_SW_RESET, &ret); + cci_write(ov5693->regmap, OV5693_SW_RESET_REG, OV5693_SW_RESET, &ret); return ret; } @@ -771,7 +630,8 @@ static int ov5693_sensor_init(struct ov5693_device *ov5693) return dev_err_probe(ov5693->dev, ret, "software reset error\n"); - ret = ov5693_write_reg_array(ov5693, &ov5693_global_setting); + ret = cci_multi_reg_write(ov5693->regmap, ov5693_global_regs, + ARRAY_SIZE(ov5693_global_regs), NULL); if (ret) return dev_err_probe(ov5693->dev, ret, "global settings error\n"); @@ -871,15 +731,15 @@ static int __maybe_unused ov5693_sensor_resume(struct device *dev) static int ov5693_detect(struct ov5693_device *ov5693) { int ret; - u32 id; + u64 id; - ret = ov5693_read_reg(ov5693, OV5693_REG_CHIP_ID, &id); + ret = cci_read(ov5693->regmap, OV5693_REG_CHIP_ID, &id, NULL); if (ret) return ret; if (id != OV5693_CHIP_ID) return dev_err_probe(ov5693->dev, -ENODEV, - "sensor ID mismatch. Found 0x%04x\n", id); + "sensor ID mismatch. Found 0x%04llx\n", id); return 0; } @@ -1410,6 +1270,10 @@ static int ov5693_probe(struct i2c_client *client) ov5693->client = client; ov5693->dev = &client->dev; + ov5693->regmap = cci_regmap_init_i2c(client, 16); + if (IS_ERR(ov5693->regmap)) + return PTR_ERR(ov5693->regmap); + ret = ov5693_check_hwcfg(ov5693); if (ret) return ret;