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Disable it if EL3 is forced off by the board or command-line. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 6 ++++++ target/arm/cpu.c | 4 ++++ 2 files changed, 10 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index af0119addf..c84ec2752f 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2195,6 +2195,7 @@ FIELD(ID_AA64PFR0, SEL2, 36, 4) FIELD(ID_AA64PFR0, MPAM, 40, 4) FIELD(ID_AA64PFR0, AMU, 44, 4) FIELD(ID_AA64PFR0, DIT, 48, 4) +FIELD(ID_AA64PFR0, RME, 52, 4) FIELD(ID_AA64PFR0, CSV2, 56, 4) FIELD(ID_AA64PFR0, CSV3, 60, 4) @@ -3814,6 +3815,11 @@ static inline bool isar_feature_aa64_sel2(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SEL2) != 0; } +static inline bool isar_feature_aa64_rme(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RME) != 0; +} + static inline bool isar_feature_aa64_vh(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) != 0; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 353fc48567..842e1b53ee 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1989,6 +1989,10 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPSDBG, 0); cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, EL3, 0); + + /* Disable the realm management extension, which requires EL3. */ + cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, + ID_AA64PFR0, RME, 0); } if (!cpu->has_el2) { From patchwork Tue Jun 20 12:44:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 694500 Delivered-To: patch@linaro.org Received: by 2002:adf:e885:0:0:0:0:0 with SMTP id d5csp285722wrm; Tue, 20 Jun 2023 05:46:05 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4eutHmREnz6cbFri+d7xthj8expiezSX2qPNWF4fQ9onIUSOlNSAUBGXhB5EVwcewEL1Lg X-Received: by 2002:a05:620a:8290:b0:763:98b4:e81f with SMTP id ox16-20020a05620a829000b0076398b4e81fmr4903945qkn.39.1687265165005; Tue, 20 Jun 2023 05:46:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687265164; cv=none; d=google.com; s=arc-20160816; b=kr9i0sUyrToFwmzO/M5DiCXnSYCYi0AX1MSsv6kXeid30MRW31TzX79/CINhC59riB At43srrvUtET6sXm8zR/F/46lniVyY4mzR2V0wsFn5Q72LGhEl2iXff3kE4T/FoIaUdP KrQi4c8JdkID22TULK00WAW4IZqKb//GbjhywR2LxEchKZf1LCeterjWAmf+QBsNJzzk fcQfzFw4lnNkVh8ji0PvCBw5D2Ntv/eF8nCaAOvDHhuznTcumwfFpZT7EluCcs0UVyp5 HVBXp+dvhFTAKKw4cNOcfT5I9XwPguq0CuFiebZnk20n9uB3C+DXUtMs1GccZiXldUO9 KzEA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=tr1rTDfiq0RcGbvkGBpYZNXlVGVfs0mzt9B/xYUDj8Q=; b=CrAADBAWj/OmM1wl7LLTu0pavrzEVGds7YrJXfYoquvigYF96AyQua4tIO1FLQaX3b YM0BBSXh08qvXOmHJlVJC1ICsJu2k7rJhbQMJQXrprPJVjzu1Jy8ZbLunicLsjAJOs58 obopYWb9vQqz1OwkzcwsIO6/HVJcxsPLeyOqy/8MRrGboHMNoI2U4ELLpje+gGhDBO53 CUHqk4dJ9DRmHPJWF4/cVWVJFq3h8i0njWKkAfyMWxAot2AON+lPl0dmESZxu42Ci9TC bKCpWfjq+s+k7BDSkR2l6BL1XImxAVBO0jpSoh8xDZ5hC491O0ZEuCa69oPTlMhEYjPE rN8g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="pIZ+S/eP"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id v18-20020a05620a123200b0076396dee5f1si769533qkj.502.2023.06.20.05.46.04 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 20 Jun 2023 05:46:04 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="pIZ+S/eP"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qBaip-0001WM-Dm; Tue, 20 Jun 2023 08:44:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qBaim-0001Ty-Iz for qemu-devel@nongnu.org; Tue, 20 Jun 2023 08:44:32 -0400 Received: from mail-lf1-x12e.google.com ([2a00:1450:4864:20::12e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qBaii-0001tS-EN for qemu-devel@nongnu.org; Tue, 20 Jun 2023 08:44:32 -0400 Received: by mail-lf1-x12e.google.com with SMTP id 2adb3069b0e04-4f87592ecaeso2432869e87.0 for ; Tue, 20 Jun 2023 05:44:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687265062; x=1689857062; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=tr1rTDfiq0RcGbvkGBpYZNXlVGVfs0mzt9B/xYUDj8Q=; b=pIZ+S/ePfHYaVxByvQGvc317/MW5QwsPUDyxlsXFk7nWSZi+diPyqWwySV3YCXdVzS f44jGspyRAgTzfQt42mdg8U9J3Tzy+NAVQq5kpR92PW9W+jcWNiCfIlGTTPEmk4zs21G K+QKoUx91MXIPq97vhRGtJdIncetbS2COC4Ugi3RAEYhUetdYacOxx+NcbFID4/zZCB0 /ImSHa5hbKTCon77DZ4X9iNk5R164A5TsWh/sR2Hmb+vwDu6lyV6Nzjj1VuUqLqNx/KW bfdZlEDYI5TvCThrsVSBBV9u2eIBl1yVtV2zxA2EwQQQ/PuCoVR+tHGQh4dWgaVMDmDk gwMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687265062; x=1689857062; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tr1rTDfiq0RcGbvkGBpYZNXlVGVfs0mzt9B/xYUDj8Q=; b=MRTvFZ/8ZDvx+Z9BuMcCKee7emHKoiyLbQQmmRcHjs9uRfYdLY1qif6/H6ef0X2tt8 gnMZHeZdmPFO+o6B9HBr0kQWkeOBlPGIePOYrsNGtVGB1mXHQf7ZwVBLUOYa+K1VdH0H X9IQNBb2EQNHGva7Wg9S8cykjY+lVan/SbBc6qWgizmiry0hFK7UAeQS739wPAjmrISs cU5pixMLVYspHSQLx1x1l2jWtniB3K+urKfhqvhXxUASUM+wmtmtGQFYe/ZGKlfoBIoG 6GXj+oNfbXXXHK6t1VrK8D0uggP+jhrspb4uvYswTSlaED1sDRTRMftbQK1wWd/BR4Mc mJYw== X-Gm-Message-State: AC+VfDyZqi08tykNjwPzhyja8z0KvFYmWAWX9OblQm0zfx5pPDG2Srcz AfoSqTGxJJmUV+6iwYNhtutcrq1sUu/2xJH4GkkRBEC+ X-Received: by 2002:a19:6519:0:b0:4f8:6d54:72fa with SMTP id z25-20020a196519000000b004f86d5472famr3546755lfb.2.1687265062685; Tue, 20 Jun 2023 05:44:22 -0700 (PDT) Received: from stoup.lan ([176.176.183.29]) by smtp.gmail.com with ESMTPSA id w9-20020aa7dcc9000000b0051a313a66e8sm1142541edu.45.2023.06.20.05.44.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Jun 2023 05:44:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v5 02/20] target/arm: Update SCR and HCR for RME Date: Tue, 20 Jun 2023 14:44:00 +0200 Message-Id: <20230620124418.805717-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230620124418.805717-1-richard.henderson@linaro.org> References: <20230620124418.805717-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::12e; envelope-from=richard.henderson@linaro.org; helo=mail-lf1-x12e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Define the missing SCR and HCR bits, allow SCR_NSE and {SCR,HCR}_GPF to be set, and invalidate TLBs when NSE changes. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 5 +++-- target/arm/helper.c | 10 ++++++++-- 2 files changed, 11 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c84ec2752f..318d1033b8 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1655,7 +1655,7 @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) #define HCR_TERR (1ULL << 36) #define HCR_TEA (1ULL << 37) #define HCR_MIOCNCE (1ULL << 38) -/* RES0 bit 39 */ +#define HCR_TME (1ULL << 39) #define HCR_APK (1ULL << 40) #define HCR_API (1ULL << 41) #define HCR_NV (1ULL << 42) @@ -1664,7 +1664,7 @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) #define HCR_NV2 (1ULL << 45) #define HCR_FWB (1ULL << 46) #define HCR_FIEN (1ULL << 47) -/* RES0 bit 48 */ +#define HCR_GPF (1ULL << 48) #define HCR_TID4 (1ULL << 49) #define HCR_TICAB (1ULL << 50) #define HCR_AMVOFFEN (1ULL << 51) @@ -1729,6 +1729,7 @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) #define SCR_TRNDR (1ULL << 40) #define SCR_ENTP2 (1ULL << 41) #define SCR_GPF (1ULL << 48) +#define SCR_NSE (1ULL << 62) #define HSTR_TTEE (1 << 16) #define HSTR_TJDBX (1 << 17) diff --git a/target/arm/helper.c b/target/arm/helper.c index d4bee43bd0..d2f0d9226e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1874,6 +1874,9 @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) if (cpu_isar_feature(aa64_fgt, cpu)) { valid_mask |= SCR_FGTEN; } + if (cpu_isar_feature(aa64_rme, cpu)) { + valid_mask |= SCR_NSE | SCR_GPF; + } } else { valid_mask &= ~(SCR_RW | SCR_ST); if (cpu_isar_feature(aa32_ras, cpu)) { @@ -1903,10 +1906,10 @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) env->cp15.scr_el3 = value; /* - * If SCR_EL3.NS changes, i.e. arm_is_secure_below_el3, then + * If SCR_EL3.{NS,NSE} changes, i.e. change of security state, * we must invalidate all TLBs below EL3. */ - if (changed & SCR_NS) { + if (changed & (SCR_NS | SCR_NSE)) { tlb_flush_by_mmuidx(env_cpu(env), (ARMMMUIdxBit_E10_0 | ARMMMUIdxBit_E20_0 | ARMMMUIdxBit_E10_1 | @@ -5654,6 +5657,9 @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask) if (cpu_isar_feature(aa64_fwb, cpu)) { valid_mask |= HCR_FWB; } + if (cpu_isar_feature(aa64_rme, cpu)) { + valid_mask |= HCR_GPF; + } } if (cpu_isar_feature(any_evt, cpu)) { From patchwork Tue Jun 20 12:44:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 694507 Delivered-To: patch@linaro.org Received: by 2002:adf:e885:0:0:0:0:0 with SMTP id d5csp286311wrm; Tue, 20 Jun 2023 05:47:24 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5vodb1m6y5anRPwftHdU0g0F8jBALZfpymf/S9kqyO3ny3jc2ydaazN6RANWbN1NRae2Ct X-Received: by 2002:a05:620a:6789:b0:763:97e7:8907 with SMTP id rr9-20020a05620a678900b0076397e78907mr4455416qkn.39.1687265243985; Tue, 20 Jun 2023 05:47:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687265243; cv=none; d=google.com; s=arc-20160816; b=eFzXdAYwjlKqTmAtpdtivMD6gAtzohCBYkfKR+tWgwyUuT0ediZ1mVo/KhjZUGnbEY kxuwx7KxxzNRsSN+r0gdhuoBiO1K7C5DyGKzNl/smkbnp5MbD3XaTOD6hxIqeOBtQ+yY uHU0einxzuZWgLD6+BuUZadaKI0AJKLfvzsQUa2pOdzyFWFoEICOv+8yj1v0PF7U8ZDR /4fvtfHhCUbM41BMIkw0oZxb5GowV5RzsPKE4FnwVHd/1iKExaGklBMGV7qbv2k528w4 8uonv9DTigdSrk2zSGdOD9dg1VkOUMOiNhqbkxRNFNZ+B7TlTnWvMnPrcOoX9xAbSeGM 6uTg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=3Qb+YfsmMaXVy5lDjjPTSWHTsaQ7mtmCSzuA5ibkhpA=; b=SBDUHf31Fc1jnTWslcE4mTSf+Q9hNDdLjH7AXmZM4J7+BhgTU6epMNhCguQiREGOJI L6oieoOxeSeB/Ln3p3ueVEh5ETA/q8EDqVrF9Pmml8/3LRpQt+m9zpvIrZBfFVQi995x /RkeCGvQdcBRI+RqoE1HcPIySerLz57ByboqSWykNsjngT1nE86d28fVcVzBJcFEkrwf L3qW7fieC1IWgeBo1fxP0Cyk5ZoMKZruh0i3o5pCtUNSUB63Uo5v44VAzX3vV324QEiw WfuB6+0gigIjARWFlj7EFTCSUUYrjYfv06Q6was8jXDToUlI+W/rNdcPfnn6V6IhXCLS lweA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UQEMplP2; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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The NS bit is RES1 if SEL2 is not present. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index d2f0d9226e..9132d4de6a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1855,6 +1855,9 @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) } if (cpu_isar_feature(aa64_sel2, cpu)) { valid_mask |= SCR_EEL2; + } else if (cpu_isar_feature(aa64_rme, cpu)) { + /* With RME and without SEL2, NS is RES1 (R_GSWWH, I_DJJQJ). */ + value |= SCR_NS; } if (cpu_isar_feature(aa64_mte, cpu)) { valid_mask |= SCR_ATA; From patchwork Tue Jun 20 12:44:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 694494 Delivered-To: patch@linaro.org Received: by 2002:adf:e885:0:0:0:0:0 with SMTP id d5csp285284wrm; Tue, 20 Jun 2023 05:45:05 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ71vT+e9P1OqT/zWlan+NV2um7a3VUbC65Uv3zbdsk2+HD0AX2qAsj0W2VlEMRKB9tXV84r X-Received: by 2002:a05:620a:28c1:b0:75d:50bb:b173 with SMTP id l1-20020a05620a28c100b0075d50bbb173mr14475031qkp.16.1687265104766; Tue, 20 Jun 2023 05:45:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687265104; cv=none; d=google.com; s=arc-20160816; b=YPDl8kVEMSdHURbJRHgy6ZDdfyTHz45HGAmgf6DJzefdIozWGdc+WmCgequtuZzda6 l0BUtU9sgLc+/iQKppE9kozzRviTpUaTckiLnW0l8lFiJZ1VgZbJRHsvTplOagoJlxup stLx+h7VHhrHzSXIOQGOONA7XFYoxpb0octcO98jClSdIzPeRlLisA1VIup2Bu2fnom/ k/IBEUoSDI+W+4/uSMYmWZIacGKCQViOjlljA+4AzAiUlLjhbWkQ6AjBX56tmRkDcWvQ iM0pepq2+PX/kS85xS3hSpkdQ6R/KFqrM3eF54ku2cxCJJkKjSBbNHxdWoPrnzGy5mDY rehA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=8db1arbbArNUPiE75CY7f/HIL5XIpMmiVA6pu1+whjw=; b=n8y6zXt+eU48F+q5VEHkPHi36pAvD3hUbgfCH1/aVaXcFZbg/nob8ln3aqh3fYzvEq FouwyDypJoghpO72mSdc8h+3cSxKudhrDE7pVkYc7dFJ3WZniUkVn2mZ0LfvxCd+CvO8 fHOwaqpZGYNK4jLyDKot+2gri7cLrL36PkobtFyxYS1S8j3ZOxGKYrSLDuKdrCzAKYak +O9ubiHI/Q1jRFPWFOdwOlWnIzCSTtkxQhzX0aqyITUym8Hh825zqP9jl8v9D5DhwuzK xeAsnqz3EnUmnUtC35FOWaYtWsw2/v9+LqKIuWMbVv5+B/SZVzqgs98bh4WsOoOrQvtB 10wA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XaDGmUbC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 19 ++++++++++ target/arm/helper.c | 84 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 103 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 318d1033b8..c9c87b515d 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -541,6 +541,11 @@ typedef struct CPUArchState { uint64_t fgt_read[2]; /* HFGRTR, HDFGRTR */ uint64_t fgt_write[2]; /* HFGWTR, HDFGWTR */ uint64_t fgt_exec[1]; /* HFGITR */ + + /* RME registers */ + uint64_t gpccr_el3; + uint64_t gptbr_el3; + uint64_t mfar_el3; } cp15; struct { @@ -1055,6 +1060,7 @@ struct ArchCPU { uint64_t reset_cbar; uint32_t reset_auxcr; bool reset_hivecs; + uint8_t reset_l0gptsz; /* * Intermediate values used during property parsing. @@ -2341,6 +2347,19 @@ FIELD(MVFR1, SIMDFMAC, 28, 4) FIELD(MVFR2, SIMDMISC, 0, 4) FIELD(MVFR2, FPMISC, 4, 4) +FIELD(GPCCR, PPS, 0, 3) +FIELD(GPCCR, IRGN, 8, 2) +FIELD(GPCCR, ORGN, 10, 2) +FIELD(GPCCR, SH, 12, 2) +FIELD(GPCCR, PGS, 14, 2) +FIELD(GPCCR, GPC, 16, 1) +FIELD(GPCCR, GPCP, 17, 1) +FIELD(GPCCR, L0GPTSZ, 20, 4) + +FIELD(MFAR, FPA, 12, 40) +FIELD(MFAR, NSE, 62, 1) +FIELD(MFAR, NS, 63, 1) + QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK); /* If adding a feature bit which corresponds to a Linux ELF diff --git a/target/arm/helper.c b/target/arm/helper.c index 9132d4de6a..006447dde8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6910,6 +6910,83 @@ static const ARMCPRegInfo sme_reginfo[] = { .access = PL2_RW, .accessfn = access_esm, .type = ARM_CP_CONST, .resetvalue = 0 }, }; + +static void tlbi_aa64_paall_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + CPUState *cs = env_cpu(env); + + tlb_flush(cs); +} + +static void gpccr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* L0GPTSZ is RO; other bits not mentioned are RES0. */ + uint64_t rw_mask = R_GPCCR_PPS_MASK | R_GPCCR_IRGN_MASK | + R_GPCCR_ORGN_MASK | R_GPCCR_SH_MASK | R_GPCCR_PGS_MASK | + R_GPCCR_GPC_MASK | R_GPCCR_GPCP_MASK; + + env->cp15.gpccr_el3 = (value & rw_mask) | (env->cp15.gpccr_el3 & ~rw_mask); +} + +static void gpccr_reset(CPUARMState *env, const ARMCPRegInfo *ri) +{ + env->cp15.gpccr_el3 = FIELD_DP64(0, GPCCR, L0GPTSZ, + env_archcpu(env)->reset_l0gptsz); +} + +static void tlbi_aa64_paallos_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + CPUState *cs = env_cpu(env); + + tlb_flush_all_cpus_synced(cs); +} + +static const ARMCPRegInfo rme_reginfo[] = { + { .name = "GPCCR_EL3", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 1, .opc2 = 6, + .access = PL3_RW, .writefn = gpccr_write, .resetfn = gpccr_reset, + .fieldoffset = offsetof(CPUARMState, cp15.gpccr_el3) }, + { .name = "GPTBR_EL3", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 1, .opc2 = 4, + .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.gptbr_el3) }, + { .name = "MFAR_EL3", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 5, + .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mfar_el3) }, + { .name = "TLBI_PAALL", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 4, + .access = PL3_W, .type = ARM_CP_NO_RAW, + .writefn = tlbi_aa64_paall_write }, + { .name = "TLBI_PAALLOS", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 1, .opc2 = 4, + .access = PL3_W, .type = ARM_CP_NO_RAW, + .writefn = tlbi_aa64_paallos_write }, + /* + * QEMU does not have a way to invalidate by physical address, thus + * invalidating a range of physical addresses is accomplished by + * flushing all tlb entries in the outer sharable domain, + * just like PAALLOS. + */ + { .name = "TLBI_RPALOS", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 4, .opc2 = 7, + .access = PL3_W, .type = ARM_CP_NO_RAW, + .writefn = tlbi_aa64_paallos_write }, + { .name = "TLBI_RPAOS", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 4, .opc2 = 3, + .access = PL3_W, .type = ARM_CP_NO_RAW, + .writefn = tlbi_aa64_paallos_write }, + { .name = "DC_CIPAPA", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 14, .opc2 = 1, + .access = PL3_W, .type = ARM_CP_NOP }, +}; + +static const ARMCPRegInfo rme_mte_reginfo[] = { + { .name = "DC_CIGDPAPA", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 14, .opc2 = 5, + .access = PL3_W, .type = ARM_CP_NOP }, +}; #endif /* TARGET_AARCH64 */ static void define_pmu_regs(ARMCPU *cpu) @@ -9130,6 +9207,13 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (cpu_isar_feature(aa64_fgt, cpu)) { define_arm_cp_regs(cpu, fgt_reginfo); } + + if (cpu_isar_feature(aa64_rme, cpu)) { + define_arm_cp_regs(cpu, rme_reginfo); + if (cpu_isar_feature(aa64_mte, cpu)) { + define_arm_cp_regs(cpu, rme_mte_reginfo); + } + } #endif if (cpu_isar_feature(any_predinv, cpu)) { From patchwork Tue Jun 20 12:44:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 694498 Delivered-To: patch@linaro.org Received: by 2002:adf:e885:0:0:0:0:0 with SMTP id d5csp285556wrm; Tue, 20 Jun 2023 05:45:38 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5/rQjDi0TJil5sYTYXcafmFBsZA6QjwLWCUaTNVM8X9x3LC5DkvQcIk/Rc9VHDq4vUWaMf X-Received: by 2002:a1f:5e48:0:b0:473:4e4d:8a8d with SMTP id s69-20020a1f5e48000000b004734e4d8a8dmr360332vkb.11.1687265137709; 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Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 89 ++++++++++++++++++++++++++++++++++----------- target/arm/helper.c | 60 ++++++++++++++++++++++++++++++ 2 files changed, 127 insertions(+), 22 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c9c87b515d..125e53b83f 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2414,25 +2414,53 @@ static inline int arm_feature(CPUARMState *env, int feature) void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp); -#if !defined(CONFIG_USER_ONLY) /* + * ARM v9 security states. + * The ordering of the enumeration corresponds to the low 2 bits + * of the GPI value, and (except for Root) the concat of NSE:NS. + */ + +typedef enum ARMSecuritySpace { + ARMSS_Secure = 0, + ARMSS_NonSecure = 1, + ARMSS_Root = 2, + ARMSS_Realm = 3, +} ARMSecuritySpace; + +/* Return true if @space is secure, in the pre-v9 sense. */ +static inline bool arm_space_is_secure(ARMSecuritySpace space) +{ + return space == ARMSS_Secure || space == ARMSS_Root; +} + +/* Return the ARMSecuritySpace for @secure, assuming !RME or EL[0-2]. */ +static inline ARMSecuritySpace arm_secure_to_space(bool secure) +{ + return secure ? ARMSS_Secure : ARMSS_NonSecure; +} + +#if !defined(CONFIG_USER_ONLY) +/** + * arm_security_space_below_el3: + * @env: cpu context + * + * Return the security space of exception levels below EL3, following + * an exception return to those levels. Unlike arm_security_space, + * this doesn't care about the current EL. + */ +ARMSecuritySpace arm_security_space_below_el3(CPUARMState *env); + +/** + * arm_is_secure_below_el3: + * @env: cpu context + * * Return true if exception levels below EL3 are in secure state, - * or would be following an exception return to that level. - * Unlike arm_is_secure() (which is always a question about the - * _current_ state of the CPU) this doesn't care about the current - * EL or mode. + * or would be following an exception return to those levels. */ static inline bool arm_is_secure_below_el3(CPUARMState *env) { - assert(!arm_feature(env, ARM_FEATURE_M)); - if (arm_feature(env, ARM_FEATURE_EL3)) { - return !(env->cp15.scr_el3 & SCR_NS); - } else { - /* If EL3 is not supported then the secure state is implementation - * defined, in which case QEMU defaults to non-secure. - */ - return false; - } + ARMSecuritySpace ss = arm_security_space_below_el3(env); + return ss == ARMSS_Secure; } /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ @@ -2452,16 +2480,23 @@ static inline bool arm_is_el3_or_mon(CPUARMState *env) return false; } -/* Return true if the processor is in secure state */ +/** + * arm_security_space: + * @env: cpu context + * + * Return the current security space of the cpu. + */ +ARMSecuritySpace arm_security_space(CPUARMState *env); + +/** + * arm_is_secure: + * @env: cpu context + * + * Return true if the processor is in secure state. + */ static inline bool arm_is_secure(CPUARMState *env) { - if (arm_feature(env, ARM_FEATURE_M)) { - return env->v7m.secure; - } - if (arm_is_el3_or_mon(env)) { - return true; - } - return arm_is_secure_below_el3(env); + return arm_space_is_secure(arm_security_space(env)); } /* @@ -2480,11 +2515,21 @@ static inline bool arm_is_el2_enabled(CPUARMState *env) } #else +static inline ARMSecuritySpace arm_security_space_below_el3(CPUARMState *env) +{ + return ARMSS_NonSecure; +} + static inline bool arm_is_secure_below_el3(CPUARMState *env) { return false; } +static inline ARMSecuritySpace arm_security_space(CPUARMState *env) +{ + return ARMSS_NonSecure; +} + static inline bool arm_is_secure(CPUARMState *env) { return false; diff --git a/target/arm/helper.c b/target/arm/helper.c index 006447dde8..f68923d73b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12136,3 +12136,63 @@ void aarch64_sve_change_el(CPUARMState *env, int old_el, } } #endif + +#ifndef CONFIG_USER_ONLY +ARMSecuritySpace arm_security_space(CPUARMState *env) +{ + if (arm_feature(env, ARM_FEATURE_M)) { + return arm_secure_to_space(env->v7m.secure); + } + + /* + * If EL3 is not supported then the secure state is implementation + * defined, in which case QEMU defaults to non-secure. + */ + if (!arm_feature(env, ARM_FEATURE_EL3)) { + return ARMSS_NonSecure; + } + + /* Check for AArch64 EL3 or AArch32 Mon. */ + if (is_a64(env)) { + if (extract32(env->pstate, 2, 2) == 3) { + if (cpu_isar_feature(aa64_rme, env_archcpu(env))) { + return ARMSS_Root; + } else { + return ARMSS_Secure; + } + } + } else { + if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { + return ARMSS_Secure; + } + } + + return arm_security_space_below_el3(env); +} + +ARMSecuritySpace arm_security_space_below_el3(CPUARMState *env) +{ + assert(!arm_feature(env, ARM_FEATURE_M)); + + /* + * If EL3 is not supported then the secure state is implementation + * defined, in which case QEMU defaults to non-secure. + */ + if (!arm_feature(env, ARM_FEATURE_EL3)) { + return ARMSS_NonSecure; + } + + /* + * Note NSE cannot be set without RME, and NSE & !NS is Reserved. + * Ignoring NSE when !NS retains consistency without having to + * modify other predicates. + */ + if (!(env->cp15.scr_el3 & SCR_NS)) { + return ARMSS_Secure; + } else if (env->cp15.scr_el3 & SCR_NSE) { + return ARMSS_Realm; + } else { + return ARMSS_NonSecure; + } +} +#endif /* !CONFIG_USER_ONLY */ From patchwork Tue Jun 20 12:44:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 694493 Delivered-To: patch@linaro.org Received: by 2002:adf:e885:0:0:0:0:0 with SMTP id d5csp285282wrm; Tue, 20 Jun 2023 05:45:04 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4KmKWGkkI53ZYEObNlcmpxj8/aKcvCUNdNWFU/Qw7FONA/o3obyWuWKUIc75zSnndh16aB X-Received: by 2002:a05:620a:63c9:b0:75b:3a5d:5b3a with SMTP id pw9-20020a05620a63c900b0075b3a5d5b3amr4112498qkn.62.1687265104707; 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[209.51.188.17]) by mx.google.com with ESMTPS id m4-20020a05620a13a400b00761fc2f8b84si782318qki.3.2023.06.20.05.45.04 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 20 Jun 2023 05:45:04 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=s8gCJp92; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qBaim-0001UR-Vh; Tue, 20 Jun 2023 08:44:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qBail-0001SH-Ad for qemu-devel@nongnu.org; Tue, 20 Jun 2023 08:44:31 -0400 Received: from mail-ed1-x531.google.com ([2a00:1450:4864:20::531]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qBaii-0001uI-Cx for qemu-devel@nongnu.org; Tue, 20 Jun 2023 08:44:30 -0400 Received: by mail-ed1-x531.google.com with SMTP id 4fb4d7f45d1cf-51a426e4f4bso5547955a12.1 for ; Tue, 20 Jun 2023 05:44:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687265066; x=1689857066; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0zAr88doy4l35/U8kOUIKFNAL46N655Bwwt/mOy9kK4=; b=s8gCJp921WXRNPAyCTF+FWN5A4gYJBUlq0brZTVZXS6YYJ+RsCLjWfk7Axrtp9yjFg 7Ws7c4w2/5+6d9zMm8qUO7dufshEV4xS8yWT5t/A46AULdA1a76s2HoYLOoOW9935M55 MtvlP6DJxHI/LHPiLrS3n4vJBQeaxG29mZfSHV3Ckxiz24/3080OPhhbkpUWRkJwNNwW UsmLYEOeSOhucTyjtlkIqffNH1ThdkEIF/PKOeTiQi3L/DyIWULL9jlvZQ8ueWIHSL1r FHYLkzEIFkLrJnkoPIouPAHCM+E7JaBKsaz5srxsEcQxfHOeOrZPXv2kfAZqKdwP+vLB GCWg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687265066; x=1689857066; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0zAr88doy4l35/U8kOUIKFNAL46N655Bwwt/mOy9kK4=; b=YP+G0K9wTtD+AbETuJwUKpwKP4ShLasUEpS9tglY5vi8nw6M5R+8ZzSgeM84/v0/Pd plFNMEhnGBie9aF4i478Hfap6mrw6+s6vrBimdd6kbzfJbQFiiByvxCATMx4BEZbmPWd hgf74D+ojuBXabGA14bf6jk+VoYrBfwhrCwEN5XqlUxkfc3tloaCfJ8+J+HcS67BtdcQ xLKWVHHFdB3eOuZL0c+LxVM6/6D740VyKndK9Xnr3+f2rSOBSiwZc+wwePjPAZaBEsWB 02g0fXi7V4ciqbdL8MXDwuVpb+z8/6lImGeS8p21dgU3PdnQYsOYyjm04HBOfXajau64 4Y1w== X-Gm-Message-State: AC+VfDxK8WsotlGzHfpfIhueWxwdMSAGtvkFCUjoL0mR8UrDcyZXUbOA c1P2npKVSDcvCwRTM8DPirpsZVSfnzGXFwfQHCRwV0Nz X-Received: by 2002:a50:fb0e:0:b0:51a:47d4:f515 with SMTP id d14-20020a50fb0e000000b0051a47d4f515mr5954252edq.27.1687265066036; Tue, 20 Jun 2023 05:44:26 -0700 (PDT) Received: from stoup.lan ([176.176.183.29]) by smtp.gmail.com with ESMTPSA id w9-20020aa7dcc9000000b0051a313a66e8sm1142541edu.45.2023.06.20.05.44.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Jun 2023 05:44:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v5 06/20] include/exec/memattrs: Add two bits of space to MemTxAttrs Date: Tue, 20 Jun 2023 14:44:04 +0200 Message-Id: <20230620124418.805717-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230620124418.805717-1-richard.henderson@linaro.org> References: <20230620124418.805717-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::531; envelope-from=richard.henderson@linaro.org; helo=mail-ed1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org We will need 2 bits to represent ARMSecurityState. Do not attempt to replace or widen secure, even though it logically overlaps the new field -- there are uses within e.g. hw/block/pflash_cfi01.c, which don't know anything specific about ARM. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- include/exec/memattrs.h | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h index 9fb98bc1ef..d04170aa27 100644 --- a/include/exec/memattrs.h +++ b/include/exec/memattrs.h @@ -29,10 +29,17 @@ typedef struct MemTxAttrs { * "didn't specify" if necessary. */ unsigned int unspecified:1; - /* ARM/AMBA: TrustZone Secure access + /* + * ARM/AMBA: TrustZone Secure access * x86: System Management Mode access */ unsigned int secure:1; + /* + * ARM: ArmSecuritySpace. This partially overlaps secure, but it is + * easier to have both fields to assist code that does not understand + * ARMv9 RME, or no specific knowledge of ARM at all (e.g. pflash). + */ + unsigned int space:2; /* Memory access is usermode (unprivileged) */ unsigned int user:1; /* From patchwork Tue Jun 20 12:44:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 694508 Delivered-To: patch@linaro.org Received: by 2002:adf:e885:0:0:0:0:0 with SMTP id d5csp286808wrm; Tue, 20 Jun 2023 05:48:32 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4jaEbZRX4q1+70kRP14vqSXeZ+ECtdIHPHBlrimLBlWtDhvFlnngt4GbsNe896H5Rl8ksS X-Received: by 2002:a05:620a:450f:b0:75f:5df:1652 with SMTP id t15-20020a05620a450f00b0075f05df1652mr15561349qkp.68.1687265312239; Tue, 20 Jun 2023 05:48:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687265312; cv=none; d=google.com; s=arc-20160816; b=ysays6Ukb4o0rC1+l3CFoo4er+iaIN2nSyacwF4OHeTsLUZZy6daPuXOBo4jJ3BW5s iWnblYx56rZOIIGGXluP3usIlJc8yN5lTUN9VJRuUUkeAkucNQHNqL1mVmLLN7sM9AJ4 Lt6TZdgMPRA3oMBF19EctKlV7ZZOqO8TfOd5BeKTsv/K06Zkjr3oJ1eJckTNMQPxPt74 TC4vUgIr4eq5PJ7hwxpw+1nlyk/R6rQrpAAeU7HACf5Kl24Hke71oN3CSWkTSaGkpn4Z 735KTK9p8OZjZ64zn9P/K7tGGigl3/Scm3vn1yeuBBSL8hOECK97hKmDLhHjjTKWnw0X 8GUw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=ufvtDg+SmNGDf9pVWsSClAqyvu8TpfX9hKzFT9IdNIg=; b=Ru8UxVJ6H+SozJCjMt46SfoY7ZH6KLFKCQW9cbsLkl1HPR5oRxYFb1tp+yTDk1Vp9V OfDN0yAwG9xpeLxl48CxaqIxLU8X3Z3kynHtKh1sBiopr9+2vYJzOROfy0t6dAtUhSSK epzIw/mkFlOmuJ2E7l9f24mGErAg4NtFHOls0A1mGJYxEziYMNwu5WumLxL1ubB54pNe oMP7jNolaBjtVonsTeOnkKuIOyfuPsm0IQHOQ9R0Lpx/u/9tfx/38g85DIf7QoQXOubx 4AeJNuuD8d33oumhE+M+X0F/V1UrxB1SRrKTsy3S5CWMxKEn/LSOB2m1vSXWRRjTe155 981Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=uvyAKOQP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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This requires the adjustment to the nstable check. While there, check for being in secure state rather than rely on clearing the low bit making no change to non-secure state. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 12 ++++++------ target/arm/ptw.c | 12 +++++------- 2 files changed, 11 insertions(+), 13 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 125e53b83f..b338619775 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2860,18 +2860,18 @@ typedef enum ARMMMUIdx { ARMMMUIdx_E2 = 6 | ARM_MMU_IDX_A, ARMMMUIdx_E3 = 7 | ARM_MMU_IDX_A, - /* TLBs with 1-1 mapping to the physical address spaces. */ - ARMMMUIdx_Phys_NS = 8 | ARM_MMU_IDX_A, - ARMMMUIdx_Phys_S = 9 | ARM_MMU_IDX_A, - /* * Used for second stage of an S12 page table walk, or for descriptor * loads during first stage of an S1 page table walk. Note that both * are in use simultaneously for SecureEL2: the security state for * the S2 ptw is selected by the NS bit from the S1 ptw. */ - ARMMMUIdx_Stage2 = 10 | ARM_MMU_IDX_A, - ARMMMUIdx_Stage2_S = 11 | ARM_MMU_IDX_A, + ARMMMUIdx_Stage2_S = 8 | ARM_MMU_IDX_A, + ARMMMUIdx_Stage2 = 9 | ARM_MMU_IDX_A, + + /* TLBs with 1-1 mapping to the physical address spaces. */ + ARMMMUIdx_Phys_S = 10 | ARM_MMU_IDX_A, + ARMMMUIdx_Phys_NS = 11 | ARM_MMU_IDX_A, /* * These are not allocated TLBs and are used only for AT system diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 37bcb17a9e..3f3517f70b 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1449,16 +1449,14 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, descaddr |= (address >> (stride * (4 - level))) & indexmask; descaddr &= ~7ULL; nstable = !regime_is_stage2(mmu_idx) && extract32(tableattrs, 4, 1); - if (nstable) { + if (nstable && ptw->in_secure) { /* * Stage2_S -> Stage2 or Phys_S -> Phys_NS - * Assert that the non-secure idx are even, and relative order. + * Assert the relative order of the secure/non-secure indexes. */ - QEMU_BUILD_BUG_ON((ARMMMUIdx_Phys_NS & 1) != 0); - QEMU_BUILD_BUG_ON((ARMMMUIdx_Stage2 & 1) != 0); - QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_NS + 1 != ARMMMUIdx_Phys_S); - QEMU_BUILD_BUG_ON(ARMMMUIdx_Stage2 + 1 != ARMMMUIdx_Stage2_S); - ptw->in_ptw_idx &= ~1; + QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_S + 1 != ARMMMUIdx_Phys_NS); + QEMU_BUILD_BUG_ON(ARMMMUIdx_Stage2_S + 1 != ARMMMUIdx_Stage2); + ptw->in_ptw_idx += 1; ptw->in_secure = false; } if (!S1_ptw_translate(env, ptw, descaddr, fi)) { From patchwork Tue Jun 20 12:44:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 694495 Delivered-To: patch@linaro.org Received: by 2002:adf:e885:0:0:0:0:0 with SMTP id d5csp285350wrm; Tue, 20 Jun 2023 05:45:12 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4lCHd3xVXkGI8yOEy89aJZ/ZvakRYiuz/Zl39EhakGAOWjJr2cMlRzHVseQ8wnlfjim0jk X-Received: by 2002:a05:620a:3953:b0:75b:23a1:460 with SMTP id qs19-20020a05620a395300b0075b23a10460mr15199896qkn.38.1687265112262; Tue, 20 Jun 2023 05:45:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687265112; cv=none; d=google.com; s=arc-20160816; b=wnqHJIA3nas8VIPR2n/Ikki2idbjZdrEuXMur5i7+nC0nC/L1XNIwX1X5zRXeoLF0S 3acEXzeaULkS4n595G135WZ3HNccBhYnlkY51kpSpuCqoPivWnZ954eYV01hSONJDL9m pYRsMpEb2sfk0zwD1fO1Pxk4bocMhqiW+puKvx9XCpUU+404tfm3GrzjMYZM3ltzpLtK OFNyqtiFdxWC+HMeKDNOXwLEKi4pA+zTX5kq0N+AmocIE66xaAAZZDWHRPwMj/W7+hAw vUBb/tVKpQaP4fo9thoGE//SNEW+SywyPlWAgLqDSf30rQdX4TVQrLEUMWe5NBaNtrm8 3fEQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=WJWL093vV/sudKyK+aOjpNFbGT4nrMy+vm7a5Pxrsp0=; b=ddiPermymrJtS4dtC77GeJtzAgzzQUmVPBWAIqVbq6KDdjYcWXoKY68NwqlfBz6fzb OkjA7Cz4ykdUasTdH/CO4wWSirz2tcRvULtdo6WtGLD4zMfKzzMMgLC1jAbAG3btJ1Ww RlTuB4WG9zNZl/gvDbBmBH7Oy2ZF7Hx9oSU7ONElVLNz99fVFBCrOyBLU6hF5uKyhe8I 5RIKw5nGTb6NeaoR1fPsbQlpWimrXDn7AvGcZI3TY1CSh9a5jTshCtRyyNnKCF23hUhp rRvcgopwxrMYOjNK6qQ7a4Ehrvw2NTi8cL6Fi796bFjreHE703fkju2nYDGWVBtOh0E1 5ALQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=whFhR45r; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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For now, just define the symbols, and mention them in the same spots as the other Phys indexes in ptw.c. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 23 +++++++++++++++++++++-- target/arm/ptw.c | 10 ++++++++-- 2 files changed, 29 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index b338619775..590216b855 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2870,8 +2870,10 @@ typedef enum ARMMMUIdx { ARMMMUIdx_Stage2 = 9 | ARM_MMU_IDX_A, /* TLBs with 1-1 mapping to the physical address spaces. */ - ARMMMUIdx_Phys_S = 10 | ARM_MMU_IDX_A, - ARMMMUIdx_Phys_NS = 11 | ARM_MMU_IDX_A, + ARMMMUIdx_Phys_S = 10 | ARM_MMU_IDX_A, + ARMMMUIdx_Phys_NS = 11 | ARM_MMU_IDX_A, + ARMMMUIdx_Phys_Root = 12 | ARM_MMU_IDX_A, + ARMMMUIdx_Phys_Realm = 13 | ARM_MMU_IDX_A, /* * These are not allocated TLBs and are used only for AT system @@ -2935,6 +2937,23 @@ typedef enum ARMASIdx { ARMASIdx_TagS = 3, } ARMASIdx; +static inline ARMMMUIdx arm_space_to_phys(ARMSecuritySpace space) +{ + /* Assert the relative order of the physical mmu indexes. */ + QEMU_BUILD_BUG_ON(ARMSS_Secure != 0); + QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_NS != ARMMMUIdx_Phys_S + ARMSS_NonSecure); + QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_Root != ARMMMUIdx_Phys_S + ARMSS_Root); + QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_Realm != ARMMMUIdx_Phys_S + ARMSS_Realm); + + return ARMMMUIdx_Phys_S + space; +} + +static inline ARMSecuritySpace arm_phys_to_space(ARMMMUIdx idx) +{ + assert(idx >= ARMMMUIdx_Phys_S && idx <= ARMMMUIdx_Phys_Realm); + return idx - ARMMMUIdx_Phys_S; +} + static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu) { /* If all the CLIDR.Ctypem bits are 0 there are no caches, and diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 3f3517f70b..a742bc1826 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -215,8 +215,10 @@ static bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx, case ARMMMUIdx_E3: break; - case ARMMMUIdx_Phys_NS: case ARMMMUIdx_Phys_S: + case ARMMMUIdx_Phys_NS: + case ARMMMUIdx_Phys_Root: + case ARMMMUIdx_Phys_Realm: /* No translation for physical address spaces. */ return true; @@ -2672,8 +2674,10 @@ static bool get_phys_addr_disabled(CPUARMState *env, target_ulong address, switch (mmu_idx) { case ARMMMUIdx_Stage2: case ARMMMUIdx_Stage2_S: - case ARMMMUIdx_Phys_NS: case ARMMMUIdx_Phys_S: + case ARMMMUIdx_Phys_NS: + case ARMMMUIdx_Phys_Root: + case ARMMMUIdx_Phys_Realm: break; default: @@ -2861,6 +2865,8 @@ static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw, switch (mmu_idx) { case ARMMMUIdx_Phys_S: case ARMMMUIdx_Phys_NS: + case ARMMMUIdx_Phys_Root: + case ARMMMUIdx_Phys_Realm: /* Checking Phys early avoids special casing later vs regime_el. */ return get_phys_addr_disabled(env, address, access_type, mmu_idx, is_secure, result, fi); From patchwork Tue Jun 20 12:44:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 694506 Delivered-To: patch@linaro.org Received: by 2002:adf:e885:0:0:0:0:0 with SMTP id d5csp286302wrm; Tue, 20 Jun 2023 05:47:23 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7kcDmJRKnjWEigNJhyQaWF7BkiJhKDc6NBdCq1aPRs5ujYgQVbi1KcGCT0IfkL5wNyme2A X-Received: by 2002:a1f:c1cf:0:b0:471:1785:e838 with SMTP id r198-20020a1fc1cf000000b004711785e838mr3743961vkf.2.1687265243580; Tue, 20 Jun 2023 05:47:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687265243; cv=none; d=google.com; s=arc-20160816; b=Ud3nK1gUPTDg4HMSe+KeaF3Cdg9s2Vz9msvlfO2DA2jogGndn6v5uC9aMsU49885ZP g2+EfKnRApXM+1jGOi9uFrtsTGLVoHxYPPP3gBNSJVIx7UN4dTfPbUkiWpWUK5O9nAkr 3r10LPBnetr1ypKhQFa4o1HXCq8CsP50VNCQmRPAA7O1x2dau1Uw0+7KGMtSZIHuKk8P ooPClKf8FCEzdK08iKRHI0GvyvTRfWvQjaXcpZOOU8f4SLSqkUuB4nrJsEZHdKx7JDr7 VyPJGreb31YgVAQAHLctH0piee8XzQTEhPGNkheXlfV9ffa2DjTUECFwIK1gFxQ/utHA W7QA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=oYM1MGsrvUKsckHAPaAPGoH4M7K9gyTZzZ7Te/btT8c=; b=SW/mb5OxDg8U57AWErh47lDox129tR/UwQCpO4l6fu+I2mOhbrbIYl8livZ+hnfCaa 2tdpzYJSPubW0+qWu1TmJaz1BOl7T+qGXjYvfBRTVuLw6mDgI1bkj2NihYrHJk6Cxm1Z gY3jELmhOiJymYs45E273qihXsAXarKkiwS67SButIsap8g29xl+cX+Qzsg099ab/7yh z18YHKP4FwB5n7cvF9s+D6eIUyB4a4Ph5hWrFou5DUHvjqr8Xy7/mUiQHrZofdVU9U7g PnrjUpjs5OoVjYaYearUY0TwibisCuqv+muboM/eOY1WB24PLB1RonmQWr0mpUzelA+M uLNw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SPEhzb+A; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Now that the reorg is complete, this serves little purpose. Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/arm/ptw.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index a742bc1826..f7cbb984f9 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -34,15 +34,13 @@ typedef struct S1Translate { static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, uint64_t address, MMUAccessType access_type, bool s1_is_el0, - GetPhysAddrResult *result, ARMMMUFaultInfo *fi) - __attribute__((nonnull)); + GetPhysAddrResult *result, ARMMMUFaultInfo *fi); static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw, target_ulong address, MMUAccessType access_type, GetPhysAddrResult *result, - ARMMMUFaultInfo *fi) - __attribute__((nonnull)); + ARMMMUFaultInfo *fi); /* This mapping is common between ID_AA64MMFR0.PARANGE and TCR_ELx.{I}PS. */ static const uint8_t pamax_map[] = { From patchwork Tue Jun 20 12:44:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 694509 Delivered-To: patch@linaro.org Received: by 2002:adf:e885:0:0:0:0:0 with SMTP id d5csp287002wrm; Tue, 20 Jun 2023 05:48:59 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ78jehtaM86X9yMzQJcecTTnsRmLTp0B1C1an6EG8dDR2l1zpmGKbei777EUQHpEQU2ab4E X-Received: by 2002:a1f:c807:0:b0:461:98db:89a3 with SMTP id y7-20020a1fc807000000b0046198db89a3mr4566912vkf.9.1687265338903; Tue, 20 Jun 2023 05:48:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687265338; cv=none; d=google.com; s=arc-20160816; b=qxl3FRY1w1e2UeUrXabvmpJ+q6LuU2PG8qHUTk3gQAOUd5dURurLnEmDtVvm9fyNlT MS0ddDW3esAm+tNf5spCdZlGDnzNcn2UC9KPDYRwWa1THzfMCOhqr1Pi2aU2oXG65e0J oruqAOQotrh+8EWuj7XeeVVx3/gXpjM69TLYmlHd6vFJhw1OUjL8rjM06T/Ia7fZaZ+g Br/i+E2XB1WN8mAcQGy2ZpcrfhLPrlb7I+yYkoyDIA+vo50QLrFXHztQ0+ROq3SRmffl YBeJzIrGEaj1oG9OKZBb7IlxITqrJ4R6kKg7Sr4QH+HaqZ5I/BLQhT4C5JcLK6bIocGo 3gQA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=64kg+SV3talnh4LFHnsMC7T72wL0UZ7F9UrDoB7T0v4=; b=A03QKTiSu4iMHe/7SzEVtMg1W4wpZuuNZxkvB/GQ9/RQrRansrSdaIXJLSz3qGdoKS 9LlfI90dsWCKbqM7axwnoAY74NLhwPzmNcj/to8hkcG6GSxp7Cs1wI8+BL8KuLCxpOWu b4n7lK8GbEc0Y9kU2jJLny7NjDC/s2eckAJn2xMosL0cD5xMZWw5q65d+LFcncD4NZhX W/XTK3R14PIAe94DrHXQdnNmx+cHDFTwvIDeEenpigbXB1CJzPciOBWkma8MWXaldc5l Jevn+lyLdEKKIo1v2jVhS+y7jTLa3OM4StWpNFaRgUX4Y7FocyyDHTH5jyoinxA7m5zW JkmQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=qiCd6TuG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Set and adjust them in S1_ptw_translate, and the various points at which we drop secure state. Initialize the space in get_phys_addr; for now leave get_phys_addr_with_secure considering only secure vs non-secure spaces. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/ptw.c | 86 +++++++++++++++++++++++++++++++++++++++--------- 1 file changed, 71 insertions(+), 15 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index f7cbb984f9..e1e7c9a3d2 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -21,11 +21,13 @@ typedef struct S1Translate { ARMMMUIdx in_mmu_idx; ARMMMUIdx in_ptw_idx; + ARMSecuritySpace in_space; bool in_secure; bool in_debug; bool out_secure; bool out_rw; bool out_be; + ARMSecuritySpace out_space; hwaddr out_virt; hwaddr out_phys; void *out_host; @@ -249,6 +251,7 @@ static bool S2_attrs_are_device(uint64_t hcr, uint8_t attrs) static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, hwaddr addr, ARMMMUFaultInfo *fi) { + ARMSecuritySpace space = ptw->in_space; bool is_secure = ptw->in_secure; ARMMMUIdx mmu_idx = ptw->in_mmu_idx; ARMMMUIdx s2_mmu_idx = ptw->in_ptw_idx; @@ -266,6 +269,9 @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, .in_mmu_idx = s2_mmu_idx, .in_ptw_idx = ptw_idx_for_stage_2(env, s2_mmu_idx), .in_secure = s2_mmu_idx == ARMMMUIdx_Stage2_S, + .in_space = (s2_mmu_idx == ARMMMUIdx_Stage2_S ? ARMSS_Secure + : space == ARMSS_Realm ? ARMSS_Realm + : ARMSS_NonSecure), .in_debug = true, }; GetPhysAddrResult s2 = { }; @@ -277,11 +283,15 @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, ptw->out_phys = s2.f.phys_addr; pte_attrs = s2.cacheattrs.attrs; ptw->out_secure = s2.f.attrs.secure; + ptw->out_space = s2.f.attrs.space; } else { /* Regime is physical. */ ptw->out_phys = addr; pte_attrs = 0; ptw->out_secure = s2_mmu_idx == ARMMMUIdx_Phys_S; + ptw->out_space = (s2_mmu_idx == ARMMMUIdx_Phys_S ? ARMSS_Secure + : space == ARMSS_Realm ? ARMSS_Realm + : ARMSS_NonSecure); } ptw->out_host = NULL; ptw->out_rw = false; @@ -303,6 +313,7 @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, ptw->out_rw = full->prot & PAGE_WRITE; pte_attrs = full->pte_attrs; ptw->out_secure = full->attrs.secure; + ptw->out_space = full->attrs.space; #else g_assert_not_reached(); #endif @@ -355,7 +366,10 @@ static uint32_t arm_ldl_ptw(CPUARMState *env, S1Translate *ptw, } } else { /* Page tables are in MMIO. */ - MemTxAttrs attrs = { .secure = ptw->out_secure }; + MemTxAttrs attrs = { + .secure = ptw->out_secure, + .space = ptw->out_space, + }; AddressSpace *as = arm_addressspace(cs, attrs); MemTxResult result = MEMTX_OK; @@ -398,7 +412,10 @@ static uint64_t arm_ldq_ptw(CPUARMState *env, S1Translate *ptw, #endif } else { /* Page tables are in MMIO. */ - MemTxAttrs attrs = { .secure = ptw->out_secure }; + MemTxAttrs attrs = { + .secure = ptw->out_secure, + .space = ptw->out_space, + }; AddressSpace *as = arm_addressspace(cs, attrs); MemTxResult result = MEMTX_OK; @@ -909,6 +926,7 @@ static bool get_phys_addr_v6(CPUARMState *env, S1Translate *ptw, * regime, because the attribute will already be non-secure. */ result->f.attrs.secure = false; + result->f.attrs.space = ARMSS_NonSecure; } result->f.phys_addr = phys_addr; return false; @@ -1616,6 +1634,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, * regime, because the attribute will already be non-secure. */ result->f.attrs.secure = false; + result->f.attrs.space = ARMSS_NonSecure; } if (regime_is_stage2(mmu_idx)) { @@ -2400,6 +2419,7 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address, */ if (sattrs.ns) { result->f.attrs.secure = false; + result->f.attrs.space = ARMSS_NonSecure; } else if (!secure) { /* * NS access to S memory must fault. @@ -2750,6 +2770,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw, bool is_secure = ptw->in_secure; bool ret, ipa_secure; ARMCacheAttrs cacheattrs1; + ARMSecuritySpace ipa_space; bool is_el0; uint64_t hcr; @@ -2762,10 +2783,12 @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw, ipa = result->f.phys_addr; ipa_secure = result->f.attrs.secure; + ipa_space = result->f.attrs.space; is_el0 = ptw->in_mmu_idx == ARMMMUIdx_Stage1_E0; ptw->in_mmu_idx = ipa_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2; ptw->in_secure = ipa_secure; + ptw->in_space = ipa_space; ptw->in_ptw_idx = ptw_idx_for_stage_2(env, ptw->in_mmu_idx); /* @@ -2854,11 +2877,12 @@ static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw, ARMMMUIdx s1_mmu_idx; /* - * The page table entries may downgrade secure to non-secure, but - * cannot upgrade an non-secure translation regime's attributes - * to secure. + * The page table entries may downgrade Secure to NonSecure, but + * cannot upgrade a NonSecure translation regime's attributes + * to Secure or Realm. */ result->f.attrs.secure = is_secure; + result->f.attrs.space = ptw->in_space; switch (mmu_idx) { case ARMMMUIdx_Phys_S: @@ -2910,7 +2934,7 @@ static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw, default: /* Single stage uses physical for ptw. */ - ptw->in_ptw_idx = is_secure ? ARMMMUIdx_Phys_S : ARMMMUIdx_Phys_NS; + ptw->in_ptw_idx = arm_space_to_phys(ptw->in_space); break; } @@ -2985,6 +3009,7 @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address, S1Translate ptw = { .in_mmu_idx = mmu_idx, .in_secure = is_secure, + .in_space = arm_secure_to_space(is_secure), }; return get_phys_addr_with_struct(env, &ptw, address, access_type, result, fi); @@ -2994,7 +3019,10 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, MMUAccessType access_type, ARMMMUIdx mmu_idx, GetPhysAddrResult *result, ARMMMUFaultInfo *fi) { - bool is_secure; + S1Translate ptw = { + .in_mmu_idx = mmu_idx, + }; + ARMSecuritySpace ss; switch (mmu_idx) { case ARMMMUIdx_E10_0: @@ -3007,30 +3035,55 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, case ARMMMUIdx_Stage1_E1: case ARMMMUIdx_Stage1_E1_PAN: case ARMMMUIdx_E2: - is_secure = arm_is_secure_below_el3(env); + ss = arm_security_space_below_el3(env); break; case ARMMMUIdx_Stage2: + /* + * For Secure EL2, we need this index to be NonSecure; + * otherwise this will already be NonSecure or Realm. + */ + ss = arm_security_space_below_el3(env); + if (ss == ARMSS_Secure) { + ss = ARMSS_NonSecure; + } + break; case ARMMMUIdx_Phys_NS: case ARMMMUIdx_MPrivNegPri: case ARMMMUIdx_MUserNegPri: case ARMMMUIdx_MPriv: case ARMMMUIdx_MUser: - is_secure = false; + ss = ARMSS_NonSecure; break; - case ARMMMUIdx_E3: case ARMMMUIdx_Stage2_S: case ARMMMUIdx_Phys_S: case ARMMMUIdx_MSPrivNegPri: case ARMMMUIdx_MSUserNegPri: case ARMMMUIdx_MSPriv: case ARMMMUIdx_MSUser: - is_secure = true; + ss = ARMSS_Secure; + break; + case ARMMMUIdx_E3: + if (arm_feature(env, ARM_FEATURE_AARCH64) && + cpu_isar_feature(aa64_rme, env_archcpu(env))) { + ss = ARMSS_Root; + } else { + ss = ARMSS_Secure; + } + break; + case ARMMMUIdx_Phys_Root: + ss = ARMSS_Root; + break; + case ARMMMUIdx_Phys_Realm: + ss = ARMSS_Realm; break; default: g_assert_not_reached(); } - return get_phys_addr_with_secure(env, address, access_type, mmu_idx, - is_secure, result, fi); + + ptw.in_space = ss; + ptw.in_secure = arm_space_is_secure(ss); + return get_phys_addr_with_struct(env, &ptw, address, access_type, + result, fi); } hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, @@ -3038,9 +3091,12 @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, { ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; + ARMMMUIdx mmu_idx = arm_mmu_idx(env); + ARMSecuritySpace ss = arm_security_space(env); S1Translate ptw = { - .in_mmu_idx = arm_mmu_idx(env), - .in_secure = arm_is_secure(env), + .in_mmu_idx = mmu_idx, + .in_space = ss, + .in_secure = arm_space_is_secure(ss), .in_debug = true, }; GetPhysAddrResult res = {}; From patchwork Tue Jun 20 12:44:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 694497 Delivered-To: patch@linaro.org Received: by 2002:adf:e885:0:0:0:0:0 with SMTP id d5csp285554wrm; Tue, 20 Jun 2023 05:45:37 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4XTTHIMBI83SsS5SNGsK74OuvjrV9ldUeWGloaQGcL7nLu5JfM+zVr1YB8Ku6SZQ4v3Y/z X-Received: by 2002:a67:f8d7:0:b0:43f:4779:49ca with SMTP id c23-20020a67f8d7000000b0043f477949camr3074736vsp.5.1687265137667; Tue, 20 Jun 2023 05:45:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687265137; cv=none; d=google.com; s=arc-20160816; b=xfu3BnRpc5MEzXHLNcVFvphB1JeWsnrd85dh/e85Im7HUbUNSrtBnBztOXFlA/mmwh j+UKhb96Atx+dfrMssWMoy+UpsDzcih+GD6+1AYZUswf0XJJi8DaV6Mb+Jvk7hGI8TqO s8sOJizSJoEtYXqLKxVs1xQ+bJf0RBxdQzFn4WurrQN99HG7YC5nfRA5zOgFPc/yovCw eail22Yqqs+EUI/HUCeGjPisNVluPiJY2G11pAA+j/jGt6svyNO6znY2JGjmQqW0jKyd Kzuhzkq7x5YkJ9goqpYo8SZeVKLFzTixoN8oj/zx/n/su4vmqPEqeowyADsSR+w0uJjD /IKw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=gZoCPFOzdlqGrG+xNAx7E2r/mp3y3fmrhU6I+AHQFUA=; b=t+zu9xE3zBY25e1VAebhmKI1DaB+X0lB7nAcUnimxnsiNJH1a0nT/5ySPv8a6EXSs7 X10PV1rOnZMuGBtxYFzqMuEWZH5N+HWURGVYcSYaicR3JMATeEqmIGhhnGnFkVZm4CzR BbKD4ZwAiAtK9SDYBmWV40ERa+KF2YwGbP8PqfOSaF4a7d6P3cWGYZ455xBHnkcMkqzY MMDDuuGEjUeST5/Qdq1AjX/KUU+BoForaRQUwUYZ0spXX98oQxyhJE9DJYwdFbOfffWb c2r0jeRui9H2KlA3ByAS639PfQ/Rk6gdWPq8hjwi1tXK9W4jlybQCFNiQjfxsQptXpNJ +QeA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=rmZ17cyz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/ptw.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index e1e7c9a3d2..ea0ad56f13 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1275,7 +1275,6 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, { ARMCPU *cpu = env_archcpu(env); ARMMMUIdx mmu_idx = ptw->in_mmu_idx; - bool is_secure = ptw->in_secure; int32_t level; ARMVAParameters param; uint64_t ttbr; @@ -1291,7 +1290,6 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, uint64_t descaddrmask; bool aarch64 = arm_el_is_aa64(env, el); uint64_t descriptor, new_descriptor; - bool nstable; /* TODO: This code does not support shareability levels. */ if (aarch64) { @@ -1453,21 +1451,21 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, descaddrmask = MAKE_64BIT_MASK(0, 40); } descaddrmask &= ~indexmask_grainsize; - - /* - * Secure stage 1 accesses start with the page table in secure memory and - * can be downgraded to non-secure at any step. Non-secure accesses - * remain non-secure. We implement this by just ORing in the NSTable/NS - * bits at each step. - * Stage 2 never gets this kind of downgrade. - */ - tableattrs = is_secure ? 0 : (1 << 4); + tableattrs = 0; next_level: descaddr |= (address >> (stride * (4 - level))) & indexmask; descaddr &= ~7ULL; - nstable = !regime_is_stage2(mmu_idx) && extract32(tableattrs, 4, 1); - if (nstable && ptw->in_secure) { + + /* + * Process the NSTable bit from the previous level. This changes + * the table address space and the output space from Secure to + * NonSecure. With RME, the EL3 translation regime does not change + * from Root to NonSecure. + */ + if (ptw->in_space == ARMSS_Secure + && !regime_is_stage2(mmu_idx) + && extract32(tableattrs, 4, 1)) { /* * Stage2_S -> Stage2 or Phys_S -> Phys_NS * Assert the relative order of the secure/non-secure indexes. @@ -1476,7 +1474,9 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, QEMU_BUILD_BUG_ON(ARMMMUIdx_Stage2_S + 1 != ARMMMUIdx_Stage2); ptw->in_ptw_idx += 1; ptw->in_secure = false; + ptw->in_space = ARMSS_NonSecure; } + if (!S1_ptw_translate(env, ptw, descaddr, fi)) { goto do_fault; } @@ -1579,7 +1579,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, */ attrs = new_descriptor & (MAKE_64BIT_MASK(2, 10) | MAKE_64BIT_MASK(50, 14)); if (!regime_is_stage2(mmu_idx)) { - attrs |= nstable << 5; /* NS */ + attrs |= !ptw->in_secure << 5; /* NS */ if (!param.hpd) { attrs |= extract64(tableattrs, 0, 2) << 53; /* XN, PXN */ /* From patchwork Tue Jun 20 12:44:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 694496 Delivered-To: patch@linaro.org Received: by 2002:adf:e885:0:0:0:0:0 with SMTP id d5csp285451wrm; Tue, 20 Jun 2023 05:45:24 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7Fc/IOdyw5gL1kFH2y/ouHPmnv3nap2fD5bZYBQ94oOBYo1nSm4UzKEL77q8C6lZ3gEdOn X-Received: by 2002:a05:620a:3d0d:b0:75f:403:77a8 with SMTP id tq13-20020a05620a3d0d00b0075f040377a8mr3700684qkn.31.1687265123857; Tue, 20 Jun 2023 05:45:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687265123; cv=none; d=google.com; s=arc-20160816; b=lBIAk2EB3fEjoU7myATNp8V5qfVZ2+BykfCZn5kjp8L2fddcnQaGlI/UJG6jRy+dF2 QtMkRsUtqHcj1ZcSFZb1n9RqrVUAWNScAol76TYXrhtFRx3N/DirUOyuWzGHYhkx+xVS qaqa28LmAOveiplw+JGg1KPC+RDyTVorbhRzfBFP8WBtgtioXrGmlel7kTvJevwh1Z31 AvG4d+8CMVCHnDiV8VnyDJfxLHprP8WWzp8tAyYSdheN3Imh8voQsL2hpSPrhqrzKbgC Sg0UIRKphE2+P2ue3hUgxvqPvbuEe0delNSt4sGjXDzDTVvce5OWBoO5UtDKPv0xiZ19 K3VA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=P7nEO8a+eNnzXCBeEFSRpz3ImKrw9b1VGkr4avGc3a4=; b=YUjv+jg2uBx1osdWD23Ac1WCD4LWBvmmi6L37X3kZ/wbLvqACcqOrm6HasXViey6KF 2IKMemOJfEkbl/hI92O95ZXKuUuAF8hB/PixeXkLpawqtqj0kAXkSOMQ50nLcVjUenMq 5REUk3kgbGGu3K2OXd93j/+bAo4yNI26h+spuclQYv8g1utyi0GLNk1rw5+J8Ctd4h6y cnatUoVEGQDgIvYucgfXyf8UC/9/jUeNoHZumDR9aS2ImJYcrY1MKe9QgdZF9hVYxY/+ tmPvivj/BP63leznaF9tIi68V+7Tt4JvpWaeCBUtHTGEJ+8hbS3VK7an/h5s43owHToT VhdA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SRihU2uA; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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With Root security state, bit 11 of the block or page descriptor during the stage1 walk becomes the NSE bit. Rather than collecting an NS bit and applying it later, compute the output pa space from the input pa space and unconditionally assign. This means that we no longer need to adjust the output space earlier for the NSTable bit. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/ptw.c | 89 +++++++++++++++++++++++++++++++++++++++--------- 1 file changed, 73 insertions(+), 16 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index ea0ad56f13..bbae432861 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -990,12 +990,14 @@ static int get_S2prot(CPUARMState *env, int s2ap, int xn, bool s1_is_el0) * @mmu_idx: MMU index indicating required translation regime * @is_aa64: TRUE if AArch64 * @ap: The 2-bit simple AP (AP[2:1]) - * @ns: NS (non-secure) bit * @xn: XN (execute-never) bit * @pxn: PXN (privileged execute-never) bit + * @in_pa: The original input pa space + * @out_pa: The output pa space, modified by NSTable, NS, and NSE */ static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64, - int ap, int ns, int xn, int pxn) + int ap, int xn, int pxn, + ARMSecuritySpace in_pa, ARMSecuritySpace out_pa) { ARMCPU *cpu = env_archcpu(env); bool is_user = regime_is_user(env, mmu_idx); @@ -1028,7 +1030,8 @@ static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64, } } - if (ns && arm_is_secure(env) && (env->cp15.scr_el3 & SCR_SIF)) { + if (out_pa == ARMSS_NonSecure && in_pa == ARMSS_Secure && + (env->cp15.scr_el3 & SCR_SIF)) { return prot_rw; } @@ -1285,11 +1288,12 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, int32_t stride; int addrsize, inputsize, outputsize; uint64_t tcr = regime_tcr(env, mmu_idx); - int ap, ns, xn, pxn; + int ap, xn, pxn; uint32_t el = regime_el(env, mmu_idx); uint64_t descaddrmask; bool aarch64 = arm_el_is_aa64(env, el); uint64_t descriptor, new_descriptor; + ARMSecuritySpace out_space; /* TODO: This code does not support shareability levels. */ if (aarch64) { @@ -1592,15 +1596,75 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, } ap = extract32(attrs, 6, 2); + out_space = ptw->in_space; if (regime_is_stage2(mmu_idx)) { - ns = mmu_idx == ARMMMUIdx_Stage2; + /* + * R_GYNXY: For stage2 in Realm security state, bit 55 is NS. + * The bit remains ignored for other security states. + */ + if (out_space == ARMSS_Realm && extract64(attrs, 55, 1)) { + out_space = ARMSS_NonSecure; + } xn = extract64(attrs, 53, 2); result->f.prot = get_S2prot(env, ap, xn, s1_is_el0); } else { - ns = extract32(attrs, 5, 1); + int nse, ns = extract32(attrs, 5, 1); + switch (out_space) { + case ARMSS_Root: + /* + * R_GVZML: Bit 11 becomes the NSE field in the EL3 regime. + * R_XTYPW: NSE and NS together select the output pa space. + */ + nse = extract32(attrs, 11, 1); + out_space = (nse << 1) | ns; + if (out_space == ARMSS_Secure && + !cpu_isar_feature(aa64_sel2, cpu)) { + out_space = ARMSS_NonSecure; + } + break; + case ARMSS_Secure: + if (ns) { + out_space = ARMSS_NonSecure; + } + break; + case ARMSS_Realm: + switch (mmu_idx) { + case ARMMMUIdx_Stage1_E0: + case ARMMMUIdx_Stage1_E1: + case ARMMMUIdx_Stage1_E1_PAN: + /* I_CZPRF: For Realm EL1&0 stage1, NS bit is RES0. */ + break; + case ARMMMUIdx_E2: + case ARMMMUIdx_E20_0: + case ARMMMUIdx_E20_2: + case ARMMMUIdx_E20_2_PAN: + /* + * R_LYKFZ, R_WGRZN: For Realm EL2 and EL2&1, + * NS changes the output to non-secure space. + */ + if (ns) { + out_space = ARMSS_NonSecure; + } + break; + default: + g_assert_not_reached(); + } + break; + case ARMSS_NonSecure: + /* R_QRMFF: For NonSecure state, the NS bit is RES0. */ + break; + default: + g_assert_not_reached(); + } xn = extract64(attrs, 54, 1); pxn = extract64(attrs, 53, 1); - result->f.prot = get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, pxn); + + /* + * Note that we modified ptw->in_space earlier for NSTable, but + * result->f.attrs retains a copy of the original security space. + */ + result->f.prot = get_S1prot(env, mmu_idx, aarch64, ap, xn, pxn, + result->f.attrs.space, out_space); } if (!(result->f.prot & (1 << access_type))) { @@ -1627,15 +1691,8 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, } } - if (ns) { - /* - * The NS bit will (as required by the architecture) have no effect if - * the CPU doesn't support TZ or this is a non-secure translation - * regime, because the attribute will already be non-secure. - */ - result->f.attrs.secure = false; - result->f.attrs.space = ARMSS_NonSecure; - } + result->f.attrs.space = out_space; + result->f.attrs.secure = arm_space_is_secure(out_space); if (regime_is_stage2(mmu_idx)) { result->cacheattrs.is_s2_format = true; From patchwork Tue Jun 20 12:44:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 694512 Delivered-To: patch@linaro.org Received: by 2002:adf:e885:0:0:0:0:0 with SMTP id d5csp287575wrm; Tue, 20 Jun 2023 05:50:21 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6ZfM2A890uI9VFUs29o7mtVg9h9ALn3Dp+FUGqWqKaInEtYyvzjvTeDpmrX1ZNYQr+NLzu X-Received: by 2002:a05:6214:d42:b0:62f:eb6d:1796 with SMTP id 2-20020a0562140d4200b0062feb6d1796mr16848590qvr.30.1687265420947; Tue, 20 Jun 2023 05:50:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687265420; cv=none; d=google.com; s=arc-20160816; b=bKZWajCEdDWwFW8dOsxioUA0l7lOTPe+Mc8hBgBvmfWeAOvKYmbfUqet0oH5s4OILy +zwP+EoY7CR/07QNH0sOWpuvB1xdUpSZYLWDs1ZZX9tQPIgqKYklGOzQ4jqlN7Vn6X6W u3cbNmdqJFJwLVJZNA4slf4aaCh5LsfU3JK14I3bSlgmbu13kOKLJ02fFCTm4h2FqaZV V1LJ3JYApU6PFnUA0x6dUhs34UhYVjNq6TMvSsWtgqhFgGnSUr3e3DHPdiNJy5btLKA1 DuQYaL60LNJoaDtx7qp1ihymzuGO4auHG83101JFPfUyOiCYuzuKgwU19WBgFj7bTP9B 3Opw== ARC-Message-Signature: i=1; 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[209.51.188.17]) by mx.google.com with ESMTPS id dv1-20020ad44ee1000000b0062de8284254si793392qvb.422.2023.06.20.05.50.20 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 20 Jun 2023 05:50:20 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vpa1OMsK; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qBais-0001aI-D8; Tue, 20 Jun 2023 08:44:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qBaiq-0001Yk-NR for qemu-devel@nongnu.org; Tue, 20 Jun 2023 08:44:36 -0400 Received: from mail-ed1-x52d.google.com ([2a00:1450:4864:20::52d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qBaio-00021W-Or for qemu-devel@nongnu.org; Tue, 20 Jun 2023 08:44:36 -0400 Received: by mail-ed1-x52d.google.com with SMTP id 4fb4d7f45d1cf-51a2c60c529so5723432a12.3 for ; Tue, 20 Jun 2023 05:44:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687265073; x=1689857073; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=B3vaNoeWOKh3oA6oL5GGZU6lEHzFz6aNnkyZ0kOs9Ug=; b=vpa1OMsK3fdWKMiOcyrkmbDccqzuLMaETqOmy9ddzjl0K38WMX3SmvLYYiL402qfpP SfIu81l1GiY67iaUdSt9fFfF32FiwqY/H/OxbMqyxjuqejV/iNtgc+tEFpz+9smyKgXO aiXQeYbZueQiC1uUL0AnupX09KfQqU28WDFbKEpdZOXTX4eMieXBoVwyp9AwqtCTOLKg AREvsPCg8e4oMXeL+9Uj43ICAhu0CPGv6EYWbEn3elIx8NkWGr81B4z1a7QuiRTX18KB ZRQxZRyAph16mMoT9sPYl40c8+1EQ1yAOpUJ1JFHSXldczA8LoeCJg5q5j4f6xd/DB45 3LMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687265073; x=1689857073; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=B3vaNoeWOKh3oA6oL5GGZU6lEHzFz6aNnkyZ0kOs9Ug=; b=jEVz291QiQfVNwyjF91mQDLcjh1ZLMV19bFhF1C+27pWTuUaXbBhgqLbruNJa96wEC rsuMsbxZTwMgg28iZy2B22zgX7If+zk3pUUGSO7vKKzPH+6nEkYwFR45xFJLrYCsiHBm mFHTTtyt+mNnLhjHDdRKw+j4CPN5e1I1Nu3YT3eL06Mf+TcDVV8GFojTIfQh+2anQJ5c UnklZ58cH15vx/b7X3iMALCSLxkge6y+OA63pM+L37pTGAgDFyBtKvv/QtxQJ9CqYSU8 nF5L3IB0HGALNbVYGcXOzuS2CGT8LcZoa94YjGDAtl7coge+6e4w+hTAWL+6tGk3iW+9 jjrQ== X-Gm-Message-State: AC+VfDw63coasQgRIrjPQgLbKF8sqj2prIbqZVIBMM8TOWYUC6BYSvso lvs9DvWogdWmvm9WNV9kXl3MDbXNd9R3BI9dmN51hq4u X-Received: by 2002:aa7:cfc4:0:b0:518:79d7:57be with SMTP id r4-20020aa7cfc4000000b0051879d757bemr8092749edy.9.1687265073334; Tue, 20 Jun 2023 05:44:33 -0700 (PDT) Received: from stoup.lan ([176.176.183.29]) by smtp.gmail.com with ESMTPSA id w9-20020aa7dcc9000000b0051a313a66e8sm1142541edu.45.2023.06.20.05.44.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Jun 2023 05:44:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v5 13/20] target/arm: Handle no-execute for Realm and Root regimes Date: Tue, 20 Jun 2023 14:44:11 +0200 Message-Id: <20230620124418.805717-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230620124418.805717-1-richard.henderson@linaro.org> References: <20230620124418.805717-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-ed1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org While Root and Realm may read and write data from other spaces, neither may execute from other pa spaces. This happens for Stage1 EL3, EL2, EL2&0, and Stage2 EL1&0. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/ptw.c | 52 ++++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 46 insertions(+), 6 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index bbae432861..45271d666b 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -943,7 +943,7 @@ do_fault: * @xn: XN (execute-never) bits * @s1_is_el0: true if this is S2 of an S1+2 walk for EL0 */ -static int get_S2prot(CPUARMState *env, int s2ap, int xn, bool s1_is_el0) +static int get_S2prot_noexecute(int s2ap) { int prot = 0; @@ -953,6 +953,12 @@ static int get_S2prot(CPUARMState *env, int s2ap, int xn, bool s1_is_el0) if (s2ap & 2) { prot |= PAGE_WRITE; } + return prot; +} + +static int get_S2prot(CPUARMState *env, int s2ap, int xn, bool s1_is_el0) +{ + int prot = get_S2prot_noexecute(s2ap); if (cpu_isar_feature(any_tts2uxn, env_archcpu(env))) { switch (xn) { @@ -1030,9 +1036,39 @@ static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64, } } - if (out_pa == ARMSS_NonSecure && in_pa == ARMSS_Secure && - (env->cp15.scr_el3 & SCR_SIF)) { - return prot_rw; + if (in_pa != out_pa) { + switch (in_pa) { + case ARMSS_Root: + /* + * R_ZWRVD: permission fault for insn fetched from non-Root, + * I_WWBFB: SIF has no effect in EL3. + */ + return prot_rw; + case ARMSS_Realm: + /* + * R_PKTDS: permission fault for insn fetched from non-Realm, + * for Realm EL2 or EL2&0. The corresponding fault for EL1&0 + * happens during any stage2 translation. + */ + switch (mmu_idx) { + case ARMMMUIdx_E2: + case ARMMMUIdx_E20_0: + case ARMMMUIdx_E20_2: + case ARMMMUIdx_E20_2_PAN: + return prot_rw; + default: + break; + } + break; + case ARMSS_Secure: + if (env->cp15.scr_el3 & SCR_SIF) { + return prot_rw; + } + break; + default: + /* Input NonSecure must have output NonSecure. */ + g_assert_not_reached(); + } } /* TODO have_wxn should be replaced with @@ -1601,12 +1637,16 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, /* * R_GYNXY: For stage2 in Realm security state, bit 55 is NS. * The bit remains ignored for other security states. + * R_YMCSL: Executing an insn fetched from non-Realm causes + * a stage2 permission fault. */ if (out_space == ARMSS_Realm && extract64(attrs, 55, 1)) { out_space = ARMSS_NonSecure; + result->f.prot = get_S2prot_noexecute(ap); + } else { + xn = extract64(attrs, 53, 2); + result->f.prot = get_S2prot(env, ap, xn, s1_is_el0); } - xn = extract64(attrs, 53, 2); - result->f.prot = get_S2prot(env, ap, xn, s1_is_el0); } else { int nse, ns = extract32(attrs, 5, 1); switch (out_space) { From patchwork Tue Jun 20 12:44:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 694501 Delivered-To: patch@linaro.org Received: by 2002:adf:e885:0:0:0:0:0 with SMTP id d5csp285933wrm; Tue, 20 Jun 2023 05:46:33 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6hCbTYvKZXAnJJTJy6wF1HSrEUhFLHQ24+jdltJ60Q/M1wE3ORK+TEY09i4KHCdy6vNHJv X-Received: by 2002:a05:622a:491:b0:3fd:da36:3e97 with SMTP id p17-20020a05622a049100b003fdda363e97mr14319815qtx.34.1687265193341; Tue, 20 Jun 2023 05:46:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687265193; cv=none; d=google.com; s=arc-20160816; b=ch2kkBJ418YJoAwW64cYm5c2f7t9uKs3Dea22vr0J/rG9Gav1VEzab7jIZ2btIdekR F0X+GXn2OxoV+ExRmEckNFiMNoCxnKWWCLabb7IJoDV/6EoWiyy9xg8rizIvBFAkdhes /BZ2JeURdcWVRUznGTV0E728+QexC2nUkVlF+WGycQudF/9kiGaj0intJAruXG4mpONm 8tbX/xC7nzLMqVtHb+U/MlUDLPOfej9TeBxr1J1De9hci1puSfhdMkG0/k9e+1J648qB hTWXiz/4iBn8HIEBAIWQLXHObM2zDr6+MJQO3xOzyXO7CHwRt6JBQlL6P/fZwzRwj4LR 4+BQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=2sdgIiqPnMV4fPsIp02tsJUyVwHllql7Gpq+1+0e7tM=; b=DdKy9INR5Gl1dVW+JcdSHKoroQjjYc1yCae2lM8F6TSwJMZjqPlftRDkEWg6tgBVEl Uupe6FCEuxxQ8KvE3Dr1HkjekFgJvKFQRbMnTnVzzBUlsKQxQxgd/we0NGq8M4uTypV0 DokVe5zX4cnwXN8joFRvrjHouL7OkOJxO/GY13oj1998BPArwUPK0ceM4bChJbXeJEtw QCr/91wKjxCEtxFqp6jTWT4ygINxZS7Nr7qgWZjEpVCgIoFaY+2nMJWQwEdAxdIAANyz zFFCc6DRI4zeK21NuQxwCMC7p81T/+ArF9WjWgf8SFsvSKKzoFYfOITqxNqHFlMaPXtA VkKA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZzcbZpiX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/ptw.c | 44 +++++++++++++++++--------------------------- 1 file changed, 17 insertions(+), 27 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 45271d666b..6d5e4855a3 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -264,37 +264,27 @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, * From gdbstub, do not use softmmu so that we don't modify the * state of the cpu at all, including softmmu tlb contents. */ - if (regime_is_stage2(s2_mmu_idx)) { - S1Translate s2ptw = { - .in_mmu_idx = s2_mmu_idx, - .in_ptw_idx = ptw_idx_for_stage_2(env, s2_mmu_idx), - .in_secure = s2_mmu_idx == ARMMMUIdx_Stage2_S, - .in_space = (s2_mmu_idx == ARMMMUIdx_Stage2_S ? ARMSS_Secure - : space == ARMSS_Realm ? ARMSS_Realm - : ARMSS_NonSecure), - .in_debug = true, - }; - GetPhysAddrResult s2 = { }; + S1Translate s2ptw = { + .in_mmu_idx = s2_mmu_idx, + .in_ptw_idx = ptw_idx_for_stage_2(env, s2_mmu_idx), + .in_secure = s2_mmu_idx == ARMMMUIdx_Stage2_S, + .in_space = (s2_mmu_idx == ARMMMUIdx_Stage2_S ? ARMSS_Secure + : space == ARMSS_Realm ? ARMSS_Realm + : ARMSS_NonSecure), + .in_debug = true, + }; + GetPhysAddrResult s2 = { }; - if (get_phys_addr_lpae(env, &s2ptw, addr, MMU_DATA_LOAD, - false, &s2, fi)) { - goto fail; - } - ptw->out_phys = s2.f.phys_addr; - pte_attrs = s2.cacheattrs.attrs; - ptw->out_secure = s2.f.attrs.secure; - ptw->out_space = s2.f.attrs.space; - } else { - /* Regime is physical. */ - ptw->out_phys = addr; - pte_attrs = 0; - ptw->out_secure = s2_mmu_idx == ARMMMUIdx_Phys_S; - ptw->out_space = (s2_mmu_idx == ARMMMUIdx_Phys_S ? ARMSS_Secure - : space == ARMSS_Realm ? ARMSS_Realm - : ARMSS_NonSecure); + if (get_phys_addr_with_struct(env, &s2ptw, addr, + MMU_DATA_LOAD, &s2, fi)) { + goto fail; } + ptw->out_phys = s2.f.phys_addr; + pte_attrs = s2.cacheattrs.attrs; ptw->out_host = NULL; ptw->out_rw = false; + ptw->out_secure = s2.f.attrs.secure; + ptw->out_space = s2.f.attrs.space; } else { #ifdef CONFIG_TCG CPUTLBEntryFull *full; From patchwork Tue Jun 20 12:44:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 694499 Delivered-To: patch@linaro.org Received: by 2002:adf:e885:0:0:0:0:0 with SMTP id d5csp285678wrm; Tue, 20 Jun 2023 05:45:58 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6NO8W4Mj6KIk0/dTPI0ZOLSdut7U92t9Kus67QpXj7k8OXZ7cSJtCWWidCuY0+uN/jbqGK X-Received: by 2002:a05:622a:303:b0:3f5:4da8:1a84 with SMTP id q3-20020a05622a030300b003f54da81a84mr16477518qtw.57.1687265158211; Tue, 20 Jun 2023 05:45:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687265158; cv=none; d=google.com; s=arc-20160816; b=xqboy5xQkaxSE+lpyvOPOFmsko0ZgHjJEHfZDWiP7xojEQYRE3jYeXBzg/eulqHaN/ ZTObtzXv+7rohcnWKitdSJ5sAGC5nSUwWTWAgwPZwkmAQslIlJoPwJ2beLeZl8DBe80E ycyInWSUK+Y6RU0rgqQumVVKkLYFfYx7xV+pOUvGgZNw4YuDZXWeJce3xkZaolu09a2K lhBM81R4eOFUPeCRu40PngO7xMbIlPeSsCBErHBBxeB9NN/8MRSvDZXgvW6wD4twf2rZ mfAXqNeQmGhH2HSTES/YPjJrb2Mp6IO7dWpv0XqVFfStNEaUXW2HNlP6bZja/xUTYzgY KDbg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=pwtewtSNTpSONPyBLmZuBuFoTg9ObSjoVeJpdVVh5D0=; b=bjpM87YLarpfcDxPG7DPuz+/0f068HAlm6OjC8P0EXWxWpRGhbTAC5giIY4ORWvX/9 Vi1ZOJTLkf6jp1ZMxZvCY6Xhgi65vzE6UMeAibxWcsi3PVV7iAmBlSwJQdmXkWI2yUV+ 0jqTY7AdOpfdjPSMRRC+b/H7Jb02k6KuugOEFNlwfGF9/KiHZZljpCTEQuucW/3fLEQk BnOwvjtZ4iqRzdCpMjyAn9/XiefsaUAwZN0MNH6p5UqSQmR1GrR+0e4nmu/thMulbrgL FKzPmYO4XTfFQB6qWNom7iYqaE6pxsT72NbKjmOsafasGOTUYcWbnuSqD/V7yZvUMHN1 6Lwg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=n5qRUEQt; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/ptw.c | 27 ++++++++++++--------------- 1 file changed, 12 insertions(+), 15 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 6d5e4855a3..558b4b731b 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -24,6 +24,12 @@ typedef struct S1Translate { ARMSecuritySpace in_space; bool in_secure; bool in_debug; + /* + * If this is stage 2 of a stage 1+2 page table walk, then this must + * be true if stage 1 is an EL0 access; otherwise this is ignored. + * Stage 2 is indicated by in_mmu_idx set to ARMMMUIdx_Stage2{,_S}. + */ + bool in_s1_is_el0; bool out_secure; bool out_rw; bool out_be; @@ -34,8 +40,7 @@ typedef struct S1Translate { } S1Translate; static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, - uint64_t address, - MMUAccessType access_type, bool s1_is_el0, + uint64_t address, MMUAccessType access_type, GetPhysAddrResult *result, ARMMMUFaultInfo *fi); static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw, @@ -1289,17 +1294,12 @@ static int check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, uint64_t tcr, * @ptw: Current and next stage parameters for the walk. * @address: virtual address to get physical address for * @access_type: MMU_DATA_LOAD, MMU_DATA_STORE or MMU_INST_FETCH - * @s1_is_el0: if @ptw->in_mmu_idx is ARMMMUIdx_Stage2 - * (so this is a stage 2 page table walk), - * must be true if this is stage 2 of a stage 1+2 - * walk for an EL0 access. If @mmu_idx is anything else, - * @s1_is_el0 is ignored. * @result: set on translation success, * @fi: set to fault info if the translation fails */ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, uint64_t address, - MMUAccessType access_type, bool s1_is_el0, + MMUAccessType access_type, GetPhysAddrResult *result, ARMMMUFaultInfo *fi) { ARMCPU *cpu = env_archcpu(env); @@ -1635,7 +1635,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, result->f.prot = get_S2prot_noexecute(ap); } else { xn = extract64(attrs, 53, 2); - result->f.prot = get_S2prot(env, ap, xn, s1_is_el0); + result->f.prot = get_S2prot(env, ap, xn, ptw->in_s1_is_el0); } } else { int nse, ns = extract32(attrs, 5, 1); @@ -2858,7 +2858,6 @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw, bool ret, ipa_secure; ARMCacheAttrs cacheattrs1; ARMSecuritySpace ipa_space; - bool is_el0; uint64_t hcr; ret = get_phys_addr_with_struct(env, ptw, address, access_type, result, fi); @@ -2872,7 +2871,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw, ipa_secure = result->f.attrs.secure; ipa_space = result->f.attrs.space; - is_el0 = ptw->in_mmu_idx == ARMMMUIdx_Stage1_E0; + ptw->in_s1_is_el0 = ptw->in_mmu_idx == ARMMMUIdx_Stage1_E0; ptw->in_mmu_idx = ipa_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2; ptw->in_secure = ipa_secure; ptw->in_space = ipa_space; @@ -2891,8 +2890,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw, ret = get_phys_addr_pmsav8(env, ipa, access_type, ptw->in_mmu_idx, is_secure, result, fi); } else { - ret = get_phys_addr_lpae(env, ptw, ipa, access_type, - is_el0, result, fi); + ret = get_phys_addr_lpae(env, ptw, ipa, access_type, result, fi); } fi->s2addr = ipa; @@ -3078,8 +3076,7 @@ static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw, } if (regime_using_lpae_format(env, mmu_idx)) { - return get_phys_addr_lpae(env, ptw, address, access_type, false, - result, fi); + return get_phys_addr_lpae(env, ptw, address, access_type, result, fi); } else if (arm_feature(env, ARM_FEATURE_V7) || regime_sctlr(env, mmu_idx) & SCTLR_XP) { return get_phys_addr_v6(env, ptw, address, access_type, result, fi); From patchwork Tue Jun 20 12:44:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 694510 Delivered-To: patch@linaro.org Received: by 2002:adf:e885:0:0:0:0:0 with SMTP id d5csp287172wrm; Tue, 20 Jun 2023 05:49:22 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ48sNcjhUa9BqV+EKV2yWHfxmfSok/+r/nh5yBY3Bw9GlYJmEWmW9lkyI+qUWrthty0HOaw X-Received: by 2002:a05:6214:1303:b0:626:2bf5:d532 with SMTP id pn3-20020a056214130300b006262bf5d532mr17793581qvb.14.1687265361857; Tue, 20 Jun 2023 05:49:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687265361; cv=none; d=google.com; s=arc-20160816; b=Imw4QYXiUfRCunbLvO8ifovMkWzNqF8AH7bivM0Mj8rw7lx6QRWgoWyYLP3NzOg51m TB7hNLDvEL57jR0nvOIDg617FmIRgzO7vqGRfq+3Xay2uwxqqY+IFqtdAPBONwNm49Zv YQuEDOw7iHtNmb3XWf1vBT+aCGFsWSYFRCetiZCqjazIXn91eIMNb7dfg++dPtxv8zgn e9V3LT01b51pcxhA017eFG6AV1carkzO2VyVc2K3QeKfIHnAYWdDVAX3aBAWVRwU12px SQ3IBlcMuct43PZoV++Ahg4HJrghgUD5cOeCDMnGIyXGO3x4Kd+R6q1ICH0+16hKO18b rnjg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=c5AwidcO4tfQ++xn12IPRLJwHDY5LLSrHnZYAWEeDsc=; b=X7T1jVAtWE9/gSwOYK1wJtzZ5q0eS5qmYRbHx+DcZwPVbxxuHhfnsqYdsobYGhlN9s Ebun4JVE4YjmrzHKy1VJCHjPzr/Ye7B9okF4Ihp31mdmFdv5dwCqoInM7NxnoYFvmOa/ th12Qi8Qb3I81y3PO2OKFx9essJVpN85TCzploM80kFRdK+ZQ2IWcgbo+eQ1yRFRQGFX t9FBQrCFjt2/P979nsuP0WsMFJH7B0XVg+5WNu7wyKiND30X5RM547PhWFh3dDbvTPAZ AuWf2tke21SsjfM3BOfGFGFByzNKXITlBVj0kAqWwz2VWYKZSQ9eBk8fDFm/brLDPET0 8wFg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=oHA1ewzo; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/arm/ptw.c | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 558b4b731b..7c4526e2da 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -39,10 +39,6 @@ typedef struct S1Translate { void *out_host; } S1Translate; -static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, - uint64_t address, MMUAccessType access_type, - GetPhysAddrResult *result, ARMMMUFaultInfo *fi); - static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw, target_ulong address, MMUAccessType access_type, @@ -2886,12 +2882,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw, cacheattrs1 = result->cacheattrs; memset(result, 0, sizeof(*result)); - if (arm_feature(env, ARM_FEATURE_PMSA)) { - ret = get_phys_addr_pmsav8(env, ipa, access_type, - ptw->in_mmu_idx, is_secure, result, fi); - } else { - ret = get_phys_addr_lpae(env, ptw, ipa, access_type, result, fi); - } + ret = get_phys_addr_with_struct(env, ptw, ipa, access_type, result, fi); fi->s2addr = ipa; /* Combine the S1 and S2 perms. */ From patchwork Tue Jun 20 12:44:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 694505 Delivered-To: patch@linaro.org Received: by 2002:adf:e885:0:0:0:0:0 with SMTP id d5csp286035wrm; Tue, 20 Jun 2023 05:46:46 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5wFlLrAd1oHzsFHeNNfw1XTV3GivPiZim5GcH9GYYMtnt+go4KpkQGYEqWyR19FFfN5Xz9 X-Received: by 2002:a05:620a:490c:b0:763:b30c:60dc with SMTP id ed12-20020a05620a490c00b00763b30c60dcmr1264820qkb.51.1687265206166; Tue, 20 Jun 2023 05:46:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687265206; cv=none; d=google.com; s=arc-20160816; b=zgAVnnKAwLHlUwvKpseXxR5569eIhAa/JvmX7SGlref1IcdT5peoTSZiZx8o54/EwH b+TV6IjSOT52tQKibBfWzIuALge9JgNL4C2cgOocLFsxGu0u1kAiksPyq5KwP8Z1duvc Tmh+w+pq2/EKKeYc3Q6MmFh7VYPkwQXzdMzNgkfVDD33vFxYA+RhqBAR3IJRYR5fcYBv 8PQ0sxkVwcbXAKecScuYmORHDba+N/p3b3saT9zL1aK5+YKoCDwEuWL/MCD+bALScoRY 3sMJAc742xe96LXhsvpr9HfhDwy/TirmDD9jO2LxOayTzv/ATRoMxStny887UPiEOER3 Hq5w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=BdnIrBC/vjhypfMOEhRm01STyDVGWe2QDHvXiznUOKk=; b=TJlNimqokBKfBe8I6h470qJn/yZ23cSFtHdneIPt1QwgNAWO4A6diQ57BYK0TgmzMr op17Brwc5rcmhD6zEo7Hd8vmppLHW9lYD0OIuylpjHEbKcJTeolG7tVrukr0QMbP/Crp hS0fKhjCWkKqYnXQ9+0Ak/i1Qggx37MgGcPwKTkbLl67SXgLCROgXuZhe0aIyeVQQtTx pgYr2kxNTA/ukwHX9fD+4weDBMYCdfGi3HA87KVbRGj4xPPLwvzzIhFkGKHyDbwwgDvi NHLxi4QVcNHOIVaJ9yQFjnyVFfwXVz0w/dEb5wBJxqHE44XdWammhFqInv1kV1qLPfIU UqRA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=nE23sk6E; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/syndrome.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h index d27d1bc31f..62254d0e51 100644 --- a/target/arm/syndrome.h +++ b/target/arm/syndrome.h @@ -50,6 +50,7 @@ enum arm_exception_class { EC_SVEACCESSTRAP = 0x19, EC_ERETTRAP = 0x1a, EC_SMETRAP = 0x1d, + EC_GPC = 0x1e, EC_INSNABORT = 0x20, EC_INSNABORT_SAME_EL = 0x21, EC_PCALIGNMENT = 0x22, @@ -247,6 +248,15 @@ static inline uint32_t syn_bxjtrap(int cv, int cond, int rm) (cv << 24) | (cond << 20) | rm; } +static inline uint32_t syn_gpc(int s2ptw, int ind, int gpcsc, + int cm, int s1ptw, int wnr, int fsc) +{ + /* TODO: FEAT_NV2 adds VNCR */ + return (EC_GPC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (s2ptw << 21) + | (ind << 20) | (gpcsc << 14) | (cm << 8) | (s1ptw << 7) + | (wnr << 6) | fsc; +} + static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int fsc) { return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) From patchwork Tue Jun 20 12:44:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 694502 Delivered-To: patch@linaro.org Received: by 2002:adf:e885:0:0:0:0:0 with SMTP id d5csp285964wrm; Tue, 20 Jun 2023 05:46:36 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5mXNgkJ5SkE7neGdfor52k/WCJ1T70AdWi0u0f8ZxuFouWHwBfGL0UCkgdgSOW/Z3G7FFO X-Received: by 2002:a05:6214:c62:b0:62d:e946:5187 with SMTP id t2-20020a0562140c6200b0062de9465187mr7045486qvj.13.1687265196761; Tue, 20 Jun 2023 05:46:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687265196; cv=none; d=google.com; s=arc-20160816; b=vW/aYFaCkm7S3ohlr8Vp0Xmu/9aabLJlxq6cKMOffhc7dh/vOgJIdTavPBmIqP4gsc WL98E25gk+8wB83FQmRXTuy7xeItmjJchJA2T82FHw6ZH0AlfS8fjdw7z6M9CMVbr4ib Mi74CkmsBE1793TJoVXepQmOIlk12WmwZgQVDhiEdJc5pLeBnOhctxvYV5DNjno8p8f8 gMWTLzDO5jNM89gWfbDxLxZwAJBjLKlmPQ2C+73Ka+s29YxYVFTxpsM6WOXZC+Yq/kro 8eqjHBHTNV76ISej10P1tXWcls+7FaDeTATs2yuW0jjTa4cIP3QVNAfSC3jqhu0d+oYk 4VCw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=WGRPT9xJksw52ykTIhoF0rIbEJgZNow1e2+J7repfVA=; b=jEVAGtXtXUqqbBiKoKD7Dfq2vyHTqXZGHajvU//pe2iugrANaEcLRI5vL0HfHhbs6I TwQdCkX7PZJE41MBdq9O2La3Stj0ApQhAUGc8okN2llET1g2rKV1qW+9pdjWp2AgWEaM sL4Hdg5S++1k0WcCoFA8DDhkULmh6zjNd7ubfM9RiwD+LyCNnqI6dZ8oG6J0J6wfNZg2 6JWyvW/kJV1nqCnSBh/YkQyoTkzKJzzIS/fyQSH49pXDjNCtZwL8M4zP+hzhE07U10hL t5/OmnTax9erGY2jBOi+Kdsy0IDAJEIuadT4AIzVHVvOgXzMmKkes+PQ9BLWF60DajfQ 6cYQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tqZcJMZa; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 1 + target/arm/internals.h | 27 +++++++++++ target/arm/helper.c | 5 ++ target/arm/tcg/tlb_helper.c | 96 +++++++++++++++++++++++++++++++++++-- 4 files changed, 126 insertions(+), 3 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 590216b855..11c3850ad9 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -57,6 +57,7 @@ #define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */ #define EXCP_DIVBYZERO 23 /* v7M DIVBYZERO UsageFault */ #define EXCP_VSERR 24 +#define EXCP_GPC 25 /* v9 Granule Protection Check Fault */ /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ #define ARMV7M_EXCP_RESET 1 diff --git a/target/arm/internals.h b/target/arm/internals.h index e3029bdc37..0f01bc32a8 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -358,14 +358,27 @@ typedef enum ARMFaultType { ARMFault_ICacheMaint, ARMFault_QEMU_NSCExec, /* v8M: NS executing in S&NSC memory */ ARMFault_QEMU_SFault, /* v8M: SecureFault INVTRAN, INVEP or AUVIOL */ + ARMFault_GPCFOnWalk, + ARMFault_GPCFOnOutput, } ARMFaultType; +typedef enum ARMGPCF { + GPCF_None, + GPCF_AddressSize, + GPCF_Walk, + GPCF_EABT, + GPCF_Fail, +} ARMGPCF; + /** * ARMMMUFaultInfo: Information describing an ARM MMU Fault * @type: Type of fault + * @gpcf: Subtype of ARMFault_GPCFOn{Walk,Output}. * @level: Table walk level (for translation, access flag and permission faults) * @domain: Domain of the fault address (for non-LPAE CPUs only) * @s2addr: Address that caused a fault at stage 2 + * @paddr: physical address that caused a fault for gpc + * @paddr_space: physical address space that caused a fault for gpc * @stage2: True if we faulted at stage 2 * @s1ptw: True if we faulted at stage 2 while doing a stage 1 page-table walk * @s1ns: True if we faulted on a non-secure IPA while in secure state @@ -374,7 +387,10 @@ typedef enum ARMFaultType { typedef struct ARMMMUFaultInfo ARMMMUFaultInfo; struct ARMMMUFaultInfo { ARMFaultType type; + ARMGPCF gpcf; target_ulong s2addr; + target_ulong paddr; + ARMSecuritySpace paddr_space; int level; int domain; bool stage2; @@ -548,6 +564,17 @@ static inline uint32_t arm_fi_to_lfsc(ARMMMUFaultInfo *fi) case ARMFault_Exclusive: fsc = 0x35; break; + case ARMFault_GPCFOnWalk: + assert(fi->level >= -1 && fi->level <= 3); + if (fi->level < 0) { + fsc = 0b100011; + } else { + fsc = 0b100100 | fi->level; + } + break; + case ARMFault_GPCFOnOutput: + fsc = 0b101000; + break; default: /* Other faults can't occur in a context that requires a * long-format status code. diff --git a/target/arm/helper.c b/target/arm/helper.c index f68923d73b..323cadd3c8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10184,6 +10184,7 @@ void arm_log_exception(CPUState *cs) [EXCP_UNALIGNED] = "v7M UNALIGNED UsageFault", [EXCP_DIVBYZERO] = "v7M DIVBYZERO UsageFault", [EXCP_VSERR] = "Virtual SERR", + [EXCP_GPC] = "Granule Protection Check", }; if (idx >= 0 && idx < ARRAY_SIZE(excnames)) { @@ -10915,6 +10916,10 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) } switch (cs->exception_index) { + case EXCP_GPC: + qemu_log_mask(CPU_LOG_INT, "...with MFAR 0x%" PRIx64 "\n", + env->cp15.mfar_el3); + /* fall through */ case EXCP_PREFETCH_ABORT: case EXCP_DATA_ABORT: /* diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c index 8df36c2cbf..b22b2a4c6e 100644 --- a/target/arm/tcg/tlb_helper.c +++ b/target/arm/tcg/tlb_helper.c @@ -107,17 +107,106 @@ static uint32_t compute_fsr_fsc(CPUARMState *env, ARMMMUFaultInfo *fi, return fsr; } +static bool report_as_gpc_exception(ARMCPU *cpu, int current_el, + ARMMMUFaultInfo *fi) +{ + bool ret; + + switch (fi->gpcf) { + case GPCF_None: + return false; + case GPCF_AddressSize: + case GPCF_Walk: + case GPCF_EABT: + /* R_PYTGX: GPT faults are reported as GPC. */ + ret = true; + break; + case GPCF_Fail: + /* + * R_BLYPM: A GPF at EL3 is reported as insn or data abort. + * R_VBZMW, R_LXHQR: A GPF at EL[0-2] is reported as a GPC + * if SCR_EL3.GPF is set, otherwise an insn or data abort. + */ + ret = (cpu->env.cp15.scr_el3 & SCR_GPF) && current_el != 3; + break; + default: + g_assert_not_reached(); + } + + assert(cpu_isar_feature(aa64_rme, cpu)); + assert(fi->type == ARMFault_GPCFOnWalk || + fi->type == ARMFault_GPCFOnOutput); + if (fi->gpcf == GPCF_AddressSize) { + assert(fi->level == 0); + } else { + assert(fi->level >= 0 && fi->level <= 1); + } + + return ret; +} + +static unsigned encode_gpcsc(ARMMMUFaultInfo *fi) +{ + static uint8_t const gpcsc[] = { + [GPCF_AddressSize] = 0b000000, + [GPCF_Walk] = 0b000100, + [GPCF_Fail] = 0b001100, + [GPCF_EABT] = 0b010100, + }; + + /* Note that we've validated fi->gpcf and fi->level above. */ + return gpcsc[fi->gpcf] | fi->level; +} + static G_NORETURN void arm_deliver_fault(ARMCPU *cpu, vaddr addr, MMUAccessType access_type, int mmu_idx, ARMMMUFaultInfo *fi) { CPUARMState *env = &cpu->env; - int target_el; + int target_el = exception_target_el(env); + int current_el = arm_current_el(env); bool same_el; uint32_t syn, exc, fsr, fsc; - target_el = exception_target_el(env); + if (report_as_gpc_exception(cpu, current_el, fi)) { + target_el = 3; + + fsr = compute_fsr_fsc(env, fi, target_el, mmu_idx, &fsc); + + syn = syn_gpc(fi->stage2 && fi->type == ARMFault_GPCFOnWalk, + access_type == MMU_INST_FETCH, + encode_gpcsc(fi), 0, fi->s1ptw, + access_type == MMU_DATA_STORE, fsc); + + env->cp15.mfar_el3 = fi->paddr; + switch (fi->paddr_space) { + case ARMSS_Secure: + break; + case ARMSS_NonSecure: + env->cp15.mfar_el3 |= R_MFAR_NS_MASK; + break; + case ARMSS_Root: + env->cp15.mfar_el3 |= R_MFAR_NSE_MASK; + break; + case ARMSS_Realm: + env->cp15.mfar_el3 |= R_MFAR_NSE_MASK | R_MFAR_NS_MASK; + break; + default: + g_assert_not_reached(); + } + + exc = EXCP_GPC; + goto do_raise; + } + + /* If SCR_EL3.GPF is unset, GPF may still be routed to EL2. */ + if (fi->gpcf == GPCF_Fail && target_el < 2) { + if (arm_hcr_el2_eff(env) & HCR_GPF) { + target_el = 2; + } + } + if (fi->stage2) { target_el = 2; env->cp15.hpfar_el2 = extract64(fi->s2addr, 12, 47) << 4; @@ -125,8 +214,8 @@ void arm_deliver_fault(ARMCPU *cpu, vaddr addr, env->cp15.hpfar_el2 |= HPFAR_NS; } } - same_el = (arm_current_el(env) == target_el); + same_el = current_el == target_el; fsr = compute_fsr_fsc(env, fi, target_el, mmu_idx, &fsc); if (access_type == MMU_INST_FETCH) { @@ -143,6 +232,7 @@ void arm_deliver_fault(ARMCPU *cpu, vaddr addr, exc = EXCP_DATA_ABORT; } + do_raise: env->exception.vaddress = addr; env->exception.fsr = fsr; raise_exception(env, exc, syn, target_el); From patchwork Tue Jun 20 12:44:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 694503 Delivered-To: patch@linaro.org Received: by 2002:adf:e885:0:0:0:0:0 with SMTP id d5csp285971wrm; Tue, 20 Jun 2023 05:46:37 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5EM0scluxAN3Z0cHVN9+T0uCjB/WqHlId9H4aW/SUa8A8uJ7+PzPkLiE8OC7y0u4TdTv0+ X-Received: by 2002:ad4:5bce:0:b0:626:c17:8b55 with SMTP id t14-20020ad45bce000000b006260c178b55mr10031913qvt.25.1687265196498; Tue, 20 Jun 2023 05:46:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687265196; cv=none; d=google.com; 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Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/ptw.c | 249 +++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 232 insertions(+), 17 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 7c4526e2da..6015121b99 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -39,11 +39,17 @@ typedef struct S1Translate { void *out_host; } S1Translate; -static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw, - target_ulong address, - MMUAccessType access_type, - GetPhysAddrResult *result, - ARMMMUFaultInfo *fi); +static bool get_phys_addr_nogpc(CPUARMState *env, S1Translate *ptw, + target_ulong address, + MMUAccessType access_type, + GetPhysAddrResult *result, + ARMMMUFaultInfo *fi); + +static bool get_phys_addr_gpc(CPUARMState *env, S1Translate *ptw, + target_ulong address, + MMUAccessType access_type, + GetPhysAddrResult *result, + ARMMMUFaultInfo *fi); /* This mapping is common between ID_AA64MMFR0.PARANGE and TCR_ELx.{I}PS. */ static const uint8_t pamax_map[] = { @@ -230,6 +236,197 @@ static bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx, return (regime_sctlr(env, mmu_idx) & SCTLR_M) == 0; } +static bool granule_protection_check(CPUARMState *env, uint64_t paddress, + ARMSecuritySpace pspace, + ARMMMUFaultInfo *fi) +{ + MemTxAttrs attrs = { + .secure = true, + .space = ARMSS_Root, + }; + ARMCPU *cpu = env_archcpu(env); + uint64_t gpccr = env->cp15.gpccr_el3; + unsigned pps, pgs, l0gptsz, level = 0; + uint64_t tableaddr, pps_mask, align, entry, index; + AddressSpace *as; + MemTxResult result; + int gpi; + + if (!FIELD_EX64(gpccr, GPCCR, GPC)) { + return true; + } + + /* + * GPC Priority 1 (R_GMGRR): + * R_JWCSM: If the configuration of GPCCR_EL3 is invalid, + * the access fails as GPT walk fault at level 0. + */ + + /* + * Configuration of PPS to a value exceeding the implemented + * physical address size is invalid. + */ + pps = FIELD_EX64(gpccr, GPCCR, PPS); + if (pps > FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE)) { + goto fault_walk; + } + pps = pamax_map[pps]; + pps_mask = MAKE_64BIT_MASK(0, pps); + + switch (FIELD_EX64(gpccr, GPCCR, SH)) { + case 0b10: /* outer shareable */ + break; + case 0b00: /* non-shareable */ + case 0b11: /* inner shareable */ + /* Inner and Outer non-cacheable requires Outer shareable. */ + if (FIELD_EX64(gpccr, GPCCR, ORGN) == 0 && + FIELD_EX64(gpccr, GPCCR, IRGN) == 0) { + goto fault_walk; + } + break; + default: /* reserved */ + goto fault_walk; + } + + switch (FIELD_EX64(gpccr, GPCCR, PGS)) { + case 0b00: /* 4KB */ + pgs = 12; + break; + case 0b01: /* 64KB */ + pgs = 16; + break; + case 0b10: /* 16KB */ + pgs = 14; + break; + default: /* reserved */ + goto fault_walk; + } + + /* Note this field is read-only and fixed at reset. */ + l0gptsz = 30 + FIELD_EX64(gpccr, GPCCR, L0GPTSZ); + + /* + * GPC Priority 2: Secure, Realm or Root address exceeds PPS. + * R_CPDSB: A NonSecure physical address input exceeding PPS + * does not experience any fault. + */ + if (paddress & ~pps_mask) { + if (pspace == ARMSS_NonSecure) { + return true; + } + goto fault_size; + } + + /* GPC Priority 3: the base address of GPTBR_EL3 exceeds PPS. */ + tableaddr = env->cp15.gptbr_el3 << 12; + if (tableaddr & ~pps_mask) { + goto fault_size; + } + + /* + * BADDR is aligned per a function of PPS and L0GPTSZ. + * These bits of GPTBR_EL3 are RES0, but are not a configuration error, + * unlike the RES0 bits of the GPT entries (R_XNKFZ). + */ + align = MAX(pps - l0gptsz + 3, 12); + align = MAKE_64BIT_MASK(0, align); + tableaddr &= ~align; + + as = arm_addressspace(env_cpu(env), attrs); + + /* Level 0 lookup. */ + index = extract64(paddress, l0gptsz, pps - l0gptsz); + tableaddr += index * 8; + entry = address_space_ldq_le(as, tableaddr, attrs, &result); + if (result != MEMTX_OK) { + goto fault_eabt; + } + + switch (extract32(entry, 0, 4)) { + case 1: /* block descriptor */ + if (entry >> 8) { + goto fault_walk; /* RES0 bits not 0 */ + } + gpi = extract32(entry, 4, 4); + goto found; + case 3: /* table descriptor */ + tableaddr = entry & ~0xf; + align = MAX(l0gptsz - pgs - 1, 12); + align = MAKE_64BIT_MASK(0, align); + if (tableaddr & (~pps_mask | align)) { + goto fault_walk; /* RES0 bits not 0 */ + } + break; + default: /* invalid */ + goto fault_walk; + } + + /* Level 1 lookup */ + level = 1; + index = extract64(paddress, pgs + 4, l0gptsz - pgs - 4); + tableaddr += index * 8; + entry = address_space_ldq_le(as, tableaddr, attrs, &result); + if (result != MEMTX_OK) { + goto fault_eabt; + } + + switch (extract32(entry, 0, 4)) { + case 1: /* contiguous descriptor */ + if (entry >> 10) { + goto fault_walk; /* RES0 bits not 0 */ + } + /* + * Because the softmmu tlb only works on units of TARGET_PAGE_SIZE, + * and because we cannot invalidate by pa, and thus will always + * flush entire tlbs, we don't actually care about the range here + * and can simply extract the GPI as the result. + */ + if (extract32(entry, 8, 2) == 0) { + goto fault_walk; /* reserved contig */ + } + gpi = extract32(entry, 4, 4); + break; + default: + index = extract64(paddress, pgs, 4); + gpi = extract64(entry, index * 4, 4); + break; + } + + found: + switch (gpi) { + case 0b0000: /* no access */ + break; + case 0b1111: /* all access */ + return true; + case 0b1000: + case 0b1001: + case 0b1010: + case 0b1011: + if (pspace == (gpi & 3)) { + return true; + } + break; + default: + goto fault_walk; /* reserved */ + } + + fi->gpcf = GPCF_Fail; + goto fault_common; + fault_eabt: + fi->gpcf = GPCF_EABT; + goto fault_common; + fault_size: + fi->gpcf = GPCF_AddressSize; + goto fault_common; + fault_walk: + fi->gpcf = GPCF_Walk; + fault_common: + fi->level = level; + fi->paddr = paddress; + fi->paddr_space = pspace; + return false; +} + static bool S2_attrs_are_device(uint64_t hcr, uint8_t attrs) { /* @@ -276,10 +473,10 @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, }; GetPhysAddrResult s2 = { }; - if (get_phys_addr_with_struct(env, &s2ptw, addr, - MMU_DATA_LOAD, &s2, fi)) { + if (get_phys_addr_gpc(env, &s2ptw, addr, MMU_DATA_LOAD, &s2, fi)) { goto fail; } + ptw->out_phys = s2.f.phys_addr; pte_attrs = s2.cacheattrs.attrs; ptw->out_host = NULL; @@ -332,6 +529,9 @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, fail: assert(fi->type != ARMFault_None); + if (fi->type == ARMFault_GPCFOnOutput) { + fi->type = ARMFault_GPCFOnWalk; + } fi->s2addr = addr; fi->stage2 = true; fi->s1ptw = true; @@ -2769,7 +2969,7 @@ static bool get_phys_addr_disabled(CPUARMState *env, target_ulong address, ARMMMUFaultInfo *fi) { uint8_t memattr = 0x00; /* Device nGnRnE */ - uint8_t shareability = 0; /* non-sharable */ + uint8_t shareability = 0; /* non-shareable */ int r_el; switch (mmu_idx) { @@ -2828,7 +3028,7 @@ static bool get_phys_addr_disabled(CPUARMState *env, target_ulong address, } else { memattr = 0x44; /* Normal, NC, No */ } - shareability = 2; /* outer sharable */ + shareability = 2; /* outer shareable */ } result->cacheattrs.is_s2_format = false; break; @@ -2856,7 +3056,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw, ARMSecuritySpace ipa_space; uint64_t hcr; - ret = get_phys_addr_with_struct(env, ptw, address, access_type, result, fi); + ret = get_phys_addr_nogpc(env, ptw, address, access_type, result, fi); /* If S1 fails, return early. */ if (ret) { @@ -2882,7 +3082,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw, cacheattrs1 = result->cacheattrs; memset(result, 0, sizeof(*result)); - ret = get_phys_addr_with_struct(env, ptw, ipa, access_type, result, fi); + ret = get_phys_addr_nogpc(env, ptw, ipa, access_type, result, fi); fi->s2addr = ipa; /* Combine the S1 and S2 perms. */ @@ -2942,7 +3142,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw, return false; } -static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw, +static bool get_phys_addr_nogpc(CPUARMState *env, S1Translate *ptw, target_ulong address, MMUAccessType access_type, GetPhysAddrResult *result, @@ -3076,6 +3276,23 @@ static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw, } } +static bool get_phys_addr_gpc(CPUARMState *env, S1Translate *ptw, + target_ulong address, + MMUAccessType access_type, + GetPhysAddrResult *result, + ARMMMUFaultInfo *fi) +{ + if (get_phys_addr_nogpc(env, ptw, address, access_type, result, fi)) { + return true; + } + if (!granule_protection_check(env, result->f.phys_addr, + result->f.attrs.space, fi)) { + fi->type = ARMFault_GPCFOnOutput; + return true; + } + return false; +} + bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address, MMUAccessType access_type, ARMMMUIdx mmu_idx, bool is_secure, GetPhysAddrResult *result, @@ -3086,8 +3303,7 @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address, .in_secure = is_secure, .in_space = arm_secure_to_space(is_secure), }; - return get_phys_addr_with_struct(env, &ptw, address, access_type, - result, fi); + return get_phys_addr_gpc(env, &ptw, address, access_type, result, fi); } bool get_phys_addr(CPUARMState *env, target_ulong address, @@ -3157,8 +3373,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, ptw.in_space = ss; ptw.in_secure = arm_space_is_secure(ss); - return get_phys_addr_with_struct(env, &ptw, address, access_type, - result, fi); + return get_phys_addr_gpc(env, &ptw, address, access_type, result, fi); } hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, @@ -3178,7 +3393,7 @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, ARMMMUFaultInfo fi = {}; bool ret; - ret = get_phys_addr_with_struct(env, &ptw, addr, MMU_DATA_LOAD, &res, &fi); + ret = get_phys_addr_gpc(env, &ptw, addr, MMU_DATA_LOAD, &res, &fi); *attrs = res.f.attrs; if (ret) { From patchwork Tue Jun 20 12:44:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 694511 Delivered-To: patch@linaro.org Received: by 2002:adf:e885:0:0:0:0:0 with SMTP id d5csp287241wrm; Tue, 20 Jun 2023 05:49:30 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4uOUCYkAOvhxCwjdYzRdQ6kuGn6p+9XA8liQRvFTLkZJnPntUcnYTKaOoYmx+IUDCD2xu3 X-Received: by 2002:a1f:450e:0:b0:471:549e:c1ff with SMTP id s14-20020a1f450e000000b00471549ec1ffmr4405650vka.7.1687265370667; Tue, 20 Jun 2023 05:49:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687265370; cv=none; d=google.com; s=arc-20160816; b=e5x6taOpp26x1GcgPrkwy0x5mN6rsXR8gJ/utiACk4PvCUuRK5CCWDlDq2O2C6q3V5 Z0hT/+gkaGrpIBLDXHJJ3LFomS+j5hCZS1BtHMxJNUkFbLUaiRH0PS4XXKLGajY/8I4S t8hrFsXtWqGhO/zNkQ5I7rOT9JAUvMsyKYnb7hS3ucWobReK/H7xfnewsgn6Y1rmGdGu +EgyGC0R5hm+YEpmTpSnDWj1u1uwb+/K++RR3KTAFGXt+nlkvmeNi8hpdkeK9zQ8+Hc3 Wv8NQLd1YNfei0Y8xuzTQnRp6vE4Gxm2NJ3n8C2/yeNmbdxItoz3oXFf7WPODJuzkGJt IrjA== ARC-Message-Signature: i=1; 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Add an x-l0gptsz property to set GPCCR_EL3.L0GPTSZ, for testing various possible configurations. Signed-off-by: Richard Henderson --- target/arm/tcg/cpu64.c | 53 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 2976f94ae4..6fec2d8a57 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -142,6 +142,56 @@ static void cpu_max_set_sve_max_vq(Object *obj, Visitor *v, const char *name, cpu->sve_max_vq = max_vq; } +static bool cpu_arm_get_rme(Object *obj, Error **errp) +{ + ARMCPU *cpu = ARM_CPU(obj); + return cpu_isar_feature(aa64_rme, cpu); +} + +static void cpu_arm_set_rme(Object *obj, bool value, Error **errp) +{ + ARMCPU *cpu = ARM_CPU(obj); + uint64_t t; + + t = cpu->isar.id_aa64pfr0; + t = FIELD_DP64(t, ID_AA64PFR0, RME, value); + cpu->isar.id_aa64pfr0 = t; +} + +static void cpu_max_set_l0gptsz(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + ARMCPU *cpu = ARM_CPU(obj); + uint32_t value; + + if (!visit_type_uint32(v, name, &value, errp)) { + return; + } + + /* Encode the value for the GPCCR_EL3 field. */ + switch (value) { + case 30: + case 34: + case 36: + case 39: + cpu->reset_l0gptsz = value - 30; + break; + default: + error_setg(errp, "invalid value for l0gptsz"); + error_append_hint(errp, "valid values are 30, 34, 36, 39\n"); + break; + } +} + +static void cpu_max_get_l0gptsz(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + ARMCPU *cpu = ARM_CPU(obj); + uint32_t value = cpu->reset_l0gptsz + 30; + + visit_type_uint32(v, name, &value, errp); +} + static Property arm_cpu_lpa2_property = DEFINE_PROP_BOOL("lpa2", ARMCPU, prop_lpa2, true); @@ -700,6 +750,9 @@ void aarch64_max_tcg_initfn(Object *obj) aarch64_add_sme_properties(obj); object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq, cpu_max_set_sve_max_vq, NULL, NULL); + object_property_add_bool(obj, "x-rme", cpu_arm_get_rme, cpu_arm_set_rme); + object_property_add(obj, "x-l0gptsz", "uint32", cpu_max_get_l0gptsz, + cpu_max_set_l0gptsz, NULL, NULL); qdev_property_add_static(DEVICE(obj), &arm_cpu_lpa2_property); }