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helo=mail.ilande.co.uk X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson Message-Id: <20230628071202.230991-2-richard.henderson@linaro.org> Signed-off-by: Mark Cave-Ayland --- target/sparc/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index bad2ec90a0..28d4cdb8b4 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -318,10 +318,10 @@ static void gen_goto_tb(DisasContext *s, int tb_num, tcg_gen_movi_tl(cpu_npc, npc); tcg_gen_exit_tb(s->base.tb, tb_num); } else { - /* jump to another page: currently not optimized */ + /* jump to another page: we can use an indirect jump */ tcg_gen_movi_tl(cpu_pc, pc); tcg_gen_movi_tl(cpu_npc, npc); - tcg_gen_exit_tb(NULL, 0); + tcg_gen_lookup_and_goto_ptr(); } } From patchwork Wed Jun 28 11:44:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 697227 Delivered-To: patch@linaro.org Received: by 2002:adf:e885:0:0:0:0:0 with SMTP id d5csp4293888wrm; Wed, 28 Jun 2023 04:45:49 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6pCAnToqBc4VKBKUPRrsmpDqBlO8YWxG/qyR8q8CnuTXDFjUMGrM3zoAjqmacDIndaSJrY X-Received: by 2002:a05:620a:a96:b0:766:a495:63f1 with SMTP id v22-20020a05620a0a9600b00766a49563f1mr6151315qkg.59.1687952748907; Wed, 28 Jun 2023 04:45:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687952748; cv=none; d=google.com; s=arc-20160816; b=DhzZbvCu/zOS+g/LwMK3gtcweyPe2tMBINmcFgShajhbvPOM9ki2oW/LzCO+aevxI4 VlvNjR+RUJEDc+8efJw2UlTg17ES7OBoVP71PBqsLyhYphRnrrR559YqFl1H8KXQFFyS kHnTfE+XwwWRUL64VkdxGewdE97PFLzYChjKubEG0WPxiLMOXFdo0DqRdDP/5qHhz+XK YXS8i9gmefFuBW63vRtaGd+ANaWZNdJSMrw+xa7XrTw8FTrgtSZwWv7LkO+95amEFd3k hYqPIV+1bfYq0zvJ5dm+Jngwh1kIDjpKvO/M6mnoooOkfn0SI6DnRQ5pzJuyMNmEMcO4 M/0Q== ARC-Message-Signature: i=1; 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[209.51.188.17]) by mx.google.com with ESMTPS id sn19-20020a05620a949300b007670d709a19si1916074qkn.667.2023.06.28.04.45.48 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 28 Jun 2023 04:45:48 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@ilande.co.uk header.s=20220518 header.b=MI5HTISL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=ilande.co.uk Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qETcB-0002Uc-OY; Wed, 28 Jun 2023 07:45:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qETbz-0002GU-Pj for qemu-devel@nongnu.org; Wed, 28 Jun 2023 07:45:28 -0400 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qETby-00055S-Be for qemu-devel@nongnu.org; Wed, 28 Jun 2023 07:45:27 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=ilande.co.uk; s=20220518; h=Subject:Content-Transfer-Encoding:Content-Type: MIME-Version:References:In-Reply-To:Message-Id:Date:To:From:Sender:Reply-To: Cc:Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=kA8U5ZqxC+smogql+DAxDyinmV9IOFsn3lSKwKB0BTU=; b=MI5HTISLb7cbS3trzdbz9nfh/b B4rco69fQgG9jTvfrJEaQul8Jc+StmB+QDq2bhR8jBJCz31VQ+YxuDj1ja4ZCoOAtcFHt1DKxle/+ LabU6zh1MsKUAxMMtCG2lKMHkuTEqJcuDvcXk6WPmHIKfVL4IsISzU3HJGxM6+wPXiCUVPUZKiXlL Y5ThxuqLnfv35GwMi6CwpQynPm2jU5QGQcbxuIszYfMwdC5XWozU3ZFwaGrLwTuj0sExofx6nQet/ HIPdQWHhgKF5DT4n1mw4KF1sONnO8e+AwebkINxc9e331eKKwCO29nMpLCyKDnxwkIHZytRzb6jYT xqQtNJcakMW5OcUP00/wlrIA5HH9V1JFKOqwO0zBTA7UAJOLyLooLuibuOICIckwxdI/mff66bmNy otHjY6EtWnvXPbe+0ni3G7AUUGJwfXlqrgTTd0oIEOUWLeChFwDv3+kGSFO+VlZwY1THoG9ZifHN5 3KyxD4RTW0Zr3/+mrkPoMfiNB+SsS/LZ7H20+yrA5QF5bwHStrD9kWVFPUTsXlyJ3lYHfTh/elxNt /KarAwFN7oTWbfkv9G7mcY/UxFlga9CNkrh59S1HY2qZp+LJi6wG5g/cPOAaKOSu+yt+SaVoCGGMB TLw9vp6bjqKrlM8jKrEU9VR8Fs2LbQEBS/M25P2Zs=; Received: from host86-130-37-216.range86-130.btcentralplus.com ([86.130.37.216] helo=kentang.home) by mail.ilande.co.uk with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1qETbk-00007c-1P; Wed, 28 Jun 2023 12:45:16 +0100 From: Mark Cave-Ayland To: richard.henderson@linaro.org, qemu-devel@nongnu.org Date: Wed, 28 Jun 2023 12:44:57 +0100 Message-Id: <20230628114504.546265-4-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230628114504.546265-1-mark.cave-ayland@ilande.co.uk> References: <20230628114504.546265-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 86.130.37.216 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PULL 03/10] target/sparc: Fix npc comparison in sparc_tr_insn_start X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.ilande.co.uk) Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.ilande.co.uk X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson During translation, npc == address, DYNAMIC_PC, or JUMP_PC. It is only the encoding between here and sparc_restore_state_to_opc that considers JUMP_PC to be a bit within a larger value. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson Message-Id: <20230628071202.230991-3-richard.henderson@linaro.org> Signed-off-by: Mark Cave-Ayland --- target/sparc/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 28d4cdb8b4..eec6f9ca67 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -5594,7 +5594,7 @@ static void sparc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) { DisasContext *dc = container_of(dcbase, DisasContext, base); - if (dc->npc & JUMP_PC) { + if (dc->npc == JUMP_PC) { assert(dc->jump_pc[1] == dc->pc + 4); tcg_gen_insn_start(dc->pc, dc->jump_pc[0] | JUMP_PC); } else { From patchwork Wed Jun 28 11:44:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 697228 Delivered-To: patch@linaro.org Received: by 2002:adf:e885:0:0:0:0:0 with SMTP id d5csp4294291wrm; Wed, 28 Jun 2023 04:46:34 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4yyUjn+q8NEMeZmIcmK2TDNUW7+X5G5Cjm/oGAYz8yQzbQOz7hZVx5hHxPVq5XCrL5a8P1 X-Received: by 2002:a05:622a:24a:b0:3f9:d1c3:cc45 with SMTP id c10-20020a05622a024a00b003f9d1c3cc45mr1079792qtx.28.1687952793922; Wed, 28 Jun 2023 04:46:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687952793; cv=none; d=google.com; s=arc-20160816; b=vsNfIR64bQybuSG4pvF3nZlLV9vIO7KHmMP9p9lMpvHRslV0YZ2v9/G2HQYqyWvXDe j3BHCVeOeH89z4uCVd/S+sU9mXSmVA7sKRw6iT1IQ2d8Gn8sVmbAHVApPb9z399wUOKK LiHAOZgV3u67jX2HAa514x3sZJx2N6cOC0CwfgxgBliEtUdYHiViTDQ9HAt3hadx5NGo afMHC8H9jpqlx5YfKs5unafkG/Eel6olot4kk1WYk7AZ2zhwGGkiMyhYUZC8Oh5KmyRK 2goHwW0xBiIV9v+NuWs6sEfoCm+i9MkHeadV5yXVU4jdd/7tP/6rA6P2U8Wu/IkyUFVk nIcw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=140iotHyAXb8nQrPtoMETKLOoTmg8PCnWh1NNG0FORE=; fh=dxNoli/Xs5PJEU4/5g3muAZqP4q86W456+YpDLBdAUw=; b=bbubDRnwIiaB97wRDeP9v9uPbmWYyI6S0HKqTtlE9sRFrxw2+8EO6ZKUT1i2OGi6mP QRiTuLY0YGqWEnEoC4sZ6M3FxnLDbrJFFUWKz5bmJsZEd2PLgxqjA9A1pLmfWxzpFn5X l6Iq0FLcZVQuOgWM6/1G289IjyJUemfDKG0CZcjXt6LYEsXpXajO1p1LUvGqmNB04vAw PxygfqfhFwREZUjS6RYf+0b29OsDATuv6iWgGbvZusBCu6E+VcsQ7wUwzB6+qnJI8gq3 ouoGmDD+BkyRNsIBVDYvZl66bA/tTLeKpUUH1awtRYrKuxp0L5XfPKck2od3wEtAZRFO 2uoA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@ilande.co.uk header.s=20220518 header.b=xiitRSyP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=ilande.co.uk Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson Message-Id: <20230628071202.230991-4-richard.henderson@linaro.org> Signed-off-by: Mark Cave-Ayland --- target/sparc/translate.c | 237 ++++++++++++++++++--------------------- 1 file changed, 111 insertions(+), 126 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index eec6f9ca67..1312c3e94d 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -125,7 +125,7 @@ static int sign_extend(int x, int len) #define IS_IMM (insn & (1<<13)) -static inline void gen_update_fprs_dirty(DisasContext *dc, int rd) +static void gen_update_fprs_dirty(DisasContext *dc, int rd) { #if defined(TARGET_SPARC64) int bit = (rd < 32) ? 1 : 2; @@ -264,7 +264,7 @@ static void gen_move_Q(DisasContext *dc, unsigned int rd, unsigned int rs) #endif #endif -static inline void gen_address_mask(DisasContext *dc, TCGv addr) +static void gen_address_mask(DisasContext *dc, TCGv addr) { #ifdef TARGET_SPARC64 if (AM_CHECK(dc)) @@ -272,7 +272,7 @@ static inline void gen_address_mask(DisasContext *dc, TCGv addr) #endif } -static inline TCGv gen_load_gpr(DisasContext *dc, int reg) +static TCGv gen_load_gpr(DisasContext *dc, int reg) { if (reg > 0) { assert(reg < 32); @@ -284,7 +284,7 @@ static inline TCGv gen_load_gpr(DisasContext *dc, int reg) } } -static inline void gen_store_gpr(DisasContext *dc, int reg, TCGv v) +static void gen_store_gpr(DisasContext *dc, int reg, TCGv v) { if (reg > 0) { assert(reg < 32); @@ -292,7 +292,7 @@ static inline void gen_store_gpr(DisasContext *dc, int reg, TCGv v) } } -static inline TCGv gen_dest_gpr(DisasContext *dc, int reg) +static TCGv gen_dest_gpr(DisasContext *dc, int reg) { if (reg > 0) { assert(reg < 32); @@ -326,31 +326,31 @@ static void gen_goto_tb(DisasContext *s, int tb_num, } // XXX suboptimal -static inline void gen_mov_reg_N(TCGv reg, TCGv_i32 src) +static void gen_mov_reg_N(TCGv reg, TCGv_i32 src) { tcg_gen_extu_i32_tl(reg, src); tcg_gen_extract_tl(reg, reg, PSR_NEG_SHIFT, 1); } -static inline void gen_mov_reg_Z(TCGv reg, TCGv_i32 src) +static void gen_mov_reg_Z(TCGv reg, TCGv_i32 src) { tcg_gen_extu_i32_tl(reg, src); tcg_gen_extract_tl(reg, reg, PSR_ZERO_SHIFT, 1); } -static inline void gen_mov_reg_V(TCGv reg, TCGv_i32 src) +static void gen_mov_reg_V(TCGv reg, TCGv_i32 src) { tcg_gen_extu_i32_tl(reg, src); tcg_gen_extract_tl(reg, reg, PSR_OVF_SHIFT, 1); } -static inline void gen_mov_reg_C(TCGv reg, TCGv_i32 src) +static void gen_mov_reg_C(TCGv reg, TCGv_i32 src) { tcg_gen_extu_i32_tl(reg, src); tcg_gen_extract_tl(reg, reg, PSR_CARRY_SHIFT, 1); } -static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2) +static void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2) { tcg_gen_mov_tl(cpu_cc_src, src1); tcg_gen_mov_tl(cpu_cc_src2, src2); @@ -465,7 +465,7 @@ static void gen_op_addx_int(DisasContext *dc, TCGv dst, TCGv src1, } } -static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2) +static void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2) { tcg_gen_mov_tl(cpu_cc_src, src1); tcg_gen_mov_tl(cpu_cc_src2, src2); @@ -538,7 +538,7 @@ static void gen_op_subx_int(DisasContext *dc, TCGv dst, TCGv src1, } } -static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2) +static void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2) { TCGv r_temp, zero, t0; @@ -577,7 +577,7 @@ static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2) tcg_gen_mov_tl(dst, cpu_cc_dst); } -static inline void gen_op_multiply(TCGv dst, TCGv src1, TCGv src2, int sign_ext) +static void gen_op_multiply(TCGv dst, TCGv src1, TCGv src2, int sign_ext) { #if TARGET_LONG_BITS == 32 if (sign_ext) { @@ -602,32 +602,32 @@ static inline void gen_op_multiply(TCGv dst, TCGv src1, TCGv src2, int sign_ext) #endif } -static inline void gen_op_umul(TCGv dst, TCGv src1, TCGv src2) +static void gen_op_umul(TCGv dst, TCGv src1, TCGv src2) { /* zero-extend truncated operands before multiplication */ gen_op_multiply(dst, src1, src2, 0); } -static inline void gen_op_smul(TCGv dst, TCGv src1, TCGv src2) +static void gen_op_smul(TCGv dst, TCGv src1, TCGv src2) { /* sign-extend truncated operands before multiplication */ gen_op_multiply(dst, src1, src2, 1); } // 1 -static inline void gen_op_eval_ba(TCGv dst) +static void gen_op_eval_ba(TCGv dst) { tcg_gen_movi_tl(dst, 1); } // Z -static inline void gen_op_eval_be(TCGv dst, TCGv_i32 src) +static void gen_op_eval_be(TCGv dst, TCGv_i32 src) { gen_mov_reg_Z(dst, src); } // Z | (N ^ V) -static inline void gen_op_eval_ble(TCGv dst, TCGv_i32 src) +static void gen_op_eval_ble(TCGv dst, TCGv_i32 src) { TCGv t0 = tcg_temp_new(); gen_mov_reg_N(t0, src); @@ -638,7 +638,7 @@ static inline void gen_op_eval_ble(TCGv dst, TCGv_i32 src) } // N ^ V -static inline void gen_op_eval_bl(TCGv dst, TCGv_i32 src) +static void gen_op_eval_bl(TCGv dst, TCGv_i32 src) { TCGv t0 = tcg_temp_new(); gen_mov_reg_V(t0, src); @@ -647,7 +647,7 @@ static inline void gen_op_eval_bl(TCGv dst, TCGv_i32 src) } // C | Z -static inline void gen_op_eval_bleu(TCGv dst, TCGv_i32 src) +static void gen_op_eval_bleu(TCGv dst, TCGv_i32 src) { TCGv t0 = tcg_temp_new(); gen_mov_reg_Z(t0, src); @@ -656,73 +656,73 @@ static inline void gen_op_eval_bleu(TCGv dst, TCGv_i32 src) } // C -static inline void gen_op_eval_bcs(TCGv dst, TCGv_i32 src) +static void gen_op_eval_bcs(TCGv dst, TCGv_i32 src) { gen_mov_reg_C(dst, src); } // V -static inline void gen_op_eval_bvs(TCGv dst, TCGv_i32 src) +static void gen_op_eval_bvs(TCGv dst, TCGv_i32 src) { gen_mov_reg_V(dst, src); } // 0 -static inline void gen_op_eval_bn(TCGv dst) +static void gen_op_eval_bn(TCGv dst) { tcg_gen_movi_tl(dst, 0); } // N -static inline void gen_op_eval_bneg(TCGv dst, TCGv_i32 src) +static void gen_op_eval_bneg(TCGv dst, TCGv_i32 src) { gen_mov_reg_N(dst, src); } // !Z -static inline void gen_op_eval_bne(TCGv dst, TCGv_i32 src) +static void gen_op_eval_bne(TCGv dst, TCGv_i32 src) { gen_mov_reg_Z(dst, src); tcg_gen_xori_tl(dst, dst, 0x1); } // !(Z | (N ^ V)) -static inline void gen_op_eval_bg(TCGv dst, TCGv_i32 src) +static void gen_op_eval_bg(TCGv dst, TCGv_i32 src) { gen_op_eval_ble(dst, src); tcg_gen_xori_tl(dst, dst, 0x1); } // !(N ^ V) -static inline void gen_op_eval_bge(TCGv dst, TCGv_i32 src) +static void gen_op_eval_bge(TCGv dst, TCGv_i32 src) { gen_op_eval_bl(dst, src); tcg_gen_xori_tl(dst, dst, 0x1); } // !(C | Z) -static inline void gen_op_eval_bgu(TCGv dst, TCGv_i32 src) +static void gen_op_eval_bgu(TCGv dst, TCGv_i32 src) { gen_op_eval_bleu(dst, src); tcg_gen_xori_tl(dst, dst, 0x1); } // !C -static inline void gen_op_eval_bcc(TCGv dst, TCGv_i32 src) +static void gen_op_eval_bcc(TCGv dst, TCGv_i32 src) { gen_mov_reg_C(dst, src); tcg_gen_xori_tl(dst, dst, 0x1); } // !N -static inline void gen_op_eval_bpos(TCGv dst, TCGv_i32 src) +static void gen_op_eval_bpos(TCGv dst, TCGv_i32 src) { gen_mov_reg_N(dst, src); tcg_gen_xori_tl(dst, dst, 0x1); } // !V -static inline void gen_op_eval_bvc(TCGv dst, TCGv_i32 src) +static void gen_op_eval_bvc(TCGv dst, TCGv_i32 src) { gen_mov_reg_V(dst, src); tcg_gen_xori_tl(dst, dst, 0x1); @@ -735,23 +735,21 @@ static inline void gen_op_eval_bvc(TCGv dst, TCGv_i32 src) 2 > 3 unordered */ -static inline void gen_mov_reg_FCC0(TCGv reg, TCGv src, +static void gen_mov_reg_FCC0(TCGv reg, TCGv src, unsigned int fcc_offset) { tcg_gen_shri_tl(reg, src, FSR_FCC0_SHIFT + fcc_offset); tcg_gen_andi_tl(reg, reg, 0x1); } -static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src, - unsigned int fcc_offset) +static void gen_mov_reg_FCC1(TCGv reg, TCGv src, unsigned int fcc_offset) { tcg_gen_shri_tl(reg, src, FSR_FCC1_SHIFT + fcc_offset); tcg_gen_andi_tl(reg, reg, 0x1); } // !0: FCC0 | FCC1 -static inline void gen_op_eval_fbne(TCGv dst, TCGv src, - unsigned int fcc_offset) +static void gen_op_eval_fbne(TCGv dst, TCGv src, unsigned int fcc_offset) { TCGv t0 = tcg_temp_new(); gen_mov_reg_FCC0(dst, src, fcc_offset); @@ -760,8 +758,7 @@ static inline void gen_op_eval_fbne(TCGv dst, TCGv src, } // 1 or 2: FCC0 ^ FCC1 -static inline void gen_op_eval_fblg(TCGv dst, TCGv src, - unsigned int fcc_offset) +static void gen_op_eval_fblg(TCGv dst, TCGv src, unsigned int fcc_offset) { TCGv t0 = tcg_temp_new(); gen_mov_reg_FCC0(dst, src, fcc_offset); @@ -770,15 +767,13 @@ static inline void gen_op_eval_fblg(TCGv dst, TCGv src, } // 1 or 3: FCC0 -static inline void gen_op_eval_fbul(TCGv dst, TCGv src, - unsigned int fcc_offset) +static void gen_op_eval_fbul(TCGv dst, TCGv src, unsigned int fcc_offset) { gen_mov_reg_FCC0(dst, src, fcc_offset); } // 1: FCC0 & !FCC1 -static inline void gen_op_eval_fbl(TCGv dst, TCGv src, - unsigned int fcc_offset) +static void gen_op_eval_fbl(TCGv dst, TCGv src, unsigned int fcc_offset) { TCGv t0 = tcg_temp_new(); gen_mov_reg_FCC0(dst, src, fcc_offset); @@ -787,15 +782,13 @@ static inline void gen_op_eval_fbl(TCGv dst, TCGv src, } // 2 or 3: FCC1 -static inline void gen_op_eval_fbug(TCGv dst, TCGv src, - unsigned int fcc_offset) +static void gen_op_eval_fbug(TCGv dst, TCGv src, unsigned int fcc_offset) { gen_mov_reg_FCC1(dst, src, fcc_offset); } // 2: !FCC0 & FCC1 -static inline void gen_op_eval_fbg(TCGv dst, TCGv src, - unsigned int fcc_offset) +static void gen_op_eval_fbg(TCGv dst, TCGv src, unsigned int fcc_offset) { TCGv t0 = tcg_temp_new(); gen_mov_reg_FCC0(dst, src, fcc_offset); @@ -804,8 +797,7 @@ static inline void gen_op_eval_fbg(TCGv dst, TCGv src, } // 3: FCC0 & FCC1 -static inline void gen_op_eval_fbu(TCGv dst, TCGv src, - unsigned int fcc_offset) +static void gen_op_eval_fbu(TCGv dst, TCGv src, unsigned int fcc_offset) { TCGv t0 = tcg_temp_new(); gen_mov_reg_FCC0(dst, src, fcc_offset); @@ -814,8 +806,7 @@ static inline void gen_op_eval_fbu(TCGv dst, TCGv src, } // 0: !(FCC0 | FCC1) -static inline void gen_op_eval_fbe(TCGv dst, TCGv src, - unsigned int fcc_offset) +static void gen_op_eval_fbe(TCGv dst, TCGv src, unsigned int fcc_offset) { TCGv t0 = tcg_temp_new(); gen_mov_reg_FCC0(dst, src, fcc_offset); @@ -825,8 +816,7 @@ static inline void gen_op_eval_fbe(TCGv dst, TCGv src, } // 0 or 3: !(FCC0 ^ FCC1) -static inline void gen_op_eval_fbue(TCGv dst, TCGv src, - unsigned int fcc_offset) +static void gen_op_eval_fbue(TCGv dst, TCGv src, unsigned int fcc_offset) { TCGv t0 = tcg_temp_new(); gen_mov_reg_FCC0(dst, src, fcc_offset); @@ -836,16 +826,14 @@ static inline void gen_op_eval_fbue(TCGv dst, TCGv src, } // 0 or 2: !FCC0 -static inline void gen_op_eval_fbge(TCGv dst, TCGv src, - unsigned int fcc_offset) +static void gen_op_eval_fbge(TCGv dst, TCGv src, unsigned int fcc_offset) { gen_mov_reg_FCC0(dst, src, fcc_offset); tcg_gen_xori_tl(dst, dst, 0x1); } // !1: !(FCC0 & !FCC1) -static inline void gen_op_eval_fbuge(TCGv dst, TCGv src, - unsigned int fcc_offset) +static void gen_op_eval_fbuge(TCGv dst, TCGv src, unsigned int fcc_offset) { TCGv t0 = tcg_temp_new(); gen_mov_reg_FCC0(dst, src, fcc_offset); @@ -855,16 +843,14 @@ static inline void gen_op_eval_fbuge(TCGv dst, TCGv src, } // 0 or 1: !FCC1 -static inline void gen_op_eval_fble(TCGv dst, TCGv src, - unsigned int fcc_offset) +static void gen_op_eval_fble(TCGv dst, TCGv src, unsigned int fcc_offset) { gen_mov_reg_FCC1(dst, src, fcc_offset); tcg_gen_xori_tl(dst, dst, 0x1); } // !2: !(!FCC0 & FCC1) -static inline void gen_op_eval_fbule(TCGv dst, TCGv src, - unsigned int fcc_offset) +static void gen_op_eval_fbule(TCGv dst, TCGv src, unsigned int fcc_offset) { TCGv t0 = tcg_temp_new(); gen_mov_reg_FCC0(dst, src, fcc_offset); @@ -874,8 +860,7 @@ static inline void gen_op_eval_fbule(TCGv dst, TCGv src, } // !3: !(FCC0 & FCC1) -static inline void gen_op_eval_fbo(TCGv dst, TCGv src, - unsigned int fcc_offset) +static void gen_op_eval_fbo(TCGv dst, TCGv src, unsigned int fcc_offset) { TCGv t0 = tcg_temp_new(); gen_mov_reg_FCC0(dst, src, fcc_offset); @@ -884,8 +869,8 @@ static inline void gen_op_eval_fbo(TCGv dst, TCGv src, tcg_gen_xori_tl(dst, dst, 0x1); } -static inline void gen_branch2(DisasContext *dc, target_ulong pc1, - target_ulong pc2, TCGv r_cond) +static void gen_branch2(DisasContext *dc, target_ulong pc1, + target_ulong pc2, TCGv r_cond) { TCGLabel *l1 = gen_new_label(); @@ -935,7 +920,7 @@ static void gen_branch_n(DisasContext *dc, target_ulong pc1) } } -static inline void gen_generic_branch(DisasContext *dc) +static void gen_generic_branch(DisasContext *dc) { TCGv npc0 = tcg_constant_tl(dc->jump_pc[0]); TCGv npc1 = tcg_constant_tl(dc->jump_pc[1]); @@ -946,7 +931,7 @@ static inline void gen_generic_branch(DisasContext *dc) /* call this function before using the condition register as it may have been set for a jump */ -static inline void flush_cond(DisasContext *dc) +static void flush_cond(DisasContext *dc) { if (dc->npc == JUMP_PC) { gen_generic_branch(dc); @@ -954,7 +939,7 @@ static inline void flush_cond(DisasContext *dc) } } -static inline void save_npc(DisasContext *dc) +static void save_npc(DisasContext *dc) { if (dc->npc == JUMP_PC) { gen_generic_branch(dc); @@ -964,7 +949,7 @@ static inline void save_npc(DisasContext *dc) } } -static inline void update_psr(DisasContext *dc) +static void update_psr(DisasContext *dc) { if (dc->cc_op != CC_OP_FLAGS) { dc->cc_op = CC_OP_FLAGS; @@ -972,7 +957,7 @@ static inline void update_psr(DisasContext *dc) } } -static inline void save_state(DisasContext *dc) +static void save_state(DisasContext *dc) { tcg_gen_movi_tl(cpu_pc, dc->pc); save_npc(dc); @@ -990,7 +975,7 @@ static void gen_check_align(TCGv addr, int mask) gen_helper_check_align(cpu_env, addr, tcg_constant_i32(mask)); } -static inline void gen_mov_pc_npc(DisasContext *dc) +static void gen_mov_pc_npc(DisasContext *dc) { if (dc->npc == JUMP_PC) { gen_generic_branch(dc); @@ -1004,7 +989,7 @@ static inline void gen_mov_pc_npc(DisasContext *dc) } } -static inline void gen_op_next_insn(void) +static void gen_op_next_insn(void) { tcg_gen_mov_tl(cpu_pc, cpu_npc); tcg_gen_addi_tl(cpu_npc, cpu_npc, 4); @@ -1305,7 +1290,7 @@ static void gen_compare_reg(DisasCompare *cmp, int cond, TCGv r_src) cmp->c2 = tcg_constant_tl(0); } -static inline void gen_cond_reg(TCGv r_dst, int cond, TCGv r_src) +static void gen_cond_reg(TCGv r_dst, int cond, TCGv r_src) { DisasCompare cmp; gen_compare_reg(&cmp, cond, r_src); @@ -1414,7 +1399,7 @@ static void do_branch_reg(DisasContext *dc, int32_t offset, uint32_t insn, } } -static inline void gen_op_fcmps(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2) +static void gen_op_fcmps(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2) { switch (fccno) { case 0: @@ -1432,7 +1417,7 @@ static inline void gen_op_fcmps(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2) } } -static inline void gen_op_fcmpd(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2) +static void gen_op_fcmpd(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2) { switch (fccno) { case 0: @@ -1450,7 +1435,7 @@ static inline void gen_op_fcmpd(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2) } } -static inline void gen_op_fcmpq(int fccno) +static void gen_op_fcmpq(int fccno) { switch (fccno) { case 0: @@ -1468,7 +1453,7 @@ static inline void gen_op_fcmpq(int fccno) } } -static inline void gen_op_fcmpes(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2) +static void gen_op_fcmpes(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2) { switch (fccno) { case 0: @@ -1486,7 +1471,7 @@ static inline void gen_op_fcmpes(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2) } } -static inline void gen_op_fcmped(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2) +static void gen_op_fcmped(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2) { switch (fccno) { case 0: @@ -1504,7 +1489,7 @@ static inline void gen_op_fcmped(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2) } } -static inline void gen_op_fcmpeq(int fccno) +static void gen_op_fcmpeq(int fccno) { switch (fccno) { case 0: @@ -1524,32 +1509,32 @@ static inline void gen_op_fcmpeq(int fccno) #else -static inline void gen_op_fcmps(int fccno, TCGv r_rs1, TCGv r_rs2) +static void gen_op_fcmps(int fccno, TCGv r_rs1, TCGv r_rs2) { gen_helper_fcmps(cpu_fsr, cpu_env, r_rs1, r_rs2); } -static inline void gen_op_fcmpd(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2) +static void gen_op_fcmpd(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2) { gen_helper_fcmpd(cpu_fsr, cpu_env, r_rs1, r_rs2); } -static inline void gen_op_fcmpq(int fccno) +static void gen_op_fcmpq(int fccno) { gen_helper_fcmpq(cpu_fsr, cpu_env); } -static inline void gen_op_fcmpes(int fccno, TCGv r_rs1, TCGv r_rs2) +static void gen_op_fcmpes(int fccno, TCGv r_rs1, TCGv r_rs2) { gen_helper_fcmpes(cpu_fsr, cpu_env, r_rs1, r_rs2); } -static inline void gen_op_fcmped(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2) +static void gen_op_fcmped(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2) { gen_helper_fcmped(cpu_fsr, cpu_env, r_rs1, r_rs2); } -static inline void gen_op_fcmpeq(int fccno) +static void gen_op_fcmpeq(int fccno) { gen_helper_fcmpeq(cpu_fsr, cpu_env); } @@ -1573,12 +1558,12 @@ static int gen_trap_ifnofpu(DisasContext *dc) return 0; } -static inline void gen_op_clear_ieee_excp_and_FTT(void) +static void gen_op_clear_ieee_excp_and_FTT(void) { tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_CEXC_NMASK); } -static inline void gen_fop_FF(DisasContext *dc, int rd, int rs, +static void gen_fop_FF(DisasContext *dc, int rd, int rs, void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i32)) { TCGv_i32 dst, src; @@ -1592,8 +1577,8 @@ static inline void gen_fop_FF(DisasContext *dc, int rd, int rs, gen_store_fpr_F(dc, rd, dst); } -static inline void gen_ne_fop_FF(DisasContext *dc, int rd, int rs, - void (*gen)(TCGv_i32, TCGv_i32)) +static void gen_ne_fop_FF(DisasContext *dc, int rd, int rs, + void (*gen)(TCGv_i32, TCGv_i32)) { TCGv_i32 dst, src; @@ -1605,7 +1590,7 @@ static inline void gen_ne_fop_FF(DisasContext *dc, int rd, int rs, gen_store_fpr_F(dc, rd, dst); } -static inline void gen_fop_FFF(DisasContext *dc, int rd, int rs1, int rs2, +static void gen_fop_FFF(DisasContext *dc, int rd, int rs1, int rs2, void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32)) { TCGv_i32 dst, src1, src2; @@ -1621,8 +1606,8 @@ static inline void gen_fop_FFF(DisasContext *dc, int rd, int rs1, int rs2, } #ifdef TARGET_SPARC64 -static inline void gen_ne_fop_FFF(DisasContext *dc, int rd, int rs1, int rs2, - void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32)) +static void gen_ne_fop_FFF(DisasContext *dc, int rd, int rs1, int rs2, + void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32)) { TCGv_i32 dst, src1, src2; @@ -1636,8 +1621,8 @@ static inline void gen_ne_fop_FFF(DisasContext *dc, int rd, int rs1, int rs2, } #endif -static inline void gen_fop_DD(DisasContext *dc, int rd, int rs, - void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i64)) +static void gen_fop_DD(DisasContext *dc, int rd, int rs, + void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i64)) { TCGv_i64 dst, src; @@ -1651,8 +1636,8 @@ static inline void gen_fop_DD(DisasContext *dc, int rd, int rs, } #ifdef TARGET_SPARC64 -static inline void gen_ne_fop_DD(DisasContext *dc, int rd, int rs, - void (*gen)(TCGv_i64, TCGv_i64)) +static void gen_ne_fop_DD(DisasContext *dc, int rd, int rs, + void (*gen)(TCGv_i64, TCGv_i64)) { TCGv_i64 dst, src; @@ -1665,7 +1650,7 @@ static inline void gen_ne_fop_DD(DisasContext *dc, int rd, int rs, } #endif -static inline void gen_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2, +static void gen_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2, void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64)) { TCGv_i64 dst, src1, src2; @@ -1681,8 +1666,8 @@ static inline void gen_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2, } #ifdef TARGET_SPARC64 -static inline void gen_ne_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2, - void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64)) +static void gen_ne_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2, + void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64)) { TCGv_i64 dst, src1, src2; @@ -1695,8 +1680,8 @@ static inline void gen_ne_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2, gen_store_fpr_D(dc, rd, dst); } -static inline void gen_gsr_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2, - void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64)) +static void gen_gsr_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2, + void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64)) { TCGv_i64 dst, src1, src2; @@ -1709,8 +1694,8 @@ static inline void gen_gsr_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2, gen_store_fpr_D(dc, rd, dst); } -static inline void gen_ne_fop_DDDD(DisasContext *dc, int rd, int rs1, int rs2, - void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64)) +static void gen_ne_fop_DDDD(DisasContext *dc, int rd, int rs1, int rs2, + void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64)) { TCGv_i64 dst, src0, src1, src2; @@ -1725,8 +1710,8 @@ static inline void gen_ne_fop_DDDD(DisasContext *dc, int rd, int rs1, int rs2, } #endif -static inline void gen_fop_QQ(DisasContext *dc, int rd, int rs, - void (*gen)(TCGv_ptr)) +static void gen_fop_QQ(DisasContext *dc, int rd, int rs, + void (*gen)(TCGv_ptr)) { gen_op_load_fpr_QT1(QFPREG(rs)); @@ -1738,8 +1723,8 @@ static inline void gen_fop_QQ(DisasContext *dc, int rd, int rs, } #ifdef TARGET_SPARC64 -static inline void gen_ne_fop_QQ(DisasContext *dc, int rd, int rs, - void (*gen)(TCGv_ptr)) +static void gen_ne_fop_QQ(DisasContext *dc, int rd, int rs, + void (*gen)(TCGv_ptr)) { gen_op_load_fpr_QT1(QFPREG(rs)); @@ -1750,8 +1735,8 @@ static inline void gen_ne_fop_QQ(DisasContext *dc, int rd, int rs, } #endif -static inline void gen_fop_QQQ(DisasContext *dc, int rd, int rs1, int rs2, - void (*gen)(TCGv_ptr)) +static void gen_fop_QQQ(DisasContext *dc, int rd, int rs1, int rs2, + void (*gen)(TCGv_ptr)) { gen_op_load_fpr_QT0(QFPREG(rs1)); gen_op_load_fpr_QT1(QFPREG(rs2)); @@ -1763,7 +1748,7 @@ static inline void gen_fop_QQQ(DisasContext *dc, int rd, int rs1, int rs2, gen_update_fprs_dirty(dc, QFPREG(rd)); } -static inline void gen_fop_DFF(DisasContext *dc, int rd, int rs1, int rs2, +static void gen_fop_DFF(DisasContext *dc, int rd, int rs1, int rs2, void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32, TCGv_i32)) { TCGv_i64 dst; @@ -1779,8 +1764,8 @@ static inline void gen_fop_DFF(DisasContext *dc, int rd, int rs1, int rs2, gen_store_fpr_D(dc, rd, dst); } -static inline void gen_fop_QDD(DisasContext *dc, int rd, int rs1, int rs2, - void (*gen)(TCGv_ptr, TCGv_i64, TCGv_i64)) +static void gen_fop_QDD(DisasContext *dc, int rd, int rs1, int rs2, + void (*gen)(TCGv_ptr, TCGv_i64, TCGv_i64)) { TCGv_i64 src1, src2; @@ -1795,8 +1780,8 @@ static inline void gen_fop_QDD(DisasContext *dc, int rd, int rs1, int rs2, } #ifdef TARGET_SPARC64 -static inline void gen_fop_DF(DisasContext *dc, int rd, int rs, - void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32)) +static void gen_fop_DF(DisasContext *dc, int rd, int rs, + void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32)) { TCGv_i64 dst; TCGv_i32 src; @@ -1811,8 +1796,8 @@ static inline void gen_fop_DF(DisasContext *dc, int rd, int rs, } #endif -static inline void gen_ne_fop_DF(DisasContext *dc, int rd, int rs, - void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32)) +static void gen_ne_fop_DF(DisasContext *dc, int rd, int rs, + void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32)) { TCGv_i64 dst; TCGv_i32 src; @@ -1825,8 +1810,8 @@ static inline void gen_ne_fop_DF(DisasContext *dc, int rd, int rs, gen_store_fpr_D(dc, rd, dst); } -static inline void gen_fop_FD(DisasContext *dc, int rd, int rs, - void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i64)) +static void gen_fop_FD(DisasContext *dc, int rd, int rs, + void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i64)) { TCGv_i32 dst; TCGv_i64 src; @@ -1840,8 +1825,8 @@ static inline void gen_fop_FD(DisasContext *dc, int rd, int rs, gen_store_fpr_F(dc, rd, dst); } -static inline void gen_fop_FQ(DisasContext *dc, int rd, int rs, - void (*gen)(TCGv_i32, TCGv_ptr)) +static void gen_fop_FQ(DisasContext *dc, int rd, int rs, + void (*gen)(TCGv_i32, TCGv_ptr)) { TCGv_i32 dst; @@ -1854,8 +1839,8 @@ static inline void gen_fop_FQ(DisasContext *dc, int rd, int rs, gen_store_fpr_F(dc, rd, dst); } -static inline void gen_fop_DQ(DisasContext *dc, int rd, int rs, - void (*gen)(TCGv_i64, TCGv_ptr)) +static void gen_fop_DQ(DisasContext *dc, int rd, int rs, + void (*gen)(TCGv_i64, TCGv_ptr)) { TCGv_i64 dst; @@ -1868,8 +1853,8 @@ static inline void gen_fop_DQ(DisasContext *dc, int rd, int rs, gen_store_fpr_D(dc, rd, dst); } -static inline void gen_ne_fop_QF(DisasContext *dc, int rd, int rs, - void (*gen)(TCGv_ptr, TCGv_i32)) +static void gen_ne_fop_QF(DisasContext *dc, int rd, int rs, + void (*gen)(TCGv_ptr, TCGv_i32)) { TCGv_i32 src; @@ -1881,8 +1866,8 @@ static inline void gen_ne_fop_QF(DisasContext *dc, int rd, int rs, gen_update_fprs_dirty(dc, QFPREG(rd)); } -static inline void gen_ne_fop_QD(DisasContext *dc, int rd, int rs, - void (*gen)(TCGv_ptr, TCGv_i64)) +static void gen_ne_fop_QD(DisasContext *dc, int rd, int rs, + void (*gen)(TCGv_ptr, TCGv_i64)) { TCGv_i64 src; @@ -2813,7 +2798,7 @@ static void gen_fmovq(DisasContext *dc, DisasCompare *cmp, int rd, int rs) } #ifndef CONFIG_USER_ONLY -static inline void gen_load_trap_state_at_tl(TCGv_ptr r_tsptr, TCGv_env cpu_env) +static void gen_load_trap_state_at_tl(TCGv_ptr r_tsptr, TCGv_env cpu_env) { TCGv_i32 r_tl = tcg_temp_new_i32(); From patchwork Wed Jun 28 11:44:59 2023 Content-Type: text/plain; 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[209.51.188.17]) by mx.google.com with ESMTPS id uc17-20020a05620a6a1100b0075b06bf2f4dsi1916623qkn.159.2023.06.28.04.49.01 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 28 Jun 2023 04:49:01 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@ilande.co.uk header.s=20220518 header.b=zO8zufq5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=ilande.co.uk Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qETdK-0003sC-90; Wed, 28 Jun 2023 07:46:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qETcO-0002gB-5u for qemu-devel@nongnu.org; Wed, 28 Jun 2023 07:46:04 -0400 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qETcJ-00058t-6D for qemu-devel@nongnu.org; Wed, 28 Jun 2023 07:45:50 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=ilande.co.uk; s=20220518; h=Subject:Content-Transfer-Encoding:Content-Type: MIME-Version:References:In-Reply-To:Message-Id:Date:To:From:Sender:Reply-To: Cc:Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=WmsO4TdphjoYdEaQr+/EGzlsRw5mm7MRTDUQrp4kIrg=; b=zO8zufq5dB+Hd6vZ5OULF5twvR brqayWv90YC4GrkmkPL1zklS4TVG9qEE3Y7a9cc0NY5b+KRervkqZ5VdVw6MyLMU0FbCVuq2J7opf x3kXFGe0VNlaDBfa1/McrKTE8jLQPi88J1h3SO9DpNTt9Je48YZLVsAN4V2IZgEEG7zoS5IEjLzTZ FCNCwaKddXXYKwt4EwRXyRM5tmFYPnuntuE3/e/p09KklZLQbgtVpEdHAGNFw5Gu8smPxoY9ArXtq 2B8gw9HDxFI5iFj9twHU5NIYNQ6E7ywg/u/47qjkJCg65reUkKqpXu0Nqc2M6rXqwont7c9zbV4e/ dIhc7bS988bEzYxvuoMwio6kwxe2T9NePiRF6N0LM0bOU3vWRPWFRbD9riAXkRlQ16Ke6Mnnhaw8e jbuOr9B6KAyQ0hCCSoe0+KFE+eFha+3yclbGuYkcTwuMVt2CbuaQ7ZPeq33qQGJuYjjTexItoVXQV SzOR/Df+kY6btAH/dGTcwArmM4rypkaBvAe5zgpmoBytURV7Y1PwkMV3LIopIIEDDW6iZcMhjj0aP K0glhyW0iei35RMd6g+MV52arDH9Z6Mh8qYpMCU9s7jLrA/ItAy3Xq8vg5ZOMhd1no8p03hngN4+w yCADvz9acF5Ca8qOsVU4Jg3VWF1A9S1DaWvcFLuzo=; Received: from host86-130-37-216.range86-130.btcentralplus.com ([86.130.37.216] helo=kentang.home) by mail.ilande.co.uk with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1qETbt-00007c-AW; Wed, 28 Jun 2023 12:45:25 +0100 From: Mark Cave-Ayland To: richard.henderson@linaro.org, qemu-devel@nongnu.org Date: Wed, 28 Jun 2023 12:44:59 +0100 Message-Id: <20230628114504.546265-6-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230628114504.546265-1-mark.cave-ayland@ilande.co.uk> References: <20230628114504.546265-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 86.130.37.216 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PULL 05/10] target/sparc: Introduce DYNAMIC_PC_LOOKUP X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.ilande.co.uk) Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.ilande.co.uk X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson Create a new artificial "next pc" which also indicates that nothing has changed within the cpu state which requires returning to the main loop. Pipe this new value though all pc/npc checks. Do not produce this new value yet. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20230628071202.230991-5-richard.henderson@linaro.org> Signed-off-by: Mark Cave-Ayland --- target/sparc/translate.c | 147 +++++++++++++++++++++++++++------------ 1 file changed, 103 insertions(+), 44 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 1312c3e94d..75aa1a138e 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -37,9 +37,12 @@ #include "exec/helper-info.c.inc" #undef HELPER_H -#define DYNAMIC_PC 1 /* dynamic pc value */ -#define JUMP_PC 2 /* dynamic pc value which takes only two values - according to jump_pc[T2] */ +/* Dynamic PC, must exit to main loop. */ +#define DYNAMIC_PC 1 +/* Dynamic PC, one of two values according to jump_pc[T2]. */ +#define JUMP_PC 2 +/* Dynamic PC, may lookup next TB. */ +#define DYNAMIC_PC_LOOKUP 3 #define DISAS_EXIT DISAS_TARGET_0 @@ -901,22 +904,25 @@ static void gen_branch_n(DisasContext *dc, target_ulong pc1) { target_ulong npc = dc->npc; - if (likely(npc != DYNAMIC_PC)) { + if (npc & 3) { + switch (npc) { + case DYNAMIC_PC: + case DYNAMIC_PC_LOOKUP: + tcg_gen_mov_tl(cpu_pc, cpu_npc); + tcg_gen_addi_tl(cpu_npc, cpu_npc, 4); + tcg_gen_movcond_tl(TCG_COND_NE, cpu_npc, + cpu_cond, tcg_constant_tl(0), + tcg_constant_tl(pc1), cpu_npc); + dc->pc = npc; + break; + default: + g_assert_not_reached(); + } + } else { dc->pc = npc; dc->jump_pc[0] = pc1; dc->jump_pc[1] = npc + 4; dc->npc = JUMP_PC; - } else { - TCGv t, z; - - tcg_gen_mov_tl(cpu_pc, cpu_npc); - - tcg_gen_addi_tl(cpu_npc, cpu_npc, 4); - t = tcg_constant_tl(pc1); - z = tcg_constant_tl(0); - tcg_gen_movcond_tl(TCG_COND_NE, cpu_npc, cpu_cond, z, t, cpu_npc); - - dc->pc = DYNAMIC_PC; } } @@ -941,10 +947,19 @@ static void flush_cond(DisasContext *dc) static void save_npc(DisasContext *dc) { - if (dc->npc == JUMP_PC) { - gen_generic_branch(dc); - dc->npc = DYNAMIC_PC; - } else if (dc->npc != DYNAMIC_PC) { + if (dc->npc & 3) { + switch (dc->npc) { + case JUMP_PC: + gen_generic_branch(dc); + dc->npc = DYNAMIC_PC; + break; + case DYNAMIC_PC: + case DYNAMIC_PC_LOOKUP: + break; + default: + g_assert_not_reached(); + } + } else { tcg_gen_movi_tl(cpu_npc, dc->npc); } } @@ -977,13 +992,21 @@ static void gen_check_align(TCGv addr, int mask) static void gen_mov_pc_npc(DisasContext *dc) { - if (dc->npc == JUMP_PC) { - gen_generic_branch(dc); - tcg_gen_mov_tl(cpu_pc, cpu_npc); - dc->pc = DYNAMIC_PC; - } else if (dc->npc == DYNAMIC_PC) { - tcg_gen_mov_tl(cpu_pc, cpu_npc); - dc->pc = DYNAMIC_PC; + if (dc->npc & 3) { + switch (dc->npc) { + case JUMP_PC: + gen_generic_branch(dc); + tcg_gen_mov_tl(cpu_pc, cpu_npc); + dc->pc = DYNAMIC_PC; + break; + case DYNAMIC_PC: + case DYNAMIC_PC_LOOKUP: + tcg_gen_mov_tl(cpu_pc, cpu_npc); + dc->pc = dc->npc; + break; + default: + g_assert_not_reached(); + } } else { dc->pc = dc->npc; } @@ -5501,13 +5524,21 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) break; } /* default case for non jump instructions */ - if (dc->npc == DYNAMIC_PC) { - dc->pc = DYNAMIC_PC; - gen_op_next_insn(); - } else if (dc->npc == JUMP_PC) { - /* we can do a static jump */ - gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_cond); - dc->base.is_jmp = DISAS_NORETURN; + if (dc->npc & 3) { + switch (dc->npc) { + case DYNAMIC_PC: + case DYNAMIC_PC_LOOKUP: + dc->pc = dc->npc; + gen_op_next_insn(); + break; + case JUMP_PC: + /* we can do a static jump */ + gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_cond); + dc->base.is_jmp = DISAS_NORETURN; + break; + default: + g_assert_not_reached(); + } } else { dc->pc = dc->npc; dc->npc = dc->npc + 4; @@ -5578,13 +5609,23 @@ static void sparc_tr_tb_start(DisasContextBase *db, CPUState *cs) static void sparc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) { DisasContext *dc = container_of(dcbase, DisasContext, base); + target_ulong npc = dc->npc; - if (dc->npc == JUMP_PC) { - assert(dc->jump_pc[1] == dc->pc + 4); - tcg_gen_insn_start(dc->pc, dc->jump_pc[0] | JUMP_PC); - } else { - tcg_gen_insn_start(dc->pc, dc->npc); + if (npc & 3) { + switch (npc) { + case JUMP_PC: + assert(dc->jump_pc[1] == dc->pc + 4); + npc = dc->jump_pc[0] | JUMP_PC; + break; + case DYNAMIC_PC: + case DYNAMIC_PC_LOOKUP: + npc = DYNAMIC_PC; + break; + default: + g_assert_not_reached(); + } } + tcg_gen_insn_start(dc->pc, npc); } static void sparc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) @@ -5608,19 +5649,37 @@ static void sparc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) static void sparc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) { DisasContext *dc = container_of(dcbase, DisasContext, base); + bool may_lookup; switch (dc->base.is_jmp) { case DISAS_NEXT: case DISAS_TOO_MANY: - if (dc->pc != DYNAMIC_PC && - (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) { + if (((dc->pc | dc->npc) & 3) == 0) { /* static PC and NPC: we can use direct chaining */ gen_goto_tb(dc, 0, dc->pc, dc->npc); - } else { - if (dc->pc != DYNAMIC_PC) { - tcg_gen_movi_tl(cpu_pc, dc->pc); + break; + } + + if (dc->pc & 3) { + switch (dc->pc) { + case DYNAMIC_PC_LOOKUP: + may_lookup = true; + break; + case DYNAMIC_PC: + may_lookup = false; + break; + default: + g_assert_not_reached(); } - save_npc(dc); + } else { + tcg_gen_movi_tl(cpu_pc, dc->pc); + may_lookup = true; + } + + save_npc(dc); + if (may_lookup) { + tcg_gen_lookup_and_goto_ptr(); + } else { tcg_gen_exit_tb(NULL, 0); } break; From patchwork Wed Jun 28 11:45:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 697229 Delivered-To: patch@linaro.org Received: by 2002:adf:e885:0:0:0:0:0 with SMTP id d5csp4294363wrm; Wed, 28 Jun 2023 04:46:46 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ66k4A7lDSAaQQafoYi2u7mEfPB0u9FaYE0CrJ+8zL6oJsn5T2Sl6aldZ/d1lnzsqpDySLc X-Received: by 2002:ac8:5881:0:b0:3f6:b151:7db1 with SMTP id t1-20020ac85881000000b003f6b1517db1mr44376331qta.62.1687952805819; Wed, 28 Jun 2023 04:46:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687952805; cv=none; d=google.com; s=arc-20160816; b=cy+JKJ8ZInbA6qRHYrONkXhNBldoKslXMC/gDmOABvh26EzsiXsp/yufMAOmKs+q44 KZQucF6CWKdRMmrhTajdXoTNwpBF0MjFl/9lx937VXGTNc6/dEX5rPZV2FAqzStQNYel BPqwTG8/iWkBbXpL1VujDApIzE1pCPJHX21vzR5amqsNso7hGseeqR8i4shbO6XlRAat 7uYsQylbLHJbnMhjAISkwsb+NM6SKZpYO9qK1Hs9rrhFxpzvLvlPRk/kr8cDZanI6rIK haYqzzSozyEZ6btFGwHTAdR81FAxBFSg7RI0cgrtLVzKW0vZO3mGsbFcm7Y4GmKvB697 d6eQ== ARC-Message-Signature: i=1; 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[209.51.188.17]) by mx.google.com with ESMTPS id w22-20020a05622a135600b003e4d3bae4c6si4489487qtk.739.2023.06.28.04.46.45 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 28 Jun 2023 04:46:45 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@ilande.co.uk header.s=20220518 header.b=aAdkK7e4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=ilande.co.uk Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qETd9-0003X5-Iw; Wed, 28 Jun 2023 07:46:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qETcO-0002gE-6H for qemu-devel@nongnu.org; Wed, 28 Jun 2023 07:46:04 -0400 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qETcK-0005AX-7J for qemu-devel@nongnu.org; Wed, 28 Jun 2023 07:45:51 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=ilande.co.uk; s=20220518; h=Subject:Content-Transfer-Encoding:Content-Type: MIME-Version:References:In-Reply-To:Message-Id:Date:To:From:Sender:Reply-To: Cc:Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=/bMeEkjfg3tpxVE70QjaEvS5dMR3vXSEfAF08boX70Q=; b=aAdkK7e4yMAOUVvTyK/0E8o0XC YFWR9RIOrZYVpn7ZuzB5VxVYFAAjlFDRLXQxwXX+lcbIe/cR3pX+pF5vj0w5SKdxXB7LEeeKralxC B1CG/dbVYb/oIPOyFAsYEj6Cw0k0+6AizNI6XFWK1sZatwvQpluHHRXCXUfKMg22ta3iJ1Ut2EX3X dPk178cFtoqAzVJS8U2ixWlsSWSaMZmAE+cPN9kcgAUcd9SIqT+Gr25PTtAJRk2nbJnnON0aeqctL L7A1j2QchLci1u/YAnv5U5KphGQR0X9MiiTn0yfQMuHa0Tg2dEA1I6jw2gEGxTUy6YL+kYA+fbN2i KSpw+tQEdL5X3666xAuJ/vT1nEh6KfF3je971JM+Gl2hPqWoRcWQbRmxqQKyefR+/jDYQn8ocynkc uvZBNlWBSeEqPdj9/D8C6YRC4gHoacNQ4fwVHaY439Np0rtwi8zEFYUdLr1soiqaBeUhhIV2UNjws ZHNjBX2qnw44lb3ff9cZ49cggzbZFoylkSEPDnVUpGkRngk+1yTEWBnsbqBXuB6p/K5ttEmfLi0Or WPyd/N3KLLac73gkgbgEjHhVTI7Im2uTKN7WhdWgrEKiXiyK0M1plZsfe/vN2SOUo7v9VCZkCYMpj waYFX/1o9/R/mtGK3ARZr1tBrDZzcs1WJKpdOkaRI=; Received: from host86-130-37-216.range86-130.btcentralplus.com ([86.130.37.216] helo=kentang.home) by mail.ilande.co.uk with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1qETbx-00007c-J6; Wed, 28 Jun 2023 12:45:29 +0100 From: Mark Cave-Ayland To: richard.henderson@linaro.org, qemu-devel@nongnu.org Date: Wed, 28 Jun 2023 12:45:00 +0100 Message-Id: <20230628114504.546265-7-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230628114504.546265-1-mark.cave-ayland@ilande.co.uk> References: <20230628114504.546265-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 86.130.37.216 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PULL 06/10] target/sparc: Use DYNAMIC_PC_LOOKUP for conditional branches X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.ilande.co.uk) Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.ilande.co.uk X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson When resolving JUMP_PC, we know this is for a plain branch with no other side effects. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson Message-Id: <20230628071202.230991-6-richard.henderson@linaro.org> Signed-off-by: Mark Cave-Ayland --- target/sparc/translate.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 75aa1a138e..d7b569d910 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -941,7 +941,7 @@ static void flush_cond(DisasContext *dc) { if (dc->npc == JUMP_PC) { gen_generic_branch(dc); - dc->npc = DYNAMIC_PC; + dc->npc = DYNAMIC_PC_LOOKUP; } } @@ -951,7 +951,7 @@ static void save_npc(DisasContext *dc) switch (dc->npc) { case JUMP_PC: gen_generic_branch(dc); - dc->npc = DYNAMIC_PC; + dc->npc = DYNAMIC_PC_LOOKUP; break; case DYNAMIC_PC: case DYNAMIC_PC_LOOKUP: @@ -997,7 +997,7 @@ static void gen_mov_pc_npc(DisasContext *dc) case JUMP_PC: gen_generic_branch(dc); tcg_gen_mov_tl(cpu_pc, cpu_npc); - dc->pc = DYNAMIC_PC; + dc->pc = DYNAMIC_PC_LOOKUP; break; case DYNAMIC_PC: case DYNAMIC_PC_LOOKUP: From patchwork Wed Jun 28 11:45:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 697231 Delivered-To: patch@linaro.org Received: by 2002:adf:e885:0:0:0:0:0 with SMTP id d5csp4295034wrm; Wed, 28 Jun 2023 04:48:43 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5mplelYZ9S/0zp76vcgdAn+zWVjz8HYyfdkQFYotS/oHV069tmgeDhPfdUs6OXn1YM60IQ X-Received: by 2002:a05:620a:e92:b0:767:90a:ae9e with SMTP id w18-20020a05620a0e9200b00767090aae9emr5028071qkm.65.1687952923254; Wed, 28 Jun 2023 04:48:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687952923; cv=none; d=google.com; s=arc-20160816; b=nNoG/r9TGjGnOHeNezK73XtMxm1fqCC6BdWAMxGSYsNk4rjfVltpIPGyS1thJtyCTe PX/MT2xLw+gnMbVj61soQbiqlPAFow8AVEn4kU2ItBd9ixJxmHsOM/91gshyXDl+jgs2 OwpYSrgdKGMhyImeI/VOiu33YpC5cLbaBtnqbDeR+CQc5IhMDJcDOb6N1/4CqPTIq1L6 MD7sRIw7cWczeVLFHenNTBtFcRRo6UH+VJzeOF+z80ao8vCsoHI5PaKmtf17wen+mzaf bJKjcFMo+8nIdd6L4ieJ33Meo/uRaHuvKnH2lWCGte4Z43b/Um2vgLFofHk84gJ2folK b4aw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=puy44AvdZMQUEA3aEHuBFbJ1B7IKOJW00RpQVJ7zYyE=; fh=dxNoli/Xs5PJEU4/5g3muAZqP4q86W456+YpDLBdAUw=; b=lWs3cX9Omu+qndfHUU664LWcPGziWiWQ8gwA4Itb5v1nJtTLDTLxulsWFQPcHL8BV2 sTKDtdT61u3VOkx43dYp+yxF9BnsBC03o+QJsFdqPDnzQRaywfOWX8GXbE8dFOqQ14Ym TntYXV40FOE9r7vvSFE94AORTrS6R7s3V1dipo2WU8LRQjdvrPBf1s6TMppgu4q1f8qi y85ia62VI+OkiDgfaRpeoiq/V2Yy83hotgW2DWShsBADD9rI+oAXwHibabh0meUZMf5h XGJxp+Si7CXjhqzWw03eW8nixefi3PrED0/05jEhahKtHeYZaxijWggO7V2z7QwlQoyU I2Wg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@ilande.co.uk header.s=20220518 header.b=hnnQhb+m; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=ilande.co.uk Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id i4-20020a05620a248400b0075d3abe966asi4615486qkn.440.2023.06.28.04.48.43 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 28 Jun 2023 04:48:43 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@ilande.co.uk header.s=20220518 header.b=hnnQhb+m; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=ilande.co.uk Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qETdK-00040X-KW; Wed, 28 Jun 2023 07:46:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qETcM-0002g8-Ku for qemu-devel@nongnu.org; Wed, 28 Jun 2023 07:46:04 -0400 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qETcJ-0005BW-6z for qemu-devel@nongnu.org; Wed, 28 Jun 2023 07:45:50 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=ilande.co.uk; s=20220518; h=Subject:Content-Transfer-Encoding:Content-Type: MIME-Version:References:In-Reply-To:Message-Id:Date:To:From:Sender:Reply-To: Cc:Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=puy44AvdZMQUEA3aEHuBFbJ1B7IKOJW00RpQVJ7zYyE=; b=hnnQhb+mFJjUGNwrPIDeToupEM YYR5SHaA3zcFfUUYrzw0qydAIqp/FyjIgrEfFb2tNFeJ2eWbRzaNn6TjO9xr2OaGTN6IQ17e7FUBu NZuTRhp/APe4vFI9LUfQwAk70FZVS46HFdC7HAETxVKMFgCrRrytwWb6KvoqILW9nthsRoz/d3mZU BD2As80vPf/W0in7xqN0MvHjOwvfSP/SFligdnaAT0snYB1MmsqjNeVaTKFzcdwpeag1YGJfnEZ9W oc4pRItLnh7pnybzuQl27m9SMc/Yd7PYxtEvxYk7vRzisnvsacDOkLbXsYJRILsJF2YtHWPyJKyru WFfkxWP5Ba3eSjX1MCsSRx2Bq6LzlV8zR8F2v4l/xdyWg5FatEI6RmjqWas8J0DVijdU62SMnHKZg /7zZK/EwS/AgxZQHIQ3PJYDHLPPE5J/JzzPKdBAJqdS1B2OAAWWpReB5lv/If16tL80e7SZefAX/h ByzAx9aOvFOOGr6UaasMTDppfGwVXWSfPPE0Ig2NS3ZJTeJ3RzaTkQY0nR7ljCnDHyybll8XW+Ewi C+tcUOn7JKdTV0Ip3jQJeJx5Q+Llqn25phg4h/+d/XStdL7RZOSXUDI8bpDtFRmLGUwY0EnIP5zn4 tr1nddMJ8bmXkF9Pxxaj09ELWS4ZODloPn7BHWqwQ=; Received: from host86-130-37-216.range86-130.btcentralplus.com ([86.130.37.216] helo=kentang.home) by mail.ilande.co.uk with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1qETc1-00007c-Ov; Wed, 28 Jun 2023 12:45:31 +0100 From: Mark Cave-Ayland To: richard.henderson@linaro.org, qemu-devel@nongnu.org Date: Wed, 28 Jun 2023 12:45:01 +0100 Message-Id: <20230628114504.546265-8-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230628114504.546265-1-mark.cave-ayland@ilande.co.uk> References: <20230628114504.546265-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 86.130.37.216 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PULL 07/10] target/sparc: Use DYNAMIC_PC_LOOKUP for JMPL X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.ilande.co.uk) Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.ilande.co.uk X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson This is for a plain indirect branch with no other side effects. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson Message-Id: <20230628071202.230991-7-richard.henderson@linaro.org> Signed-off-by: Mark Cave-Ayland --- target/sparc/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index d7b569d910..17afe98523 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -5058,7 +5058,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) gen_check_align(cpu_tmp0, 3); gen_address_mask(dc, cpu_tmp0); tcg_gen_mov_tl(cpu_npc, cpu_tmp0); - dc->npc = DYNAMIC_PC; + dc->npc = DYNAMIC_PC_LOOKUP; } goto jmp_insn; #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64) From patchwork Wed Jun 28 11:45:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 697230 Delivered-To: patch@linaro.org Received: by 2002:adf:e885:0:0:0:0:0 with SMTP id d5csp4294689wrm; Wed, 28 Jun 2023 04:47:44 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6fln48M+eLzBVQY27WcomQeNxAAHdZbluyX5+IWFmCSnPFlKsZbZYjaF922yKJITsVCxVr X-Received: by 2002:a05:6214:508b:b0:632:2649:d719 with SMTP id kk11-20020a056214508b00b006322649d719mr18505270qvb.30.1687952864355; Wed, 28 Jun 2023 04:47:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687952864; cv=none; d=google.com; s=arc-20160816; b=cidexDAfcweAjk2PDizdYxPiL4QdBAz+zdk047yZeZOoWMmmqxSLtMHt99gGiDS/Ay 6w8o5hHYyGxfquYsnHgeHKhKikvvIk+e6mdApPxVGQTA/eXpS4pAmCTEyN4w8BdXOnMD Jwu6e5QAySeUpRTSuql1Jgy5FihEBh07rksB0UYT/yb3/qhUrqMIoKt8r6oif8wKZeAx gEQM0Q8TPMeXgfxpWgBo5jZQoIG+jBul3HzWfuf5Pdd5HjvbGc8G3j8qpsJAOJIx1H0B qWcYSQP4ttkyG0MeaNW5VzOhQtG5l41bIMzioXe4hcWUVu9f/0Ed5GQdphO7Nd04iTxx Fehg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=mZEYH3EO9Ckj3bPrCqjVynHhC4HScMvpjZTuEQOMNYE=; fh=dxNoli/Xs5PJEU4/5g3muAZqP4q86W456+YpDLBdAUw=; b=jnFqKUmdtu/9akzQAuIbaQn0egAV8qe4/AadESbeTKhgZKNzaMkveMAcdtkSM+o0RG yycsyJdqnqlowxuWIgG1tZuzdoMgfH4dOZwV6h8Hwd6UWUYQGipmea3PKflAEX8XyPN5 ibkcPNis/X2AJrvZt9IG7NlBx/ZRN/Mr8yVtiaI7Ka/60BNmTDV4FFbfMoLUr59aO4Gj CWmt4YiWFw1ejTwQeVAlGRP7sQBMHeXux1zU6ctwXZmiNtGxwlTqEKijmF8QFOcYIwrI B+Yh1B5S8zkr4rYo9WaJo2t57OqFOqiAv9m5RV8OdcS3z4UCClh+TBhhzPCM9/jqgKGR ejIQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@ilande.co.uk header.s=20220518 header.b=r63f37dr; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=ilande.co.uk Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id q2-20020a05621419e200b006259adfabbcsi4683805qvc.283.2023.06.28.04.47.44 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 28 Jun 2023 04:47:44 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@ilande.co.uk header.s=20220518 header.b=r63f37dr; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=ilande.co.uk Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qETdU-0004P2-5j; Wed, 28 Jun 2023 07:47:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qETcO-0002gC-5y for qemu-devel@nongnu.org; Wed, 28 Jun 2023 07:46:04 -0400 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qETcL-0005D5-1i for qemu-devel@nongnu.org; Wed, 28 Jun 2023 07:45:51 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=ilande.co.uk; s=20220518; h=Subject:Content-Transfer-Encoding:Content-Type: MIME-Version:References:In-Reply-To:Message-Id:Date:To:From:Sender:Reply-To: Cc:Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=mZEYH3EO9Ckj3bPrCqjVynHhC4HScMvpjZTuEQOMNYE=; b=r63f37drXS2+xIsASLrOmjNzBL wYxj23TD6rUpF2rak4g6CMwGGPAmqRZ3Sh4ot7uFT+EFUeQ+qSENCXkWTpd7s8WHo3sdMu0hkJJWF KAEQ4HF+PnpVpKTKHPRzryQ47A8iifnP5urDJqRVrTLXAV82ahjTYvrVBzgAROK6vrP2Nt4wdgZQQ ttLOiGF8GOewsMYF+FVXSfDhWxvKy8eWsB6Y5xZMebSHQQXm+R0qxQYRVY3CR5a6+VbVCBczIOVQG duJmeRLq9MfdGzYuGG0PNTJoIRFWQ06qc8uFqMs/Lb07sVaxvlSy/qQCsAVOjq8CZR3qj/bo6BAP1 YzrlhG53rKMwEYVUT1rl8IBxg5PCAJxGnM2iRtDVI7PqnrhpDbnW0vCWKKlu4lHAHpoJ2CHXSpzz9 ud7FkvnpHAAQji9wuL4qtdZcREKUQqoH4rJjqNoMrjKS/wFAcX/xvaKmIJm7jRVY2twsXBS3zrNSY ktnux17LZBY6sVNaxIPiVkKkKItrhojmLv01dB6EWHRoyqp3B453nPi+Qsh3opJd+PpdgDH+swCqO MZVQQqFbncG3+yxgFR0KulWk1B3xJ7HnTc7PXqL7OsUJmeujRRY7mM8sHDJ4b9j2zdwek8O4iX9UO tusY0Vu/4xn0xk4GB9C6rGlukBaiWG0XKQocLwlsg=; Received: from host86-130-37-216.range86-130.btcentralplus.com ([86.130.37.216] helo=kentang.home) by mail.ilande.co.uk with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1qETc3-00007c-P0; Wed, 28 Jun 2023 12:45:35 +0100 From: Mark Cave-Ayland To: richard.henderson@linaro.org, qemu-devel@nongnu.org Date: Wed, 28 Jun 2023 12:45:02 +0100 Message-Id: <20230628114504.546265-9-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230628114504.546265-1-mark.cave-ayland@ilande.co.uk> References: <20230628114504.546265-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 86.130.37.216 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PULL 08/10] target/sparc: Use DYNAMIC_PC_LOOKUP for v9 RETURN X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.ilande.co.uk) Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.ilande.co.uk X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson After the register window unwind, this is for a plain indirect branch with no further side effects. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson Message-Id: <20230628071202.230991-8-richard.henderson@linaro.org> Signed-off-by: Mark Cave-Ayland --- target/sparc/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 17afe98523..9148e33283 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -5029,7 +5029,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) gen_mov_pc_npc(dc); gen_check_align(cpu_tmp0, 3); tcg_gen_mov_tl(cpu_npc, cpu_tmp0); - dc->npc = DYNAMIC_PC; + dc->npc = DYNAMIC_PC_LOOKUP; goto jmp_insn; #endif } else { From patchwork Wed Jun 28 11:45:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 697233 Delivered-To: patch@linaro.org Received: by 2002:adf:e885:0:0:0:0:0 with SMTP id d5csp4295144wrm; Wed, 28 Jun 2023 04:48:58 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7rkMGQMhKWpHEGk+TmjRBfOzILePUO0MKWvd2VZ6paS0JKnMvY+duFeLy4RGp42C1qkkwS X-Received: by 2002:a05:620a:3902:b0:765:70cf:d7a4 with SMTP id qr2-20020a05620a390200b0076570cfd7a4mr13024321qkn.71.1687952938719; Wed, 28 Jun 2023 04:48:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687952938; cv=none; d=google.com; s=arc-20160816; b=snxXth37KWMUHVQtBq1EutHpxyPFI6o/0DPdRVL03mt539pDg1i3oXqpFYyVdVwsBK KHVT8pJVuXX5ch5A3AbrbwXm+pae8XzCJnuObEyCjL/UONCpjKn2SWdzrfo5y7/xehl/ zT0iVyGiU3yjJ3jUFRP61YPQOPVUkb/QGVQnTLZoKnbQAzB8LXgzd2kC8eKcJ1xt7ssT OsUxS4Q9deftRUIOHCAAlvdbJtOkNuW6MdXIg2d8Ui1CVlZuqlRflrxHk7UuWBGJ8z4S Z4ypBFK0JePGEvLYrf2BFB/EilyzKtMDpg8YQ5DbJ2O0FJpGOJoYqRyS9pblEisLf2ed qaoA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=FV+chXvjmNEXKyHiXB6vsfOn/aoT2Gsa6mwo/x6dy/A=; fh=dxNoli/Xs5PJEU4/5g3muAZqP4q86W456+YpDLBdAUw=; b=TsfaHT8kw+3RlwQU7Busr4PNGtXEgm2bgQj1AA0wZeya62V6dPM4b3SRUwqMKpd325 ORr+1dFBFi8yIo3fVDT30sXsHMVhpALbMbmUjeqAlWNP0/+Ry1Te4qRlRbh9UmqCfYmw eoGFCrFdl8+IOSEX1hZN5YeH+iswFZMKLTGUX3YZKJrGSAXxMIKzTFyBnjwnrLmt2NWe UpsUSIIhiVDStjrZBJKagyMbzNHwy+l2hSWSjZd+Xat7nUENFHwaitAmXwCg0V9jlt/t 4dZmlvsiQCnCyfLSj6TMWCQkoTuyvO2ClzYsIwkyk5qBOVKC31IVJ+qELdtUyHXyXUON TzCQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@ilande.co.uk header.s=20220518 header.b="k44+/gkv"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=ilande.co.uk Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id bp10-20020a05620a458a00b0075dabfdefb4si4637964qkb.331.2023.06.28.04.48.58 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 28 Jun 2023 04:48:58 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@ilande.co.uk header.s=20220518 header.b="k44+/gkv"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=ilande.co.uk Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qETd7-0003KE-A4; Wed, 28 Jun 2023 07:46:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qETcO-0002gD-62 for qemu-devel@nongnu.org; Wed, 28 Jun 2023 07:46:04 -0400 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qETcL-0005F5-Hp for qemu-devel@nongnu.org; Wed, 28 Jun 2023 07:45:51 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=ilande.co.uk; s=20220518; h=Subject:Content-Transfer-Encoding:Content-Type: MIME-Version:References:In-Reply-To:Message-Id:Date:To:From:Sender:Reply-To: Cc:Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=FV+chXvjmNEXKyHiXB6vsfOn/aoT2Gsa6mwo/x6dy/A=; b=k44+/gkvrg96DyXI7wEj/HPu+g MNgtOi8+sSfBhrniLJEdevSh/Vo6qH3DdK0m7JJEC6TC9FaOTqoiir65Jgz1secpFALo8xJiU0Tfv muqHVAQYqupxioVh7Kpkp3i9YlMVf/f2wvyhbBRjFkQuSiHy2bzUaGCz94gahIWYhoMEzwTOGTZT+ 6swtuAXVQD5LDvc7pIivNSK/ahSa6cXnNIFYCaxl4W9thaZPF+epYrdsk6Aunb829aKY1xtMT0/W8 bYLkgio+Qc3cIB4KUZ1E54F4v9UgtCztll+RGpu06xhvhF1ww3KGk5wnrmFCBA+T4u5OnE6PoPNzl UoV93tw+sqqSQUKVHQhaFiVg4LYCfuS06cJSKbCerQ/JYnJvfNZUkKFmUItYy/cqi/qAtLZKLjBNn Tjwr6GfrHjw8upDgXu9NdSVmyqtvd9I/yAg9Q6b/koKHw4ncimEeoq+17czQ1vQ4qvbTiP2orv3vW y01d0gFskWDjXiGHuWX5mtLDg/e+bugG1wXFnmJhJopzp5spajcku+OTF3np/BWlj2xHx/SmZsKpT otGh0VUBBQdD51ZzTMcSmCpnQHKZ88Fgtoae7Lf/A4L3eLXP7io0/oyE3QtUm2GupZ7urNSQL/8Jo cVAd98olF9aD3wy5xoZ+kBxvV5COBGJNaeIZ3ENvc=; Received: from host86-130-37-216.range86-130.btcentralplus.com ([86.130.37.216] helo=kentang.home) by mail.ilande.co.uk with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1qETc7-00007c-En; Wed, 28 Jun 2023 12:45:39 +0100 From: Mark Cave-Ayland To: richard.henderson@linaro.org, qemu-devel@nongnu.org Date: Wed, 28 Jun 2023 12:45:03 +0100 Message-Id: <20230628114504.546265-10-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230628114504.546265-1-mark.cave-ayland@ilande.co.uk> References: <20230628114504.546265-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 86.130.37.216 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PULL 09/10] target/sparc: Use tcg_gen_lookup_and_goto_ptr for v9 WRASI X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.ilande.co.uk) Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.ilande.co.uk X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson We incorporate %asi into tb->flags so that we may generate inline code for the many ASIs for which it is easy to do so. Setting %asi is common for e.g. memcpy and memset performing block copy and clear, so it is worth noticing this case. We must end the TB but do not need to return to the main loop. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson Message-Id: <20230628071202.230991-9-richard.henderson@linaro.org> Signed-off-by: Mark Cave-Ayland --- target/sparc/translate.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 9148e33283..bd877a5e4a 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -4147,10 +4147,14 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xff); tcg_gen_st32_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, asi)); - /* End TB to notice changed ASI. */ + /* + * End TB to notice changed ASI. + * TODO: Could notice src1 = %g0 and IS_IMM, + * update DisasContext and not exit the TB. + */ save_state(dc); gen_op_next_insn(); - tcg_gen_exit_tb(NULL, 0); + tcg_gen_lookup_and_goto_ptr(); dc->base.is_jmp = DISAS_NORETURN; break; case 0x6: /* V9 wrfprs */