From patchwork Thu Jul 6 13:24:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 699592 Delivered-To: patch@linaro.org Received: by 2002:adf:fcc5:0:0:0:0:0 with SMTP id f5csp3311987wrs; Thu, 6 Jul 2023 06:26:29 -0700 (PDT) X-Google-Smtp-Source: APBJJlGEwQhKcFiA/q/ghbbxpxE6m9kJystu+RJBwClGEIH/Ve3rDAYdUx+h/zGIou8QaGRTP1xL X-Received: by 2002:a37:f715:0:b0:767:58ed:593a with SMTP id q21-20020a37f715000000b0076758ed593amr1509337qkj.78.1688649989339; Thu, 06 Jul 2023 06:26:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1688649989; cv=none; d=google.com; s=arc-20160816; b=lwEiQBiQlqm/KW9mK6XrlxZSdcUSQWwNmFX8O/NUzpcAVX6qG5pF1+re0BodNs7nwp MhheirYcrqfeI3xf8vm6UlDtzcnutPQrtbC4cubryk9MxLqJ3wnj3NxxIW3Hs735qDlT vlPXQhgd/Ud25nx4LeORy5f4p4vjYvIPCPmBmrgpJNy1ra3xMVcPVc05DH5PPM2PQIm1 8KKLfji7s6GAmN5tn3/vIfVfTxevu50DXa7FsfhTZMKFt/XkKSXE3jBXfxlJY57dBPmy xaZmdEwRmz9/NY0efBhHtZDIq3jaqgxgsjEpiW+dm0NmFLWzQmGzExmm25rT2b9DG2hp bYxw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=woUU+HiOTdfeWxIkByv1Ka1J61xMATqCD7GSJSY7c+4=; fh=bFDrUYhlTVi/QyetgXx/byg2+yO/22Hp9SjwoefyKLk=; b=vJDUtc+IDKTydpNuXqHjDsqnPoeGdhUVtnzDlzFiSS9IHstu/H8w/elzrfH0j5SGFG u705VQB1QNqxg5+fJmvdOLgo5KtH1OhDcOUYfHD+u7LtmaK2Qyo+BnCuIhibpbabshXp cJ9mykulA9Q0vT7yxnDFHmH3ZdJAseFx4IpartL/xSl0bSysPEwOz5DgMCu9AjQFOCC9 j/UR8fwfQyLJq1PPtZ873M7LzDFj4D6+otGbYe5z1qK3F+F48MOdW2eefojqQHWiEhQQ pyMn3/AHmGmcrJPBJZ76COnsIUcOV2IvN29rBaqriRtPtpOOQQv3XqnggohdimQZHsnO aBpg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=nwqia1cC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id h10-20020a05620a13ea00b0075ca93fd907si1013929qkl.371.2023.07.06.06.26.29 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 06 Jul 2023 06:26:29 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=nwqia1cC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qHOzA-0004mL-L5; Thu, 06 Jul 2023 09:25:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qHOz7-0004lj-FF for qemu-devel@nongnu.org; Thu, 06 Jul 2023 09:25:25 -0400 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qHOz0-0000qU-SC for qemu-devel@nongnu.org; Thu, 06 Jul 2023 09:25:21 -0400 Received: by mail-wr1-x430.google.com with SMTP id ffacd0b85a97d-3142970df44so595722f8f.3 for ; Thu, 06 Jul 2023 06:25:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1688649914; x=1691241914; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=woUU+HiOTdfeWxIkByv1Ka1J61xMATqCD7GSJSY7c+4=; b=nwqia1cCeC72BqRokDx9wfzmBeNWi9/RU7p3TkupwCGtXbvTTsfubW5tQpjbb+lNHX WvKtKXUgGuHQPZQT0Wohrn/1OqdXiSQDK95Q5dPYTdNv0EEtocZbLbvjDl1dwVLFSwO/ LO+AMIBLTOntx4NAmPUBwsKczyEZPqVZhiaAKoavfUAYYQvYViP2wutMCXpLE8UYz/aY Bvd1WLqV/+VVBhS8jYZ10fcHxkV+AIfLr3FPLBj+tJlPoO1FPLOZoRA0D9i1abJ1797c XL4fB7hgZJzQP6dlg09V1Ml+WZcxB64eGZgoeUTgywFzV/Gur3/c6kX1ircwJFik6c5X jEQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688649915; x=1691241915; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=woUU+HiOTdfeWxIkByv1Ka1J61xMATqCD7GSJSY7c+4=; b=ltpeWR/C6ydF5U5M6bUlpFVZ+fvyS9zr5apIgWpzau1cJZJDO4IRwpKCde4qXAUmV0 W2ZhkzXk4XHp61PkezMpIxBMw7R8uiH30WJh99mG6k3SqBe3uF5WP1At2regXIJ6+1yO MVXVBlFEXPfm2qMJetvjmJB/kZVAFzfn1ahvAwy1wpjAVYNoaN1jly4/yccwhGKRrvJ4 I92NJpS0EMCYXkLVCc/7LzXssViJfnawG/kGuvSJrjtEjS7ngjw2d8Y4HG+OUQGMA6f6 AIQNMqZ3Z4T87ujblgd8IceO5tBW7c1fY4t+kJBmCjLOiKKsP3IuqZB43uZlkSCRFO9E kwPw== X-Gm-Message-State: ABy/qLb/FRCs5ooSXm/N4Q3u4osJTonIZdXdZ7Bkrgk7aJsR44vtUUbl 6ST2sgH4cZ/hCNelgAOKpj6mygRpVQagwdPoevs= X-Received: by 2002:adf:e803:0:b0:314:11ea:480d with SMTP id o3-20020adfe803000000b0031411ea480dmr1455520wrm.9.1688649914726; Thu, 06 Jul 2023 06:25:14 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id s15-20020a5d510f000000b00304adbeeabbsm1856170wrt.99.2023.07.06.06.25.14 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Jul 2023 06:25:14 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/14] target/arm: Add raw_writes ops for register whose write induce TLB maintenance Date: Thu, 6 Jul 2023 14:24:59 +0100 Message-Id: <20230706132512.3534397-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230706132512.3534397-1-peter.maydell@linaro.org> References: <20230706132512.3534397-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Eric Auger Some registers whose 'cooked' writefns induce TLB maintenance do not have raw_writefn ops defined. If only the writefn ops is set (ie. no raw_writefn is provided), it is assumed the cooked also work as the raw one. For those registers it is not obvious the tlb_flush works on KVM mode so better/safer setting the raw write. Signed-off-by: Eric Auger Suggested-by: Peter Maydell Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/helper.c | 23 +++++++++++++---------- 1 file changed, 13 insertions(+), 10 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index d08c058e424..a0b84efab52 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4189,14 +4189,14 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = { .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0, .access = PL1_RW, .accessfn = access_tvm_trvm, .fgt = FGT_TTBR0_EL1, - .writefn = vmsa_ttbr_write, .resetvalue = 0, + .writefn = vmsa_ttbr_write, .resetvalue = 0, .raw_writefn = raw_write, .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s), offsetof(CPUARMState, cp15.ttbr0_ns) } }, { .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 1, .access = PL1_RW, .accessfn = access_tvm_trvm, .fgt = FGT_TTBR1_EL1, - .writefn = vmsa_ttbr_write, .resetvalue = 0, + .writefn = vmsa_ttbr_write, .resetvalue = 0, .raw_writefn = raw_write, .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s), offsetof(CPUARMState, cp15.ttbr1_ns) } }, { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64, @@ -4456,13 +4456,13 @@ static const ARMCPRegInfo lpae_cp_reginfo[] = { .type = ARM_CP_64BIT | ARM_CP_ALIAS, .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s), offsetof(CPUARMState, cp15.ttbr0_ns) }, - .writefn = vmsa_ttbr_write, }, + .writefn = vmsa_ttbr_write, .raw_writefn = raw_write }, { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1, .access = PL1_RW, .accessfn = access_tvm_trvm, .type = ARM_CP_64BIT | ARM_CP_ALIAS, .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s), offsetof(CPUARMState, cp15.ttbr1_ns) }, - .writefn = vmsa_ttbr_write, }, + .writefn = vmsa_ttbr_write, .raw_writefn = raw_write }, }; static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri) @@ -5911,7 +5911,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { .type = ARM_CP_IO, .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2), - .writefn = hcr_write }, + .writefn = hcr_write, .raw_writefn = raw_write }, { .name = "HCR", .state = ARM_CP_STATE_AA32, .type = ARM_CP_ALIAS | ARM_CP_IO, .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, @@ -5983,6 +5983,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2, .access = PL2_RW, .writefn = vmsa_tcr_el12_write, + .raw_writefn = raw_write, .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) }, { .name = "VTCR", .state = ARM_CP_STATE_AA32, .cp = 15, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2, @@ -5999,10 +6000,10 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { .type = ARM_CP_64BIT | ARM_CP_ALIAS, .access = PL2_RW, .accessfn = access_el3_aa32ns, .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2), - .writefn = vttbr_write }, + .writefn = vttbr_write, .raw_writefn = raw_write }, { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0, - .access = PL2_RW, .writefn = vttbr_write, + .access = PL2_RW, .writefn = vttbr_write, .raw_writefn = raw_write, .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2) }, { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0, @@ -6014,7 +6015,8 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[2]) }, { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0, - .access = PL2_RW, .resetvalue = 0, .writefn = vmsa_tcr_ttbr_el2_write, + .access = PL2_RW, .resetvalue = 0, + .writefn = vmsa_tcr_ttbr_el2_write, .raw_writefn = raw_write, .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) }, { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2, .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS, @@ -6201,12 +6203,12 @@ static const ARMCPRegInfo el3_cp_reginfo[] = { { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0, .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3), - .resetfn = scr_reset, .writefn = scr_write }, + .resetfn = scr_reset, .writefn = scr_write, .raw_writefn = raw_write }, { .name = "SCR", .type = ARM_CP_ALIAS | ARM_CP_NEWEL, .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0, .access = PL1_RW, .accessfn = access_trap_aa32s_el1, .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3), - .writefn = scr_write }, + .writefn = scr_write, .raw_writefn = raw_write }, { .name = "SDER32_EL3", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 1, .access = PL3_RW, .resetvalue = 0, @@ -7927,6 +7929,7 @@ static const ARMCPRegInfo vhe_reginfo[] = { { .name = "TTBR1_EL2", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 1, .access = PL2_RW, .writefn = vmsa_tcr_ttbr_el2_write, + .raw_writefn = raw_write, .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el[2]) }, #ifndef CONFIG_USER_ONLY { .name = "CNTHV_CVAL_EL2", .state = ARM_CP_STATE_AA64, From patchwork Thu Jul 6 13:25:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 699589 Delivered-To: patch@linaro.org Received: by 2002:adf:fcc5:0:0:0:0:0 with SMTP id f5csp3311623wrs; Thu, 6 Jul 2023 06:25:35 -0700 (PDT) X-Google-Smtp-Source: APBJJlGVtjufRTUNzC5ov26eODBTvwnMTV1TR1uhRqWNBiFJj6I6y/dJlUIL/3nVdawt89kBt9r9 X-Received: by 2002:a05:622a:11c9:b0:3eb:1512:91c5 with SMTP id n9-20020a05622a11c900b003eb151291c5mr2458370qtk.12.1688649935372; Thu, 06 Jul 2023 06:25:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1688649935; cv=none; d=google.com; s=arc-20160816; b=B7Wpco2w69D0IFvv7B5p3ktSTVTlQDlOCp5Gnmc0UW6nm+tzlmjIIUlSF+fxCSrnbs czwiQUN2A6dSOeq/f+mg87FRKwIJ9en2XfeAu1LqqdxjBF4dX5xI0ktKSR7S+CY4feSO tS0/u3UNFhFDOJQV26ntQLRyqlE0r/z1dcalqY6NlF+8GA+j53TtaXVvW0ZDTAOJAlDD 147oIY3D4AmMHgS/cF5fsm0Yj5/aLZ/Srd1tWboAjzr4ddkRCUl6Vxmm+7X4ofkmtbH2 F1e250UkFNkEZhJUSdvT1MHQ3aQuknZ0oB0f9ndsteihAHTvj2R6xY0minjEX7FzrRu7 IMww== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=xgCaPGnXl46UU9A6jcwSSpnZq6M2JkIzMN4VboZNQHE=; fh=bFDrUYhlTVi/QyetgXx/byg2+yO/22Hp9SjwoefyKLk=; b=i1zZJRD7a9Kw+TXYk1rpxjsms5evgDnXydMC/31PkIuVqDddbLPDGTKxOGf3aDWK9m cgSi0eh1Y5ZpAj9afS7s1PhbQLKal0Nu2nP+nY8Wgh4HnR0r4H2Np4w0iRxlBKNHjKc8 Tg50UwYJPHHGOVIzWBa8yEDOQjxcw9a5akO4pHBSS4DGD3LQWh07Wu9cDBXllR+TfyuS dLH22H7Q0hlkJSJQ+E1Se2EjBh2Gcx0HnjH2CA7SzpCvs0YOsGugfRmO+R7TwLYBy05i /tMCEdizL6DISOpKj2i/oK8klaGo3lXYFBpM2lNKEsWyxlN/gDTlaUPSECkv9k6oQdW3 Al2A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Jfs4Q7ue; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id z1-20020ac87f81000000b003f548ca984asi884430qtj.604.2023.07.06.06.25.35 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 06 Jul 2023 06:25:35 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Jfs4Q7ue; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qHOz9-0004mE-H4; Thu, 06 Jul 2023 09:25:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qHOz7-0004lk-FB for qemu-devel@nongnu.org; Thu, 06 Jul 2023 09:25:25 -0400 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qHOz0-0000qk-Ur for qemu-devel@nongnu.org; Thu, 06 Jul 2023 09:25:22 -0400 Received: by mail-wm1-x336.google.com with SMTP id 5b1f17b1804b1-3fbac8b01b3so16590335e9.1 for ; Thu, 06 Jul 2023 06:25:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1688649915; x=1691241915; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=xgCaPGnXl46UU9A6jcwSSpnZq6M2JkIzMN4VboZNQHE=; b=Jfs4Q7ueOgzHMHxFvv61dJi4FzmQY3FW+IWCeM5qD/EMEd4s3DTllYNounuZmSKkuO A6BqG7kKAZm8huOToNBnLs+xEfjN3we8u3mviCVqDwyq/Y3aj4F6HtPLuBDAiX6IOAUw ffKRYFKdIoQ4EWx+OHeOvOgzXaq1CKcLbaCVobTY64UyMERynLWTkIWzirbsW/QcD/+s 5WiKIzepxSNCqFVh802P6xp31fgk2Qropb411ZP0Z22CO/yXpqsaqR0WFzwXdqPfzCSp gZstJh1m9SGCtVg59tYTtoDs2Ny6l4FmyWwMEmXvoLiSJBm08efCpjx1KB/4CTUgO/xu G0IQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688649915; x=1691241915; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xgCaPGnXl46UU9A6jcwSSpnZq6M2JkIzMN4VboZNQHE=; b=C3O+mKD74NLQsoz8GsSLSiGn0FrCd5Ty5WZ50VH9t1MByDQkRXPVeOsx0jz905HATh 6FJGy9dZ7RuoAZAQfJIzGa1d8p4HZmGtMeeslw7yC6minu205sn3TM/wK6P+G1t2ih2x tihuZscfb4FmAFznDhvqMAfuxLDVYyE6yYfSxD844CPpd2nEgpdbnl5DB1XAyrZiYuJB 7DWfXXPzkLOlHxDm6RJ1h4xnhCVPketS5RmKHworUYtd++DKzk4/Y1CT/4aL1ztEZnEX vTlz98/T+mzMYvIPeRWkhEOOlNUFoW415WFssnHuM1kaJADBIVUkLIRn5RlP1BIRDbPH AfZA== X-Gm-Message-State: ABy/qLYdv0uuPmPI38AoFUBzxnqZVoZnvmxV2H/kHzMVSMPcm3QlYkZX vvdgtQrDbYRqPt8Oj8A/s9y4ta+owPz9yrdv3KI= X-Received: by 2002:adf:f589:0:b0:314:3a9a:d70e with SMTP id f9-20020adff589000000b003143a9ad70emr5032056wro.11.1688649915175; Thu, 06 Jul 2023 06:25:15 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id s15-20020a5d510f000000b00304adbeeabbsm1856170wrt.99.2023.07.06.06.25.14 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Jul 2023 06:25:14 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/14] hw/arm/sbsa-ref: use XHCI to replace EHCI Date: Thu, 6 Jul 2023 14:25:00 +0100 Message-Id: <20230706132512.3534397-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230706132512.3534397-1-peter.maydell@linaro.org> References: <20230706132512.3534397-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Yuquan Wang The current sbsa-ref cannot use EHCI controller which is only able to do 32-bit DMA, since sbsa-ref doesn't have RAM below 4GB. Hence, this uses XHCI to provide a usb controller with 64-bit DMA capablity instead of EHCI. We bump the platform version to 0.3 with this change. Although the hardware at the USB controller address changes, the firmware and Linux can both cope with this -- on an older non-XHCI-aware firmware/kernel setup the probe routine simply fails and the guest proceeds without any USB. (This isn't a loss of functionality, because the old USB controller never worked in the first place.) So we can call this a backwards-compatible change and only bump the minor version. Signed-off-by: Yuquan Wang Message-id: 20230621103847.447508-2-wangyuquan1236@phytium.com.cn [PMM: tweaked commit message; add line to docs about what changes in platform version 0.3] Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- docs/system/arm/sbsa.rst | 5 ++++- hw/arm/sbsa-ref.c | 23 +++++++++++++---------- hw/arm/Kconfig | 2 +- 3 files changed, 18 insertions(+), 12 deletions(-) diff --git a/docs/system/arm/sbsa.rst b/docs/system/arm/sbsa.rst index a8e0b530a24..bca61608ff8 100644 --- a/docs/system/arm/sbsa.rst +++ b/docs/system/arm/sbsa.rst @@ -19,7 +19,7 @@ The ``sbsa-ref`` board supports: - A configurable number of AArch64 CPUs - GIC version 3 - System bus AHCI controller - - System bus EHCI controller + - System bus XHCI controller - CDROM and hard disc on AHCI bus - E1000E ethernet card on PCIe bus - Bochs display adapter on PCIe bus @@ -68,3 +68,6 @@ Platform version changes: 0.2 GIC ITS information is present in devicetree. + +0.3 + The USB controller is an XHCI device, not EHCI diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index 82a28b2e0be..1a8519b868f 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -42,6 +42,7 @@ #include "hw/pci-host/gpex.h" #include "hw/qdev-properties.h" #include "hw/usb.h" +#include "hw/usb/xhci.h" #include "hw/char/pl011.h" #include "hw/watchdog/sbsa_gwdt.h" #include "net/net.h" @@ -85,7 +86,7 @@ enum { SBSA_SECURE_UART_MM, SBSA_SECURE_MEM, SBSA_AHCI, - SBSA_EHCI, + SBSA_XHCI, }; struct SBSAMachineState { @@ -123,7 +124,7 @@ static const MemMapEntry sbsa_ref_memmap[] = { [SBSA_SMMU] = { 0x60050000, 0x00020000 }, /* Space here reserved for more SMMUs */ [SBSA_AHCI] = { 0x60100000, 0x00010000 }, - [SBSA_EHCI] = { 0x60110000, 0x00010000 }, + [SBSA_XHCI] = { 0x60110000, 0x00010000 }, /* Space here reserved for other devices */ [SBSA_PCIE_PIO] = { 0x7fff0000, 0x00010000 }, /* 32-bit address PCIE MMIO space */ @@ -143,7 +144,7 @@ static const int sbsa_ref_irqmap[] = { [SBSA_SECURE_UART] = 8, [SBSA_SECURE_UART_MM] = 9, [SBSA_AHCI] = 10, - [SBSA_EHCI] = 11, + [SBSA_XHCI] = 11, [SBSA_SMMU] = 12, /* ... to 15 */ [SBSA_GWDT_WS0] = 16, }; @@ -230,7 +231,7 @@ static void create_fdt(SBSAMachineState *sms) * fw compatibility. */ qemu_fdt_setprop_cell(fdt, "/", "machine-version-major", 0); - qemu_fdt_setprop_cell(fdt, "/", "machine-version-minor", 2); + qemu_fdt_setprop_cell(fdt, "/", "machine-version-minor", 3); if (ms->numa_state->have_numa_distance) { int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); @@ -604,13 +605,15 @@ static void create_ahci(const SBSAMachineState *sms) } } -static void create_ehci(const SBSAMachineState *sms) +static void create_xhci(const SBSAMachineState *sms) { - hwaddr base = sbsa_ref_memmap[SBSA_EHCI].base; - int irq = sbsa_ref_irqmap[SBSA_EHCI]; + hwaddr base = sbsa_ref_memmap[SBSA_XHCI].base; + int irq = sbsa_ref_irqmap[SBSA_XHCI]; + DeviceState *dev = qdev_new(TYPE_XHCI_SYSBUS); - sysbus_create_simple("platform-ehci-usb", base, - qdev_get_gpio_in(sms->gic, irq)); + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(sms->gic, irq)); } static void create_smmu(const SBSAMachineState *sms, PCIBus *bus) @@ -832,7 +835,7 @@ static void sbsa_ref_init(MachineState *machine) create_ahci(sms); - create_ehci(sms); + create_xhci(sms); create_pcie(sms); diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 7de17d1e8c3..7e683484405 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -266,7 +266,7 @@ config SBSA_REF select PL011 # UART select PL031 # RTC select PL061 # GPIO - select USB_EHCI_SYSBUS + select USB_XHCI_SYSBUS select WDT_SBSA select BOCHS_DISPLAY From patchwork Thu Jul 6 13:25:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 699603 Delivered-To: patch@linaro.org Received: by 2002:adf:fcc5:0:0:0:0:0 with SMTP id f5csp3312561wrs; Thu, 6 Jul 2023 06:27:46 -0700 (PDT) X-Google-Smtp-Source: APBJJlGc+JdAqGFTKMnk7dewI9x3MpS4UiStFlpKLiAN62KtBrKGzxU0ZoGVB2TuMwBHRrxKi6+G X-Received: by 2002:a0c:dd13:0:b0:636:4d4f:190a with SMTP id u19-20020a0cdd13000000b006364d4f190amr1208146qvk.31.1688650066293; Thu, 06 Jul 2023 06:27:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1688650066; cv=none; d=google.com; s=arc-20160816; b=w/e2wwAGfGbwKGs+qReNas3Q2+y6SgzVHgINfAtKYmE1C98tL/6g/20DdydtOesHBE XQwjvzCrIhwIUjgjQcK2/LMov/nxylJtP5504AQpGsPIQ8tcVv0RUbHDe6TArosEKQhR lWDbrvSlGxV6db2ew5o9uQ5PKqCZWRyYNe+GN2VHYrSRivGhC+lu7YtJ+hD1EzqHCwut 29duZ4AXWMaUXuiJYD3nqC4lRFdGGoEFhnh2h9i0pUAF9X0qoz2KMhaMYoYfQwGlWHJW K+CHvHqF26LFDqmiHWVwMcP5tDJ2UNZfiV2KWhWt+RKDPdtTirKJPO8677VohIPyYnNW dWOg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=11dmJzi1SZBc11U8ovpYkYYocCgASa/aNmWlfY/CVCM=; fh=bFDrUYhlTVi/QyetgXx/byg2+yO/22Hp9SjwoefyKLk=; b=bDR3XphnYJLYup3x2679aV2xE5ZHrY9jSBcVtNKpphR4QO+nEGeBZsVc1Sm8REYQK5 aL6g33t9hUvBHgadBjZ9tFeLIicq/1LcYpHxjrvFnFxkQduAmVbzAaHrseXGJmx3aq2M ygsqqXJgDFqh9r4mF/DPathjLy+w4PBfuOUxAImli7v8lBWgqa7XsXAhKt3Baw4OhyiN lzzuQycYFegqw/yFvhzSeN7qRFM7gLmnZozpP3b2/8LIKvOsWqYsdnYdf1xQiaJHMWyU kAJetpWjFjdccvdMkX8GwZFXCB8HiXGSDgRKQAmo9fegqA7Aaqc5iytntqnOwWM+Yc/+ SdnA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=uu73ZLE6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id s9-20020a0ca609000000b00635f39a9277si903122qva.472.2023.07.06.06.27.46 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 06 Jul 2023 06:27:46 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=uu73ZLE6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qHOzc-0005KV-Ik; Thu, 06 Jul 2023 09:25:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qHOzP-0004sI-JO for qemu-devel@nongnu.org; Thu, 06 Jul 2023 09:25:45 -0400 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qHOzM-0000r1-0o for qemu-devel@nongnu.org; Thu, 06 Jul 2023 09:25:43 -0400 Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-3fbf1b82dc7so7151345e9.2 for ; Thu, 06 Jul 2023 06:25:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1688649915; x=1691241915; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=11dmJzi1SZBc11U8ovpYkYYocCgASa/aNmWlfY/CVCM=; b=uu73ZLE6GUX6b6J/Bq6G3ASEwaStlVpaAOV/ACGHEXLNiW9TWW2L3fs2AFP+EDO4S4 c3e6D24GHxHBX2sejMKSJZji4fbvuc27clR0Y9FdLSwVArS2GQ4qRFOuSEiLdlKJAvq0 jErHYhQ5uN6pUJJiH39o0ZRwZesCoh1Ke3OtRusM1sy9xu0nTxSzIBuX+KiZ1arVlWZf Hyh/TVwlIGUIggDI/p6RHqdVAlLFG6i+rNXhmrUfy06VJ63qNv33SiL4wVhXugyswgNj jPl5Klg9Sa/aY7qanK9mlmhe0d1VyWSfizZUn3bf/iQCzpeNMIJcRWGTgr4RpBO4XBRy pFJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688649915; x=1691241915; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=11dmJzi1SZBc11U8ovpYkYYocCgASa/aNmWlfY/CVCM=; b=XiPexeQom/bhlXrxiNOURyvST1oe52e+Y3/1eK8Q4VdG38WkIQzHMoDHq4PFMVavw0 m4Pc8rQlabYOgmX+K8P15DQPaYYkKXJFOiRuGkh8Qmcy2Z6i3i3q4QkJMHt7AlkHeXjh QFj93CWDJZ/CkQNwab6ZnKGbIsQZUawmhBeSeqcTS1hN5idJpb0HEJ6ywhwbXuV+NvDp M93k+WE1tTaszedkbDxCnCBCoylieDeycaiWK2QUJIJeRlA/iiPtjJJYdJkDMTX25mGp NeTacssvB7v8aKBmCLDeD83QyGnIjKHH6i63smmeutmMVZJ64DNetxEXZ896qa+TSwpl 6+mw== X-Gm-Message-State: ABy/qLY9yZUszDJ2hknDCLhaV1VCNqzoPDRFeNXbE7oHabVwL/IN7P05 L21+87WJee5xmHg9KpQp7cXBC3bhMa7nvRw80iw= X-Received: by 2002:adf:ecc8:0:b0:30f:af06:7320 with SMTP id s8-20020adfecc8000000b0030faf067320mr1506244wro.23.1688649915584; Thu, 06 Jul 2023 06:25:15 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id s15-20020a5d510f000000b00304adbeeabbsm1856170wrt.99.2023.07.06.06.25.15 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Jul 2023 06:25:15 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/14] tests/tcg/aarch64/sysregs.c: Use S syntax for id_aa64zfr0_el1 and id_aa64smfr0_el1 Date: Thu, 6 Jul 2023 14:25:01 +0100 Message-Id: <20230706132512.3534397-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230706132512.3534397-1-peter.maydell@linaro.org> References: <20230706132512.3534397-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Some assemblers will complain about attempts to access id_aa64zfr0_el1 and id_aa64smfr0_el1 by name if the test binary isn't built for the right processor type: /tmp/ccASXpLo.s:782: Error: selected processor does not support system register name 'id_aa64zfr0_el1' /tmp/ccASXpLo.s:829: Error: selected processor does not support system register name 'id_aa64smfr0_el1' However, these registers are in the ID space and are guaranteed to read-as-zero on older CPUs, so the access is both safe and sensible. Switch to using the S syntax, as we already do for ID_AA64ISAR2_EL1 and ID_AA64MMFR2_EL1. This allows us to drop the HAS_ARMV9_SME check and the makefile machinery to adjust the CFLAGS for this test, so we don't rely on having a sufficiently new compiler to be able to check these registers. This means we're actually testing the SME ID register: no released GCC yet recognizes -march=armv9-a+sme, so that was always skipped. It also avoids a future problem if we try to switch the "do we have SME support in the toolchain" check from "in the compiler" to "in the assembler" (at which point we would otherwise run into the above errors). Signed-off-by: Peter Maydell --- tests/tcg/aarch64/sysregs.c | 11 +++++++---- tests/tcg/aarch64/Makefile.target | 7 +------ 2 files changed, 8 insertions(+), 10 deletions(-) diff --git a/tests/tcg/aarch64/sysregs.c b/tests/tcg/aarch64/sysregs.c index 46b931f781d..d8eb06abcf2 100644 --- a/tests/tcg/aarch64/sysregs.c +++ b/tests/tcg/aarch64/sysregs.c @@ -25,9 +25,14 @@ /* * Older assemblers don't recognize newer system register names, * but we can still access them by the Sn_n_Cn_Cn_n syntax. + * This also means we don't need to specifically request that the + * assembler enables whatever architectural features the ID registers + * syntax might be gated behind. */ #define SYS_ID_AA64ISAR2_EL1 S3_0_C0_C6_2 #define SYS_ID_AA64MMFR2_EL1 S3_0_C0_C7_2 +#define SYS_ID_AA64ZFR0_EL1 S3_0_C0_C4_4 +#define SYS_ID_AA64SMFR0_EL1 S3_0_C0_C4_5 int failed_bit_count; @@ -132,10 +137,8 @@ int main(void) /* all hidden, DebugVer fixed to 0x6 (ARMv8 debug architecture) */ get_cpu_reg_check_mask(id_aa64dfr0_el1, _m(0000,0000,0000,0006)); get_cpu_reg_check_zero(id_aa64dfr1_el1); - get_cpu_reg_check_mask(id_aa64zfr0_el1, _m(0ff0,ff0f,00ff,00ff)); -#ifdef HAS_ARMV9_SME - get_cpu_reg_check_mask(id_aa64smfr0_el1, _m(80f1,00fd,0000,0000)); -#endif + get_cpu_reg_check_mask(SYS_ID_AA64ZFR0_EL1, _m(0ff0,ff0f,00ff,00ff)); + get_cpu_reg_check_mask(SYS_ID_AA64SMFR0_EL1, _m(80f1,00fd,0000,0000)); get_cpu_reg_check_zero(id_aa64afr0_el1); get_cpu_reg_check_zero(id_aa64afr1_el1); diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target index cec1d4b2875..ea9ceb31e61 100644 --- a/tests/tcg/aarch64/Makefile.target +++ b/tests/tcg/aarch64/Makefile.target @@ -61,15 +61,10 @@ AARCH64_TESTS += mte-1 mte-2 mte-3 mte-4 mte-5 mte-6 mte-7 mte-%: CFLAGS += -march=armv8.5-a+memtag endif -ifneq ($(CROSS_CC_HAS_SVE),) # System Registers Tests AARCH64_TESTS += sysregs -ifneq ($(CROSS_CC_HAS_ARMV9_SME),) -sysregs: CFLAGS+=-march=armv9-a+sme -DHAS_ARMV9_SME -else -sysregs: CFLAGS+=-march=armv8.1-a+sve -endif +ifneq ($(CROSS_CC_HAS_SVE),) # SVE ioctl test AARCH64_TESTS += sve-ioctls sve-ioctls: CFLAGS+=-march=armv8.1-a+sve From patchwork Thu Jul 6 13:25:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 699601 Delivered-To: patch@linaro.org Received: by 2002:adf:fcc5:0:0:0:0:0 with SMTP id f5csp3312482wrs; Thu, 6 Jul 2023 06:27:35 -0700 (PDT) X-Google-Smtp-Source: APBJJlGkNqPrBYMLTAy2qp9zYui0/UMIWi0qpS2yifv+WdQgPws82h3NMWjj3NJVWEleEf3dDYPp X-Received: by 2002:ac8:4e91:0:b0:400:8d80:9040 with SMTP id 17-20020ac84e91000000b004008d809040mr2478525qtp.40.1688650055299; Thu, 06 Jul 2023 06:27:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1688650055; cv=none; d=google.com; s=arc-20160816; b=QWzGhXZWXDKxlDvv/R8THo2J3XjC5wnR+aZMwozG1KZfNPTGBiftDgVES79hVVUMS+ zL4Pa+TW8uz+z7OqwIzKB70ZA9nWoyTz6lRfdmvjqAdWk+VKMvl7LDWvI7FhcdEBHjVN JcIGK2WbV4h6gyJrCyDKqGJtstcBcHcf54zaOiLto56RIlBvUbIXjlQoyrM+6RceU9Rt MZIpru1nEjELkHZmKQ8JYT4j6GJ13d0mh2hbg5yjAm+JafyIVTLyCyfqL8GkeC84iStG m2ZhOamYV797Cw23JLTt/23K1KnXo9ZtTB9MA2yxEHwi00mZ0hhHk2vQKOajjLh8wheb 0h0Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ANDE8o5tT4TCHpJ1lybjyH19qs/lumWSbTmj9hQZYtk=; fh=bFDrUYhlTVi/QyetgXx/byg2+yO/22Hp9SjwoefyKLk=; b=JaEymgTjOqXlEyn+nyKYOP83tm4S9XW1iXyx64neoelM8QIpBcKB8K6/HD5kjcbtJD LKqIEsyi/2iJLLt9KVvvbroGtdjmlFQzfy/wmkB++0241AerFmjrXhdAhqTuWwg4gx4j L1iK5vQFecMU+oX7Qety5tnb/5WI+Zhfxn+NPN/962kpDhwaa6oNlUb7MCEFiP/RBus9 unkt2DXxvyth/DHsoNNkS5mhXeSA2k7ObBF3KkGjCdtMbf8S/zNcUaHJ7q22gWzZdmAw ZBUg8DQHJO+G1EoRBd4SvK6pbFWX5SOTNoEQAaOHl2Jf0T/Fm28UnhTYDXdi9pe6vDZV M9PA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FKrawGvb; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id s16-20020a05622a019000b00401fdf331a1si887420qtw.216.2023.07.06.06.27.35 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 06 Jul 2023 06:27:35 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FKrawGvb; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qHOzc-0005Lz-RC; Thu, 06 Jul 2023 09:25:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qHOzP-0004sH-Eh for qemu-devel@nongnu.org; Thu, 06 Jul 2023 09:25:45 -0400 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qHOzL-0000r9-SE for qemu-devel@nongnu.org; Thu, 06 Jul 2023 09:25:43 -0400 Received: by mail-wr1-x42e.google.com with SMTP id ffacd0b85a97d-31427ddd3fbso643062f8f.0 for ; Thu, 06 Jul 2023 06:25:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1688649916; x=1691241916; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=ANDE8o5tT4TCHpJ1lybjyH19qs/lumWSbTmj9hQZYtk=; b=FKrawGvb0YULfhnbhpMnujLdzjpBqwRsVs9Fk4GUfcYCSVItQS7XqJIplTllGnb0fc FMbdOXq+FoUy+HFQ68HLUmY5du/CMi1806TOcLJUrK3VV7r5977x46RRyZRv5ntUfS7c AaJP+EPdl3pa1z1GShrk4jNQ5qinH7YeRQ8qo3qQhOZc/gVC06AwfGp0nHg5Mgw58mC2 poP+zjYIZpp3lVv3TalxdBJsb90nBOIu/qPUqHmGtfzYe+LfBG/91yakT7EnZTAMW1jI QJ4Ba+SdvaNDQJtIGpN5Zc9guOdUSjCtrBw7XTYwamBYXWDIlAzWNRBfNgtozVrJBdiL K+rg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688649916; x=1691241916; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ANDE8o5tT4TCHpJ1lybjyH19qs/lumWSbTmj9hQZYtk=; b=DXTR2ECPU3yNR2U4HLOX4YpnDac0X0/FOiT6KWOPC5OIhhD+RVuc1L8f/KfE8QfCwS DTBjFcCzsCGUX9bBulLhRMYERHUd6kI2gEudWGYP7VF0UrSrfyc+Ooo7N+hHHJD2Ilno TKcBdAC3MF+3TFb7/a/bTtho2WTuc8c+q2Iqf1IhiF+gDIPWsYCYx9h9/4iPmACRZzPa hNZwkvcY/7xCAfp4n9o0cZgY7hJmSToVysd8/eSPOz5KxA8JSIRYC+izqHyMzwlVL3aQ +ncv5eyqAV1PZTg1XpweNZuUgbLp6Td/tl5e9C7DbJEy4x8NlmSGlmrk3kVz81OyGt7M 7wiA== X-Gm-Message-State: ABy/qLZp0trgeitN/mvXwiLEr6D4apwd8fVePvl91zJmz4pWlHkW0NLb igkPpGRtkKJYeVBKypwRT4FxWAAmrjCNibJ7ISM= X-Received: by 2002:a05:6000:90c:b0:313:f7f1:e34c with SMTP id cw12-20020a056000090c00b00313f7f1e34cmr1461376wrb.60.1688649916035; Thu, 06 Jul 2023 06:25:16 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id s15-20020a5d510f000000b00304adbeeabbsm1856170wrt.99.2023.07.06.06.25.15 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Jul 2023 06:25:15 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/14] target/arm: Avoid splitting Zregs across lines in dump Date: Thu, 6 Jul 2023 14:25:02 +0100 Message-Id: <20230706132512.3534397-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230706132512.3534397-1-peter.maydell@linaro.org> References: <20230706132512.3534397-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson Allow the line length to extend to 548 columns. While annoyingly wide, it's still less confusing than the continuations we print. Also, the default VL used by Linux (and max for A64FX) uses only 140 columns. Signed-off-by: Richard Henderson Message-id: 20230622151201.1578522-2-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/cpu.c | 36 ++++++++++++++---------------------- 1 file changed, 14 insertions(+), 22 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index a1e77698ba2..f12c714bc43 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -955,7 +955,7 @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; uint32_t psr = pstate_read(env); - int i; + int i, j; int el = arm_current_el(env); const char *ns_status; bool sve; @@ -1014,7 +1014,7 @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) } if (sve) { - int j, zcr_len = sve_vqm1_for_el(env, el); + int zcr_len = sve_vqm1_for_el(env, el); for (i = 0; i <= FFR_PRED_NUM; i++) { bool eol; @@ -1054,32 +1054,24 @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) } } - for (i = 0; i < 32; i++) { - if (zcr_len == 0) { + if (zcr_len == 0) { + /* + * With vl=16, there are only 37 columns per register, + * so output two registers per line. + */ + for (i = 0; i < 32; i++) { qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s", i, env->vfp.zregs[i].d[1], env->vfp.zregs[i].d[0], i & 1 ? "\n" : " "); - } else if (zcr_len == 1) { - qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 - ":%016" PRIx64 ":%016" PRIx64 "\n", - i, env->vfp.zregs[i].d[3], env->vfp.zregs[i].d[2], - env->vfp.zregs[i].d[1], env->vfp.zregs[i].d[0]); - } else { + } + } else { + for (i = 0; i < 32; i++) { + qemu_fprintf(f, "Z%02d=", i); for (j = zcr_len; j >= 0; j--) { - bool odd = (zcr_len - j) % 2 != 0; - if (j == zcr_len) { - qemu_fprintf(f, "Z%02d[%x-%x]=", i, j, j - 1); - } else if (!odd) { - if (j > 0) { - qemu_fprintf(f, " [%x-%x]=", j, j - 1); - } else { - qemu_fprintf(f, " [%x]=", j); - } - } qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s", env->vfp.zregs[i].d[j * 2 + 1], - env->vfp.zregs[i].d[j * 2], - odd || j == 0 ? "\n" : ":"); + env->vfp.zregs[i].d[j * 2 + 0], + j ? ":" : "\n"); } } } From patchwork Thu Jul 6 13:25:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 699598 Delivered-To: patch@linaro.org Received: by 2002:adf:fcc5:0:0:0:0:0 with SMTP id f5csp3312280wrs; Thu, 6 Jul 2023 06:27:08 -0700 (PDT) X-Google-Smtp-Source: APBJJlFsEoxChIhSia76dMU6vKs6grnWZLMyNzEAYQo+7wZvS/QRf5FezvcKk81UpK9cUnHjr/XE X-Received: by 2002:a05:620a:40c5:b0:765:3ab9:df8d with SMTP id g5-20020a05620a40c500b007653ab9df8dmr2023974qko.32.1688650028213; Thu, 06 Jul 2023 06:27:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1688650028; cv=none; d=google.com; s=arc-20160816; b=cDayMJNS0i896JtYVXZd+vu0G/WZ6/FjDOG54H8+t5QMeTXDbWmCz1FViBVQ4O3noh O1xfiqWqhr/eikwWCHPvvUyE9Y+CgQisIGVN/wL/w0TnIGfF5cyVOqfsUhnP/d4uSxc1 aDOLx4qlUDKIyLo3VK/EUu+kGNQV5pJ22Ildca5t1XrZFgennVH/yQaGJgN0aaQcwTH+ zhCbBpdFKXfTEC2lZ19uZH9wnrnPb7xD1YyIFM80gGUwhDZsPPksFAzmQLHzaHDp7H7V 6nFqZbF9SfdU8TgBxF25b0AAa7cgwp6dgDiBAhUrT+QuE0xrxEp4/maHKL74dehEQUvN hgsQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=kTYABhSkRPbMfHK4MqNnIuIncwaUJ0xXtOeHrnGp338=; fh=bFDrUYhlTVi/QyetgXx/byg2+yO/22Hp9SjwoefyKLk=; b=Ok+mCZPHQrQBRVidQ9C34CCMYuC3w9K+N1hB61zshnzePP8VqwqrvdQ8jZE6f3YenW 3cK6wZY4P18bnQViZW9jpwS9WjCwyTdsNxk7oOHrGKkEecpBVSTaTZVIV+N6MiHUlByS XfPRrEC+SZz8i8cnTIK9bOsCqpkJ4UDVcgcC3xodO8cR69pCjUUd3rpu+HKXlRdqzbSh bEt3fb8WRECZg95B/aUC90g8qh7vgo+uDAAqvnwLclASqPOK8SLNj3J99l4LfYlR56O0 8PAkrnP8ww9DG25ROHHsNFM52z7urJIXkb6gi30ntOXM+NiY0agovG0yXY4tepUJ86Wh Dd8A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=H3umnWHW; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id w8-20020a05620a128800b007624010271esi1055259qki.343.2023.07.06.06.27.08 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 06 Jul 2023 06:27:08 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=H3umnWHW; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qHOzb-0005E7-G4; Thu, 06 Jul 2023 09:25:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qHOzP-0004sG-EE for qemu-devel@nongnu.org; Thu, 06 Jul 2023 09:25:45 -0400 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qHOzM-0000rR-1F for qemu-devel@nongnu.org; Thu, 06 Jul 2023 09:25:43 -0400 Received: by mail-wm1-x335.google.com with SMTP id 5b1f17b1804b1-3fbc63c2e84so7582835e9.3 for ; Thu, 06 Jul 2023 06:25:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1688649916; x=1691241916; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=kTYABhSkRPbMfHK4MqNnIuIncwaUJ0xXtOeHrnGp338=; b=H3umnWHWDBIXVy6Bnx4og1aOwr5TnkX2OiHshU2ZRhVpjOPMzJRyMqCfPNtbH4/MEp 4dME/MxuDimzzhQIcaOMo2s2moB6f7TvPBwYEr+AmACJ93ECbm2FG0sgjFnlBp76Xs1V UJytsB9PG3VMvgAl7xB5PTcUWUWAgdst2IZEW2lKoCq0mN/6Dw0+nzZchosr6MPcZ9l3 eC5WpdRpt8EHePI3mr1Hs+BCTmy6di7leXpYRALEVgCxAxqIjUWhy8OWZDtf+EG3KyJ5 x+SJefEaloQetNmAhjpOlaVvK9XNWV/7qAISGLM9wgkQn9Xk+sFkNF9+qZ5lqB5kHL9U Rblw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688649916; x=1691241916; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kTYABhSkRPbMfHK4MqNnIuIncwaUJ0xXtOeHrnGp338=; b=ArXjFt/yEf2/1n5dLARjiIXHnE1FDVvDA56xyQTPUCeys0vqOBZB9KeEzwOm5ENhT3 SwzvBt+oO2tUgzUL0VcgsOluCOqfocbCh2O0uhXW31NjKh6rjKf1mcQROaMbVw0JaGhZ DzqDo+KGVxlnxqryy4kUoqONPHaP80gCknN3wrdGaia+jolkM+ZILDjvZq6GzMh91kKq ccSdbSPQ560KizljwhVnPJH4H1KqLbanFf9MLWlbtr3L7fg3RAUMZzM/2qmZfJ5HkTq/ NaBspuEkSK2WIwYodwCy9Toen4b0Dcjy1+CIb7iLOQgMR7BAYYJ3cHm5qUxWyao2aO34 lqLw== X-Gm-Message-State: ABy/qLY/MlpLwOXS+oTIxzCAtxvXzcNVnL10zhRyd3ZsRKWmFuQRZcmC 9KfZRAVPto8KusfCcFphqeHMtsejyLZOvIGfNKE= X-Received: by 2002:a7b:c8d1:0:b0:3fa:8fb1:50fe with SMTP id f17-20020a7bc8d1000000b003fa8fb150femr1352408wml.15.1688649916396; Thu, 06 Jul 2023 06:25:16 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id s15-20020a5d510f000000b00304adbeeabbsm1856170wrt.99.2023.07.06.06.25.16 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Jul 2023 06:25:16 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/14] target/arm: Dump ZA[] when active Date: Thu, 6 Jul 2023 14:25:03 +0100 Message-Id: <20230706132512.3534397-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230706132512.3534397-1-peter.maydell@linaro.org> References: <20230706132512.3534397-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson Always print each matrix row whole, one per line, so that we get the entire matrix in the proper shape. Signed-off-by: Richard Henderson Message-id: 20230622151201.1578522-3-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/cpu.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index f12c714bc43..adf84f96860 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1082,6 +1082,24 @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) i, q[1], q[0], (i & 1 ? "\n" : " ")); } } + + if (cpu_isar_feature(aa64_sme, cpu) && + FIELD_EX64(env->svcr, SVCR, ZA) && + sme_exception_el(env, el) == 0) { + int zcr_len = sve_vqm1_for_el_sm(env, el, true); + int svl = (zcr_len + 1) * 16; + int svl_lg10 = svl < 100 ? 2 : 3; + + for (i = 0; i < svl; i++) { + qemu_fprintf(f, "ZA[%0*d]=", svl_lg10, i); + for (j = zcr_len; j >= 0; --j) { + qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%c", + env->zarray[i].d[2 * j + 1], + env->zarray[i].d[2 * j], + j ? ':' : '\n'); + } + } + } } #else From patchwork Thu Jul 6 13:25:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 699596 Delivered-To: patch@linaro.org Received: by 2002:adf:fcc5:0:0:0:0:0 with SMTP id f5csp3312198wrs; Thu, 6 Jul 2023 06:26:58 -0700 (PDT) X-Google-Smtp-Source: APBJJlFwkob8oVLgLbjOyLNESFTxbH0TWjs9J2koHtkSK68JgYeES20BnMrA4wI4LsvrN3Y4Q5eQ X-Received: by 2002:a05:622a:2cb:b0:403:27b6:a341 with SMTP id a11-20020a05622a02cb00b0040327b6a341mr2292349qtx.56.1688650018079; Thu, 06 Jul 2023 06:26:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1688650018; cv=none; d=google.com; s=arc-20160816; b=WF1wfXPeVVR5Vh8IUf/k5fUR6T0GW929KtuAOt9wW8MxtDyppuvKYic3cWgULD0rjt A4kS6ue4sEYSBQOZPOg6eiDCOjoCgAJzzKnMsdDJW4ViMB5hziqHj/AbS1yno1doTOc8 lr2NYQBdrM1bJsCH/GUFJ04wRyFHTgQudY+x41xHGzMF9eKzQBioX/cfOs9RBpBTd5Wh cRzcrJWhORxaVbsBHq91ZDQj+psO7qBpBkFgjIQuG7HiCCA4nGIUYi3vTGKq9m4n3Yg2 I/Jxzd4wDo3cx+JSFxKfdZB0U3E07ilnmL14MQVinhh1ufgS7M4gXK7eSma1vr7+AVaE jh6A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=zL/RsA9jgMyW4dfuMsDxRj6eRvGZr65D1dgfSc/yjEQ=; fh=bFDrUYhlTVi/QyetgXx/byg2+yO/22Hp9SjwoefyKLk=; b=JGoOwzBy94PyxLMlNkTpmmh7nsL06xWx9f9pWf+Ae2ePnUIggN7eUcKb1aQrv0JLWX PnTsqQZEP8q/vEQgnKq3kFCVkwJRE/thFOtngtd+0yQnpBgFIA15KdzcTQ2KmKQEtvMZ xjqukFD9EaHbXhVpCYi3ZdCwjvRQE0Q7iN7AchwHMgIJkO9RFnSbvY4Al20MUe9TtDIL hE4Npmkdk8Z6Rd+UWDXI/BPEOJe5c0q/QCFl/A3lcG8JKi2hh4vzoVem2F9Rvqc3Og70 SpdWFHdQHpc59WgMo7d+Ho4d9ksf1cKOEX31GHJ5/hlE4KF6FNPeSX0T4tyfpGjPnHKE z4zg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WP9yIwYS; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 19-20020ac85953000000b004032ebaef28si862410qtz.567.2023.07.06.06.26.57 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 06 Jul 2023 06:26:58 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WP9yIwYS; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qHOza-00053u-04; Thu, 06 Jul 2023 09:25:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qHOzF-0004n4-3I for qemu-devel@nongnu.org; Thu, 06 Jul 2023 09:25:34 -0400 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qHOz2-0000rh-Ll for qemu-devel@nongnu.org; Thu, 06 Jul 2023 09:25:27 -0400 Received: by mail-wr1-x430.google.com with SMTP id ffacd0b85a97d-307d58b3efbso592372f8f.0 for ; Thu, 06 Jul 2023 06:25:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1688649917; x=1691241917; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=zL/RsA9jgMyW4dfuMsDxRj6eRvGZr65D1dgfSc/yjEQ=; b=WP9yIwYSRueVZLLi2+SKOYojqeefsOCXBjfFAlqx8/aLyDYdCIhRra85HKzRY5P0lY W38lCQEbJ7jN+7xL655pM2jXNyyjP7saeizcLqdapXyna9jdyBgSZ8T8ADqYzJspSZ+i oRviJ2NFZN5RbSaisx921u82JWm16aB5xb6ysgeGQJo9jzEJx6Rf8l3XcMXhdX3PcDJp Cxqcd2vRU9GZ1BjMZum9lDzgSDvxQd9c5shdvnreWc/SXGSfjG5L+AQsXynoZ462Kb87 nnSUxoBl/wEkYKSaN6bIfN3niE+6XZRtx2ufj0j5zD5KqTLelmxN9KqaHeucwSUabgcg n+iQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688649917; x=1691241917; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zL/RsA9jgMyW4dfuMsDxRj6eRvGZr65D1dgfSc/yjEQ=; b=BP7PBdI08xtMhOn0nCBJfFA2SVetgrfASsBekLepflwg2YVTebaXhFHoM1cG1tBrcM hhkS6u1MvlVgpdGMnXtXcgMwpgZMvqX3avXZjdrBcZATNnS5VEs+XFEidU2pSRV93hkA 27Y14P72r9lI+5zHqLIYYvedEbJCYIGRD1/VJQIT2DMLm1XzslgS3nG1hfwXfe+Oz7kq kw1Bq1Q4A4Y69uzdwRgEHDsKvNHVOEDQ78+dB0EB54QGjxUQgl+ThwLMbc3gasjPc+os 4ZV/zZIbWP1kVtU8w4Q1NU7/Qtk1ZGB4Yc8TocKxqPbQt+sUlMCUB13pOx6NYXu1KN0C 33zg== X-Gm-Message-State: ABy/qLbrAcuQTIvQH3ROy+G57wo1dTgfky6XlO4sDWM/nMITZZhnY0bk Ja3Bt+FBxmcC4DGHXvRt5JVUqmDYhIQ7EW+H5j4= X-Received: by 2002:adf:e268:0:b0:313:f86f:2851 with SMTP id bl40-20020adfe268000000b00313f86f2851mr1435425wrb.3.1688649916859; Thu, 06 Jul 2023 06:25:16 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id s15-20020a5d510f000000b00304adbeeabbsm1856170wrt.99.2023.07.06.06.25.16 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Jul 2023 06:25:16 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 06/14] target/arm: Fix SME full tile indexing Date: Thu, 6 Jul 2023 14:25:04 +0100 Message-Id: <20230706132512.3534397-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230706132512.3534397-1-peter.maydell@linaro.org> References: <20230706132512.3534397-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson For the outer product set of insns, which take an entire matrix tile as output, the argument is not a combined tile+column. Therefore using get_tile_rowcol was incorrect, as we extracted the tile number from itself. The test case relies only on assembler support for SME, since no release of GCC recognizes -march=armv9-a+sme yet. Cc: qemu-stable@nongnu.org Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1620 Signed-off-by: Richard Henderson Message-id: 20230622151201.1578522-5-richard.henderson@linaro.org Reviewed-by: Peter Maydell [PMM: dropped now-unneeded changes to sysregs CFLAGS] Signed-off-by: Peter Maydell --- target/arm/tcg/translate-sme.c | 24 ++++++--- tests/tcg/aarch64/sme-outprod1.c | 83 +++++++++++++++++++++++++++++++ tests/tcg/aarch64/Makefile.target | 7 ++- 3 files changed, 107 insertions(+), 7 deletions(-) create mode 100644 tests/tcg/aarch64/sme-outprod1.c diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c index d0054e3f775..6038b0a06f1 100644 --- a/target/arm/tcg/translate-sme.c +++ b/target/arm/tcg/translate-sme.c @@ -95,6 +95,21 @@ static TCGv_ptr get_tile_rowcol(DisasContext *s, int esz, int rs, return addr; } +/* + * Resolve tile.size[0] to a host pointer. + * Used by e.g. outer product insns where we require the entire tile. + */ +static TCGv_ptr get_tile(DisasContext *s, int esz, int tile) +{ + TCGv_ptr addr = tcg_temp_new_ptr(); + int offset; + + offset = tile * sizeof(ARMVectorReg) + offsetof(CPUARMState, zarray); + + tcg_gen_addi_ptr(addr, cpu_env, offset); + return addr; +} + static bool trans_ZERO(DisasContext *s, arg_ZERO *a) { if (!dc_isar_feature(aa64_sme, s)) { @@ -260,8 +275,7 @@ static bool do_adda(DisasContext *s, arg_adda *a, MemOp esz, return true; } - /* Sum XZR+zad to find ZAd. */ - za = get_tile_rowcol(s, esz, 31, a->zad, false); + za = get_tile(s, esz, a->zad); zn = vec_full_reg_ptr(s, a->zn); pn = pred_full_reg_ptr(s, a->pn); pm = pred_full_reg_ptr(s, a->pm); @@ -286,8 +300,7 @@ static bool do_outprod(DisasContext *s, arg_op *a, MemOp esz, return true; } - /* Sum XZR+zad to find ZAd. */ - za = get_tile_rowcol(s, esz, 31, a->zad, false); + za = get_tile(s, esz, a->zad); zn = vec_full_reg_ptr(s, a->zn); zm = vec_full_reg_ptr(s, a->zm); pn = pred_full_reg_ptr(s, a->pn); @@ -308,8 +321,7 @@ static bool do_outprod_fpst(DisasContext *s, arg_op *a, MemOp esz, return true; } - /* Sum XZR+zad to find ZAd. */ - za = get_tile_rowcol(s, esz, 31, a->zad, false); + za = get_tile(s, esz, a->zad); zn = vec_full_reg_ptr(s, a->zn); zm = vec_full_reg_ptr(s, a->zm); pn = pred_full_reg_ptr(s, a->pn); diff --git a/tests/tcg/aarch64/sme-outprod1.c b/tests/tcg/aarch64/sme-outprod1.c new file mode 100644 index 00000000000..6e5972d75e3 --- /dev/null +++ b/tests/tcg/aarch64/sme-outprod1.c @@ -0,0 +1,83 @@ +/* + * SME outer product, 1 x 1. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include + +extern void foo(float *dst); + +asm( +" .arch_extension sme\n" +" .type foo, @function\n" +"foo:\n" +" stp x29, x30, [sp, -80]!\n" +" mov x29, sp\n" +" stp d8, d9, [sp, 16]\n" +" stp d10, d11, [sp, 32]\n" +" stp d12, d13, [sp, 48]\n" +" stp d14, d15, [sp, 64]\n" +" smstart\n" +" ptrue p0.s, vl4\n" +" fmov z0.s, #1.0\n" +/* + * An outer product of a vector of 1.0 by itself should be a matrix of 1.0. + * Note that we are using tile 1 here (za1.s) rather than tile 0. + */ +" zero {za}\n" +" fmopa za1.s, p0/m, p0/m, z0.s, z0.s\n" +/* + * Read the first 4x4 sub-matrix of elements from tile 1: + * Note that za1h should be interchangable here. + */ +" mov w12, #0\n" +" mova z0.s, p0/m, za1v.s[w12, #0]\n" +" mova z1.s, p0/m, za1v.s[w12, #1]\n" +" mova z2.s, p0/m, za1v.s[w12, #2]\n" +" mova z3.s, p0/m, za1v.s[w12, #3]\n" +/* + * And store them to the input pointer (dst in the C code): + */ +" st1w {z0.s}, p0, [x0]\n" +" add x0, x0, #16\n" +" st1w {z1.s}, p0, [x0]\n" +" add x0, x0, #16\n" +" st1w {z2.s}, p0, [x0]\n" +" add x0, x0, #16\n" +" st1w {z3.s}, p0, [x0]\n" +" smstop\n" +" ldp d8, d9, [sp, 16]\n" +" ldp d10, d11, [sp, 32]\n" +" ldp d12, d13, [sp, 48]\n" +" ldp d14, d15, [sp, 64]\n" +" ldp x29, x30, [sp], 80\n" +" ret\n" +" .size foo, . - foo" +); + +int main() +{ + float dst[16]; + int i, j; + + foo(dst); + + for (i = 0; i < 16; i++) { + if (dst[i] != 1.0f) { + break; + } + } + + if (i == 16) { + return 0; /* success */ + } + + /* failure */ + for (i = 0; i < 4; ++i) { + for (j = 0; j < 4; ++j) { + printf("%f ", (double)dst[i * 4 + j]); + } + printf("\n"); + } + return 1; +} diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target index ea9ceb31e61..0606dec118a 100644 --- a/tests/tcg/aarch64/Makefile.target +++ b/tests/tcg/aarch64/Makefile.target @@ -26,7 +26,7 @@ config-cc.mak: Makefile $(call cc-option,-march=armv8.5-a, CROSS_CC_HAS_ARMV8_5); \ $(call cc-option,-mbranch-protection=standard, CROSS_CC_HAS_ARMV8_BTI); \ $(call cc-option,-march=armv8.5-a+memtag, CROSS_CC_HAS_ARMV8_MTE); \ - $(call cc-option,-march=armv9-a+sme, CROSS_CC_HAS_ARMV9_SME)) 3> config-cc.mak + $(call cc-option,-Wa$(COMMA)-march=armv9-a+sme, CROSS_AS_HAS_ARMV9_SME)) 3> config-cc.mak -include config-cc.mak ifneq ($(CROSS_CC_HAS_ARMV8_2),) @@ -61,6 +61,11 @@ AARCH64_TESTS += mte-1 mte-2 mte-3 mte-4 mte-5 mte-6 mte-7 mte-%: CFLAGS += -march=armv8.5-a+memtag endif +# SME Tests +ifneq ($(CROSS_AS_HAS_ARMV9_SME),) +AARCH64_TESTS += sme-outprod1 +endif + # System Registers Tests AARCH64_TESTS += sysregs From patchwork Thu Jul 6 13:25:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 699595 Delivered-To: patch@linaro.org Received: by 2002:adf:fcc5:0:0:0:0:0 with SMTP id f5csp3312115wrs; Thu, 6 Jul 2023 06:26:45 -0700 (PDT) X-Google-Smtp-Source: APBJJlE1b7xb9Gj5xNY1JnbcWBrkVIblHMueJhUeWS8M7ASsrY7/avLDBXrZllVh3vDA3OAUVn/G X-Received: by 2002:a0c:f0c1:0:b0:636:47a5:4bc5 with SMTP id d1-20020a0cf0c1000000b0063647a54bc5mr1612192qvl.62.1688650005126; Thu, 06 Jul 2023 06:26:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1688650005; cv=none; d=google.com; s=arc-20160816; b=ap+kK6vdXAJr6DC4HIMQw/gFReGMHFD4w39K62R4HpSu2OdNAN7dxvJq9OKPdcQjzC DOw3tyjlgcYcdgcSSjBfCssl5skOcJdxA7ID28oTVICm0kU6JwCP5Y176ZlyDltff9Dr jh//KqKQFXK/Jbdbnk4OmjnrmuiHN8H+jUTRNWmuYnYQTTEWhV2nY3/5iW48Db3pQ7EJ sNrtBMslykxUobluf6WkGulWOYJdpT+frArKvAZkRoVaU3IyLgI8YNgHWXtTJ5B3nP7Q yvspeTLDbNxHvSDGT1bNSqYwseqYfK8zy9lbCFV+K1H6LPM9WrBeDs9+c3A1KNj5Mtae P5vA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=J5PRaqRDbG1q7cJ7k1FBCGAtKCCwmrJ591DUA034EE4=; fh=bFDrUYhlTVi/QyetgXx/byg2+yO/22Hp9SjwoefyKLk=; b=EHy234DHAIoODfOgXEzXqFyznbSTdlmWtJGC820BA7x5RZF71vI1cOQ57ygPWKaAKe dSqmcmqv6H7DqIts1GVjFPljvOHM8ViMR0bE2rwjriDX8lwhcX0rULrV8FwpZORdw0QR qtIJMcuuGEnZjixz45MtDZ9rPYQHSv4bywGNIfM+tlBQ+j/eU32BNsLsgD1g/etXIh+U VR0ldOA0VpnwycsBQdMbSqbzIeD/l3n45DNR7bITFzngkursA+tQBJSHK7GIfjQTyXwn CpOD/Rdh/VOw/J7bJGXPKwGYcRNuNCcvWjt2/3IgSGASLOcw+ok4jI78BLwdmP8M076C O6IA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=uRSO6v+h; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id f7-20020a0caa87000000b006262b0bde1asi862591qvb.569.2023.07.06.06.26.44 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 06 Jul 2023 06:26:45 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=uRSO6v+h; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qHOza-00057W-8y; Thu, 06 Jul 2023 09:25:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qHOzR-0004sL-HG for qemu-devel@nongnu.org; Thu, 06 Jul 2023 09:25:45 -0400 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qHOzN-0000rr-7i for qemu-devel@nongnu.org; Thu, 06 Jul 2023 09:25:45 -0400 Received: by mail-wr1-x433.google.com with SMTP id ffacd0b85a97d-313fb7f0f80so624380f8f.2 for ; Thu, 06 Jul 2023 06:25:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1688649917; x=1691241917; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=J5PRaqRDbG1q7cJ7k1FBCGAtKCCwmrJ591DUA034EE4=; b=uRSO6v+h5HIhoV+MAJOBbD4zVj0xU3QXcMwBDD10ZXEzKztgBZmvg1Q9rKZX8oTLil Dc0zLQlklI0rUOm+zHdjAhNLiCY+rf9W7leekwCrjhy/xalXXnHaI4CZAOAli+pSo828 iSarV8ciyAT46R1Q5+7Hsk9BGxJAOjZZr37IjC2AZwcpty9KaKhnIIwSX48LeMs2+YqF z2FxCFbCwhll6Lxz2xKzTYRNzS7Jt85f6hMaS0M8GH0YGBYBFaddFi5aUZjiL0HT1wz9 0Vsvn0Y1S3ath22Mgloy/VswfhVy+uOh1Ra/7NNIIc5JSfv53zvks3W6qpZZ/7W5iX9f AP5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688649917; x=1691241917; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=J5PRaqRDbG1q7cJ7k1FBCGAtKCCwmrJ591DUA034EE4=; b=R9riqALk4FJeOwanlCFP4Uf/Zj2yQNh9Akt5nXR2WLKHCDiZUL6qaYsqxeh2TEdQgI ueDMJOzslwWfXHUg3Wum4dnTVp20GfqcAOwgBFYyJUSsUBQJ++WK3d/dE62C0bZokq5+ K/42qRLfzXQEQr8EDzMIJ+dwiqt3LKm9x+uwq+1KtHZZZUydGfdCfGT90AUHSyi3w5y/ XMcUSeAd/VeGEDx83H07CPLeNe0Te/fo+ojMODODcB/qf9YzquvNuesn+lQnVKfLmezs t/c9MullcaZEX9J0TvazdkRrKgq6j04kQBFAY5/bIP0t35zAepu2WH5/ALZnrTLe667V NQEA== X-Gm-Message-State: ABy/qLZ5IwNhNrBWxLKx102f43dgRNXScXYk9UeAtrAneQiVsMRnPVbF 1sINPwKUL1pMb+rrttafPAua6zegPucME5PQR0k= X-Received: by 2002:a5d:45cc:0:b0:314:449e:8536 with SMTP id b12-20020a5d45cc000000b00314449e8536mr1378929wrs.10.1688649917295; Thu, 06 Jul 2023 06:25:17 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id s15-20020a5d510f000000b00304adbeeabbsm1856170wrt.99.2023.07.06.06.25.16 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Jul 2023 06:25:17 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/14] target/arm: Handle IC IVAU to improve compatibility with JITs Date: Thu, 6 Jul 2023 14:25:05 +0100 Message-Id: <20230706132512.3534397-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230706132512.3534397-1-peter.maydell@linaro.org> References: <20230706132512.3534397-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: John Högberg Unlike architectures with precise self-modifying code semantics (e.g. x86) ARM processors do not maintain coherency for instruction execution and memory, requiring an instruction synchronization barrier on every core that will execute the new code, and on many models also the explicit use of cache management instructions. While this is required to make JITs work on actual hardware, QEMU has gotten away with not handling this since it does not emulate caches, and unconditionally invalidates code whenever the softmmu or the user-mode page protection logic detects that code has been modified. Unfortunately the latter does not work in the face of dual-mapped code (a common W^X workaround), where one page is executable and the other is writable: user-mode has no way to connect one with the other as that is only known to the kernel and the emulated application. This commit works around the issue by telling software that instruction cache invalidation is required by clearing the CPR_EL0.DIC flag (regardless of whether the emulated processor needs it), and then invalidating code in IC IVAU instructions. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1034 Co-authored-by: Richard Henderson Signed-off-by: John Högberg Reviewed-by: Richard Henderson Message-id: 168778890374.24232.3402138851538068785-1@git.sr.ht [PMM: removed unnecessary AArch64 feature check; moved "clear CTR_EL1.DIC" code up a bit so it's not in the middle of the vfp/neon related tests] Signed-off-by: Peter Maydell --- target/arm/cpu.c | 11 +++++++++++ target/arm/helper.c | 47 ++++++++++++++++++++++++++++++++++++++++++--- 2 files changed, 55 insertions(+), 3 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index adf84f96860..822efa5b2c1 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1694,6 +1694,17 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) return; } +#ifdef CONFIG_USER_ONLY + /* + * User mode relies on IC IVAU instructions to catch modification of + * dual-mapped code. + * + * Clear CTR_EL0.DIC to ensure that software that honors these flags uses + * IC IVAU even if the emulated processor does not normally require it. + */ + cpu->ctr = FIELD_DP64(cpu->ctr, CTR_EL0, DIC, 0); +#endif + if (arm_feature(env, ARM_FEATURE_AARCH64) && cpu->has_vfp != cpu->has_neon) { /* diff --git a/target/arm/helper.c b/target/arm/helper.c index a0b84efab52..8e836aaee13 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5234,6 +5234,36 @@ static void mdcr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri, } } +#ifdef CONFIG_USER_ONLY +/* + * `IC IVAU` is handled to improve compatibility with JITs that dual-map their + * code to get around W^X restrictions, where one region is writable and the + * other is executable. + * + * Since the executable region is never written to we cannot detect code + * changes when running in user mode, and rely on the emulated JIT telling us + * that the code has changed by executing this instruction. + */ +static void ic_ivau_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + uint64_t icache_line_mask, start_address, end_address; + const ARMCPU *cpu; + + cpu = env_archcpu(env); + + icache_line_mask = (4 << extract32(cpu->ctr, 0, 4)) - 1; + start_address = value & ~icache_line_mask; + end_address = value | icache_line_mask; + + mmap_lock(); + + tb_invalidate_phys_range(start_address, end_address); + + mmap_unlock(); +} +#endif + static const ARMCPRegInfo v8_cp_reginfo[] = { /* * Minimal set of EL0-visible registers. This will need to be expanded @@ -5273,7 +5303,10 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { { .name = "CURRENTEL", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 4, .crm = 2, .access = PL1_R, .type = ARM_CP_CURRENTEL }, - /* Cache ops: all NOPs since we don't emulate caches */ + /* + * Instruction cache ops. All of these except `IC IVAU` NOP because we + * don't emulate caches. + */ { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP, @@ -5286,9 +5319,17 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { .accessfn = access_tocu }, { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1, - .access = PL0_W, .type = ARM_CP_NOP, + .access = PL0_W, .fgt = FGT_ICIVAU, - .accessfn = access_tocu }, + .accessfn = access_tocu, +#ifdef CONFIG_USER_ONLY + .type = ARM_CP_NO_RAW, + .writefn = ic_ivau_write +#else + .type = ARM_CP_NOP +#endif + }, + /* Cache ops: all NOPs since we don't emulate caches */ { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1, .access = PL1_W, .accessfn = aa64_cacheop_poc_access, From patchwork Thu Jul 6 13:25:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 699590 Delivered-To: patch@linaro.org Received: by 2002:adf:fcc5:0:0:0:0:0 with SMTP id f5csp3311817wrs; Thu, 6 Jul 2023 06:26:03 -0700 (PDT) X-Google-Smtp-Source: APBJJlG24ewr/ATjN5CQMIEQoUv8Tw9UCzagjyu4wzwaTK5aucJ0F6ldIGJM2W2AdCtXm0l8FUuk X-Received: by 2002:a05:620a:290c:b0:765:55c9:4e02 with SMTP id m12-20020a05620a290c00b0076555c94e02mr2518202qkp.41.1688649963229; Thu, 06 Jul 2023 06:26:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1688649963; cv=none; d=google.com; s=arc-20160816; b=jWStG/Uki0I7Tfv/zyPIXGTLp5vn9xJdXzCLTQaE7Zexge8KLsWR1BCH25HtWtdPCb csOSiqGX8WfqHoJDQrbSTiOvMGN7gYklUyQKbjAVj+RvHGPzxEgotHkjiqU4j8DrWsn2 S5chS201+F4+3yjwK+/DaZec9Ksrp4T0FWRIxKQmbbbYTA1RhQoSbuxYgGtEwnMYoHPQ U4AiIbdLRWxRJxsI3fu13pUMhPL3UJZQQjQLxe/CrxnUGOYvzC8Fb+lNqMMtqFrmtupW HF33JywYIiQZGDvtydy880p/Tn9G0cUDigO375oIoxFsxS3F+NP+7AeDy4ZfOY7FiWFr 87Pg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=eZRfw+Y+qoCHkLPcJJixub5r6MA4gHrUcY1/kPyyLV8=; fh=bFDrUYhlTVi/QyetgXx/byg2+yO/22Hp9SjwoefyKLk=; b=WEC8JAYlPalu2+iz+PU9xN9AieU7jEmZQBZTOqD+Q8sQYMpAPAVDnicfyqAU5QNnmD 5OvqZ+p+COnBbkCD7RQWaQ5TCQb696+DB87Bs2bv4pnrXDQTNeaQaVZCZmy6Y9cKxgvD UQKrK555SHV6A3HBmUmjkSURKJ5m6YdSPMUOFo10RBcA22BFywRfyI2L3Cey1Zk74KIe tzqJEowHWr8ISmBKlW0W9/tiHWY/Ckn0F9moHzWBpQHdHZujH43Fgt9hQ3NnBoFWWDmL 8FhmooOtiQkAF9vglXF4Bm+j8misgFhiXaQbxiRDxS/8d2RbigVFjaej8eU5KFnNzo+R RH8A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vQL2mmkt; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id u6-20020ae9c006000000b00767327f00c9si1081103qkk.242.2023.07.06.06.26.03 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 06 Jul 2023 06:26:03 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vQL2mmkt; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qHOzJ-0004qc-VY; Thu, 06 Jul 2023 09:25:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qHOzF-0004n7-4t for qemu-devel@nongnu.org; Thu, 06 Jul 2023 09:25:34 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qHOz4-0000rz-HB for qemu-devel@nongnu.org; Thu, 06 Jul 2023 09:25:29 -0400 Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-3fbca8935bfso7474075e9.3 for ; Thu, 06 Jul 2023 06:25:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1688649917; x=1691241917; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=eZRfw+Y+qoCHkLPcJJixub5r6MA4gHrUcY1/kPyyLV8=; b=vQL2mmkt0V9P85K07yJe+oAEm/uVBF0ilHYfXzS5msprzOnQIFCq7Kn9hKbxu5OfH0 oi5l8pZ7Z7LHb5LpgrkO6ZO2gOr9/nv+Z5k0WjnvR57isukE23F5kX4MNXvrE7XuvH6N HhIW+oxHm3Bh9pmX5givrrBG8FgnSW9DNJd1ttLC4dmYLw5N68+bpP2pSJhIPX9Rhia3 e8BNTo9KmVEanzJ4ZYIFrqpG2UE9SlkBa59Ik2nQSYfBrgXD4mYADn2gMb3vq5LP/TR2 FbxkNI0w7hCuBOOOPYy837NczgBB3r9SdLu85DHG+xln4ElxsYs8P3VCZRoG+h14QdJa ECHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688649917; x=1691241917; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=eZRfw+Y+qoCHkLPcJJixub5r6MA4gHrUcY1/kPyyLV8=; b=OdQ+pq43FbheGghqhj6+UwLJaGb5s9JAbSKpYi+VIzS07ue8d/gY9vb5q1xTWNdMeo vOVMzr2r7BFy8ZfQl7nl8HhF3B0gfbcLebz/3RV8zzOh5cLaelJV+3rVXzMge6v6Wvof ufPcHPcIiZqUog94WiVXsBtgXXPogA+kIoIk91XCfzAQIDOjyYgF/qzMagrmCFaNXHY3 gniJsjnfa9ExRdbMXEeFG7QihPW/cdCCdAodo6yQDG4N5LVqbMzCneJ3/E5AVm8dtobM bngdUqI+uQX8wsgcTO4/YLEVygxrrq2vy/sfv9Bh8dQk5b0e6G/SrCPoSSznCrvJyS2U ioWA== X-Gm-Message-State: ABy/qLY6ZN69L2opyb5oUqPitNVAP8yIrG+M4R+q93K+viIBOtfXpmfb XmvJH8P6eG2wBgqSTBc53k3HZbExMsuwu8Pcj3w= X-Received: by 2002:a1c:ed14:0:b0:3fb:4149:b816 with SMTP id l20-20020a1ced14000000b003fb4149b816mr1409609wmh.8.1688649917730; Thu, 06 Jul 2023 06:25:17 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id s15-20020a5d510f000000b00304adbeeabbsm1856170wrt.99.2023.07.06.06.25.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Jul 2023 06:25:17 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/14] tests/qtest: xlnx-canfd-test: Fix code coverity issues Date: Thu, 6 Jul 2023 14:25:06 +0100 Message-Id: <20230706132512.3534397-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230706132512.3534397-1-peter.maydell@linaro.org> References: <20230706132512.3534397-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Vikram Garhwal Following are done to fix the coverity issues: 1. Change read_data to fix the CID 1512899: Out-of-bounds access (OVERRUN) 2. Fix match_rx_tx_data to fix CID 1512900: Logically dead code (DEADCODE) 3. Replace rand() in generate_random_data() with g_rand_int() Signed-off-by: Vikram Garhwal Message-id: 20230628202758.16398-1-vikram.garhwal@amd.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- tests/qtest/xlnx-canfd-test.c | 33 +++++++++++---------------------- 1 file changed, 11 insertions(+), 22 deletions(-) diff --git a/tests/qtest/xlnx-canfd-test.c b/tests/qtest/xlnx-canfd-test.c index 76ee106d4f4..78ec9ef2a76 100644 --- a/tests/qtest/xlnx-canfd-test.c +++ b/tests/qtest/xlnx-canfd-test.c @@ -170,23 +170,23 @@ static void generate_random_data(uint32_t *buf_tx, bool is_canfd_frame) /* Generate random TX data for CANFD frame. */ if (is_canfd_frame) { for (int i = 0; i < CANFD_FRAME_SIZE - 2; i++) { - buf_tx[2 + i] = rand(); + buf_tx[2 + i] = g_random_int(); } } else { /* Generate random TX data for CAN frame. */ for (int i = 0; i < CAN_FRAME_SIZE - 2; i++) { - buf_tx[2 + i] = rand(); + buf_tx[2 + i] = g_random_int(); } } } -static void read_data(QTestState *qts, uint64_t can_base_addr, uint32_t *buf_rx) +static void read_data(QTestState *qts, uint64_t can_base_addr, uint32_t *buf_rx, + uint32_t frame_size) { uint32_t int_status; uint32_t fifo_status_reg_value; /* At which RX FIFO the received data is stored. */ uint8_t store_ind = 0; - bool is_canfd_frame = false; /* Read the interrupt on CANFD rx. */ int_status = qtest_readl(qts, can_base_addr + R_ISR_OFFSET) & ISR_RXOK; @@ -207,16 +207,9 @@ static void read_data(QTestState *qts, uint64_t can_base_addr, uint32_t *buf_rx) buf_rx[0] = qtest_readl(qts, can_base_addr + R_RX0_ID_OFFSET); buf_rx[1] = qtest_readl(qts, can_base_addr + R_RX0_DLC_OFFSET); - is_canfd_frame = (buf_rx[1] >> DLC_FD_BIT_SHIFT) & 1; - - if (is_canfd_frame) { - for (int i = 0; i < CANFD_FRAME_SIZE - 2; i++) { - buf_rx[i + 2] = qtest_readl(qts, - can_base_addr + R_RX0_DATA1_OFFSET + 4 * i); - } - } else { - buf_rx[2] = qtest_readl(qts, can_base_addr + R_RX0_DATA1_OFFSET); - buf_rx[3] = qtest_readl(qts, can_base_addr + R_RX0_DATA2_OFFSET); + for (int i = 0; i < frame_size - 2; i++) { + buf_rx[i + 2] = qtest_readl(qts, + can_base_addr + R_RX0_DATA1_OFFSET + 4 * i); } /* Clear the RX interrupt. */ @@ -272,10 +265,6 @@ static void match_rx_tx_data(const uint32_t *buf_tx, const uint32_t *buf_rx, g_assert_cmpint((buf_rx[size] & DLC_FD_BIT_MASK), ==, (buf_tx[size] & DLC_FD_BIT_MASK)); } else { - if (!is_canfd_frame && size == 4) { - break; - } - g_assert_cmpint(buf_rx[size], ==, buf_tx[size]); } @@ -318,7 +307,7 @@ static void test_can_data_transfer(void) write_data(qts, CANFD0_BASE_ADDR, buf_tx, false); send_data(qts, CANFD0_BASE_ADDR); - read_data(qts, CANFD1_BASE_ADDR, buf_rx); + read_data(qts, CANFD1_BASE_ADDR, buf_rx, CAN_FRAME_SIZE); match_rx_tx_data(buf_tx, buf_rx, false); qtest_quit(qts); @@ -358,7 +347,7 @@ static void test_canfd_data_transfer(void) write_data(qts, CANFD0_BASE_ADDR, buf_tx, true); send_data(qts, CANFD0_BASE_ADDR); - read_data(qts, CANFD1_BASE_ADDR, buf_rx); + read_data(qts, CANFD1_BASE_ADDR, buf_rx, CANFD_FRAME_SIZE); match_rx_tx_data(buf_tx, buf_rx, true); qtest_quit(qts); @@ -397,7 +386,7 @@ static void test_can_loopback(void) write_data(qts, CANFD0_BASE_ADDR, buf_tx, true); send_data(qts, CANFD0_BASE_ADDR); - read_data(qts, CANFD0_BASE_ADDR, buf_rx); + read_data(qts, CANFD0_BASE_ADDR, buf_rx, CANFD_FRAME_SIZE); match_rx_tx_data(buf_tx, buf_rx, true); generate_random_data(buf_tx, true); @@ -405,7 +394,7 @@ static void test_can_loopback(void) write_data(qts, CANFD1_BASE_ADDR, buf_tx, true); send_data(qts, CANFD1_BASE_ADDR); - read_data(qts, CANFD1_BASE_ADDR, buf_rx); + read_data(qts, CANFD1_BASE_ADDR, buf_rx, CANFD_FRAME_SIZE); match_rx_tx_data(buf_tx, buf_rx, true); qtest_quit(qts); From patchwork Thu Jul 6 13:25:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 699591 Delivered-To: patch@linaro.org Received: by 2002:adf:fcc5:0:0:0:0:0 with SMTP id f5csp3311917wrs; Thu, 6 Jul 2023 06:26:18 -0700 (PDT) X-Google-Smtp-Source: APBJJlHqLZQnLv9RqQVXCVU2vLj+OtZLQiL1A3ayHyMbzd91CMo3EC8KABtqrXdKMMo7INf4kkTD X-Received: by 2002:a05:622a:487:b0:400:8613:5379 with SMTP id p7-20020a05622a048700b0040086135379mr5866907qtx.8.1688649978111; Thu, 06 Jul 2023 06:26:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1688649978; cv=none; d=google.com; s=arc-20160816; b=Kp1O8EECG9UQ+KqxkRrNwrNLO1hC1F90FvaBnib3bL9Og5PyjtGJxo18u/6In2umcl YOrW2827Anp+mltoLRcu17Wayigijfo6qRFD5pxMSqhm0iO9tk9cNcHeOv0nupXGWVb2 bch9GlEu50j7yHcZFOLDv4+yboylTfGbLlUp2GeFafu1q6wTkRkIDxUY+ZF6D2E0MFfI 6tmqXAkfgPE6ZWMNG+XJ4xHNALGSWXUrEI3HYXdZ19az0R3m+ujisIRcpem213OWERM/ IJU4h8rd5Phqfr97319ROKRd8vFT0DiSBwi75Vy6FY24tAedrKvzhbXaJpyVeqeKyC9R bpZQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=VCXSlv9PBlqNWlv08FHro1sfFi0JArXLUvRt7UUYed4=; fh=bFDrUYhlTVi/QyetgXx/byg2+yO/22Hp9SjwoefyKLk=; b=VrXJQ1xAy49TqD1LVmOtpO+WDI1c8ompEGweYk7uypwkGKg3viu+ZqNYTw09UOsZrY 5NMzksTdS44dC45hzU6t2vN5FDz4aAF6E8/LCT/16dDqov9SswzMm4l8aZR7bcU/hUpu tTT7+tBKYoUOKPxmeI5QesyLF5qQ7EqK3bHj8IhLVUxEV8Euo1djs+Wm7LtD0XkQrF3c zS4pr+rAhSqzUAnmpYzQY3l3sShZsV6J4sHp2DCIGabkF9jWDHFNnpVrK725y4sr7tfc MYOx+apfpsYQMpbr35e4xN80OrXFIHX55ChXddl930oILUzujBVPjfaK7FRiVdCLeefb kLIw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=bncF3xl6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id m9-20020ac85b09000000b004031ae3ae07si920432qtw.28.2023.07.06.06.26.17 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 06 Jul 2023 06:26:18 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=bncF3xl6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qHOzS-0004sg-0a; Thu, 06 Jul 2023 09:25:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qHOzK-0004r0-5q for qemu-devel@nongnu.org; Thu, 06 Jul 2023 09:25:38 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qHOz8-0000sC-73 for qemu-devel@nongnu.org; Thu, 06 Jul 2023 09:25:33 -0400 Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-3fbc5d5742eso7497545e9.3 for ; Thu, 06 Jul 2023 06:25:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1688649918; x=1691241918; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=VCXSlv9PBlqNWlv08FHro1sfFi0JArXLUvRt7UUYed4=; b=bncF3xl6HKSzdozLtx3UWPzc+sXVZ67RW9WYn/J5Mi/oeZnGdgOxGIhBX9a9CU1K06 WF1rDOSDi2c99/eqIgVZQtPQKeW5kJMyY98iKROMU+kaZW1XXM0bEMFelTz20S2/GH6e B4fsmFgccHU+vWO72bjp9bGtZ2WHqdmWeIJGUeVGuqgcMk1tyX0Zwfe96Pp8WT1fV/wW R9aaw2VKMSxMk1unHZGZHS5hvp5ZxwzPcsTvbRUPG3zDSOdMwwnWHKfouPg7rzo30PgL UiZrOHL3iuigrSTH0h4TMjlvcENW0Tf4WakfJEX5tvvHBt7lJeXjPVeBqSUHyfOdp/MH FlsQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688649918; x=1691241918; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VCXSlv9PBlqNWlv08FHro1sfFi0JArXLUvRt7UUYed4=; b=gjlqhfPYrOA4QfKiLoqMp7qb6Eqc0j+80SpeqrLQh+vLZ7K4bXB8lrlTF/fVqV26dY leTB6Ma5RAJxFCoSA3JSj4d/X6bLDo35HMDPIOfY2npt6bVNqZqgeRv14K27HTwRaDxe I+BNuxyKNH3X4h33wBKgngcSsLXy9ONJ262s6Rr0zneAAxUNstCp4cuvTQY5eSxiyX1a 2wf5PQqlil13CpJmenulut+BIebdVDoo4B+TRz/YUOhQk8T9eNF0nlSbZbZpD77oA9zC AoQbv8xiMEFYjSJLoRAWQIzgdJclyJQo8mhuuWfasXzojSPgAMwNeqgg39VZ+6DY5RYf a0Yg== X-Gm-Message-State: ABy/qLa2Mmv6o26yq8SGfCOYo8x4epmseouCmdJHgTjQQkDODCM9yHw9 0JzUAHhwh3tC1EDsAOpdk3ytwL9l92GlPqhP8zE= X-Received: by 2002:a05:600c:ad2:b0:3fa:99d6:4798 with SMTP id c18-20020a05600c0ad200b003fa99d64798mr1470167wmr.37.1688649918155; Thu, 06 Jul 2023 06:25:18 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id s15-20020a5d510f000000b00304adbeeabbsm1856170wrt.99.2023.07.06.06.25.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Jul 2023 06:25:17 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/14] target/arm: gdbstub: Guard M-profile code with CONFIG_TCG Date: Thu, 6 Jul 2023 14:25:07 +0100 Message-Id: <20230706132512.3534397-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230706132512.3534397-1-peter.maydell@linaro.org> References: <20230706132512.3534397-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Fabiano Rosas This code is only relevant when TCG is present in the build. Building with --disable-tcg --enable-xen on an x86 host we get: $ ../configure --target-list=x86_64-softmmu,aarch64-softmmu --disable-tcg --enable-xen $ make -j$(nproc) ... libqemu-aarch64-softmmu.fa.p/target_arm_gdbstub.c.o: in function `m_sysreg_ptr': ../target/arm/gdbstub.c:358: undefined reference to `arm_v7m_get_sp_ptr' ../target/arm/gdbstub.c:361: undefined reference to `arm_v7m_get_sp_ptr' libqemu-aarch64-softmmu.fa.p/target_arm_gdbstub.c.o: in function `arm_gdb_get_m_systemreg': ../target/arm/gdbstub.c:405: undefined reference to `arm_v7m_mrs_control' Signed-off-by: Fabiano Rosas Message-id: 20230628164821.16771-1-farosas@suse.de Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/gdbstub.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index 03b17c814f6..f421c5d041c 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -324,6 +324,7 @@ static int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg) return cpu->dyn_sysreg_xml.num; } +#ifdef CONFIG_TCG typedef enum { M_SYSREG_MSP, M_SYSREG_PSP, @@ -481,6 +482,7 @@ static int arm_gen_dynamic_m_secextreg_xml(CPUState *cs, int orig_base_reg) return cpu->dyn_m_secextreg_xml.num; } #endif +#endif /* CONFIG_TCG */ const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) { @@ -561,6 +563,7 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) arm_gen_dynamic_sysreg_xml(cs, cs->gdb_num_regs), "system-registers.xml", 0); +#ifdef CONFIG_TCG if (arm_feature(env, ARM_FEATURE_M) && tcg_enabled()) { gdb_register_coprocessor(cs, arm_gdb_get_m_systemreg, arm_gdb_set_m_systemreg, @@ -575,4 +578,5 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) } #endif } +#endif /* CONFIG_TCG */ } From patchwork Thu Jul 6 13:25:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 699593 Delivered-To: patch@linaro.org Received: by 2002:adf:fcc5:0:0:0:0:0 with SMTP id f5csp3312018wrs; Thu, 6 Jul 2023 06:26:32 -0700 (PDT) X-Google-Smtp-Source: APBJJlGgPP5VgWZzfsB6rzg7xMquXhDSBsUJN+s/JW6UiqFpBR+DVOm3I6S8zy6jyQFT6WZEzWkp X-Received: by 2002:a05:6358:9195:b0:134:d467:b751 with SMTP id j21-20020a056358919500b00134d467b751mr1887307rwa.21.1688649992598; Thu, 06 Jul 2023 06:26:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1688649992; cv=none; d=google.com; s=arc-20160816; b=m9oilsk3wvSm0DqitldZtBE+NumKiGl3r3jPWM9rBJRPxNSmeuEKYK07ndMXhTDgaj T17MoGR6HftYf0+ODFdVIANQzvTpf3lrOWCYa9EEASQFGRWlx5EIRwi5wjPoH+3VFUYg 90GzrS+nyAa/7vw029XSk3yNylxevVBpM0gPK0tFxkDMrX1NsCbNK3f7aDYqj/HcDW8X +CBw+sAu1RfOTTEg2OKS82Xgvv2NAcLdndS2HNtU5GF7dc7QMxlJlLBiUD+wqfKQQZn9 xHaB0+EOFTTx/F+RgMtfYvDh0XmAYo8UCs5mzudcutDJ1Ymi++dZifoKkz+MTK+yAd+1 EUuA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ljXuz5WdOwWpxwvCuXAlprlm5SQ6d0e/c1sdlk1yWik=; fh=bFDrUYhlTVi/QyetgXx/byg2+yO/22Hp9SjwoefyKLk=; b=Uu9mdd0R9Ryl33BpOHgNcLDsdrbJu1HX+gM/DvHxY7Vjbe28GaFIZfIqu7al1DQNGY 8cISbDp6S4jZ3/+VyhQbJCmsPKK38jKnZvJkhj82yiQQSgGrVK4+aqKWLMjqYev2S3jF Ps2I1nQ3yBvMIaTkWNgRIGan3SvqWgi6apRGR9Y5Fioj69xq1vUoLTvAwkPHwWwVxZBR HEhCTilHOgwoikDbcAEYC4Ergp2memWzbef8vhF1WZivXPs2Lne9o7nQF6EEm1F3+vup ZUn/vdr/pypEayr7OIMtd5bpViaEmFoSuIkMIveiQC99FHMJx++pfMizvwdEaMTBExEQ nhig== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="phB3Kw/H"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 17-20020a05620a079100b007654073efc6si1102427qka.281.2023.07.06.06.26.32 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 06 Jul 2023 06:26:32 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="phB3Kw/H"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qHOza-00057s-Bn; Thu, 06 Jul 2023 09:25:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qHOzK-0004r3-77 for qemu-devel@nongnu.org; Thu, 06 Jul 2023 09:25:38 -0400 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qHOzD-0000sN-Ra for qemu-devel@nongnu.org; Thu, 06 Jul 2023 09:25:34 -0400 Received: by mail-wr1-x436.google.com with SMTP id ffacd0b85a97d-314172bb818so621315f8f.1 for ; Thu, 06 Jul 2023 06:25:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1688649918; x=1691241918; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=ljXuz5WdOwWpxwvCuXAlprlm5SQ6d0e/c1sdlk1yWik=; b=phB3Kw/HaZcD6DKkUoFE+qI5nY9OXcPllIFb0eekj2xo7bO2ykUpxaAhSlGJZMldkB MPBQNP1+NdKV3ga3DUVcLhi2pKKXYhd1acwVLrCpBZ7xs7isf+GcBqO3MltkojHTYxTA 1f23mKz4j+IJsNdj0U1MPY+i6OSBK8ZChaPoi6Ht5GTlomSK/yf5xYVIP92bR5v/xB22 FGbkcnCMf94PjSLwiY09NCLioL2XKHtQvuGJoPMGDLD549JwzBXef6N9F0TwS9VOdNfX xzLt/NF7ArktHYMfMqUZc0T+ojdgua+om4TlIZTlwoNl4RCQK3Rf0YCXk94mldUu8w20 OMfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688649918; x=1691241918; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ljXuz5WdOwWpxwvCuXAlprlm5SQ6d0e/c1sdlk1yWik=; b=Rq/rKVJfbzquT8TQ66JJh5jnXuON+3C4zUJib59C9vxPwdb5Wz4youDSl42Sl0573u je5DrFk2jxCg5aDzBV5qSOvER/+YTyaUtT1/sbQJTwyil9bALpBhKH8I26tTSIE99brF u2lzwgzSZ8c/gA5J2Bss0Cx55LMDT4Lu91AIet9HDAtoQy6+45odyucYlNdgi1dSXbai wKDMiLXESqyLGv1t32IRtgH4PNrHGtoO1Ae0ZInUg04R/MXh2Eb+0uzR/QHhGH73wz0e xVSJwcvuNCcYIj1OFjsSq92RsgLFVM0zuNrfytZ0Q9fbPzs+TUpWHH66A1IeHPbNvurq iBXQ== X-Gm-Message-State: ABy/qLaAeQIcpWJiLiAx0qMH7lmEPy+wc0nAJksxYz1aoMvTdjC4QOyo 2bDyqUM7onnHbv3Bp8wB3wzVLrW2JJAPTvxMruA= X-Received: by 2002:a5d:5913:0:b0:314:350a:6912 with SMTP id v19-20020a5d5913000000b00314350a6912mr1384321wrd.36.1688649918606; Thu, 06 Jul 2023 06:25:18 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id s15-20020a5d510f000000b00304adbeeabbsm1856170wrt.99.2023.07.06.06.25.18 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Jul 2023 06:25:18 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 10/14] hw: arm: allwinner-sramc: Set class_size Date: Thu, 6 Jul 2023 14:25:08 +0100 Message-Id: <20230706132512.3534397-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230706132512.3534397-1-peter.maydell@linaro.org> References: <20230706132512.3534397-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Akihiko Odaki AwSRAMCClass is larger than SysBusDeviceClass so the class size must be advertised accordingly. Fixes: 05def917e1 ("hw: arm: allwinner-sramc: Add SRAM Controller support for R40") Signed-off-by: Akihiko Odaki Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20230628110905.38125-1-akihiko.odaki@daynix.com Signed-off-by: Peter Maydell --- hw/misc/allwinner-sramc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/misc/allwinner-sramc.c b/hw/misc/allwinner-sramc.c index a8b731f8f28..d76c24d081f 100644 --- a/hw/misc/allwinner-sramc.c +++ b/hw/misc/allwinner-sramc.c @@ -159,6 +159,7 @@ static const TypeInfo allwinner_sramc_info = { .parent = TYPE_SYS_BUS_DEVICE, .instance_init = allwinner_sramc_init, .instance_size = sizeof(AwSRAMCState), + .class_size = sizeof(AwSRAMCClass), .class_init = allwinner_sramc_class_init, }; From patchwork Thu Jul 6 13:25:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 699602 Delivered-To: patch@linaro.org Received: by 2002:adf:fcc5:0:0:0:0:0 with SMTP id f5csp3312548wrs; Thu, 6 Jul 2023 06:27:44 -0700 (PDT) X-Google-Smtp-Source: APBJJlFaCE+natuhtuSfIbVBDX07/w8XgBEQuUaF4P36/7fxd/S3vQji9EQx7PHZZ5YrHlMyHtKC X-Received: by 2002:ac8:5d91:0:b0:402:8ecd:8116 with SMTP id d17-20020ac85d91000000b004028ecd8116mr2103197qtx.57.1688650064240; Thu, 06 Jul 2023 06:27:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1688650064; cv=none; d=google.com; s=arc-20160816; b=UeIrnm/L5rUQzoQmF/vjiLNcNK7JwTzkEq14YO2ALOYXPiPNQIU2bakHklx685iPGj CngtguUVHuoyDMpy2qIo5geQ5u7e5jKz+/ioM/i0zrA6S3thilOpjbzem8iduLI1xvV6 4BeZHmOkA5NacNKPiD1lpJ1VVIz8HEq/ClTNtn/seykt0D8hJz91DfciCZ4eR3DRdSfo dgfg1gW4m2Xt0ISn00saNc7+2gvLbGUx5S+frMu6QB1BR6nUujD+wFHR9eZTmzSECURw 5V/mTFHQw95xtD0UAyOBNZyTapbfPXpLXvKU3iR/VNFXVhm2IBiLFaIHjm6VpaWmOCe6 y+jQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=REQxdvHqMD5dtevjQjK3Wnx/HFYuQ118HppndU5qJ5M=; fh=bFDrUYhlTVi/QyetgXx/byg2+yO/22Hp9SjwoefyKLk=; b=L64QeoA5tEpW37mlpHHaySGmvVgr/ob2VLGpFcIbwnfZAeJ+zN/9xNGi5F481JAeJu WPd4i3Uq/Hg97EoBkbKuAlIxmFGZwhOzTIyQLEi0HgQ2FppYLIo9d0WC1SP8rR+y/w2y tuEcfkUG3Fgmqf1B+crYFA+2WmvAfTfcQCTCp+ZieCHlQMdqCx4OVyJrP6pSmCFFnzgA tOGp89UtAD9C5f2/gD7m7q51Baa6Aj4bpfHQIh5ae8TWFpLDbsnsIzcsDedoX+IUP395 NORMiVZzucP2oplIFtHtxhRQ8zZ2n80xBuwXKkh2gW1V6NNDWVGmke9jCP104NsChWB9 fKPQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ooaS1xdb; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id f6-20020a05622a1a0600b003f3a4f93e49si834423qtb.548.2023.07.06.06.27.44 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 06 Jul 2023 06:27:44 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ooaS1xdb; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qHOzd-0005OU-Ia; Thu, 06 Jul 2023 09:25:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qHOzK-0004qw-5n for qemu-devel@nongnu.org; Thu, 06 Jul 2023 09:25:38 -0400 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qHOzE-0000sW-Vi for qemu-devel@nongnu.org; Thu, 06 Jul 2023 09:25:36 -0400 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-3fbac8b01b3so16591105e9.1 for ; Thu, 06 Jul 2023 06:25:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1688649919; x=1691241919; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=REQxdvHqMD5dtevjQjK3Wnx/HFYuQ118HppndU5qJ5M=; b=ooaS1xdbtay9lt4wBuU22N3LBehSNEH0DtKOj55QKGRf+kTMXWdvcJFbUVTlHmjNpW 8eMgjJRy3xyfnUm+hsXmBnF+a9FJo90Y64YFEH+8/laKS4Um5+ipT3hDZmC86dh982FE X6cL84gD6nLCQfam/tEPVSxcCJsV2FFzPwTlyBx/B9BfTIkRfSHgECT3D4Blgxj7gHLj e9wBlEGEj/bNrwc2LSM63fMCylUezoi/OkUS/AC7xaU7hFptrC2Ya7Z2csrJhy41ofBz zDUlJkvkqHizB88jhMFmPMHfyo+l66CatKlk7wrAg/QeHnVXJlXMI2FE5ruV34yVE480 oH8w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688649919; x=1691241919; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=REQxdvHqMD5dtevjQjK3Wnx/HFYuQ118HppndU5qJ5M=; b=bi3Ei8SJ0/dObqVo6miBDUM7U73cOBTlsbWhUOIIhSb5ynMX5QMu52ek/3Y9IGDIxS Ne3nMqWinmPctG9cn5qYGAaTR+BHl1y96B7Qh+/VCV1taFn+LT4O4pGKrrA/sioNqdZw TRy0PeL3FiNQJqVmIrEB40PxRtVZxvQxQSpm2MDj4MchquWVttzdM6sTtLuj8ORXYSG9 V9yi2cJSk+Wwj8iq1dIHphX1vVNs7J80n06AQunO/iZYNVkSYYuX/Xeoy17D0yiF2ugE nshqYO+hR2/GX+I4eFzohITncAbn3Ygem/6OiFa3ZRsVn22elR+3tjQ5kd4G0Sjy4p2x Ob9w== X-Gm-Message-State: ABy/qLbEYq0FerROdjVh0grqLqiO3kvNxyvOrDlbk9O3w/Z5s8KNoV5Q PE7gUO72fGJ24T6SZbVhJMAvh8MQSd2BC25oyP4= X-Received: by 2002:a05:600c:3582:b0:3fa:7bf0:7a81 with SMTP id p2-20020a05600c358200b003fa7bf07a81mr5359604wmq.0.1688649919112; Thu, 06 Jul 2023 06:25:19 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id s15-20020a5d510f000000b00304adbeeabbsm1856170wrt.99.2023.07.06.06.25.18 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Jul 2023 06:25:18 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/14] target/xtensa: Assert that interrupt level is within bounds Date: Thu, 6 Jul 2023 14:25:09 +0100 Message-Id: <20230706132512.3534397-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230706132512.3534397-1-peter.maydell@linaro.org> References: <20230706132512.3534397-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In handle_interrupt() we use level as an index into the interrupt_vector[] array. This is safe because we have checked it against env->config->nlevel, but Coverity can't see that (and it is only true because each CPU config sets its XCHAL_NUM_INTLEVELS to something less than MAX_NLEVELS), so it complains about a possible array overrun (CID 1507131) Add an assert() which will make Coverity happy and catch the unlikely case of a mis-set XCHAL_NUM_INTLEVELS in future. Signed-off-by: Peter Maydell Acked-by: Max Filippov Message-id: 20230623154135.1930261-1-peter.maydell@linaro.org --- target/xtensa/exc_helper.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/xtensa/exc_helper.c b/target/xtensa/exc_helper.c index d4823a65cda..43f6a862de2 100644 --- a/target/xtensa/exc_helper.c +++ b/target/xtensa/exc_helper.c @@ -169,6 +169,9 @@ static void handle_interrupt(CPUXtensaState *env) CPUState *cs = env_cpu(env); if (level > 1) { + /* env->config->nlevel check should have ensured this */ + assert(level < sizeof(env->config->interrupt_vector)); + env->sregs[EPC1 + level - 1] = env->pc; env->sregs[EPS2 + level - 2] = env->sregs[PS]; env->sregs[PS] = From patchwork Thu Jul 6 13:25:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 699600 Delivered-To: patch@linaro.org Received: by 2002:adf:fcc5:0:0:0:0:0 with SMTP id f5csp3312343wrs; Thu, 6 Jul 2023 06:27:15 -0700 (PDT) X-Google-Smtp-Source: APBJJlHURu4K9LscQKib16L1drPUm+cM+E43OiG7/qvYZAqcufFsI7VRTQ4gGJ2sPRKfUmD7d100 X-Received: by 2002:a05:620a:f03:b0:767:5ec0:baad with SMTP id v3-20020a05620a0f0300b007675ec0baadmr2062166qkl.67.1688650034857; Thu, 06 Jul 2023 06:27:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1688650034; cv=none; d=google.com; s=arc-20160816; b=hskeGDz4VIniwl6+jRhOTqjQ3QsT1qQAiBVFJaYk8dqRomrk1axNxgm7cmzNj0MQN0 T482XfSiSqBqAY8zsAKYBJGUwQlq2KC1ZYarh6OoSkCwqqXOcELOXKYy/tNqJquU55kN NYGb2ve4W02WLZd6f54I9rKxbXYDojMcybuYiwQ+mKSPpOgR7w8s79y+Lo2xkearIi2D pxLUmjWMmWz/c9wxEkY+pWR8XRsuo70FnW+40ks9zWpw5nJt5lWNsSktb/H1cUA518Jv Zo1fBYIba9w2F9oTz7YlS53vO4C8rt+/i8IXRzdQoMOmHD+4q8M6hWKFj8EHlF8zzuO1 a+ig== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=U9CeGIttj7agKc+IG3L3VXz8hzpfa363h3PPFaSP8BM=; fh=bFDrUYhlTVi/QyetgXx/byg2+yO/22Hp9SjwoefyKLk=; b=tGY07zirPNOOGwH8scgCENhlJMRwvdIkEjMrQ9kjGYKKFhxXgE3M6I0gCemLil9KXm jyrsd1AkSotez9Rs/qhKcyhSCnZeudh1cpCD6yZaHNT1QJmnraHZFbqGAtMxxPQMLNi5 h8HG92oKBeR86Ha31ILll5qhonKYxqTYn0Od/JuyWz2IIxnrYWqjJmMXjkpf7l2gBv2s exkjsMhEwrdie7loEvmH8DJ3aUwCbHMDlBm+GGmgUTu/DPofYna5BxF9Fu6gQOC8hVJR oErLuQ+z0eqQYDfpJgaP6W2N+OXuhUH7g4zSr1iat+2OSg2AX11O/saxZbvTfqfNAgZD RlRg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hGr+Oivw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id cx16-20020a05620a51d000b00767124154a4si1034383qkb.262.2023.07.06.06.27.14 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 06 Jul 2023 06:27:14 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hGr+Oivw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qHOzb-0005HS-Td; Thu, 06 Jul 2023 09:25:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qHOzM-0004re-1E for qemu-devel@nongnu.org; Thu, 06 Jul 2023 09:25:40 -0400 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qHOzE-0000sp-Ud for qemu-devel@nongnu.org; Thu, 06 Jul 2023 09:25:36 -0400 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-3fbc244d307so7637225e9.1 for ; Thu, 06 Jul 2023 06:25:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1688649919; x=1691241919; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=U9CeGIttj7agKc+IG3L3VXz8hzpfa363h3PPFaSP8BM=; b=hGr+Oivwm0S4HtGd3ZiUwg5XZK2WTrzCsqT5IqO3tPDxtj6kDwL5iPz+DmnRUh40fC 5UaY7iqBHdnTzjUioh1PqgY8hRZN/uXPAKdQ0pP9nQDNSU8jdB4xZ55LkeqK+1ep5rPC LgcllW4V/OjtoJ3I9b6fdfw89kMfGYZw1fgK7Zs+AHoc8EI6cBYxzrNrqFSE7CjSFkjk JwtmIHqQLCLosbVOTsU1pMK1HLedbI2o25DQ4RyxyuDh9J5o45Es1YoU26J53G+cNVWl Xp/57OpguJwT85h3my/eyi6UEm3dGeWvz8NiGVioIEpydWRpVOhPCAS0GUdVmmJlN4Ss HadA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688649919; x=1691241919; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=U9CeGIttj7agKc+IG3L3VXz8hzpfa363h3PPFaSP8BM=; b=e+8y02PSJuZ3s7S3ZqiyVpZClvUjNnJrAQJeluRf3AeaktaAss7RLyD5f2pf7g84DG Lo1biglsXW40oKO9IifVRN4qlETfZP7Wm75C+kiXl2UFiffHgkHIVFQYvt3QPwK9FE+M A6cdL1dBfVrnQAR4kb1abC41Pa9Ehat4u6z/aLeNSm/xQV/7mT58smNxs4i7h5dBhrVE 4qmVDaCFKxb+fgP1XHTMf+Yq/SviJGGX6MuURw8nK5nseDJinT6eCJSMlcfU4kt1d/X+ gifUdeSd7JwG4zDquAZu23hWxUdPi3wR51cVIFl28XC5IimZCuSCB2NzZIfM3zxfCVKU DTsA== X-Gm-Message-State: ABy/qLbAHFZ+bgYLTdad7NK3sipdv3jwladVDHdt7NNCnkOzzK0X/W5Y 6nnSXfO8Bq+aoS0PqzeuyEPXGs0n1/EFNbrW628= X-Received: by 2002:a7b:c043:0:b0:3f9:c04:e76c with SMTP id u3-20020a7bc043000000b003f90c04e76cmr1449802wmc.28.1688649919505; Thu, 06 Jul 2023 06:25:19 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id s15-20020a5d510f000000b00304adbeeabbsm1856170wrt.99.2023.07.06.06.25.19 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Jul 2023 06:25:19 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/14] target/arm: Suppress more TCG unimplemented features in ID registers Date: Thu, 6 Jul 2023 14:25:10 +0100 Message-Id: <20230706132512.3534397-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230706132512.3534397-1-peter.maydell@linaro.org> References: <20230706132512.3534397-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org We already squash the ID register field for FEAT_SPE (the Statistical Profiling Extension) because TCG does not implement it and if we advertise it to the guest the guest will crash trying to look at non-existent system registers. Do the same for some other features which a real hardware Neoverse-V1 implements but which TCG doesn't: * FEAT_TRF (Self-hosted Trace Extension) * Trace Macrocell system register access * Memory mapped trace * FEAT_AMU (Activity Monitors Extension) * FEAT_MPAM (Memory Partitioning and Monitoring Extension) * FEAT_NV (Nested Virtualization) Most of these, like FEAT_SPE, are "introspection/trace" type features which QEMU is unlikely to ever implement. The odd-one-out here is FEAT_NV -- we could implement that and at some point we probably will. Signed-off-by: Peter Maydell Message-id: 20230704130647.2842917-2-peter.maydell@linaro.org Reviewed-by: Alex Bennée Reviewed-by: Richard Henderson --- target/arm/cpu.c | 33 +++++++++++++++++++++++++++++---- 1 file changed, 29 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 822efa5b2c1..69e2bde3c2d 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2069,13 +2069,38 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) if (tcg_enabled()) { /* - * Don't report the Statistical Profiling Extension in the ID - * registers, because TCG doesn't implement it yet (not even a - * minimal stub version) and guests will fall over when they - * try to access the non-existent system registers for it. + * Don't report some architectural features in the ID registers + * where TCG does not yet implement it (not even a minimal + * stub version). This avoids guests falling over when they + * try to access the non-existent system registers for them. */ + /* FEAT_SPE (Statistical Profiling Extension) */ cpu->isar.id_aa64dfr0 = FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMSVER, 0); + /* FEAT_TRF (Self-hosted Trace Extension) */ + cpu->isar.id_aa64dfr0 = + FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEFILT, 0); + cpu->isar.id_dfr0 = + FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, TRACEFILT, 0); + /* Trace Macrocell system register access */ + cpu->isar.id_aa64dfr0 = + FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEVER, 0); + cpu->isar.id_dfr0 = + FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPTRC, 0); + /* Memory mapped trace */ + cpu->isar.id_dfr0 = + FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, MMAPTRC, 0); + /* FEAT_AMU (Activity Monitors Extension) */ + cpu->isar.id_aa64pfr0 = + FIELD_DP64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, AMU, 0); + cpu->isar.id_pfr0 = + FIELD_DP32(cpu->isar.id_pfr0, ID_PFR0, AMU, 0); + /* FEAT_MPAM (Memory Partitioning and Monitoring Extension) */ + cpu->isar.id_aa64pfr0 = + FIELD_DP64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, MPAM, 0); + /* FEAT_NV (Nested Virtualization) */ + cpu->isar.id_aa64mmfr2 = + FIELD_DP64(cpu->isar.id_aa64mmfr2, ID_AA64MMFR2, NV, 0); } /* MPU can be configured out of a PMSA CPU either by setting has-mpu From patchwork Thu Jul 6 13:25:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 699597 Delivered-To: patch@linaro.org Received: by 2002:adf:fcc5:0:0:0:0:0 with SMTP id f5csp3312273wrs; Thu, 6 Jul 2023 06:27:07 -0700 (PDT) X-Google-Smtp-Source: APBJJlGgR7zHlVm/o7oJWheS9L00GYTnXL51Rwbh+38pxsr5INMuk5Z10sRUD/qC041hulcNr4M+ X-Received: by 2002:a05:620a:4146:b0:767:7d86:b7fe with SMTP id k6-20020a05620a414600b007677d86b7femr2308721qko.6.1688650026909; Thu, 06 Jul 2023 06:27:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1688650026; cv=none; d=google.com; s=arc-20160816; b=MVAjyvAlWMXcpltrHpmr+fTQhKFi/UjbWKVIp2vKlfLuf4CQGLN8cMGT7AvhP1Ul/2 p0/mwmmVVL99PVAU5VWXWLlgt6Je0VxIT/5UhzXnV6hJGiY1Wvbd8+2QSojkmo2/U3TP wkDpdWzKOg1aPO6n63T3yiP5iB1sTXbgdBLQ/eatDDWK9lTtzkzKJuZoD/wgq1wo5DLs ncEig36shTxYfOPYnQsJoRW/dt8MZv4a77/r9QVGDzC9JQy6aDd9QS9LaJkCodEx2E9C nXo9Zs4d0w0gCjp8yIMaCMi7wxzSuFA2vCUdtpEeIRRSLY8wn1p3gz21GQeu/cmuCyML VGYw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=gH8Mkhg5ZXAgRegRdPk6KSzUN9/vkxemaNfVM/X3CsQ=; fh=bFDrUYhlTVi/QyetgXx/byg2+yO/22Hp9SjwoefyKLk=; b=mOntmlO613Jg+tQLtB98LXUtxTp41LfdtjfA4b2Vs51zLtJr89Y1pYC3tbmvWSyj0i 5pJyx+Wm9aEzXcOSaMEW36V6sNfuYSaSvBLqR4jN1O7G4wB9k7wz3MRQr3u4OS+U5pb2 ui6uue9mCokcqcbdMC6k2VQKbil+soLQ0lHTUOBMgX7RMxayWsolOQaQdbH0qhM0lXaw N+AeeiJ0wTvZUxdZKga7ZEIZWLi9iIinLMxw7LexLXV+f+SwqsDP3lCGXbEVVN6hY4bN ev3YHow0gSpsWFAqfhLEOosd6juFgdls33waodpLD69sP05Gb/jDUXSFzmZzpQcYtOjh 1TLA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=K1vNkFIP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id j12-20020a05620a000c00b0076397e161eesi1088458qki.190.2023.07.06.06.27.06 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 06 Jul 2023 06:27:06 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=K1vNkFIP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qHOzN-0004s0-A4; Thu, 06 Jul 2023 09:25:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qHOzK-0004qu-57 for qemu-devel@nongnu.org; Thu, 06 Jul 2023 09:25:38 -0400 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qHOz8-0000t2-7K for qemu-devel@nongnu.org; Thu, 06 Jul 2023 09:25:35 -0400 Received: by mail-wr1-x42e.google.com with SMTP id ffacd0b85a97d-3143b88faebso665896f8f.3 for ; Thu, 06 Jul 2023 06:25:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1688649920; x=1691241920; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=gH8Mkhg5ZXAgRegRdPk6KSzUN9/vkxemaNfVM/X3CsQ=; b=K1vNkFIPr/rrNkWnLvlDt6PCVSD9If7pL5lG7iAWe9ObT3niiKjKtus3shHyktBEnU k1ruK3hu1JBZdjLyww6yzpnllA4pMXxaKT4vtIlnXiXHI8fihoEj9TiNBjXfi/1WSn/A +Uik0peP505LMZOHaSjVuP8yQQIrYuJq+j6dKtxt4QThoW911HVyVFigsfPVLvIoIfSA MDG5PHg7XsXbEqqwC+G076+NPkPj16t6dEJ8E9xzg2vv2ZBJEU0EWpxWtp3lhMDZps0T 2WIkRqP8Lczx0NzcZ+iwlL80RBaycBOIofFoxx0jlCaxwSl2Wi8z/vG2eAcVJFevaZ3X jkgw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688649920; x=1691241920; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gH8Mkhg5ZXAgRegRdPk6KSzUN9/vkxemaNfVM/X3CsQ=; b=RS/avya4BREBSuJKU/vT4Y7J+QTFteNYbBqylbSOjvwTTfqjBvrldCvHT6r/97lgn3 a9k0O/3wAdSlOYpOEi6eEIE/FtLigZ6KxnmknGR90VX/EteSJ8szV/CPOGRhCX81gvxW 6GOUPLYCQNkrs1p1Sj7FbpUQlG08AunruTSjaSrryTr50fzD1KYcp6v9utmJ4Z+LEynD la5uxqgvinYFdjtLAiM2WaRh+C1qKKxE6nr1sWCYVjcDbxytDjt7Q+zVSCRfD0/GOO7v W9oQHCQwLwHRNqMif5NkuDfjhTwhgiahFcJDfquTHdhRia05kX1jC5a1uvjUpLWuQe0D gd+A== X-Gm-Message-State: ABy/qLbkfFZX3O6+E81LRDcXKbL9B2I0FNs/X4ex/EMcQ2I9NBaB3Z2K 5CtiJgxyFnzEe6tthAU8/YOawQk7a4sPdiy0E4c= X-Received: by 2002:adf:e9d1:0:b0:313:e88d:e6cf with SMTP id l17-20020adfe9d1000000b00313e88de6cfmr1562928wrn.69.1688649919894; Thu, 06 Jul 2023 06:25:19 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id s15-20020a5d510f000000b00304adbeeabbsm1856170wrt.99.2023.07.06.06.25.19 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Jul 2023 06:25:19 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/14] target/arm: Define neoverse-v1 Date: Thu, 6 Jul 2023 14:25:11 +0100 Message-Id: <20230706132512.3534397-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230706132512.3534397-1-peter.maydell@linaro.org> References: <20230706132512.3534397-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Now that we have implemented support for FEAT_LSE2, we can define a CPU model for the Neoverse-V1, and enable it for the virt and sbsa-ref boards. Signed-off-by: Peter Maydell Message-id: 20230704130647.2842917-3-peter.maydell@linaro.org Reviewed-by: Alex Bennée Reviewed-by: Richard Henderson --- docs/system/arm/virt.rst | 1 + hw/arm/sbsa-ref.c | 1 + hw/arm/virt.c | 1 + target/arm/tcg/cpu64.c | 128 +++++++++++++++++++++++++++++++++++++++ 4 files changed, 131 insertions(+) diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst index 1cab33f02e3..51cdac68410 100644 --- a/docs/system/arm/virt.rst +++ b/docs/system/arm/virt.rst @@ -61,6 +61,7 @@ Supported guest CPU types: - ``a64fx`` (64-bit) - ``host`` (with KVM only) - ``neoverse-n1`` (64-bit) +- ``neoverse-v1`` (64-bit) - ``max`` (same as ``host`` for KVM; best possible emulation with TCG) Note that the default is ``cortex-a15``, so for an AArch64 guest you must diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index 1a8519b868f..c2e0a9fa1a0 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -153,6 +153,7 @@ static const char * const valid_cpus[] = { ARM_CPU_TYPE_NAME("cortex-a57"), ARM_CPU_TYPE_NAME("cortex-a72"), ARM_CPU_TYPE_NAME("neoverse-n1"), + ARM_CPU_TYPE_NAME("neoverse-v1"), ARM_CPU_TYPE_NAME("max"), }; diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 3196db556ee..796181e1698 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -214,6 +214,7 @@ static const char *valid_cpus[] = { ARM_CPU_TYPE_NAME("cortex-a76"), ARM_CPU_TYPE_NAME("a64fx"), ARM_CPU_TYPE_NAME("neoverse-n1"), + ARM_CPU_TYPE_NAME("neoverse-v1"), #endif ARM_CPU_TYPE_NAME("cortex-a53"), ARM_CPU_TYPE_NAME("cortex-a57"), diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 6fec2d8a57a..8019f00bc3f 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -502,6 +502,31 @@ static void define_neoverse_n1_cp_reginfo(ARMCPU *cpu) define_arm_cp_regs(cpu, neoverse_n1_cp_reginfo); } +static const ARMCPRegInfo neoverse_v1_cp_reginfo[] = { + { .name = "CPUECTLR2_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 5, + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "CPUPPMCR_EL3", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 2, .opc2 = 0, + .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "CPUPPMCR2_EL3", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 2, .opc2 = 1, + .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "CPUPPMCR3_EL3", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 2, .opc2 = 6, + .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, +}; + +static void define_neoverse_v1_cp_reginfo(ARMCPU *cpu) +{ + /* + * The Neoverse V1 has all of the Neoverse N1's IMPDEF + * registers and a few more of its own. + */ + define_arm_cp_regs(cpu, neoverse_n1_cp_reginfo); + define_arm_cp_regs(cpu, neoverse_v1_cp_reginfo); +} + static void aarch64_neoverse_n1_initfn(Object *obj) { ARMCPU *cpu = ARM_CPU(obj); @@ -573,6 +598,108 @@ static void aarch64_neoverse_n1_initfn(Object *obj) define_neoverse_n1_cp_reginfo(cpu); } +static void aarch64_neoverse_v1_initfn(Object *obj) +{ + ARMCPU *cpu = ARM_CPU(obj); + + cpu->dtb_compatible = "arm,neoverse-v1"; + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_AARCH64); + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); + set_feature(&cpu->env, ARM_FEATURE_EL2); + set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_PMU); + + /* Ordered by 3.2.4 AArch64 registers by functional group */ + cpu->clidr = 0x82000023; + cpu->ctr = 0xb444c004; /* With DIC and IDC set */ + cpu->dcz_blocksize = 4; + cpu->id_aa64afr0 = 0x00000000; + cpu->id_aa64afr1 = 0x00000000; + cpu->isar.id_aa64dfr0 = 0x000001f210305519ull; + cpu->isar.id_aa64dfr1 = 0x00000000; + cpu->isar.id_aa64isar0 = 0x1011111110212120ull; /* with FEAT_RNG */ + cpu->isar.id_aa64isar1 = 0x0111000001211032ull; + cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull; + cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull; + cpu->isar.id_aa64mmfr2 = 0x0220011102101011ull; + cpu->isar.id_aa64pfr0 = 0x1101110120111112ull; /* GIC filled in later */ + cpu->isar.id_aa64pfr1 = 0x0000000000000020ull; + cpu->id_afr0 = 0x00000000; + cpu->isar.id_dfr0 = 0x15011099; + cpu->isar.id_isar0 = 0x02101110; + cpu->isar.id_isar1 = 0x13112111; + cpu->isar.id_isar2 = 0x21232042; + cpu->isar.id_isar3 = 0x01112131; + cpu->isar.id_isar4 = 0x00010142; + cpu->isar.id_isar5 = 0x11011121; + cpu->isar.id_isar6 = 0x01100111; + cpu->isar.id_mmfr0 = 0x10201105; + cpu->isar.id_mmfr1 = 0x40000000; + cpu->isar.id_mmfr2 = 0x01260000; + cpu->isar.id_mmfr3 = 0x02122211; + cpu->isar.id_mmfr4 = 0x01021110; + cpu->isar.id_pfr0 = 0x21110131; + cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */ + cpu->isar.id_pfr2 = 0x00000011; + cpu->midr = 0x411FD402; /* r1p2 */ + cpu->revidr = 0; + + /* + * The Neoverse-V1 r1p2 TRM lists 32-bit format CCSIDR_EL1 values, + * but also says it implements CCIDX, which means they should be + * 64-bit format. So we here use values which are based on the textual + * information in chapter 2 of the TRM (and on the fact that + * sets * associativity * linesize == cachesize). + * + * The 64-bit CCSIDR_EL1 format is: + * [55:32] number of sets - 1 + * [23:3] associativity - 1 + * [2:0] log2(linesize) - 4 + * so 0 == 16 bytes, 1 == 32 bytes, 2 == 64 bytes, etc + * + * L1: 4-way set associative 64-byte line size, total size 64K, + * so sets is 256. + * + * L2: 8-way set associative, 64 byte line size, either 512K or 1MB. + * We pick 1MB, so this has 2048 sets. + * + * L3: No L3 (this matches the CLIDR_EL1 value). + */ + cpu->ccsidr[0] = 0x000000ff0000001aull; /* 64KB L1 dcache */ + cpu->ccsidr[1] = 0x000000ff0000001aull; /* 64KB L1 icache */ + cpu->ccsidr[2] = 0x000007ff0000003aull; /* 1MB L2 cache */ + + /* From 3.2.115 SCTLR_EL3 */ + cpu->reset_sctlr = 0x30c50838; + + /* From 3.4.8 ICC_CTLR_EL3 and 3.4.23 ICH_VTR_EL2 */ + cpu->gic_num_lrs = 4; + cpu->gic_vpribits = 5; + cpu->gic_vprebits = 5; + cpu->gic_pribits = 5; + + /* From 3.5.1 AdvSIMD AArch64 register summary */ + cpu->isar.mvfr0 = 0x10110222; + cpu->isar.mvfr1 = 0x13211111; + cpu->isar.mvfr2 = 0x00000043; + + /* From 3.7.5 ID_AA64ZFR0_EL1 */ + cpu->isar.id_aa64zfr0 = 0x0000100000100000; + cpu->sve_vq.supported = (1 << 0) /* 128bit */ + | (1 << 1); /* 256bit */ + + /* From 5.5.1 AArch64 PMU register summary */ + cpu->isar.reset_pmcr_el0 = 0x41213000; + + define_neoverse_v1_cp_reginfo(cpu); + + aarch64_add_pauth_properties(obj); + aarch64_add_sve_properties(obj); +} + /* * -cpu max: a CPU with as many features enabled as our emulation supports. * The version of '-cpu max' for qemu-system-arm is defined in cpu32.c; @@ -763,6 +890,7 @@ static const ARMCPUInfo aarch64_cpus[] = { { .name = "cortex-a76", .initfn = aarch64_a76_initfn }, { .name = "a64fx", .initfn = aarch64_a64fx_initfn }, { .name = "neoverse-n1", .initfn = aarch64_neoverse_n1_initfn }, + { .name = "neoverse-v1", .initfn = aarch64_neoverse_v1_initfn }, }; static void aarch64_cpu_register_types(void) From patchwork Thu Jul 6 13:25:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 699594 Delivered-To: patch@linaro.org Received: by 2002:adf:fcc5:0:0:0:0:0 with SMTP id f5csp3312111wrs; Thu, 6 Jul 2023 06:26:44 -0700 (PDT) X-Google-Smtp-Source: APBJJlEWbZT29AIFlH1TfPiUF7scJSMf7tLaX43kca3qFLNR5gq3z3nnU+vgBU2KYLzlUawVqEae X-Received: by 2002:a05:622a:1704:b0:400:81a4:2ab3 with SMTP id h4-20020a05622a170400b0040081a42ab3mr2420535qtk.22.1688650004675; Thu, 06 Jul 2023 06:26:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1688650004; cv=none; d=google.com; s=arc-20160816; b=VqA8pvEgZQI4XYkMy+YsJCL3oe7AzPa+J/ihuDs5JRcM06iESw8jR3omiYDjpBY7+M ajxkZkaGedKXNfQdXThzwd+NbNAG+YTfHi1rfhU+qxW9XtOt2ABRiCb6Ay6XRdaauNsf 250AleSbAtaJF5N46dOB3U7qOyVcvlGv0zyKiW1P4dmyXNWYRLihX+OGirYFTpfX5OvA i+Fd5v9UyzKUA/NOvyOvEIwfej7CLLwBK7fcEsAIJDdbW720/Jbsk/Z5+LkdChWTtLMi 7MYPuub/248EhHrzQtPu/pvkgC5xlRPASDQ25n2G6Y7SOVXx8di8nFREZ9xzttNzU4cx VU3g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=1ed/BVXYFJwYxRqofY4hhjASHZDBl9OIQc2oGaDlpXM=; fh=bFDrUYhlTVi/QyetgXx/byg2+yO/22Hp9SjwoefyKLk=; b=Qq55vIK25ya3Ycby0hYbDI9B8XSjhtj0TMuLUvQzvvyN9uzKU6Qyzy/NR3SB5ZD5EQ xuSP3fajZk3UKxisaCUX+DXh4ELyS8Fs2WwCm/LYIP+N1R87kxJMnb4zpA4NcPNAmPMd TFqFwgmU4PNrlR3r3vQoZroc73+tZZQviggRfvtP0Tc+90+cq53qszNi8PEIgxyFjILK 43q+BJEJi/ESXRkdQTqZyfmiNZy4lWQ+VRuLcQfFHzU6aM0e35jj0nx+K2pQ+aM8gHGE ZfAP+9f4TIQaQO/HFAsPu0VSkRRgfIDKhSqBmPvnIP7zLjJtdkJDgKkDa7gmCbhcu1AT EsiA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XRA5eP4x; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id bp38-20020a05622a1ba600b003f8a00e78ecsi882940qtb.5.2023.07.06.06.26.44 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 06 Jul 2023 06:26:44 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XRA5eP4x; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qHOze-0005UB-PY; Thu, 06 Jul 2023 09:25:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qHOzO-0004s7-QH for qemu-devel@nongnu.org; Thu, 06 Jul 2023 09:25:45 -0400 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qHOzK-0000tA-Fh for qemu-devel@nongnu.org; Thu, 06 Jul 2023 09:25:41 -0400 Received: by mail-wr1-x42c.google.com with SMTP id ffacd0b85a97d-307d20548adso637748f8f.0 for ; Thu, 06 Jul 2023 06:25:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1688649920; x=1691241920; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=1ed/BVXYFJwYxRqofY4hhjASHZDBl9OIQc2oGaDlpXM=; b=XRA5eP4xPae0paRyo+1i6wtVNwJES6mHV6mzcrUPcQAOuOAop1eMPINMhddUgGB3LZ OxsC/EmPafoltOPTnGL+1WX4GhqhAqL1Y2llA6nowA8HBn7CzmYB29eSQzxQlcP4DEo/ I1NtcZJUV8Wq625xgF2H+eylfoBinqKuqZF2iLRC9IHKL8v6ZPfOKkvXqu++UMaK8soa /9ODKLUwpdv9ljtjxC3W8+9YigV2cYIaK4kH/wngMycft8rSy0jhq1/3UjCAioPzVuR9 bEGBrivMsSf0Ilhh4xeNIJ5afEBTGkiUowjHAJ0enzoGFaG08+KAHbI/+Xv0aQmZk+dt QPTw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688649920; x=1691241920; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1ed/BVXYFJwYxRqofY4hhjASHZDBl9OIQc2oGaDlpXM=; b=lFB+5FxW8C4455VTYzuBRxp4BurxxgP7D/BNnZrckPJaRSSu4Nb2wn7UcQWeoyWin7 9qYj28vtEKIHDP+4ElWQ66+fFqb7QWHZmag3Izy47WWG52JmoNeZ5CHmhLygaB3aqdYw iHydHCg5VyD0VVgsCtfhK3nQUVl0a7Y89oBPD05/hk3idXulmZf7uux93+/cwQDapwvJ tyTKSM/21SngJ8JcSA56wgbqDMnMV7VEVX5VhucHf2KG2oDRQiHZlXGiv+HB4Obac3+H MC72+Rbu4WcSLxR5lFZcD2BT16HqoRE7n4HdsJI2YASqUmWRm4HKRhdZamNSIbdDOp2H zPsA== X-Gm-Message-State: ABy/qLYwtCi/K0Y/PDrJ/XTmHgo8/JjWMxoM6GjnnvgNg1S67vRfuawi L5LB0dYshyvCeAgl/c2Tx/s/J/bjNfoCYflfgq8= X-Received: by 2002:a5d:48d2:0:b0:30f:c42e:3299 with SMTP id p18-20020a5d48d2000000b0030fc42e3299mr1269486wrs.60.1688649920276; Thu, 06 Jul 2023 06:25:20 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id s15-20020a5d510f000000b00304adbeeabbsm1856170wrt.99.2023.07.06.06.25.20 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Jul 2023 06:25:20 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/14] target/arm: Avoid over-length shift in arm_cpu_sve_finalize() error case Date: Thu, 6 Jul 2023 14:25:12 +0100 Message-Id: <20230706132512.3534397-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230706132512.3534397-1-peter.maydell@linaro.org> References: <20230706132512.3534397-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org If you build QEMU with the clang sanitizer enabled, you can see it fire when running the arm-cpu-features test: $ QTEST_QEMU_BINARY=./build/arm-clang/qemu-system-aarch64 ./build/arm-clang/tests/qtest/arm-cpu-features [...] ../../target/arm/cpu64.c:125:19: runtime error: shift exponent 64 is too large for 64-bit type 'unsigned long long' [...] This happens because the user can specify some incorrect SVE properties that result in our calculating a max_vq of 0. We catch this and error out, but before we do that we calculate vq_mask = MAKE_64BIT_MASK(0, max_vq);$ and the MAKE_64BIT_MASK() call is only valid for lengths that are greater than zero, so we hit the undefined behaviour. Change the logic so that if max_vq is 0 we specifically set vq_mask to 0 without going via MAKE_64BIT_MASK(). This lets us drop the max_vq check from the error-exit logic, because if max_vq is 0 then vq_map must now be 0. The UB only happens in the case where the user passed us an incorrect set of SVE properties, so it's not a big problem in practice. Signed-off-by: Peter Maydell Reviewed-by: Alex Bennée Reviewed-by: Richard Henderson Message-id: 20230704154332.3014896-1-peter.maydell@linaro.org --- target/arm/cpu64.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 6eaf8e32cfa..6012e4ef549 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -122,10 +122,10 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) vq = ctz32(tmp) + 1; max_vq = vq <= ARM_MAX_VQ ? vq - 1 : ARM_MAX_VQ; - vq_mask = MAKE_64BIT_MASK(0, max_vq); + vq_mask = max_vq > 0 ? MAKE_64BIT_MASK(0, max_vq) : 0; vq_map = vq_supported & ~vq_init & vq_mask; - if (max_vq == 0 || vq_map == 0) { + if (vq_map == 0) { error_setg(errp, "cannot disable sve%d", vq * 128); error_append_hint(errp, "Disabling sve%d results in all " "vector lengths being disabled.\n",