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[83.34.200.30]) by smtp.gmail.com with ESMTPSA id d18sm42594476wrb.90.2019.06.25.09.47.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 25 Jun 2019 09:47:38 -0700 (PDT) From: Jorge Ramirez-Ortiz To: jorge.ramirez-ortiz@linaro.org, sboyd@kernel.org, bjorn.andersson@linaro.org, david.brown@linaro.org, jassisinghbrar@gmail.com, mark.rutland@arm.com, mturquette@baylibre.com, robh+dt@kernel.org, will.deacon@arm.com, arnd@arndb.de, horms+renesas@verge.net.au, heiko@sntech.de, sibis@codeaurora.org, enric.balletbo@collabora.com, jagan@amarulasolutions.com, olof@lixom.net Cc: vkoul@kernel.org, niklas.cassel@linaro.org, georgi.djakov@linaro.org, amit.kucheria@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-msm@vger.kernel.org, khasim.mohammed@linaro.org Subject: [PATCH v3 01/14] clk: qcom: gcc: limit GPLL0_AO_OUT operating frequency Date: Tue, 25 Jun 2019 18:47:20 +0200 Message-Id: <20190625164733.11091-2-jorge.ramirez-ortiz@linaro.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190625164733.11091-1-jorge.ramirez-ortiz@linaro.org> References: <20190625164733.11091-1-jorge.ramirez-ortiz@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Limit the GPLL0_AO_OUT_MAIN operating frequency as per its hardware specifications. Co-developed-by: Niklas Cassel Signed-off-by: Niklas Cassel Signed-off-by: Jorge Ramirez-Ortiz Acked-by: Stephen Boyd --- drivers/clk/qcom/clk-alpha-pll.c | 8 ++++++++ drivers/clk/qcom/clk-alpha-pll.h | 1 + drivers/clk/qcom/gcc-qcs404.c | 2 +- 3 files changed, 10 insertions(+), 1 deletion(-) -- 2.21.0 diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index 0ced4a5a9a17..ef51f302bdf0 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -730,6 +730,14 @@ static long alpha_pll_huayra_round_rate(struct clk_hw *hw, unsigned long rate, return alpha_huayra_pll_round_rate(rate, *prate, &l, &a); } +const struct clk_ops clk_alpha_pll_fixed_ops = { + .enable = clk_alpha_pll_enable, + .disable = clk_alpha_pll_disable, + .is_enabled = clk_alpha_pll_is_enabled, + .recalc_rate = clk_alpha_pll_recalc_rate, +}; +EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_ops); + const struct clk_ops clk_alpha_pll_ops = { .enable = clk_alpha_pll_enable, .disable = clk_alpha_pll_disable, diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h index 66755f0f84fc..6b4eb74706b4 100644 --- a/drivers/clk/qcom/clk-alpha-pll.h +++ b/drivers/clk/qcom/clk-alpha-pll.h @@ -104,6 +104,7 @@ struct alpha_pll_config { }; extern const struct clk_ops clk_alpha_pll_ops; +extern const struct clk_ops clk_alpha_pll_fixed_ops; extern const struct clk_ops clk_alpha_pll_hwfsm_ops; extern const struct clk_ops clk_alpha_pll_postdiv_ops; extern const struct clk_ops clk_alpha_pll_huayra_ops; diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c index 29cf464dd2c8..18c6563889f3 100644 --- a/drivers/clk/qcom/gcc-qcs404.c +++ b/drivers/clk/qcom/gcc-qcs404.c @@ -330,7 +330,7 @@ static struct clk_alpha_pll gpll0_ao_out_main = { .parent_names = (const char *[]){ "cxo" }, .num_parents = 1, .flags = CLK_IS_CRITICAL, - .ops = &clk_alpha_pll_ops, + .ops = &clk_alpha_pll_fixed_ops, }, }, }; From patchwork Tue Jun 25 16:47:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jorge Ramirez-Ortiz X-Patchwork-Id: 167737 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp5779404ilk; Tue, 25 Jun 2019 09:47:51 -0700 (PDT) X-Google-Smtp-Source: APXvYqwM+bOflYmBGcU4r6c5SW7Y/7qtxZcLSEEOBpu1MF9mSYlLqJaz/Q4dNqp0VlSvNP+X5KIc X-Received: by 2002:a17:90a:2627:: with SMTP id l36mr33898712pje.71.1561481271107; Tue, 25 Jun 2019 09:47:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1561481271; cv=none; d=google.com; s=arc-20160816; b=q3DT67D+6qS50MgySUQnZESI8oiQI19+PFsX0QoxFk+T+/VBGO6f0mZRkInIedB0o1 rce3Chg456E3PaLxkVzM0OLFa19GsuORfgiON5nWc1kM7VpUS6LmmpZJuiHv6fy9BBBw gGyUfUQPQKFP2YZbcwvwiYdKaX7LsieTBmfVEAUfNbmrG1ZzbplJRZXHPWWscRQfWXcR SHOjM9Oy1IV9nGv7Yny0YTC0UW3rZ5kQm4ILmdVsJxUirrAONgkDDYwV3C9OkzLMW5Js 9cGbuEml8i/IyfRNLbZiF4MbVmgMC6y/uZvTHr7RdsQ+Zl2+UFnOeb5O1fAnCW1wEAjy gjcQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=9dd7VfnDPDvx2vEwLGJ7RznkwWv5Ux/A/r7vpBAXcyw=; b=ABPIau9Lb4REVdcIgQRd6321NzVpfyyD+JBgs29NYuqTb4Bc2VjJ68IMugiE6nA4el 5uJX3Q3PgWzfCo/9dkBiFxn4+5wyd2m+B2Hcm1wCAfYdjnNAQm3qOSNOYLvNRDAIOTJz txkKbmFnm+14aENQIYVuOIuCpusD5C0k5lFXs3sve9B6/aPuUdiZD2hiNHz5W9CaEAld DAHN6i4F1KvRHnzjuxE+5kikAJUCRsl5mjM4lHuEgSHQHTIwMEHN3g+t51ZCQhY2BBh7 k84M0+jI9cceXtul1YAGyakNd+5o3/SwM7u2+XO7l2Qb27Nydw2xJqwFaGpN8rYR5e4e 9S5A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OrnMtF5K; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[83.34.200.30]) by smtp.gmail.com with ESMTPSA id d18sm42594476wrb.90.2019.06.25.09.47.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 25 Jun 2019 09:47:45 -0700 (PDT) From: Jorge Ramirez-Ortiz To: jorge.ramirez-ortiz@linaro.org, sboyd@kernel.org, bjorn.andersson@linaro.org, david.brown@linaro.org, jassisinghbrar@gmail.com, mark.rutland@arm.com, mturquette@baylibre.com, robh+dt@kernel.org, will.deacon@arm.com, arnd@arndb.de, horms+renesas@verge.net.au, heiko@sntech.de, sibis@codeaurora.org, enric.balletbo@collabora.com, jagan@amarulasolutions.com, olof@lixom.net Cc: vkoul@kernel.org, niklas.cassel@linaro.org, georgi.djakov@linaro.org, amit.kucheria@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-msm@vger.kernel.org, khasim.mohammed@linaro.org Subject: [PATCH v3 05/14] clk: qcom: apcs-msm8916: get parent clock names from DT Date: Tue, 25 Jun 2019 18:47:24 +0200 Message-Id: <20190625164733.11091-6-jorge.ramirez-ortiz@linaro.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190625164733.11091-1-jorge.ramirez-ortiz@linaro.org> References: <20190625164733.11091-1-jorge.ramirez-ortiz@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Allow accessing the parent clock names required for the driver operation by using the device tree node. This permits extending the driver to other platforms without having to modify its source code. For backwards compatibility leave previous values as default. Co-developed-by: Niklas Cassel Signed-off-by: Niklas Cassel Signed-off-by: Jorge Ramirez-Ortiz --- drivers/clk/qcom/apcs-msm8916.c | 23 ++++++++++++++++++++--- 1 file changed, 20 insertions(+), 3 deletions(-) -- 2.21.0 Reviewed-by: Bjorn Andersson diff --git a/drivers/clk/qcom/apcs-msm8916.c b/drivers/clk/qcom/apcs-msm8916.c index a6c89a310b18..dd82eb1e5202 100644 --- a/drivers/clk/qcom/apcs-msm8916.c +++ b/drivers/clk/qcom/apcs-msm8916.c @@ -19,7 +19,7 @@ static const u32 gpll0_a53cc_map[] = { 4, 5 }; -static const char * const gpll0_a53cc[] = { +static const char *gpll0_a53cc[] = { "gpll0_vote", "a53pll", }; @@ -50,6 +50,8 @@ static int qcom_apcs_msm8916_clk_probe(struct platform_device *pdev) struct regmap *regmap; struct clk_init_data init = { }; int ret = -ENODEV; + const char *parents[2]; + int pll_index = 0; regmap = dev_get_regmap(parent, NULL); if (!regmap) { @@ -61,6 +63,16 @@ static int qcom_apcs_msm8916_clk_probe(struct platform_device *pdev) if (!a53cc) return -ENOMEM; + /* legacy bindings only defined the pll parent clock (index = 0) with no + * name; when both of the parents are specified in the bindings, the + * pll is the second one (index = 1). + */ + if (of_clk_parent_fill(parent->of_node, parents, 2) == 2) { + gpll0_a53cc[0] = parents[0]; + gpll0_a53cc[1] = parents[1]; + pll_index = 1; + } + init.name = "a53mux"; init.parent_names = gpll0_a53cc; init.num_parents = ARRAY_SIZE(gpll0_a53cc); @@ -76,10 +88,11 @@ static int qcom_apcs_msm8916_clk_probe(struct platform_device *pdev) a53cc->src_shift = 8; a53cc->parent_map = gpll0_a53cc_map; - a53cc->pclk = devm_clk_get(parent, NULL); + a53cc->pclk = of_clk_get(parent->of_node, pll_index); if (IS_ERR(a53cc->pclk)) { ret = PTR_ERR(a53cc->pclk); - dev_err(dev, "failed to get clk: %d\n", ret); + if (ret != -EPROBE_DEFER) + dev_err(dev, "failed to get clk: %d\n", ret); return ret; } @@ -87,6 +100,7 @@ static int qcom_apcs_msm8916_clk_probe(struct platform_device *pdev) ret = clk_notifier_register(a53cc->pclk, &a53cc->clk_nb); if (ret) { dev_err(dev, "failed to register clock notifier: %d\n", ret); + clk_put(a53cc->pclk); return ret; } @@ -109,6 +123,8 @@ static int qcom_apcs_msm8916_clk_probe(struct platform_device *pdev) err: clk_notifier_unregister(a53cc->pclk, &a53cc->clk_nb); + clk_put(a53cc->pclk); + return ret; } @@ -117,6 +133,7 @@ static int qcom_apcs_msm8916_clk_remove(struct platform_device *pdev) struct clk_regmap_mux_div *a53cc = platform_get_drvdata(pdev); clk_notifier_unregister(a53cc->pclk, &a53cc->clk_nb); + clk_put(a53cc->pclk); return 0; } From patchwork Tue Jun 25 16:47:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jorge Ramirez-Ortiz X-Patchwork-Id: 167740 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp5779528ilk; Tue, 25 Jun 2019 09:47:58 -0700 (PDT) X-Google-Smtp-Source: APXvYqxjdENtZjUC6lkkPAmZ9CGQWJZlJekCGGDOjTrcfPzQUS512qxqoooWssP0COjZDZMRp8oo X-Received: by 2002:a17:902:20ec:: with SMTP id v41mr71592758plg.142.1561481278314; Tue, 25 Jun 2019 09:47:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1561481278; cv=none; d=google.com; s=arc-20160816; b=zmiDwK2Bx4ZTHwWR8Xf7sf100FUtuE1QBu2kHU5vGBD2lxULM39arIRc5ytJW7lwWn LpeqtRAhxW7OhEO/s66MSEmV+7Hg3ct0H9M2atVDE4XrNiV83lcz4dZBcHFQW9XgifkZ St4TFnE+plAusHewzgd8SQNuRwGFyP+jOYzBv8q/SG+aNcNjiWhehOrWrstJeHir7x67 Fl5tfYN0nEGrRR7wecfBDUgmK3XIkKWyeRKJs5Q1vkfQ5ZKW9bev/tMPXw5SSk86CpK6 HoMDvq8Vt4yZyzTf0tJydIeXp7EXcdqOydlVe5Rqq1D1szrcWJ3gXJWfj+0deuUN8Knl 5n7A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=oKGLSmgisRO2Nmb0wB40LqsaDficvDLdoxm6cO408zE=; b=vv6pNafsy+SwzdGVsagMK7w8sX0zbOxPst0kO38xDP2gOiviuQH6Hr75qGWF2h4XxD iNrDpqIYySLh3rGmIvQzL6oIiOI9GYH0t4P2GenwWQKEddhWQ452fQZ6Aj7H78YXW5A5 h/J8yQoSnflweqqZAv9hRDlNOflp9KvnXlnBmo/5irmQkyy7zBYeX5tjGkkEVB2awlO6 a099BptOZAR2CokkeJ7kmG++KegQ1pdwvsn3XTqQFs8oQy6WdULmrvhXS/HPCxHQCK79 anlg4Gov0Bw19sqkvKKP0OLIY0vtANflecH3DkXeYJuFLEdvZu3JnGHvHMynR8TpFn8/ 7ewA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="jY2/AWow"; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[83.34.200.30]) by smtp.gmail.com with ESMTPSA id d18sm42594476wrb.90.2019.06.25.09.47.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 25 Jun 2019 09:47:52 -0700 (PDT) From: Jorge Ramirez-Ortiz To: jorge.ramirez-ortiz@linaro.org, sboyd@kernel.org, bjorn.andersson@linaro.org, david.brown@linaro.org, jassisinghbrar@gmail.com, mark.rutland@arm.com, mturquette@baylibre.com, robh+dt@kernel.org, will.deacon@arm.com, arnd@arndb.de, horms+renesas@verge.net.au, heiko@sntech.de, sibis@codeaurora.org, enric.balletbo@collabora.com, jagan@amarulasolutions.com, olof@lixom.net Cc: vkoul@kernel.org, niklas.cassel@linaro.org, georgi.djakov@linaro.org, amit.kucheria@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-msm@vger.kernel.org, khasim.mohammed@linaro.org Subject: [PATCH v3 09/14] arm64: dts: qcom: msm8916: Add the clocks for the APCS mux/divider Date: Tue, 25 Jun 2019 18:47:28 +0200 Message-Id: <20190625164733.11091-10-jorge.ramirez-ortiz@linaro.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190625164733.11091-1-jorge.ramirez-ortiz@linaro.org> References: <20190625164733.11091-1-jorge.ramirez-ortiz@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Specify the clocks that feed the APCS mux/divider instead of using default hardcoded values in the source code. The driver still supports the previous bindings; however with this update it we allow the msm8916 to access the parent clock names required by the driver operation using the device tree node. Signed-off-by: Jorge Ramirez-Ortiz --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) -- 2.21.0 diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 5ea9fb8f2f87..96dc7a12aa94 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -429,7 +429,8 @@ compatible = "qcom,msm8916-apcs-kpss-global", "syscon"; reg = <0xb011000 0x1000>; #mbox-cells = <1>; - clocks = <&a53pll>; + clocks = <&gcc GPLL0_VOTE>, <&a53pll>; + clock-names = "aux", "pll"; #clock-cells = <0>; }; From patchwork Tue Jun 25 16:47:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jorge Ramirez-Ortiz X-Patchwork-Id: 167741 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp5779541ilk; Tue, 25 Jun 2019 09:47:59 -0700 (PDT) X-Google-Smtp-Source: APXvYqxYjUyh2UzRpgj5RCwmQG9nZa9wwIpsQnhOO7J9ciHJ2a6jsf8r1+SASQQbouEuNSlYnK1y X-Received: by 2002:a17:90a:7148:: with SMTP id g8mr33425593pjs.51.1561481279274; Tue, 25 Jun 2019 09:47:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1561481279; cv=none; d=google.com; s=arc-20160816; b=asZcNoT3RtFmsrR04ucsjo4sdGUStObh1Oj1E0gsWVF7jvJi3aa8Anv87bKYcyFZRu UGESyP9M/nYSqHg8bQTAUq2nRsDUjweK+Gl6IGVnZ+GfRpBJGveuiXpzx3oY+bgoqVHA QcfSeO/keOHs1DFP+ot/5Rpe2T1OYY4RKaybu5vun+2fAlpjx7JkIX6iecH7s9NyViVp YsTnth0kPw05OBe8phNt5zYttBjIq8wMahWnXXzmBc3sD1XJRSkjZmD5b/jO75m+PBpG 8X5/hAFGtPinINEYuoLaCtGZFCPE0FnEh9e+5fnfTNu6HYCCrv7CSqNynO3y8apqSw/J pdPg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=nrzyeFr44bncESExYjY2Xqm7hHRQ10WfGAsR66xmSU0=; b=R1ve8oyZ4JUWrDO2+wP/xxa8ZVRBw1o3Uo8b2OFJ7Hx9EFwL/lOUDtyoXD226jrYFd BrRWu1zqPhiCZSSW6iQOkK7d5A4mrL6nwYYTiXxG6rUfjfakJuqCWa5Z7MiZ2MdoneEK Tn7U6T/e8hSnwqkeR3BnHnSg/1rbyD4JaWaIum8RhGK3iwPhBsF14gndctX7Pbqtynnh x1071x1TPf0SGNnj48cq26/L/GpiLGtrEnshinCc1/oInjwLaXCI1JfFNVLc9CRcO9DT 8Yiy8ZM6ZFJ51vrd0kgzfdtk401VprgqkUyjLIVHiFZTnGiyNY7FA525daUYTqqfSFPb IoiA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kI+F4y9J; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[83.34.200.30]) by smtp.gmail.com with ESMTPSA id d18sm42594476wrb.90.2019.06.25.09.47.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 25 Jun 2019 09:47:54 -0700 (PDT) From: Jorge Ramirez-Ortiz To: jorge.ramirez-ortiz@linaro.org, sboyd@kernel.org, bjorn.andersson@linaro.org, david.brown@linaro.org, jassisinghbrar@gmail.com, mark.rutland@arm.com, mturquette@baylibre.com, robh+dt@kernel.org, will.deacon@arm.com, arnd@arndb.de, horms+renesas@verge.net.au, heiko@sntech.de, sibis@codeaurora.org, enric.balletbo@collabora.com, jagan@amarulasolutions.com, olof@lixom.net Cc: vkoul@kernel.org, niklas.cassel@linaro.org, georgi.djakov@linaro.org, amit.kucheria@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-msm@vger.kernel.org, khasim.mohammed@linaro.org Subject: [PATCH v3 10/14] arm64: dts: qcom: qcs404: Add OPP table Date: Tue, 25 Jun 2019 18:47:29 +0200 Message-Id: <20190625164733.11091-11-jorge.ramirez-ortiz@linaro.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190625164733.11091-1-jorge.ramirez-ortiz@linaro.org> References: <20190625164733.11091-1-jorge.ramirez-ortiz@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add a CPU OPP table to qcs404 Co-developed-by: Niklas Cassel Signed-off-by: Niklas Cassel Signed-off-by: Jorge Ramirez-Ortiz --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) -- 2.21.0 Reviewed-by: Bjorn Andersson diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index 3f17e1b09c13..d876dae5b0a5 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -83,6 +83,24 @@ }; }; + cpu_opp_table: cpu-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-1094400000 { + opp-hz = /bits/ 64 <1094400000>; + opp-microvolt = <1224000 1224000 1224000>; + }; + opp-1248000000 { + opp-hz = /bits/ 64 <1248000000>; + opp-microvolt = <1288000 1288000 1288000>; + }; + opp-1401600000 { + opp-hz = /bits/ 64 <1401600000>; + opp-microvolt = <1384000 1384000 1384000>; + }; + }; + firmware { scm: scm { compatible = "qcom,scm-qcs404", "qcom,scm"; From patchwork Tue Jun 25 16:47:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jorge Ramirez-Ortiz X-Patchwork-Id: 167742 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp5779548ilk; Tue, 25 Jun 2019 09:47:59 -0700 (PDT) X-Google-Smtp-Source: APXvYqyTSy6QNHNgYtin6IqBgTHgcOU3pTu4XVWoiGlZoExh/hHaW1of12TB0npBQv8kkS9LBdXF X-Received: by 2002:a17:902:403:: with SMTP id 3mr153096445ple.66.1561481279591; Tue, 25 Jun 2019 09:47:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1561481279; cv=none; d=google.com; s=arc-20160816; b=KTRCXj/R+J2jXbioG+wKEeR1AKa9HHE8sCf0fa6MBOl3f5Ov3fznLd7lvWmEa4du8+ hbm26fvxTpHxNVB2YevCHdf+YUkI+G5ouG8lRdW2G49A84hhE6qpZK+XeLasaZhVferW wECKuatRXNEUz3N5zmRj/mtZaIcjKvoJwu5CLnhZXP7Wc6awHeIdc7xldelUw92OENzO fbDALaJ5AfUnZcavs6RSoeN60nkjq1KF2GmbpR8lDtwwEQ1jfOI3T7cIhWkLTmmHUQWF qjGcfFela15QgxRCF4Pb10WfpoSGHztHjPerp/dhvd9ZEaXKNHCB1Sj/yUlamHG8g/hb iXyw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=tH1fOw6y0vNQF4dreNKkipKssk8MEpaF1tmIMTiOzZ0=; b=hkU4i5+ff+0vlfzlqzrq9SCBbvcI6ZtvkxwNuonhAdXMAJBJXNO51/CkgWNNQWY2KK gTRH7AcB6bAplyFZTEXg++IbONBk7aMzGDy2z4ZD4UIpGHwBxDCFZXzFlyWoJLFBgxxB HSVUb9NaJ7FyDoeuvXyCVZSE9oMKwYTd06oyqt7/Nu1ruJPQyWPpb/oWXMB8HK9ojw5X 53rY4TpqMw9pagjg45J1wiLIMnMC6o07qXH9iU0zsdGgPzkG7DILTicZ+HfhC/Q7kuFZ NUs1NeGKVm8smMWei3f1wGYQhsCcR1B0f9FycpC2+cwgdZ5Umkhr62G2Y/nOAIuNvjU4 TQTw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=oyqB2avN; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[83.34.200.30]) by smtp.gmail.com with ESMTPSA id d18sm42594476wrb.90.2019.06.25.09.47.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 25 Jun 2019 09:47:55 -0700 (PDT) From: Jorge Ramirez-Ortiz To: jorge.ramirez-ortiz@linaro.org, sboyd@kernel.org, bjorn.andersson@linaro.org, david.brown@linaro.org, jassisinghbrar@gmail.com, mark.rutland@arm.com, mturquette@baylibre.com, robh+dt@kernel.org, will.deacon@arm.com, arnd@arndb.de, horms+renesas@verge.net.au, heiko@sntech.de, sibis@codeaurora.org, enric.balletbo@collabora.com, jagan@amarulasolutions.com, olof@lixom.net Cc: vkoul@kernel.org, niklas.cassel@linaro.org, georgi.djakov@linaro.org, amit.kucheria@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-msm@vger.kernel.org, khasim.mohammed@linaro.org Subject: [PATCH v3 11/14] arm64: dts: qcom: qcs404: Add HFPLL node Date: Tue, 25 Jun 2019 18:47:30 +0200 Message-Id: <20190625164733.11091-12-jorge.ramirez-ortiz@linaro.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190625164733.11091-1-jorge.ramirez-ortiz@linaro.org> References: <20190625164733.11091-1-jorge.ramirez-ortiz@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The high frequency pll functionality is required to enable CPU frequency scaling operation. Co-developed-by: Niklas Cassel Signed-off-by: Niklas Cassel Signed-off-by: Jorge Ramirez-Ortiz --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) -- 2.21.0 Reviewed-by: Bjorn Andersson diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index d876dae5b0a5..94471aa31979 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -852,6 +852,15 @@ #mbox-cells = <1>; }; + apcs_hfpll: clock-controller@b016000 { + compatible = "qcom,hfpll"; + reg = <0x0b016000 0x30>; + #clock-cells = <0>; + clock-output-names = "apcs_hfpll"; + clocks = <&xo_board>; + clock-names = "xo"; + }; + timer@b120000 { #address-cells = <1>; #size-cells = <1>;