From patchwork Fri Jul 7 13:17:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 700404 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 650FDC001DF for ; Fri, 7 Jul 2023 13:17:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229695AbjGGNRU (ORCPT ); Fri, 7 Jul 2023 09:17:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45562 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230289AbjGGNRT (ORCPT ); Fri, 7 Jul 2023 09:17:19 -0400 Received: from mail-lf1-x131.google.com (mail-lf1-x131.google.com [IPv6:2a00:1450:4864:20::131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 777F91FC9; Fri, 7 Jul 2023 06:17:17 -0700 (PDT) Received: by mail-lf1-x131.google.com with SMTP id 2adb3069b0e04-4fb8574a3a1so2859958e87.1; Fri, 07 Jul 2023 06:17:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1688735836; x=1691327836; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=NjW7KoRCDV8Jc0MWFIIb1Qt0B39sgkHOYdwi4ltUWdg=; b=mMGXtaXZB0onqJwWxvXQ1p+n4SqWr4gB2xYYxhHDq2ZOQ1fYn3tGP+z1WEOuggD2bX xsT1RpSXLM61XR1fSoU49e1zB93YhDTOYXsC3fiqs4DFK2KmQliuNDMUAxCzXqUb3zWE b9c5lxk5oPjIXUyN7QCekCz+u04dLUYP9NP2L5gKD3ItfrqWy4dJ/d9q4S3DczHGW+k+ 2J8NKDMoSFNm3XW41r8Kc0PfI2zP/vWIn4h6hAzB9u3esnyKuElPogs4/V10sZucvERG CSBqfrZ+m5X99UatLTYvHnHd/n/sucpRZqN/MvJHlVsum+jVxwWpVngJI8K0uPc22wlr 1Fzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688735836; x=1691327836; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=NjW7KoRCDV8Jc0MWFIIb1Qt0B39sgkHOYdwi4ltUWdg=; b=XwhWtMjL/zNlROMBvfTdIrK6iEplrrykx0hiKplceOOqqMuSvokd+xfawOnzJa9II7 BpPICx1UyytLeyOLD5LduprVLWnMejpHv1JNFQHoBuMlYp/xNihmwgkp5sELVIkIGDTg xpq0GvNQsEjuOYhswPmyGKcjutlS6kVmfgIpFqrxK1sk/0DAJSZml8lZQJVOSBmRADTA Ybuh/haTN9vFceovKmAUdLJpycJnfHyR1nJyCLLrwygaxa6NzWE0iSU5iI+o7Itb29/N oaVmUXC0b29z2DZsYlBLWr+giFdASNnt/4kx8IEpfNRdiMWeVaQD9TWkAMRPAniUq3+w ersw== X-Gm-Message-State: ABy/qLbps182pnPrBDoyRDm2F3KvJn2FEpq/9r36cZIdxtKuEycMesuL OiEsi/Jsga7nXpoxZPO55vA= X-Google-Smtp-Source: APBJJlHMKOqOebIze0oyQEHlrdB0YZclTDs/GKBdOzMguECKZYPPyhrPTmC5uAwErv4uLKHbbLsz5Q== X-Received: by 2002:ac2:4c49:0:b0:4f8:6b7f:c6d6 with SMTP id o9-20020ac24c49000000b004f86b7fc6d6mr4959560lfk.48.1688735835285; Fri, 07 Jul 2023 06:17:15 -0700 (PDT) Received: from localhost (p200300e41f4b7100f22f74fffe1f3a53.dip0.t-ipconnect.de. [2003:e4:1f4b:7100:f22f:74ff:fe1f:3a53]) by smtp.gmail.com with ESMTPSA id m22-20020a7bce16000000b003fc01189b0dsm895243wmc.42.2023.07.07.06.17.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Jul 2023 06:17:15 -0700 (PDT) From: Thierry Reding To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding Cc: Jon Hunter , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH 1/7] dt-bindings: arm: tegra: pmc: Improve property descriptions Date: Fri, 7 Jul 2023 15:17:05 +0200 Message-ID: <20230707131711.2997956-1-thierry.reding@gmail.com> X-Mailer: git-send-email 2.41.0 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Thierry Reding Reformat the description of various properties to make them more consistent with existing ones. Make use of json-schema's ability to provide a description for individual list items to make improve the documentation further. Signed-off-by: Thierry Reding --- .../arm/tegra/nvidia,tegra20-pmc.yaml | 215 +++++++++--------- 1 file changed, 104 insertions(+), 111 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml index 89191cfdf619..a90f01678775 100644 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml @@ -21,17 +21,14 @@ properties: reg: maxItems: 1 - description: - Offset and length of the register set for the device. + description: Offset and length of the register set for the device. clock-names: items: + # Tegra clock of the same name - const: pclk + # 32 KHz clock input - const: clk32k_in - description: - Must includes entries pclk and clk32k_in. - pclk is the Tegra clock of that name and clk32k_in is 32KHz clock - input to Tegra. clocks: maxItems: 2 @@ -41,105 +38,103 @@ properties: '#clock-cells': const: 1 - description: - Tegra PMC has clk_out_1, clk_out_2, and clk_out_3. - PMC also has blink control which allows 32Khz clock output to - Tegra blink pad. - Consumer of PMC clock should specify the desired clock by having - the clock ID in its "clocks" phandle cell with pmc clock provider. - See include/dt-bindings/soc/tegra-pmc.h for the list of Tegra PMC - clock IDs. + description: | + Tegra PMC has clk_out_1, clk_out_2, and clk_out_3. PMC also has blink + control which allows 32Khz clock output to Tegra blink pad. + + Consumer of PMC clock should specify the desired clock by having the + clock ID in its "clocks" phandle cell with PMC clock provider. See + include/dt-bindings/soc/tegra-pmc.h for the list of Tegra PMC clock IDs. '#interrupt-cells': const: 2 - description: - Specifies number of cells needed to encode an interrupt source. - The value must be 2. + description: Specifies number of cells needed to encode an interrupt + source. interrupt-controller: true nvidia,invert-interrupt: $ref: /schemas/types.yaml#/definitions/flag - description: Inverts the PMU interrupt signal. - The PMU is an external Power Management Unit, whose interrupt output - signal is fed into the PMC. This signal is optionally inverted, and - then fed into the ARM GIC. The PMC is not involved in the detection - or handling of this interrupt signal, merely its inversion. + description: Inverts the PMU interrupt signal. The PMU is an external Power + Management Unit, whose interrupt output signal is fed into the PMC. This + signal is optionally inverted, and then fed into the ARM GIC. The PMC is + not involved in the detection or handling of this interrupt signal, + merely its inversion. nvidia,core-power-req-active-high: $ref: /schemas/types.yaml#/definitions/flag - description: Core power request active-high. + description: core power request active-high nvidia,sys-clock-req-active-high: $ref: /schemas/types.yaml#/definitions/flag - description: System clock request active-high. + description: system clock request active-high nvidia,combined-power-req: $ref: /schemas/types.yaml#/definitions/flag - description: combined power request for CPU and Core. + description: combined power request for CPU and core nvidia,cpu-pwr-good-en: $ref: /schemas/types.yaml#/definitions/flag - description: - CPU power good signal from external PMIC to PMC is enabled. + description: CPU power good signal from external PMIC to PMC is enabled nvidia,suspend-mode: $ref: /schemas/types.yaml#/definitions/uint32 - enum: [0, 1, 2] - description: - The suspend mode that the platform should use. - Mode 0 is for LP0, CPU + Core voltage off and DRAM in self-refresh - Mode 1 is for LP1, CPU voltage off and DRAM in self-refresh - Mode 2 is for LP2, CPU voltage off + description: the suspend mode that the platform should use + oneOf: + - description: LP0, CPU + Core voltage off and DRAM in self-refresh + const: 0 + - description: LP1, CPU voltage off and DRAM in self-refresh + const: 1 + - description: LP2, CPU voltage off + const: 2 nvidia,cpu-pwr-good-time: $ref: /schemas/types.yaml#/definitions/uint32 - description: CPU power good time in uSec. + description: CPU power good time in microseconds nvidia,cpu-pwr-off-time: $ref: /schemas/types.yaml#/definitions/uint32 - description: CPU power off time in uSec. + description: CPU power off time in microseconds nvidia,core-pwr-good-time: $ref: /schemas/types.yaml#/definitions/uint32-array - description: - - Core power good time in uSec. + description: core power good time in microseconds + items: + - description: oscillator stable time + - description: power stable time nvidia,core-pwr-off-time: $ref: /schemas/types.yaml#/definitions/uint32 - description: Core power off time in uSec. + description: core power off time in microseconds nvidia,lp0-vec: $ref: /schemas/types.yaml#/definitions/uint32-array - description: - Starting address and length of LP0 vector. - The LP0 vector contains the warm boot code that is executed - by AVP when resuming from the LP0 state. - The AVP (Audio-Video Processor) is an ARM7 processor and - always being the first boot processor when chip is power on - or resume from deep sleep mode. When the system is resumed - from the deep sleep mode, the warm boot code will restore - some PLLs, clocks and then brings up CPU0 for resuming the - system. + description: | + Starting address and length of LP0 vector. The LP0 vector contains the + warm boot code that is executed by AVP when resuming from the LP0 state. + The AVP (Audio-Video Processor) is an ARM7 processor and always being + the first boot processor when chip is power on or resume from deep sleep + mode. When the system is resumed from the deep sleep mode, the warm boot + code will restore some PLLs, clocks and then brings up CPU0 for resuming + the system. + items: + - description: starting address of LP0 vector + - description: length of LP0 vector core-supply: - description: - Phandle to voltage regulator connected to the SoC Core power rail. + description: phandle to voltage regulator connected to the SoC core power + rail core-domain: type: object - description: | - The vast majority of hardware blocks of Tegra SoC belong to a - Core power domain, which has a dedicated voltage rail that powers - the blocks. - + description: The vast majority of hardware blocks of Tegra SoC belong to a + core power domain, which has a dedicated voltage rail that powers the + blocks. properties: operating-points-v2: - description: - Should contain level, voltages and opp-supported-hw property. - The supported-hw is a bitfield indicating SoC speedo or process - ID mask. + description: Should contain level, voltages and opp-supported-hw + property. The supported-hw is a bitfield indicating SoC speedo or + process ID mask. "#power-domain-cells": const: 0 @@ -152,37 +147,32 @@ properties: i2c-thermtrip: type: object - description: - On Tegra30, Tegra114 and Tegra124 if i2c-thermtrip subnode exists, - hardware-triggered thermal reset will be enabled. - + description: On Tegra30, Tegra114 and Tegra124 if i2c-thermtrip subnode + exists, hardware-triggered thermal reset will be enabled. properties: nvidia,i2c-controller-id: $ref: /schemas/types.yaml#/definitions/uint32 - description: - ID of I2C controller to send poweroff command to PMU. - Valid values are described in section 9.2.148 - "APBDEV_PMC_SCRATCH53_0" of the Tegra K1 Technical Reference - Manual. + description: ID of I2C controller to send poweroff command to PMU. + Valid values are described in section 9.2.148 "APBDEV_PMC_SCRATCH53_0" + of the Tegra K1 Technical Reference Manual. nvidia,bus-addr: $ref: /schemas/types.yaml#/definitions/uint32 - description: Bus address of the PMU on the I2C bus. + description: bus address of the PMU on the I2C bus nvidia,reg-addr: $ref: /schemas/types.yaml#/definitions/uint32 - description: PMU I2C register address to issue poweroff command. + description: PMU I2C register address to issue poweroff command nvidia,reg-data: $ref: /schemas/types.yaml#/definitions/uint32 - description: Poweroff command to write to PMU. + description: power-off command to write to PMU nvidia,pinmux-id: $ref: /schemas/types.yaml#/definitions/uint32 - description: - Pinmux used by the hardware when issuing Poweroff command. - Defaults to 0. Valid values are described in section 12.5.2 - "Pinmux Support" of the Tegra4 Technical Reference Manual. + description: Pinmux used by the hardware when issuing power-off command. + Defaults to 0. Valid values are described in section 12.5.2 "Pinmux + Support" of the Tegra4 Technical Reference Manual. required: - nvidia,i2c-controller-id @@ -195,41 +185,44 @@ properties: powergates: type: object description: | - This node contains a hierarchy of power domain nodes, which should - match the powergates on the Tegra SoC. Each powergate node - represents a power-domain on the Tegra SoC that can be power-gated - by the Tegra PMC. - Hardware blocks belonging to a power domain should contain - "power-domains" property that is a phandle pointing to corresponding - powergate node. - The name of the powergate node should be one of the below. Note that - not every powergate is applicable to all Tegra devices and the following - list shows which powergates are applicable to which devices. - Please refer to Tegra TRM for mode details on the powergate nodes to - use for each power-gate block inside Tegra. - Name Description Devices Applicable - 3d 3D Graphics Tegra20/114/124/210 - 3d0 3D Graphics 0 Tegra30 - 3d1 3D Graphics 1 Tegra30 - aud Audio Tegra210 - dfd Debug Tegra210 - dis Display A Tegra114/124/210 - disb Display B Tegra114/124/210 - heg 2D Graphics Tegra30/114/124/210 - iram Internal RAM Tegra124/210 - mpe MPEG Encode All - nvdec NVIDIA Video Decode Engine Tegra210 - nvjpg NVIDIA JPEG Engine Tegra210 - pcie PCIE Tegra20/30/124/210 - sata SATA Tegra30/124/210 - sor Display interfaces Tegra124/210 - ve2 Video Encode Engine 2 Tegra210 - venc Video Encode Engine All - vdec Video Decode Engine Tegra20/30/114/124 - vic Video Imaging Compositor Tegra124/210 - xusba USB Partition A Tegra114/124/210 - xusbb USB Partition B Tegra114/124/210 - xusbc USB Partition C Tegra114/124/210 + This node contains a hierarchy of power domain nodes, which should match + the powergates on the Tegra SoC. Each powergate node represents a power- + domain on the Tegra SoC that can be power-gated by the Tegra PMC. + + Hardware blocks belonging to a power domain should contain "power-domains" + property that is a phandle pointing to corresponding powergate node. + + The name of the powergate node should be one of the below. Note that not + every powergate is applicable to all Tegra devices and the following list + shows which powergates are applicable to which devices. + + Please refer to Tegra TRM for mode details on the powergate nodes to use + for each power-gate block inside Tegra. + + Name Description Devices Applicable + -------------------------------------------------------------- + 3d 3D Graphics Tegra20/114/124/210 + 3d0 3D Graphics 0 Tegra30 + 3d1 3D Graphics 1 Tegra30 + aud Audio Tegra210 + dfd Debug Tegra210 + dis Display A Tegra114/124/210 + disb Display B Tegra114/124/210 + heg 2D Graphics Tegra30/114/124/210 + iram Internal RAM Tegra124/210 + mpe MPEG Encode All + nvdec NVIDIA Video Decode Engine Tegra210 + nvjpg NVIDIA JPEG Engine Tegra210 + pcie PCIE Tegra20/30/124/210 + sata SATA Tegra30/124/210 + sor Display interfaces Tegra124/210 + ve2 Video Encode Engine 2 Tegra210 + venc Video Encode Engine All + vdec Video Decode Engine Tegra20/30/114/124 + vic Video Imaging Compositor Tegra124/210 + xusba USB Partition A Tegra114/124/210 + xusbb USB Partition B Tegra114/124/210 + xusbc USB Partition C Tegra114/124/210 patternProperties: "^[a-z0-9]+$": From patchwork Fri Jul 7 13:17:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 700405 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 01424EB64D9 for ; Fri, 7 Jul 2023 13:17:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229914AbjGGNRT (ORCPT ); Fri, 7 Jul 2023 09:17:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45562 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229695AbjGGNRS (ORCPT ); Fri, 7 Jul 2023 09:17:18 -0400 Received: from mail-wm1-x32e.google.com (mail-wm1-x32e.google.com [IPv6:2a00:1450:4864:20::32e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BD6791FEA; Fri, 7 Jul 2023 06:17:17 -0700 (PDT) Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-3fbc656873eso23732455e9.1; Fri, 07 Jul 2023 06:17:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1688735836; x=1691327836; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vy/0fHAoINnqH1mI2R69W8uNhvSD3tnpTeux+R7nK90=; b=hpdiWPTaG0eIIp9XDVUxByIuLC6bY1vSlUpnymjSiK4BgXGRlhCBgHVw+0YuUn27VT 4YmjioAdURXLYMdrk+1iLKN5UXe5yh/4CLT3fXMrOX4ebQ7zPENUFrgfC8R0pDQ9CuOb fVnCm2fS8ZkZfwAYWwj4W+e8Q5Pt23qs8W9cn3Rvthx+wmEc46J2ZVUgnutKVAPNI5ib MCeA5q8EXsGL/DhF0AYcPKZO5vGlA05Y/Gel4ZObjprxAoB8rzR46TW3cRUveSbdCFSh naTT/H8EewpdM90AfcnZod9BHPTH8uqZr4+wBQc/s+RtFv5+cWRTBnsLApZJMBhc8qla xgsQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688735836; x=1691327836; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vy/0fHAoINnqH1mI2R69W8uNhvSD3tnpTeux+R7nK90=; b=CekPHTvV6jBa5uGQ3v57sh31zT3gcwApGXX8vqApOHql0M3KCaSIBzUX7wOPVHtfTd oMntbF+uSDJGqoRsq6VOqINpLnvOLWFGR3VqjHvVIHpEzEXbMsq4Uv4/tA53oHgbmOsf Wk6EJGdlylmJJcrBcKvwLE+x/fsONIghOWXFqqzoKg7ZU/B//3yWSyq3cl0fPeTimtWe OIro4uyVpSFs5vdWte1bpoV8x9E/V3OzjCut+BzuW2QUWtOj2eCH++hgEkUTesnkKH8C ogqXZv7gsDLkI2BHtimpVFG3r9DGNlK2wGksPvxnZ/8iPshNToGHWN8SNI7/e0rpWk9v +5tg== X-Gm-Message-State: ABy/qLaAB3vi7QH+Z4+v070G1Qjz8wikznddoaEmxPPhFVOM5JVJGjF0 tRdpn/Xt2bywTgM5I7If+1E= X-Google-Smtp-Source: APBJJlEJcoCyC3XUC4xgP7+EOxBLZ8yqs5jfirQ5sup/G+ON795Okus1vNk0IDXHB8bzaPX3ndTp0w== X-Received: by 2002:a1c:4c08:0:b0:3fa:935e:e185 with SMTP id z8-20020a1c4c08000000b003fa935ee185mr5671832wmf.22.1688735836093; Fri, 07 Jul 2023 06:17:16 -0700 (PDT) Received: from localhost (p200300e41f4b7100f22f74fffe1f3a53.dip0.t-ipconnect.de. [2003:e4:1f4b:7100:f22f:74ff:fe1f:3a53]) by smtp.gmail.com with ESMTPSA id i7-20020a05600c290700b003fbad1b4904sm2514473wmd.0.2023.07.07.06.17.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Jul 2023 06:17:15 -0700 (PDT) From: Thierry Reding To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding Cc: Jon Hunter , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH 2/7] dt-bindings: arm: tegra: pmc: Remove useless boilerplate descriptions Date: Fri, 7 Jul 2023 15:17:06 +0200 Message-ID: <20230707131711.2997956-2-thierry.reding@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230707131711.2997956-1-thierry.reding@gmail.com> References: <20230707131711.2997956-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Thierry Reding The descriptions for the clocks and resets properties are no longer useful in the context of json-schema, so drop them. Signed-off-by: Thierry Reding --- .../bindings/arm/tegra/nvidia,tegra20-pmc.yaml | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml index a90f01678775..c5a1ae44c5e3 100644 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml @@ -32,9 +32,6 @@ properties: clocks: maxItems: 2 - description: - Must contain an entry for each entry in clock-names. - See ../clocks/clocks-bindings.txt for details. '#clock-cells': const: 1 @@ -233,18 +230,10 @@ properties: clocks: minItems: 1 maxItems: 8 - description: - Must contain an entry for each clock required by the PMC - for controlling a power-gate. - See ../clocks/clock-bindings.txt document for more details. resets: minItems: 1 maxItems: 8 - description: - Must contain an entry for each reset required by the PMC - for controlling a power-gate. - See ../reset/reset.txt for more details. power-domains: maxItems: 1 From patchwork Fri Jul 7 13:17:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 700189 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 50B2BEB64D9 for ; Fri, 7 Jul 2023 13:17:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230414AbjGGNRV (ORCPT ); Fri, 7 Jul 2023 09:17:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45562 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230516AbjGGNRU (ORCPT ); Fri, 7 Jul 2023 09:17:20 -0400 Received: from mail-lf1-x12e.google.com (mail-lf1-x12e.google.com [IPv6:2a00:1450:4864:20::12e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2F6EB1FEA; Fri, 7 Jul 2023 06:17:19 -0700 (PDT) Received: by mail-lf1-x12e.google.com with SMTP id 2adb3069b0e04-4fbbfaacfc1so2983796e87.1; Fri, 07 Jul 2023 06:17:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1688735837; x=1691327837; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=p+1LFMubo++ug8jFRY3vtws8bJ8kHKDkjh6RHI+s+u0=; b=oyVuJzRPJgC7hcc98TTUhLl3fE4ZILQcPbRP+U9DFibE/aqPlk5QnLRihDYlTdiwSd lNPkZQ1BET0GsIxp+7Zca6NXJ0x5Q1OcbeSHZGBka95SdsL0/GfIdAKZLy6y+oIv0Enf kAD6giBXao/KHrb98xdLiJeTnH4AXQj49LIHDCUvSnLYX95viancZwUpxt7geAEgpJYF F0JysSxXirucAbyzBsq0CFw519V82EaY0b9OcXxoT1seUWYBHyyosy/CdjBCcONQ7Pw0 trONk+jYYzc8zGnldgyggZgEkT4IDKH12qIa5eaX29YuH+Gckg0rw0P5ycztaEmFNDpj QjUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688735837; x=1691327837; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=p+1LFMubo++ug8jFRY3vtws8bJ8kHKDkjh6RHI+s+u0=; b=Xm947dBXOgJadaBV4MAIYQCtuz19iBq+Ntxsgqx6GWVo9unmehHI7dP5T7cQUWg4D+ uJ9ATq6SvHexaHT1sLiw+89lOoKq0mbtrnnA9ohAH0pR+tfvhHVn07YdbD/9R8qfLwY2 49JuqBtR6rY6DC6l2En3/DFBVSFm+toUduhCQCOtaly8lMKHziGo/jcARO4eHW9DQwnC czbF5AbK6grm8ftifxc0RcMjnKWrWG7rwXU1owPN9Vq1B/GEeDvraNjJDqxqKxPEX6fa uAySA6jNgfQBObepOLRz+eTYm5izQmTw91s7AluZx1xq3RA26NFA9RBMU+d7TBw5Eb54 usag== X-Gm-Message-State: ABy/qLazt0uENpIBpEgt2ELog1g2uOyNdG3H3nex+A7lfhUDZyhjsMP4 ZE8dP+dch/Tb+ASIUltHxJXv+Jq6wlo= X-Google-Smtp-Source: APBJJlE9WmBI36/PG9IFrouyVkdDnFdNZUqA3YhK6gT85PqjNKJntBOl2kbx5ru57w2x7t+MItq6zQ== X-Received: by 2002:a19:4f10:0:b0:4f8:5960:49a9 with SMTP id d16-20020a194f10000000b004f8596049a9mr3815966lfb.23.1688735837120; Fri, 07 Jul 2023 06:17:17 -0700 (PDT) Received: from localhost (p200300e41f4b7100f22f74fffe1f3a53.dip0.t-ipconnect.de. [2003:e4:1f4b:7100:f22f:74ff:fe1f:3a53]) by smtp.gmail.com with ESMTPSA id r13-20020a05600c458d00b003fa9a00d74csm9543789wmo.3.2023.07.07.06.17.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Jul 2023 06:17:16 -0700 (PDT) From: Thierry Reding To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding Cc: Jon Hunter , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH 3/7] dt-bindings: arm: tegra: pmc: Move additionalProperties Date: Fri, 7 Jul 2023 15:17:07 +0200 Message-ID: <20230707131711.2997956-3-thierry.reding@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230707131711.2997956-1-thierry.reding@gmail.com> References: <20230707131711.2997956-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Thierry Reding For indented subschemas it can be difficult to understand which block an additionalProperties property belongs to. Moving it closer to the beginning of a block is a good way to clarify this. Signed-off-by: Thierry Reding Reviewed-by: Rob Herring --- .../bindings/arm/tegra/nvidia,tegra20-pmc.yaml | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml index c5a1ae44c5e3..1d8b99938323 100644 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml @@ -127,6 +127,7 @@ properties: description: The vast majority of hardware blocks of Tegra SoC belong to a core power domain, which has a dedicated voltage rail that powers the blocks. + additionalProperties: false properties: operating-points-v2: description: Should contain level, voltages and opp-supported-hw @@ -140,12 +141,11 @@ properties: - operating-points-v2 - "#power-domain-cells" - additionalProperties: false - i2c-thermtrip: type: object description: On Tegra30, Tegra114 and Tegra124 if i2c-thermtrip subnode exists, hardware-triggered thermal reset will be enabled. + additionalProperties: false properties: nvidia,i2c-controller-id: $ref: /schemas/types.yaml#/definitions/uint32 @@ -177,10 +177,9 @@ properties: - nvidia,reg-addr - nvidia,reg-data - additionalProperties: false - powergates: type: object + additionalProperties: false description: | This node contains a hierarchy of power domain nodes, which should match the powergates on the Tegra SoC. Each powergate node represents a power- @@ -225,7 +224,6 @@ properties: "^[a-z0-9]+$": type: object additionalProperties: false - properties: clocks: minItems: 1 @@ -247,8 +245,6 @@ properties: - resets - '#power-domain-cells' - additionalProperties: false - patternProperties: "^[a-f0-9]+-[a-f0-9]+$": type: object From patchwork Fri Jul 7 13:17:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 700188 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 423E1C04A6A for ; Fri, 7 Jul 2023 13:17:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230516AbjGGNRV (ORCPT ); Fri, 7 Jul 2023 09:17:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45562 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230289AbjGGNRV (ORCPT ); Fri, 7 Jul 2023 09:17:21 -0400 Received: from mail-wr1-x429.google.com (mail-wr1-x429.google.com [IPv6:2a00:1450:4864:20::429]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CDB4C1FC9; Fri, 7 Jul 2023 06:17:19 -0700 (PDT) Received: by mail-wr1-x429.google.com with SMTP id ffacd0b85a97d-313e742a787so1616469f8f.1; Fri, 07 Jul 2023 06:17:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1688735838; x=1691327838; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=v80poZORx0WdeR8eQJuJazZFWv7nv+nmLCXVZxPw2e8=; b=Z0y8hZhaxWaz/MLM0Pbl7KlcjLEySXdmFN5P/Bh5MS2sA8ZmPje2OjTk9OgGNGuUe+ VFQvVZlwOVj+8n+FumVL/wrNcf4ZrdbLSZ4JOntNWH9izvwTPMkRKyaSfEN8zHP61Azm jCHv2U6SNVcRYigYCuVgwcKVps6eDStPIQl2/5KktOzbyHw6TOSFDvV4p+kLlD7pIUj2 HsAQr3460lzD3cs8T00HSEFYenSPMsRhGkQcis19ftY8f8qpa1aE1Tq6ndWAFGI2s8yF gTm8gbAUbiL76o6ZEBtf8IxTUwHxRpkl8yRuUH0wL09e0tOL7Jv/MSqzytum6m3mOoNo euRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688735838; x=1691327838; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=v80poZORx0WdeR8eQJuJazZFWv7nv+nmLCXVZxPw2e8=; b=D3u6C4IZX1rhM3q3vfJbo6b82lPVIEoMs9BJRYbPYiw+/243NbfS2Du6XUFfxusLGW zh63c1q7JpukBetCMCwQs7p7pkTmtjm+BUCZiHiDepB9X5ASdjVOQn/NIbbofTzPuxct CYRKN6UmRYpDo2WVJkZ2LzCkM+EqkcRe3PRkSLabRX/sfqXJDNCn4NfndvfJ4RHTyYAe bLuydkOsX8GIJylKZA7E2P9qeNmTEdH4/9OphlhWlyy2szA6+geLnsVrUOZOd5QxLV5c IhVEePuycz8PsQZWrPBK26PML8dGIflaFhMdIhgQ4lWmM0nlysuQBW2IyXZDE8L/fqKp xQJQ== X-Gm-Message-State: ABy/qLZRlPkLCyMfR5b1JCjPh62ukkOVjOKh9ohOqfwpKgIT8P68CLmN BIW3YwSzW85DTVqTDEPWvws= X-Google-Smtp-Source: APBJJlFY2A0tKMZfTki1YCz40J52tl5DdfGDWDjdxw1g/GKz+X6Ewj4+BBXOj47EXtyKwF8r1lSSGw== X-Received: by 2002:a5d:590f:0:b0:313:ed10:7f52 with SMTP id v15-20020a5d590f000000b00313ed107f52mr8196217wrd.18.1688735838269; Fri, 07 Jul 2023 06:17:18 -0700 (PDT) Received: from localhost (p200300e41f4b7100f22f74fffe1f3a53.dip0.t-ipconnect.de. [2003:e4:1f4b:7100:f22f:74ff:fe1f:3a53]) by smtp.gmail.com with ESMTPSA id n21-20020a1c7215000000b003f91e32b1ebsm2460489wmc.17.2023.07.07.06.17.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Jul 2023 06:17:17 -0700 (PDT) From: Thierry Reding To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding Cc: Jon Hunter , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH 4/7] dt-bindings: arm: tegra: pmc: Increase maximum number of clocks per powergate Date: Fri, 7 Jul 2023 15:17:08 +0200 Message-ID: <20230707131711.2997956-4-thierry.reding@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230707131711.2997956-1-thierry.reding@gmail.com> References: <20230707131711.2997956-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Thierry Reding Some powergate definitions need more than 8 clocks, so bump the number up to 10, which is the current maximum in any known device tree file. Signed-off-by: Thierry Reding --- .../devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml index 1d8b99938323..82070d47ac7c 100644 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml @@ -227,7 +227,7 @@ properties: properties: clocks: minItems: 1 - maxItems: 8 + maxItems: 10 resets: minItems: 1 From patchwork Fri Jul 7 13:17:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 700403 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 08913EB64D9 for ; Fri, 7 Jul 2023 13:17:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230289AbjGGNRY (ORCPT ); Fri, 7 Jul 2023 09:17:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45562 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231950AbjGGNRX (ORCPT ); Fri, 7 Jul 2023 09:17:23 -0400 Received: from mail-lf1-x133.google.com (mail-lf1-x133.google.com [IPv6:2a00:1450:4864:20::133]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1FB241FEA; Fri, 7 Jul 2023 06:17:21 -0700 (PDT) Received: by mail-lf1-x133.google.com with SMTP id 2adb3069b0e04-4fb7dc16ff0so2859731e87.2; Fri, 07 Jul 2023 06:17:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1688735839; x=1691327839; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=AunBb31YzZUjwaJ31r+ZHgWQ+d/p+0mUIZp67J/ATuk=; b=olVa44fi0B69r8C4Ey4sS0yWJUwbihHtJUndtukfR03C1OM7CQtjjvdw4IdvcIB+Ob 0e3TnBw94LzO+9rC5Ce/oPJpRPDqDDt6/tm9LU1c/PzYlZRv1c1jXqU7cO4PeNz6nyQo lPNuVSgNWbkaiLVr99ehCiX8uBI33PPZ1k8h1QpgrR0h0eeOeo2uxfWmZHZRoV7kWsCT dPGYZ0hGIDL9e5VkA51GnRH586vKa7/yJ/qORhCJjxfyZ2WLLroMZWNpqDD4uqYF00bD mjpTXgNuSV6TjdB1HW1nb4p2i3OZX/aTDaxZ5Rz77WFSx0+p1JtPBwsBQHH68N35rlRG Yf8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688735839; x=1691327839; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AunBb31YzZUjwaJ31r+ZHgWQ+d/p+0mUIZp67J/ATuk=; b=ToEgtHMNRzV6CF0SYpY+c4ZguRLF8h3VARYuIaFIq7A9W/qHHsKNXr1RW0gfze7fbw H/OUw2IvnMg1+XwAywFU80tql44vWtBzlnQxyA5pz7hE6rAagAVK7OUAdOTWKWoz7rux pie3oHGqWg/CvgOFVUGz48YqCVgS9Ao5gxF5OhvZBsxToojRd0wG01oC32dC/NeZoLqp 93ZhA0X6AbvmUsBd2GUj3+voUWoNxr1iHkmr1qHMmTRbw+3mA0I93L22zgkttQ6ZszB0 ApS5bQCsETVmZd6QjMdDszxn/udHLGZoZygNEGRlgP7tAIC7hRVPo1oh0MK0qP6cS5Nl K5Xg== X-Gm-Message-State: ABy/qLZMu7gLuLi2TOau85pNnqBhJNBDKIcE3ejYq+boIv5SL27v3JkV 3IG7WG5KluIMM1oauUFB20U= X-Google-Smtp-Source: APBJJlFi6xuMV5WqYTrbfSF9nbIsc9fvHJC1b3N0TSlFzrEp5v3x6vjRFsEz5OLhnO1Jj2NUJFhxLA== X-Received: by 2002:a05:6512:2005:b0:4f9:b032:5361 with SMTP id a5-20020a056512200500b004f9b0325361mr3620424lfb.10.1688735839167; Fri, 07 Jul 2023 06:17:19 -0700 (PDT) Received: from localhost (p200300e41f4b7100f22f74fffe1f3a53.dip0.t-ipconnect.de. [2003:e4:1f4b:7100:f22f:74ff:fe1f:3a53]) by smtp.gmail.com with ESMTPSA id v10-20020a05600c470a00b003f9b3829269sm10363055wmo.2.2023.07.07.06.17.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Jul 2023 06:17:18 -0700 (PDT) From: Thierry Reding To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding Cc: Jon Hunter , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH 5/7] dt-bindings: arm: tegra: pmc: Restructure pad configuration node schema Date: Fri, 7 Jul 2023 15:17:09 +0200 Message-ID: <20230707131711.2997956-5-thierry.reding@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230707131711.2997956-1-thierry.reding@gmail.com> References: <20230707131711.2997956-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Thierry Reding The pad configuration node schema in its current form can accidentally match other properties as well. Restructure the schema to better match how the device trees are using these. Signed-off-by: Thierry Reding --- .../arm/tegra/nvidia,tegra20-pmc.yaml | 181 ++++++++++++------ 1 file changed, 120 insertions(+), 61 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml index 82070d47ac7c..271aa8f80a65 100644 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml @@ -245,69 +245,82 @@ properties: - resets - '#power-domain-cells' -patternProperties: - "^[a-f0-9]+-[a-f0-9]+$": + pinmux: type: object - description: - This is a Pad configuration node. On Tegra SOCs a pad is a set of - pins which are configured as a group. The pin grouping is a fixed - attribute of the hardware. The PMC can be used to set pad power state - and signaling voltage. A pad can be either in active or power down mode. - The support for power state and signaling voltage configuration varies - depending on the pad in question. 3.3V and 1.8V signaling voltages - are supported on pins where software controllable signaling voltage - switching is available. - - The pad configuration state nodes are placed under the pmc node and they - are referred to by the pinctrl client properties. For more information - see Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt. - The pad name should be used as the value of the pins property in pin - configuration nodes. - - The following pads are present on Tegra124 and Tegra132 - audio, bb, cam, comp, csia, csb, cse, dsi, dsib, dsic, dsid, hdmi, hsic, - hv, lvds, mipi-bias, nand, pex-bias, pex-clk1, pex-clk2, pex-cntrl, - sdmmc1, sdmmc3, sdmmc4, sys_ddc, uart, usb0, usb1, usb2, usb_bias. - - The following pads are present on Tegra210 - audio, audio-hv, cam, csia, csib, csic, csid, csie, csif, dbg, - debug-nonao, dmic, dp, dsi, dsib, dsic, dsid, emmc, emmc2, gpio, hdmi, - hsic, lvds, mipi-bias, pex-bias, pex-clk1, pex-clk2, pex-cntrl, sdmmc1, - sdmmc3, spi, spi-hv, uart, usb0, usb1, usb2, usb3, usb-bias. - properties: - pins: - $ref: /schemas/types.yaml#/definitions/string - description: Must contain name of the pad(s) to be configured. - - low-power-enable: - $ref: /schemas/types.yaml#/definitions/flag - description: Configure the pad into power down mode. - - low-power-disable: - $ref: /schemas/types.yaml#/definitions/flag - description: Configure the pad into active mode. - - power-source: - $ref: /schemas/types.yaml#/definitions/uint32 - description: - Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or - TEGRA_IO_PAD_VOLTAGE_3V3 to select between signaling voltages. - The values are defined in - include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h. - Power state can be configured on all Tegra124 and Tegra132 - pads. None of the Tegra124 or Tegra132 pads support signaling - voltage switching. - All of the listed Tegra210 pads except pex-cntrl support power - state configuration. Signaling voltage switching is supported - on below Tegra210 pads. - audio, audio-hv, cam, dbg, dmic, gpio, pex-cntrl, sdmmc1, - sdmmc3, spi, spi-hv, and uart. - - required: - - pins - - additionalProperties: false + status: true + + additionalProperties: + type: object + description: | + This is a pad configuration node. On Tegra SoCs a pad is a set of pins + which are configured as a group. The pin grouping is a fixed attribute + of the hardware. The PMC can be used to set pad power state and + signaling voltage. A pad can be either in active or power down mode. + The support for power state and signaling voltage configuration varies + depending on the pad in question. 3.3V and 1.8V signaling voltages are + supported on pins where software controllable signaling voltage + switching is available. + + The pad configuration state nodes are placed under the pmc node and + they are referred to by the pinctrl client properties. For more + information see: + + Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt + + The pad name should be used as the value of the pins property in pin + configuration nodes. + + The following pads are present on Tegra124 and Tegra132: + + audio, bb, cam, comp, csia, csb, cse, dsi, dsib, dsic, dsid, hdmi, + hsic, hv, lvds, mipi-bias, nand, pex-bias, pex-clk1, pex-clk2, + pex-cntrl, sdmmc1, sdmmc3, sdmmc4, sys_ddc, uart, usb0, usb1, usb2, + usb_bias + + The following pads are present on Tegra210: + + audio, audio-hv, cam, csia, csib, csic, csid, csie, csif, dbg, + debug-nonao, dmic, dp, dsi, dsib, dsic, dsid, emmc, emmc2, gpio, + hdmi, hsic, lvds, mipi-bias, pex-bias, pex-clk1, pex-clk2, pex-cntrl, + sdmmc1, sdmmc3, spi, spi-hv, uart, usb0, usb1, usb2, usb3, usb-bias + additionalProperties: false + properties: + pins: + $ref: /schemas/types.yaml#/definitions/string-array + description: Must contain name of the pad(s) to be configured. + + low-power-enable: + $ref: /schemas/types.yaml#/definitions/flag + description: Configure the pad into power down mode. + + low-power-disable: + $ref: /schemas/types.yaml#/definitions/flag + description: Configure the pad into active mode. + + power-source: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or + TEGRA_IO_PAD_VOLTAGE_3V3 to select between signaling voltages. The + values are defined in: + + include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h + + Power state can be configured on all Tegra124 and Tegra132 pads. + None of the Tegra124 or Tegra132 pads support signaling voltage + switching. All of the listed Tegra210 pads except pex-cntrl support + power state configuration. Signaling voltage switching is supported + on the following Tegra210 pads: + + audio, audio-hv, cam, dbg, dmic, gpio, pex-cntrl, sdmmc1, sdmmc3, + spi, spi-hv, uart + + phandle: + $ref: /schemas/types.yaml#/definitions/uint32 + + required: + - pins required: - compatible @@ -316,6 +329,52 @@ required: - clocks - '#clock-cells' +allOf: + - if: + properties: + compatible: + contains: + const: nvidia,tegra124-pmc + then: + properties: + pinmux: + properties: + status: true + + additionalProperties: + type: object + properties: + pins: + items: + enum: [ audio, bb, cam, comp, csia, csb, cse, dsi, dsib, + dsic, dsid, hdmi, hsic, hv, lvds, mipi-bias, nand, + pex-bias, pex-clk1, pex-clk2, pex-cntrl, sdmmc1, + sdmmc3, sdmmc4, sys_ddc, uart, usb0, usb1, usb2, + usb_bias ] + + - if: + properties: + compatible: + contains: + const: nvidia,tegra210-pmc + then: + properties: + pinmux: + properties: + status: true + + additionalProperties: + type: object + properties: + pins: + items: + enum: [ audio, audio-hv, cam, csia, csib, csic, csid, csie, + csif, dbg, debug-nonao, dmic, dp, dsi, dsib, dsic, + dsid, emmc, emmc2, gpio, hdmi, hsic, lvds, mipi-bias, + pex-bias, pex-clk1, pex-clk2, pex-cntrl, sdmmc1, + sdmmc3, spi, spi-hv, uart, usb0, usb1, usb2, usb3, + usb-bias ] + additionalProperties: false dependencies: From patchwork Fri Jul 7 13:17:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 700187 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3AEDCC001DC for ; Fri, 7 Jul 2023 13:17:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232029AbjGGNRZ (ORCPT ); Fri, 7 Jul 2023 09:17:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45562 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229955AbjGGNRX (ORCPT ); Fri, 7 Jul 2023 09:17:23 -0400 Received: from mail-wm1-x332.google.com (mail-wm1-x332.google.com [IPv6:2a00:1450:4864:20::332]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C1F501FEB; Fri, 7 Jul 2023 06:17:21 -0700 (PDT) Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-3fbf1b82d9cso20041105e9.2; Fri, 07 Jul 2023 06:17:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1688735840; x=1691327840; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xsrBAfCGVNelsA/PKAK3tw2obc1qEvMP8nTj/zVYfec=; b=ALTfZxaV9Ay79vQgcqBUR7L/uoOwQZZ4jqPzkDebLybEhumAJeQuiitOiS3IFRdtNU aEOugqyOK8dOAvaZcY8WbKor9ofD3qGJzWvneu5dMVaee2yuNwXmhO9CWGtg+dwwBEkP cxbmvAApXjkTrOfP4surh6FfZ3B1QHvy4XP6TrIDlCKmIdNuPcudnDiDL35JV1HNkYpJ ljUSmpHp0CUtuMGiP2nxGvHGxng1eW/FkhKI2Cbx7lNZ4u5+r0xDdisikVkZYiCHZZ3t fihhUMZO1W0e75msALszFCHrYe+plKKFpa6lC4dPBx8LudzTOhvb3eRRmsCwaDSXnV93 qZYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688735840; x=1691327840; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xsrBAfCGVNelsA/PKAK3tw2obc1qEvMP8nTj/zVYfec=; b=C0/pIMLte5eEYeZ/MU7PUrsCzHDQSX7d3DjW9GkOl/UYhY8Qpmd44CYy5WcuNXJV8/ oct9M0I9uXQFZwtqrmtcapy3duOLokJ5OYQT3emWGLV3hJQUWKJAAka6IiUA2x1Bzc6L nyH9DCXkxOAQMxKU+4GNjXp5Uz6Bfsz0dNsnH5VoE/FI450yok+bLa0mgFX99mCdKyau zaI7U2h+NO5gIy0jSBXebXLWRvgGxSYT9WEAHlnJdbnuJEmzxTMIti6RATLmt7LWBCVy Ukph+XEMql5qcG5W5sMYPZP+7H/JlC9e12rKuGOGhYmoLVykg4Ix+iZS4l3apIpLUQUd JaAg== X-Gm-Message-State: ABy/qLZAx8PYwkC1WE05uJyNGq8a6rYZflzTw1cH5FHe6qeQYQ/X1kWB S71ADIsHTRjPiDalM2BQ7sc= X-Google-Smtp-Source: APBJJlE3gF5ilMRMliA8OtVBdwST0BYBJ3/KBkBLZzNnt9HNDVx3SaSZ1l8cwBv7q6jQx63fSDAtAQ== X-Received: by 2002:adf:e504:0:b0:314:248d:d9df with SMTP id j4-20020adfe504000000b00314248dd9dfmr4260597wrm.13.1688735840197; Fri, 07 Jul 2023 06:17:20 -0700 (PDT) Received: from localhost (p200300e41f4b7100f22f74fffe1f3a53.dip0.t-ipconnect.de. [2003:e4:1f4b:7100:f22f:74ff:fe1f:3a53]) by smtp.gmail.com with ESMTPSA id a5-20020adffb85000000b00313e4d02be8sm4458268wrr.55.2023.07.07.06.17.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Jul 2023 06:17:19 -0700 (PDT) From: Thierry Reding To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding Cc: Jon Hunter , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH 6/7] dt-bindings: arm: tegra: pmc: Reformat example Date: Fri, 7 Jul 2023 15:17:10 +0200 Message-ID: <20230707131711.2997956-6-thierry.reding@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230707131711.2997956-1-thierry.reding@gmail.com> References: <20230707131711.2997956-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Thierry Reding Reformat the example using 4 spaces for indentation. Signed-off-by: Thierry Reding --- .../arm/tegra/nvidia,tegra20-pmc.yaml | 77 +++++++++---------- 1 file changed, 38 insertions(+), 39 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml index 271aa8f80a65..f709a4a0853c 100644 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml @@ -384,47 +384,46 @@ dependencies: examples: - | - #include #include #include - tegra_pmc: pmc@7000e400 { - compatible = "nvidia,tegra210-pmc"; - reg = <0x7000e400 0x400>; - core-supply = <®ulator>; - clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; - clock-names = "pclk", "clk32k_in"; - #clock-cells = <1>; - - nvidia,invert-interrupt; - nvidia,suspend-mode = <0>; - nvidia,cpu-pwr-good-time = <0>; - nvidia,cpu-pwr-off-time = <0>; - nvidia,core-pwr-good-time = <4587 3876>; - nvidia,core-pwr-off-time = <39065>; - nvidia,core-power-req-active-high; - nvidia,sys-clock-req-active-high; - - pd_core: core-domain { - operating-points-v2 = <&core_opp_table>; - #power-domain-cells = <0>; - }; - - powergates { - pd_audio: aud { - clocks = <&tegra_car TEGRA210_CLK_APE>, - <&tegra_car TEGRA210_CLK_APB2APE>; - resets = <&tegra_car 198>; - power-domains = <&pd_core>; - #power-domain-cells = <0>; - }; - - pd_xusbss: xusba { - clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>; - resets = <&tegra_car TEGRA210_CLK_XUSB_SS>; - power-domains = <&pd_core>; - #power-domain-cells = <0>; - }; - }; + pmc@7000e400 { + compatible = "nvidia,tegra210-pmc"; + reg = <0x7000e400 0x400>; + core-supply = <®ulator>; + clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; + clock-names = "pclk", "clk32k_in"; + #clock-cells = <1>; + + nvidia,invert-interrupt; + nvidia,suspend-mode = <0>; + nvidia,cpu-pwr-good-time = <0>; + nvidia,cpu-pwr-off-time = <0>; + nvidia,core-pwr-good-time = <4587 3876>; + nvidia,core-pwr-off-time = <39065>; + nvidia,core-power-req-active-high; + nvidia,sys-clock-req-active-high; + + pd_core: core-domain { + operating-points-v2 = <&core_opp_table>; + #power-domain-cells = <0>; + }; + + powergates { + pd_audio: aud { + clocks = <&tegra_car TEGRA210_CLK_APE>, + <&tegra_car TEGRA210_CLK_APB2APE>; + resets = <&tegra_car 198>; + power-domains = <&pd_core>; + #power-domain-cells = <0>; + }; + + pd_xusbss: xusba { + clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>; + resets = <&tegra_car TEGRA210_CLK_XUSB_SS>; + power-domains = <&pd_core>; + #power-domain-cells = <0>; + }; + }; }; From patchwork Fri Jul 7 13:17:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 700402 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CF150C001DF for ; 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[2003:e4:1f4b:7100:f22f:74ff:fe1f:3a53]) by smtp.gmail.com with ESMTPSA id l11-20020a5d668b000000b003063db8f45bsm4444818wru.23.2023.07.07.06.17.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Jul 2023 06:17:20 -0700 (PDT) From: Thierry Reding To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding Cc: Jon Hunter , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH 7/7] dt-bindings: arm: tegra: pmc: Relicense and move into soc/tegra directory Date: Fri, 7 Jul 2023 15:17:11 +0200 Message-ID: <20230707131711.2997956-7-thierry.reding@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230707131711.2997956-1-thierry.reding@gmail.com> References: <20230707131711.2997956-1-thierry.reding@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Thierry Reding Dual-license this binding for consistency with other Tegra bindings and move it into the soc/tegra directory. Signed-off-by: Thierry Reding --- .../bindings/{arm => soc}/tegra/nvidia,tegra20-pmc.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) rename Documentation/devicetree/bindings/{arm => soc}/tegra/nvidia,tegra20-pmc.yaml (99%) diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml b/Documentation/devicetree/bindings/soc/tegra/nvidia,tegra20-pmc.yaml similarity index 99% rename from Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml rename to Documentation/devicetree/bindings/soc/tegra/nvidia,tegra20-pmc.yaml index f709a4a0853c..ef42f07e0572 100644 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml +++ b/Documentation/devicetree/bindings/soc/tegra/nvidia,tegra20-pmc.yaml @@ -1,7 +1,7 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-pmc.yaml# +$id: http://devicetree.org/schemas/soc/tegra/nvidia,tegra20-pmc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Tegra Power Management Controller (PMC)