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[176.184.47.225]) by smtp.gmail.com with ESMTPSA id f14-20020adfe90e000000b0030647449730sm18811wrm.74.2023.07.10.10.51.10 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 10 Jul 2023 10:51:11 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , Peter Maydell , Evgeny Iakovlev , =?utf-8?q?Alex_Benn=C3=A9e?= , Gavin Shan , Paolo Bonzini , qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 01/11] hw/char/pl011: Restrict MemoryRegionOps implementation access sizes Date: Mon, 10 Jul 2023 19:50:52 +0200 Message-Id: <20230710175102.32429-2-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230710175102.32429-1-philmd@linaro.org> References: <20230710175102.32429-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=philmd@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The pl011_read() and pl011_write() handlers shift the offset argument by 2, so are implemented on a 32-bit boundary. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- hw/char/pl011.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/char/pl011.c b/hw/char/pl011.c index 77bbc2a982..73f1a3aea2 100644 --- a/hw/char/pl011.c +++ b/hw/char/pl011.c @@ -358,6 +358,8 @@ static const MemoryRegionOps pl011_ops = { .read = pl011_read, .write = pl011_write, .endianness = DEVICE_NATIVE_ENDIAN, + .impl.min_access_size = 4, + .impl.max_access_size = 4, }; static bool pl011_clock_needed(void *opaque) From patchwork Mon Jul 10 17:50:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 701046 Delivered-To: patch@linaro.org Received: by 2002:adf:fcc5:0:0:0:0:0 with SMTP id f5csp5305346wrs; Mon, 10 Jul 2023 10:53:55 -0700 (PDT) X-Google-Smtp-Source: APBJJlFAmXN17bmizOf5domXplUHolw5hlLA9VSKxG+4Ks0wJ2VTFIyO+A9xEtGS58EOXZx3VuqG X-Received: by 2002:a05:620a:390d:b0:75b:23a1:35f9 with SMTP id qr13-20020a05620a390d00b0075b23a135f9mr14583330qkn.10.1689011635132; Mon, 10 Jul 2023 10:53:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689011635; cv=none; d=google.com; s=arc-20160816; b=es+7erGw8joD1Pd6Z0PGTR3c7VMtbTWWjyzec4kRz26mjV+fML3z9qOvR9xtn+Q0Hm kuMfKmWXRsqS5dZnm3XwA9hrns70lKL/WY8JDcVVgT3Q9+QS8asM0leEgL+Ki2Bjd2cV tuYM5xB+x34/NvxYxPfoIgQR7pNnVqad3qQX7HW1g+DwHFWPgobKzbmU+Hg0gbIg/NBU xy+cbDkKcSLz42hKTUs5C890PvkP/2cFPciGFeI0+RiHZU63n/oXILT27RmboLBzJ4kA 2pWcEmt/Ahzl/OITbzJQ5nEi0L4YKB3B46GgT8rD8G9U0q/ReWjsGD3f0Kzw1/sYnMDU 7f/w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=g1RcHKWAXUfeEYtWyqPORqFGKPtOv6GOxgVyqiigsFc=; fh=4TWVGTMFk+XB48cTX7H3L2FEUZf3X6lSQ5h15kr1III=; b=H6CwoIZAPtsOGhm/MWLASDoJdvlAKI/V3xixtEawjVZEJD+iOHdkUhgdv07A+Gbd4R sDUdXlYhlrKdvNLHgsfKaGv3lZleSOrFxKeFhiX/PISZMUtQNGIU3YuK3T3YNoPgOPhJ kP4IEwZdbLJaUVWIOWshi5r4Ojbeut652jSy8XkZI2DYMme/TiLxcoD+xC9I14fdiB/y +ht1DL9hB3wFRDX3+kLSEg//8n69N60aDHBBL2DE7Fcupl1VXRZwp6GID3QpMl4SkSIv 4wtLheV2nG2EJ9gANqGsmlsP2QBZh1H+ad5gh5eNqzZkW703FbQrF7oBT6xJoNPkemdX XfDA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=y5uUmDnN; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.184.47.225]) by smtp.gmail.com with ESMTPSA id w13-20020a5d4b4d000000b003143765e207sm30733wrs.49.2023.07.10.10.51.16 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 10 Jul 2023 10:51:17 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , Peter Maydell , Evgeny Iakovlev , =?utf-8?q?Alex_Benn=C3=A9e?= , Gavin Shan , Paolo Bonzini , qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 02/11] hw/char/pl011: Display register name in trace events Date: Mon, 10 Jul 2023 19:50:53 +0200 Message-Id: <20230710175102.32429-3-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230710175102.32429-1-philmd@linaro.org> References: <20230710175102.32429-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org To avoid knowing the register addresses by heart, display their name along in the trace events. Since the MMIO region is 4K wide (0x1000 bytes), displaying the address with 3 digits is enough, so reduce the address format. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée Reviewed-by: Richard Henderson --- hw/char/pl011.c | 25 ++++++++++++++++++++++--- hw/char/trace-events | 4 ++-- 2 files changed, 24 insertions(+), 5 deletions(-) diff --git a/hw/char/pl011.c b/hw/char/pl011.c index 73f1a3aea2..c3203e5b41 100644 --- a/hw/char/pl011.c +++ b/hw/char/pl011.c @@ -51,6 +51,7 @@ DeviceState *pl011_create(hwaddr addr, qemu_irq irq, Chardev *chr) #define PL011_INT_TX 0x20 #define PL011_INT_RX 0x10 +/* Flag Register, UARTFR */ #define PL011_FLAG_TXFE 0x80 #define PL011_FLAG_RXFF 0x40 #define PL011_FLAG_TXFF 0x20 @@ -76,6 +77,24 @@ static const unsigned char pl011_id_arm[8] = static const unsigned char pl011_id_luminary[8] = { 0x11, 0x00, 0x18, 0x01, 0x0d, 0xf0, 0x05, 0xb1 }; +static const char *pl011_regname(hwaddr offset) +{ + static const char *const rname[] = { + [0] = "DR", [1] = "RSR", [6] = "FR", [8] = "ILPR", [9] = "IBRD", + [10] = "FBRD", [11] = "LCRH", [12] = "CR", [13] = "IFLS", [14] = "IMSC", + [15] = "RIS", [16] = "MIS", [17] = "ICR", [18] = "DMACR", + }; + unsigned idx = offset >> 2; + + if (idx < ARRAY_SIZE(rname) && rname[idx]) { + return rname[idx]; + } + if (idx >= 0x3f8 && idx <= 0x400) { + return "ID"; + } + return "UNKN"; +} + /* Which bits in the interrupt status matter for each outbound IRQ line ? */ static const uint32_t irqmask[] = { INT_E | INT_MS | INT_RT | INT_TX | INT_RX, /* combined IRQ */ @@ -191,7 +210,7 @@ static uint64_t pl011_read(void *opaque, hwaddr offset, break; } - trace_pl011_read(offset, r); + trace_pl011_read(offset, r, pl011_regname(offset)); return r; } @@ -234,7 +253,7 @@ static void pl011_write(void *opaque, hwaddr offset, PL011State *s = (PL011State *)opaque; unsigned char ch; - trace_pl011_write(offset, value); + trace_pl011_write(offset, value, pl011_regname(offset)); switch (offset >> 2) { case 0: /* UARTDR */ @@ -252,7 +271,7 @@ static void pl011_write(void *opaque, hwaddr offset, case 6: /* UARTFR */ /* Writes to Flag register are ignored. */ break; - case 8: /* UARTUARTILPR */ + case 8: /* UARTILPR */ s->ilpr = value; break; case 9: /* UARTIBRD */ diff --git a/hw/char/trace-events b/hw/char/trace-events index 2ecb36232e..babf4d35ea 100644 --- a/hw/char/trace-events +++ b/hw/char/trace-events @@ -54,9 +54,9 @@ escc_sunmouse_event(int dx, int dy, int buttons_state) "dx=%d dy=%d buttons=0x%0 # pl011.c pl011_irq_state(int level) "irq state %d" -pl011_read(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x" +pl011_read(uint32_t addr, uint32_t value, const char *regname) "addr 0x%03x value 0x%08x reg %s" pl011_read_fifo(int read_count) "FIFO read, read_count now %d" -pl011_write(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x" +pl011_write(uint32_t addr, uint32_t value, const char *regname) "addr 0x%03x value 0x%08x reg %s" pl011_can_receive(uint32_t lcr, int read_count, int r) "LCR 0x%08x read_count %d returning %d" pl011_put_fifo(uint32_t c, int read_count) "new char 0x%x read_count now %d" pl011_put_fifo_full(void) "FIFO now full, RXFF set" From patchwork Mon Jul 10 17:50:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 701050 Delivered-To: patch@linaro.org Received: by 2002:adf:fcc5:0:0:0:0:0 with SMTP id f5csp5305470wrs; Mon, 10 Jul 2023 10:54:16 -0700 (PDT) X-Google-Smtp-Source: APBJJlEgh+WspnbCQPD6We74fGWrRokfCYizSkKy02NxH2HcRhlUz6sK0wNN3cYqi1eam8fG7rxN X-Received: by 2002:a05:622a:1653:b0:400:9c4e:2abe with SMTP id y19-20020a05622a165300b004009c4e2abemr15843693qtj.13.1689011656720; Mon, 10 Jul 2023 10:54:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689011656; cv=none; d=google.com; s=arc-20160816; b=I6WzTVOHTVxlT1tvrPs7kqqKE6zlnHuTgVKef/0vRylzHhMsp72hWMNL4SdVfSrHfA QAkFPRp+Fa04mcbKeMHrSjZFMudqRujYIktxw7icjDOsLIvS1fTs9pISsEQOU/tU7SxU fBvoKQEi1pZFXpCn13qDJAceKXs5W2L6rDLzTtk8uv4NCJreVL66vlQIlw0WBbgxc34L 5lRU9Gog+HP87FSXKnDxkn891MEfYmLK9yu7CSFgz4uLSm3TNmxn4AjAGfsLJsFPgmPZ 5udcAecQcknb/+5eQrcHILqwCqMpe0r/3ec9wS7vYVdz/s39neQ+qQT+0ILI4VjMJE2X p3nA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=MFiMwX80BmNyck0DZZOUXh/iAvr0cOgiPWTiwk+R4aM=; fh=4TWVGTMFk+XB48cTX7H3L2FEUZf3X6lSQ5h15kr1III=; b=xPXnIxN92sdJ0hTmZa7dKnL46vMAQ9B5qcrjxrgPJIO8gnhgxBujKxnOFckUK1GDI2 efORfFIFNC6Lfb5qXE0okRQyCfQwGt9lEmtPz76ZI/7dbAV9tc02N01SwO3FR0HsUIJP h1vyV4l4geuKR8nFFzeelE529vids7VO/UfH9p+2xMVw2BN+XSk9iBMBw+6BUh7VwaU6 l8sMyet+xIgRaXAFEiAFlJw/Y5V/OG5ORyf0jTOXfS5GKa1zU+20dOHQkIBKAFCPB2R6 zuJhO0A1ySq47cgUb6S13ZKwiTtYi7yYStBkTMt2SI+DJNKonkhBnnoLFYGV8rhaotws QNrg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NJq6cF1M; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.184.47.225]) by smtp.gmail.com with ESMTPSA id u13-20020a7bcb0d000000b003fbc9b9699dsm433256wmj.45.2023.07.10.10.51.22 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 10 Jul 2023 10:51:23 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , Peter Maydell , Evgeny Iakovlev , =?utf-8?q?Alex_Benn=C3=A9e?= , Gavin Shan , Paolo Bonzini , qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 03/11] hw/char/pl011: Remove duplicated PL011_INT_[RT]X definitions Date: Mon, 10 Jul 2023 19:50:54 +0200 Message-Id: <20230710175102.32429-4-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230710175102.32429-1-philmd@linaro.org> References: <20230710175102.32429-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philmd@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org PL011_INT_TX duplicates INT_TX, and PL011_INT_RX INT_RX. Follow other register fields definitions from this file, keep the shorter form. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée Reviewed-by: Richard Henderson --- hw/char/pl011.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/hw/char/pl011.c b/hw/char/pl011.c index c3203e5b41..96675f52cc 100644 --- a/hw/char/pl011.c +++ b/hw/char/pl011.c @@ -48,9 +48,6 @@ DeviceState *pl011_create(hwaddr addr, qemu_irq irq, Chardev *chr) return dev; } -#define PL011_INT_TX 0x20 -#define PL011_INT_RX 0x10 - /* Flag Register, UARTFR */ #define PL011_FLAG_TXFE 0x80 #define PL011_FLAG_RXFF 0x40 @@ -157,7 +154,7 @@ static uint64_t pl011_read(void *opaque, hwaddr offset, s->flags |= PL011_FLAG_RXFE; } if (s->read_count == s->read_trigger - 1) - s->int_level &= ~ PL011_INT_RX; + s->int_level &= ~ INT_RX; trace_pl011_read_fifo(s->read_count); s->rsr = c >> 8; pl011_update(s); @@ -262,7 +259,7 @@ static void pl011_write(void *opaque, hwaddr offset, /* XXX this blocks entire thread. Rewrite to use * qemu_chr_fe_write and background I/O callbacks */ qemu_chr_fe_write_all(&s->chr, &ch, 1); - s->int_level |= PL011_INT_TX; + s->int_level |= INT_TX; pl011_update(s); break; case 1: /* UARTRSR/UARTECR */ @@ -350,7 +347,7 @@ static void pl011_put_fifo(void *opaque, uint32_t value) s->flags |= PL011_FLAG_RXFF; } if (s->read_count == s->read_trigger) { - s->int_level |= PL011_INT_RX; + s->int_level |= INT_RX; pl011_update(s); } } From patchwork Mon Jul 10 17:50:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 701045 Delivered-To: patch@linaro.org Received: by 2002:adf:fcc5:0:0:0:0:0 with SMTP id f5csp5305291wrs; Mon, 10 Jul 2023 10:53:47 -0700 (PDT) X-Google-Smtp-Source: APBJJlGn9NApX0z/0DaVV5Y+qhvzM1EaBGHr8RJxI3Jz2tD5qoIRC0795l+FhG8VnDweYud7aNSS X-Received: by 2002:a0c:b3ce:0:b0:636:fda0:a23 with SMTP id b14-20020a0cb3ce000000b00636fda00a23mr10097988qvf.27.1689011627631; Mon, 10 Jul 2023 10:53:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689011627; cv=none; d=google.com; s=arc-20160816; b=W7VWY7JphNWM2ay2I6RAFymZtiLNUE6rJgwmAQxHjW0s09zQ2JgggTBWArAbuMI89w pGQVFH9Vr07lrJcf7KJYN/zLr7GSGYYyjoZIJBSPLAAeDuGorhhcgh3LSSBF92iqEMkZ FygWw9dLgXU+9PBIudsCmLBt+ISSs51LGUCVkp0qLq1hg10mTuILqNHHDImFLRqKKjPC ztp72Rm+2je0AmI0+KpKGUTbt6h6X1L9IQXx1kAARK5jcF1qnkuHzdAwYasbJ0IpEq/P VuHKe2yWW7b0mGhig7pklCHErkUQ3ZOz+vjwsO/nnctGTOTwiyK9Gbbj89OqhXhgxWJH bx1w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=5e/SO+N+RtoeTP991orha9zplbwHg+c4RLGUXXBx0k4=; fh=4TWVGTMFk+XB48cTX7H3L2FEUZf3X6lSQ5h15kr1III=; b=a2Ky2nSya53OAFYpTQQClUi7XtNQbQ5UcRd10eRSuhJOTsBPN4rx8ClkOl9TRXelEc Npxmwypu9qCzfqZyqxfPaQOeJ5qoUSJlmQDygRtdiwJeSgYuYMDJ8st1u8K48+0Dgzgq rAIX9dtS2z8pXFTWJhm0z+oWnkikSAnBcGjzkX/JqRzFw8lBaYamdLWx1mA2DrSU1ikS oWG8mLXuE6v+ARJmRAFuD5mNcNuBMz6LbdtvcyjyRJNcM5IUo//rKW7w04VdEKrtAvpg 1yABq6JIZss5olZagsweBiV8jSjPhfmmY29Apb+MqS3qLLhWpNR3ZAJhKWm/QUOrQudg J8Sg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=l1to8dCq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.184.47.225]) by smtp.gmail.com with ESMTPSA id q14-20020a05600000ce00b003062b2c5255sm36246wrx.40.2023.07.10.10.51.27 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 10 Jul 2023 10:51:28 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , Peter Maydell , Evgeny Iakovlev , =?utf-8?q?Alex_Benn=C3=A9e?= , Gavin Shan , Paolo Bonzini , qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 04/11] hw/char/pl011: Replace magic values by register field definitions Date: Mon, 10 Jul 2023 19:50:55 +0200 Message-Id: <20230710175102.32429-5-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230710175102.32429-1-philmd@linaro.org> References: <20230710175102.32429-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org 0x400 is Data Register Break Error (DR_BE), 0x10 is Line Control Register Fifo Enabled (LCR_FEN) and 0x1 is Send Break (LCR_BRK). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée Reviewed-by: Richard Henderson --- hw/char/pl011.c | 22 +++++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/hw/char/pl011.c b/hw/char/pl011.c index 96675f52cc..58edeb9ddb 100644 --- a/hw/char/pl011.c +++ b/hw/char/pl011.c @@ -54,6 +54,9 @@ DeviceState *pl011_create(hwaddr addr, qemu_irq irq, Chardev *chr) #define PL011_FLAG_TXFF 0x20 #define PL011_FLAG_RXFE 0x10 +/* Data Register, UARTDR */ +#define DR_BE (1 << 10) + /* Interrupt status bits in UARTRIS, UARTMIS, UARTIMSC */ #define INT_OE (1 << 10) #define INT_BE (1 << 9) @@ -69,6 +72,10 @@ DeviceState *pl011_create(hwaddr addr, qemu_irq irq, Chardev *chr) #define INT_E (INT_OE | INT_BE | INT_PE | INT_FE) #define INT_MS (INT_RI | INT_DSR | INT_DCD | INT_CTS) +/* Line Control Register, UARTLCR_H */ +#define LCR_FEN (1 << 4) +#define LCR_BRK (1 << 0) + static const unsigned char pl011_id_arm[8] = { 0x11, 0x10, 0x14, 0x00, 0x0d, 0xf0, 0x05, 0xb1 }; static const unsigned char pl011_id_luminary[8] = @@ -116,7 +123,7 @@ static void pl011_update(PL011State *s) static bool pl011_is_fifo_enabled(PL011State *s) { - return (s->lcr & 0x10) != 0; + return (s->lcr & LCR_FEN) != 0; } static inline unsigned pl011_get_fifo_depth(PL011State *s) @@ -218,7 +225,7 @@ static void pl011_set_read_trigger(PL011State *s) the threshold. However linux only reads the FIFO in response to an interrupt. Triggering the interrupt when the FIFO is non-empty seems to make things work. */ - if (s->lcr & 0x10) + if (s->lcr & LCR_FEN) s->read_trigger = (s->ifl >> 1) & 0x1c; else #endif @@ -281,11 +288,11 @@ static void pl011_write(void *opaque, hwaddr offset, break; case 11: /* UARTLCR_H */ /* Reset the FIFO state on FIFO enable or disable */ - if ((s->lcr ^ value) & 0x10) { + if ((s->lcr ^ value) & LCR_FEN) { pl011_reset_fifo(s); } - if ((s->lcr ^ value) & 0x1) { - int break_enable = value & 0x1; + if ((s->lcr ^ value) & LCR_BRK) { + int break_enable = value & LCR_BRK; qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_BREAK, &break_enable); } @@ -359,8 +366,9 @@ static void pl011_receive(void *opaque, const uint8_t *buf, int size) static void pl011_event(void *opaque, QEMUChrEvent event) { - if (event == CHR_EVENT_BREAK) - pl011_put_fifo(opaque, 0x400); + if (event == CHR_EVENT_BREAK) { + pl011_put_fifo(opaque, DR_BE); + } } static void pl011_clock_update(void *opaque, ClockEvent event) From patchwork Mon Jul 10 17:50:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 701049 Delivered-To: patch@linaro.org Received: by 2002:adf:fcc5:0:0:0:0:0 with SMTP id f5csp5305457wrs; Mon, 10 Jul 2023 10:54:16 -0700 (PDT) X-Google-Smtp-Source: APBJJlE00ZRLiL2zIJZOTCH2+g2SmWNYJPrlfJOmPfIoArOoVJhODzAXo0bKb2KxAhtG6sac+huS X-Received: by 2002:ac8:5907:0:b0:403:929f:12e2 with SMTP id 7-20020ac85907000000b00403929f12e2mr13646141qty.49.1689011655819; Mon, 10 Jul 2023 10:54:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689011655; cv=none; d=google.com; s=arc-20160816; b=CRDvMWvIJILqIJXNPD6WeJvJBLM56Dr8XoP42Y70Y4NUJ2O9rYnpFqQhAYMCxt+1Ln JtjeEyHlzFEoEVQmHkVgeqKx+yyQgOiaULvNYo+FhFApo/FZQvlCsY1RXncWuhSgE9ts 6h8Ye2z/cpxj2+urb5EbfkhB41tBp9+QwMVWDHVBUR18DFoOIerNXUXmsuEOydseFbJ8 O9YYAvq5vf6Eifj2yXSHfjnQqWZ3l8/SlR7oBehq57P/9F44xflXw2dfmgHys2rBY7pF iM/vLidrMbNzUMPvaNWh8ttceYfS7cFF5FqYZ+IyxmZq9ISHH1VQx/Si17cwgPOZIYSZ gLTA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=vINMBBFp0tNBmc0jxCNSawkrMv3zFmYswmW1JkHmuF4=; fh=4TWVGTMFk+XB48cTX7H3L2FEUZf3X6lSQ5h15kr1III=; b=YJk5aBUsm2oJPrqFpV2ReV4j8f5HhKrojeXnwKS/ExSJ2g8dk9mYvri33gbhNidPWx lIZda+Qf6X7wS+ohQ5hkFyefgfLQ21eVMQ5BF2YIm5z05zU/WSEvCRMiOe7LY+avRFPy IVUJbkuaSrIqEUyscqVDumAEoiOB+gtB97dohsMojez86oKMWkli7e3NPhwX12isceBy W+/6554dtFHkub3jKhxeB4riEBRwFrRjrCz8VYghrxKxpRdhRTVN5SLuLxzaMyRgI+6z 0QKrcmwBDqDrTFXitWbvYmFW7Bw2Fw2x+oKCZpC363/wp973FFntlndF5C8zgaWlWQTD fu3g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jn7tXF0V; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.184.47.225]) by smtp.gmail.com with ESMTPSA id k3-20020a5d66c3000000b00314398e4dd4sm29988wrw.54.2023.07.10.10.51.33 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 10 Jul 2023 10:51:34 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , Peter Maydell , Evgeny Iakovlev , =?utf-8?q?Alex_Benn=C3=A9e?= , Gavin Shan , Paolo Bonzini , qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 05/11] hw/char/pl011: Split RX/TX path of pl011_reset_fifo() Date: Mon, 10 Jul 2023 19:50:56 +0200 Message-Id: <20230710175102.32429-6-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230710175102.32429-1-philmd@linaro.org> References: <20230710175102.32429-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=philmd@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org To be able to reset the RX or TX FIFO separately, split pl011_reset_fifo() in two. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée Reviewed-by: Richard Henderson --- hw/char/pl011.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/hw/char/pl011.c b/hw/char/pl011.c index 58edeb9ddb..1f07c7b021 100644 --- a/hw/char/pl011.c +++ b/hw/char/pl011.c @@ -132,14 +132,21 @@ static inline unsigned pl011_get_fifo_depth(PL011State *s) return pl011_is_fifo_enabled(s) ? PL011_FIFO_DEPTH : 1; } -static inline void pl011_reset_fifo(PL011State *s) +static inline void pl011_reset_rx_fifo(PL011State *s) { s->read_count = 0; s->read_pos = 0; /* Reset FIFO flags */ - s->flags &= ~(PL011_FLAG_RXFF | PL011_FLAG_TXFF); - s->flags |= PL011_FLAG_RXFE | PL011_FLAG_TXFE; + s->flags &= ~PL011_FLAG_RXFF; + s->flags |= PL011_FLAG_RXFE; +} + +static inline void pl011_reset_tx_fifo(PL011State *s) +{ + /* Reset FIFO flags */ + s->flags &= ~PL011_FLAG_TXFF; + s->flags |= PL011_FLAG_TXFE; } static uint64_t pl011_read(void *opaque, hwaddr offset, @@ -289,7 +296,8 @@ static void pl011_write(void *opaque, hwaddr offset, case 11: /* UARTLCR_H */ /* Reset the FIFO state on FIFO enable or disable */ if ((s->lcr ^ value) & LCR_FEN) { - pl011_reset_fifo(s); + pl011_reset_rx_fifo(s); + pl011_reset_tx_fifo(s); } if ((s->lcr ^ value) & LCR_BRK) { int break_enable = value & LCR_BRK; @@ -506,7 +514,8 @@ static void pl011_reset(DeviceState *dev) s->ifl = 0x12; s->cr = 0x300; s->flags = 0; - pl011_reset_fifo(s); + pl011_reset_rx_fifo(s); + pl011_reset_tx_fifo(s); } static void pl011_class_init(ObjectClass *oc, void *data) From patchwork Mon Jul 10 17:50:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 701043 Delivered-To: patch@linaro.org Received: by 2002:adf:fcc5:0:0:0:0:0 with SMTP id f5csp5304901wrs; Mon, 10 Jul 2023 10:52:38 -0700 (PDT) X-Google-Smtp-Source: APBJJlFtGyueoXMhu/Sa/dnq5TPC/worzdyZGXA+Mt/2RjYPz3iYDmuczH78sGWWCga8RnWt2G12 X-Received: by 2002:a0c:f4c3:0:b0:632:1e12:cc35 with SMTP id o3-20020a0cf4c3000000b006321e12cc35mr11714402qvm.28.1689011557803; Mon, 10 Jul 2023 10:52:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689011557; cv=none; d=google.com; s=arc-20160816; b=yZKBhDhfWy2SqZvLPqV1w226POdFlIPnfGR+9O/3U/8zKjTEkZE221/egBRzFqEZXt YIKI5HlzdWXk+ku4CTtDIIEETO3uqjnaemH02kM2G1ZQyfS3XKloMTrT6VSa4ps3KmDy 5gyjAaM/MoDoZsl4KcS8Z7Ew+CvoCz2yjnVZPjjEp3yJg5qf8m0O4uN2YcapOdnI0WDf To/KWQcBOgGLFHpxyCcSceaV4UvFpTQSNNofU7D+WTMoTYRsCKjJBx0yZdRQtTDLRtzg KK/fkyzsfSbORMuLVHa2HTj9HP3m9e2qsCUKY/5hNwbPWRQ1hWV9VS0CFJAr9QekNRRz Wn8g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=HV7jdQi4bEVcp54eyyf8vkcdig+8iB+0mpkWJfR4/DM=; fh=4TWVGTMFk+XB48cTX7H3L2FEUZf3X6lSQ5h15kr1III=; b=NKhcXsDckCeAs2GxDCjvtk4xBhVsBRJPMiw0M+Ce9KX5844Y4xU7U0yDnnGZde/amx amQt2elmBySKb/OORw8vNXz0qZz3gCnhfOp+lpFSzdCbPJO9Em1YqzA/8K16zchyUyzQ 3mANKM0U8nnpwlHOqQ57dz19gxmjgwzSQwhkrhMLJvnJlIEcP7mXJLSANWMo9JlMOtKW TmO+m+9pjRClNRiAZ+d06rtdn1rsotTfMKrazXyqAPFFu1610Mqfm4ZugmNQYwrYFxpd Hhv2MFBdr3fAYQDNsJvol8kHPrN41ITEZSwsoypcXWtWUZj1/9YQmeNazv2/zPU00JYg pJnQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=fY5N0dtv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.184.47.225]) by smtp.gmail.com with ESMTPSA id cr13-20020a05600004ed00b003143ba62cf4sm15384wrb.86.2023.07.10.10.51.39 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 10 Jul 2023 10:51:40 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , Peter Maydell , Evgeny Iakovlev , =?utf-8?q?Alex_Benn=C3=A9e?= , Gavin Shan , Paolo Bonzini , qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 06/11] hw/char/pl011: Extract pl011_write_txdata() from pl011_write() Date: Mon, 10 Jul 2023 19:50:57 +0200 Message-Id: <20230710175102.32429-7-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230710175102.32429-1-philmd@linaro.org> References: <20230710175102.32429-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=philmd@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org When implementing FIFO, this code will become more complex. Start by factoring it out to a new pl011_write_txdata() function. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée --- hw/char/pl011.c | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/hw/char/pl011.c b/hw/char/pl011.c index 1f07c7b021..7bc7819d8b 100644 --- a/hw/char/pl011.c +++ b/hw/char/pl011.c @@ -149,6 +149,17 @@ static inline void pl011_reset_tx_fifo(PL011State *s) s->flags |= PL011_FLAG_TXFE; } +static void pl011_write_txdata(PL011State *s, const uint8_t *buf, int length) +{ + /* ??? Check if transmitter is enabled. */ + + /* XXX this blocks entire thread. Rewrite to use + * qemu_chr_fe_write and background I/O callbacks */ + qemu_chr_fe_write_all(&s->chr, buf, 1); + s->int_level |= INT_TX; + pl011_update(s); +} + static uint64_t pl011_read(void *opaque, hwaddr offset, unsigned size) { @@ -262,19 +273,12 @@ static void pl011_write(void *opaque, hwaddr offset, uint64_t value, unsigned size) { PL011State *s = (PL011State *)opaque; - unsigned char ch; trace_pl011_write(offset, value, pl011_regname(offset)); switch (offset >> 2) { case 0: /* UARTDR */ - /* ??? Check if transmitter is enabled. */ - ch = value; - /* XXX this blocks entire thread. Rewrite to use - * qemu_chr_fe_write and background I/O callbacks */ - qemu_chr_fe_write_all(&s->chr, &ch, 1); - s->int_level |= INT_TX; - pl011_update(s); + pl011_write_txdata(s, (uint8_t *) &value, 1); break; case 1: /* UARTRSR/UARTECR */ s->rsr = 0; From patchwork Mon Jul 10 17:50:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 701048 Delivered-To: patch@linaro.org Received: by 2002:adf:fcc5:0:0:0:0:0 with SMTP id f5csp5305455wrs; Mon, 10 Jul 2023 10:54:16 -0700 (PDT) X-Google-Smtp-Source: APBJJlFziAebFplImaLjbWcN3LoaKuAGzgVEX3FMYj+SUrfhcUXYdV7XBOeLEgoWGDMNklBjpcYt X-Received: by 2002:a05:622a:180d:b0:403:b0f3:8a9 with SMTP id t13-20020a05622a180d00b00403b0f308a9mr3437046qtc.61.1689011655751; Mon, 10 Jul 2023 10:54:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689011655; cv=none; d=google.com; s=arc-20160816; b=pdLHf/VWkmQwnVG2OsUOBCB1cExOxYR6PTn5+uNYM6Xs0hCPq8jaL7mHwhoAUxCcR8 2RA2tgdZYLn5f/1oVOKtItJQEgNXlJvSN/ki6lBg/DNzHyrwevlE+VKZSjzLpUM1ZlNS J5Jy7a+KsDFWezzFaCPUI5A5mkqlvYkhwq0m0vYl9wF5WfR9BLpgZJUkcPEq08RH0+Wb /IPsdDe969ZvKxgLkAEcsAr6crvP2iPHbF8LixKMeTwTS3aGHDJ6ou7fMxO5FK6e8YXo EE3+e7gwh3B8CNz3PQxWmBv0Y8KoU4XkjNWtTHd0Tq5euP6es9+3Ehb+/zVb3k3LWDgo Kftg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=OE5HK+6QzUc16kbWLHpwXHz/gljwcqm0t8YsiPIa+LE=; fh=4TWVGTMFk+XB48cTX7H3L2FEUZf3X6lSQ5h15kr1III=; b=pAvdRFY7D6lSfFaAhYQYb1XprApq+2XzdVvcw8LaSEKE073z/dTWuwRteoAh48Mn2B KorAVsp1uwanf/Id6nuDb8m1gEZFDMgnVmxBnFECZZcsKfUUV9vUU36AtK6G+ueoCQtc 9sf0EwRvStV3gMODV/BdlKZz4eZRGO/YPcEH5uP8zisKAnaKTNuYlbF0CPKwQU1kUc/3 NUZSUhSbYNIrQe751hsGtcJRS7ODslksVA/rSKq1bsadwq00sSjAqhYtG/bkqnwXs/uM VEiMoO4X8ADNHvUdVrUA99hKu0rVc2zQaBV/Qp7jx85r8SVUK5u9TTUVCpBb4KknvRwg uPGg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tsYQMg2N; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.184.47.225]) by smtp.gmail.com with ESMTPSA id k12-20020a7bc30c000000b003fba92fad35sm10908860wmj.26.2023.07.10.10.51.44 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 10 Jul 2023 10:51:46 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , Peter Maydell , Evgeny Iakovlev , =?utf-8?q?Alex_Benn=C3=A9e?= , Gavin Shan , Paolo Bonzini , qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 07/11] hw/char/pl011: Extract pl011_read_rxdata() from pl011_read() Date: Mon, 10 Jul 2023 19:50:58 +0200 Message-Id: <20230710175102.32429-8-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230710175102.32429-1-philmd@linaro.org> References: <20230710175102.32429-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org To keep MemoryRegionOps read/write handlers with similar logic, factor pl011_read_txdata() out of pl011_read(), similar to the previous commit did to pl011_write(). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- hw/char/pl011.c | 40 +++++++++++++++++++++++----------------- 1 file changed, 23 insertions(+), 17 deletions(-) diff --git a/hw/char/pl011.c b/hw/char/pl011.c index 7bc7819d8b..e2e3d48b91 100644 --- a/hw/char/pl011.c +++ b/hw/char/pl011.c @@ -160,31 +160,37 @@ static void pl011_write_txdata(PL011State *s, const uint8_t *buf, int length) pl011_update(s); } +static uint32_t pl011_read_rxdata(PL011State *s) +{ + uint32_t c; + + s->flags &= ~PL011_FLAG_RXFF; + c = s->read_fifo[s->read_pos]; + if (s->read_count > 0) { + s->read_count--; + s->read_pos = (s->read_pos + 1) & (pl011_get_fifo_depth(s) - 1); + } + if (s->read_count == 0) { + s->flags |= PL011_FLAG_RXFE; + } + if (s->read_count == s->read_trigger - 1) + s->int_level &= ~ INT_RX; + trace_pl011_read_fifo(s->read_count); + s->rsr = c >> 8; + pl011_update(s); + qemu_chr_fe_accept_input(&s->chr); + return c; +} + static uint64_t pl011_read(void *opaque, hwaddr offset, unsigned size) { PL011State *s = (PL011State *)opaque; - uint32_t c; uint64_t r; switch (offset >> 2) { case 0: /* UARTDR */ - s->flags &= ~PL011_FLAG_RXFF; - c = s->read_fifo[s->read_pos]; - if (s->read_count > 0) { - s->read_count--; - s->read_pos = (s->read_pos + 1) & (pl011_get_fifo_depth(s) - 1); - } - if (s->read_count == 0) { - s->flags |= PL011_FLAG_RXFE; - } - if (s->read_count == s->read_trigger - 1) - s->int_level &= ~ INT_RX; - trace_pl011_read_fifo(s->read_count); - s->rsr = c >> 8; - pl011_update(s); - qemu_chr_fe_accept_input(&s->chr); - r = c; + r = pl011_read_rxdata(s); break; case 1: /* UARTRSR */ r = s->rsr; From patchwork Mon Jul 10 17:50:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 701042 Delivered-To: patch@linaro.org Received: by 2002:adf:fcc5:0:0:0:0:0 with SMTP id f5csp5304787wrs; Mon, 10 Jul 2023 10:52:20 -0700 (PDT) X-Google-Smtp-Source: APBJJlGkXDiuVlOPuoTL/RCHjpRrWWNzZszisyw+58twVUTVkc4e1ISgGx8mDfaxZ9sCxXKrOHnt X-Received: by 2002:a05:620a:45a0:b0:765:67fe:5325 with SMTP id bp32-20020a05620a45a000b0076567fe5325mr14537530qkb.44.1689011540090; Mon, 10 Jul 2023 10:52:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689011540; cv=none; d=google.com; s=arc-20160816; b=Lz4clQ81YQ9OnAJ5LpKo35QFMUtkEq0EXydW9r4aZ6HJeZFOOvEc5gWp5EL2N2a8l/ HWj3qpl8rT0vNVnVUY1RP8tG1aS48Tbly7aXGVEMGSYqIbAvIVn/ysj9GJS3xGgj+QFI 0xxKBroxmfGP8r4nDHYPwV7CWT7MC2ibjBQX4WpOsxr7CsydiPxLc9ev4zzDHsPO8lH3 xQCoYOOaovxdU9x8RQLbQNr//JPIDqAkXmddRoG0ZLfFfA7XrDb+4elNsDh1k8EfbKxe REJqs5e1TjfEhooO5JF596O4RSYzLcBjckp/EYjCYnlZ0qp25H50lXseNBWEV2ReQ3Iy ILng== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=lXGp8ZoE5V8TDGBHBusqjmtpGceSTb5WuIHztmt2l2Q=; fh=4TWVGTMFk+XB48cTX7H3L2FEUZf3X6lSQ5h15kr1III=; b=gSA3BVPXZOqSRbKtjNLzvOeK3n5xzeWWMDPBnq3uLm87ruU/I+zpL46SGZPZs0b6la g+VMbA3sZ7mFmVRHEHkjjfVGk4kCJO65u/FhFfd8jMbsjgd8Y/RCKgi7C77di12KYkg9 VmeUznslVOhdu8f0D9305AmCFVbhDNWIY/wY97HnsXjWQ3xgaaHQ08gw4D90XbAa9RpZ szg7GLwK1jaycNo3g90faqoLrVjOYgCc2UK4kcpajyNwz9ALRZjA8pF8jaYevQeOQ5O7 qVJ1GaWHRstD+zRmxkBMma3oymUEylNf/t9xf/qBwGwfoCni1x6vYn1evPK+yJMx4R/H 1UNQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vKiyNgJX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.184.47.225]) by smtp.gmail.com with ESMTPSA id l3-20020a1ced03000000b003fc0062f0f8sm489126wmh.9.2023.07.10.10.51.50 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 10 Jul 2023 10:51:51 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , Peter Maydell , Evgeny Iakovlev , =?utf-8?q?Alex_Benn=C3=A9e?= , Gavin Shan , Paolo Bonzini , qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 08/11] hw/char/pl011: Warn when using disabled transmitter Date: Mon, 10 Jul 2023 19:50:59 +0200 Message-Id: <20230710175102.32429-9-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230710175102.32429-1-philmd@linaro.org> References: <20230710175102.32429-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philmd@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org We shouldn't transmit characters when the full UART or its transmitter is disabled. However we don't want to break the possibly incomplete "my first bare metal assembly program"s, so we choose to simply display a warning when this occurs. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée Reviewed-by: Richard Henderson --- hw/char/pl011.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/hw/char/pl011.c b/hw/char/pl011.c index e2e3d48b91..03dce0a1ec 100644 --- a/hw/char/pl011.c +++ b/hw/char/pl011.c @@ -76,6 +76,10 @@ DeviceState *pl011_create(hwaddr addr, qemu_irq irq, Chardev *chr) #define LCR_FEN (1 << 4) #define LCR_BRK (1 << 0) +/* Control Register, UARTCR */ +#define CR_TXE (1 << 8) +#define CR_UARTEN (1 << 0) + static const unsigned char pl011_id_arm[8] = { 0x11, 0x10, 0x14, 0x00, 0x0d, 0xf0, 0x05, 0xb1 }; static const unsigned char pl011_id_luminary[8] = @@ -151,7 +155,12 @@ static inline void pl011_reset_tx_fifo(PL011State *s) static void pl011_write_txdata(PL011State *s, const uint8_t *buf, int length) { - /* ??? Check if transmitter is enabled. */ + if (!(s->cr & CR_UARTEN)) { + qemu_log_mask(LOG_GUEST_ERROR, "PL011 write data but UART disabled\n"); + } + if (!(s->cr & CR_TXE)) { + qemu_log_mask(LOG_GUEST_ERROR, "PL011 write data but TX disabled\n"); + } /* XXX this blocks entire thread. Rewrite to use * qemu_chr_fe_write and background I/O callbacks */ From patchwork Mon Jul 10 17:51:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 701047 Delivered-To: patch@linaro.org Received: by 2002:adf:fcc5:0:0:0:0:0 with SMTP id f5csp5305446wrs; Mon, 10 Jul 2023 10:54:15 -0700 (PDT) X-Google-Smtp-Source: APBJJlGXJg6yfiAjvGH6Ha4BMlKfv3dyacpbFc/HXPxtDuO6/XctagK92QSuZdKs7ymlELlxTjfo X-Received: by 2002:a05:622a:130b:b0:402:36dd:20f6 with SMTP id v11-20020a05622a130b00b0040236dd20f6mr14616038qtk.53.1689011655254; Mon, 10 Jul 2023 10:54:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689011655; cv=none; d=google.com; s=arc-20160816; b=hq937UrVKfup8oU8EGxd7J5b95k3hxwq7aZw7BuDb2nKd+dz9REHgB45SlRrVaZev9 Yv4USjy+Hzfq+6Ycnss5OiMtOv5GCB+2XwKx8aWjj9GfEn8xn34fXI214poJtv9GFpel +h6z0jJf+b+xMHz5jzHKPvsa7G8H5etQm/BHu4Z4UlaG+SR+PZU7etnwa5iQZr+OcUFK JtIQqwEfgZe0Jn2GuzHD+q4w2HxT7/epKgpClzMoNfm6yAcNeowC57NLLCExMTwAjCJB dNbVupS6Mj2c+uEzdEyvrYOLkkUFS4LNvEhrAMcwUMLlR0pYzS3Cu2bVAxK6j/E7DMLe NUaA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=ef0gwQxZ6wwALYiU0bKC0wOaAk58Ouu2v7vVPMXHDsg=; fh=4TWVGTMFk+XB48cTX7H3L2FEUZf3X6lSQ5h15kr1III=; b=Z8DPAydn+FhcpRXyuq8BynsWk8VGuLihLGsHLv1ZDzdxGmhtXDZQpTkh3+2x6RfC6/ dXy9r/Gz0dCcHhNExKa+RJXhX7M3HcLuwuGYqRPaXDEBOuC0m5DHb0G22RTsUA4v5T9O m+wk7upAAiDYRapU8vAixPCZ592wjIOAxdETYun+ZZiii+3E0aLHH6Fq0cuX7MCegio+ p41OAD/o7lC3wVxqKJ1CezAzfDlcgy+7q4BT23oz+kG6jwaooUiIU+BAP8ete2tjZAng 5xRSxYzH1E1xi4xEF5aMqhqOm/8kX4ed3Y5P9BAUFKjGM+5KlBjrUvhk2mz3RRTMbfEd y+2g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=eb39i6i7; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.184.47.225]) by smtp.gmail.com with ESMTPSA id p7-20020a5d6387000000b003143801f8d8sm7154wru.103.2023.07.10.10.51.56 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 10 Jul 2023 10:51:57 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , Peter Maydell , Evgeny Iakovlev , =?utf-8?q?Alex_Benn=C3=A9e?= , Gavin Shan , Paolo Bonzini , qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 09/11] hw/char/pl011: Check if receiver is enabled Date: Mon, 10 Jul 2023 19:51:00 +0200 Message-Id: <20230710175102.32429-10-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230710175102.32429-1-philmd@linaro.org> References: <20230710175102.32429-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=philmd@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Do not receive characters when UART or receiver are disabled. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- hw/char/pl011.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/hw/char/pl011.c b/hw/char/pl011.c index 03dce0a1ec..59d239cb83 100644 --- a/hw/char/pl011.c +++ b/hw/char/pl011.c @@ -77,6 +77,7 @@ DeviceState *pl011_create(hwaddr addr, qemu_irq irq, Chardev *chr) #define LCR_BRK (1 << 0) /* Control Register, UARTCR */ +#define CR_RXE (1 << 9) #define CR_TXE (1 << 8) #define CR_UARTEN (1 << 0) @@ -357,9 +358,11 @@ static void pl011_write(void *opaque, hwaddr offset, static int pl011_can_receive(void *opaque) { PL011State *s = (PL011State *)opaque; - int r; + int r = 0; - r = s->read_count < pl011_get_fifo_depth(s); + if ((s->cr & CR_UARTEN) && (s->cr & CR_RXE)) { + r = s->read_count < pl011_get_fifo_depth(s); + } trace_pl011_can_receive(s->lcr, s->read_count, r); return r; } From patchwork Mon Jul 10 17:51:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 701051 Delivered-To: patch@linaro.org Received: by 2002:adf:fcc5:0:0:0:0:0 with SMTP id f5csp5305519wrs; Mon, 10 Jul 2023 10:54:24 -0700 (PDT) X-Google-Smtp-Source: APBJJlFMA/uO8gsPT/74sKhnAQB86akVze3k7roJJFXmdo/3ZfCDdderg6ZrqS8Mna2hm6m6dDe2 X-Received: by 2002:ac8:5785:0:b0:3fd:e5d2:f47 with SMTP id v5-20020ac85785000000b003fde5d20f47mr13560723qta.12.1689011664514; Mon, 10 Jul 2023 10:54:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689011664; cv=none; d=google.com; s=arc-20160816; b=mwJH40m4lSsX5CbvsqPD85Xm3iKzau/5o4y78ft4sOAFAeqRp3CnGBo0swm10w0zsS 6TN8sCbtMPMuYn+377QD06iJ+knMkK0ZpH59d05qJe7jPcTb9t9j1T4q5oF0u7v9sL4c JCEYvx7aUTlC6RgC70VeCFZAxPRjAmohjRQVHLBppnbdEfjKQAKRyWwpk58O198qTziL uTyu5A6cwXxVBc0gpKMYeA7IPHxuybppNaBYA7ftaeSfc6TeEHfjacgvL4Cy2I+CDmqP D9LkVRUbW/PfOpx62UEdUEGDCTbrmdau7tTVKOs48kllCgU1JFuSCcTeT9nngKRNvcXg /F3Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=NZ8DNr0ETWD1Ms+NV1FciyuZYg6CvPu0oUthK2WDbYk=; fh=4TWVGTMFk+XB48cTX7H3L2FEUZf3X6lSQ5h15kr1III=; b=YTdolNmWuiWE2oLaDODp9pwOEq8rtVxRjff0fOuE5jeOL41bs+v/IaTO9T7AC6d53Q wUU/qtCxlXMHTkkU2fiKEMRmKcneOdFHO0dw1dhxV3P/Gv8RQoBy/XmP0xoeiJgUOivZ a5VH2SxkwhFiDohIesehjEoW6dbeKaxQaq9rWtlMVLWHkxdnW9NrXlpiwpfWAv6JwvoN W1Y4iXgj1NfbTD0dLkgVl0QwpjsFwA24M3gLONfbJbuqtbGS6GX1bOrKaQ3FgevPKSf4 vM04B0roID70I4B9eTBRx84YUpIVeap/5oFi/F1ompaBlC5qJ3iwIkYlpQze6qOk5IE2 U3CQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="jRPo//N8"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.184.47.225]) by smtp.gmail.com with ESMTPSA id d6-20020adfe846000000b0030fd03e3d25sm20872wrn.75.2023.07.10.10.52.02 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 10 Jul 2023 10:52:03 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , Peter Maydell , Evgeny Iakovlev , =?utf-8?q?Alex_Benn=C3=A9e?= , Gavin Shan , Paolo Bonzini , qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 10/11] hw/char/pl011: Rename RX FIFO methods Date: Mon, 10 Jul 2023 19:51:01 +0200 Message-Id: <20230710175102.32429-11-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230710175102.32429-1-philmd@linaro.org> References: <20230710175102.32429-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=philmd@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In preparation of having a TX FIFO, rename the RX FIFO methods. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée Reviewed-by: Richard Henderson --- hw/char/pl011.c | 10 +++++----- hw/char/trace-events | 4 ++-- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/hw/char/pl011.c b/hw/char/pl011.c index 59d239cb83..7c785e7bb0 100644 --- a/hw/char/pl011.c +++ b/hw/char/pl011.c @@ -367,7 +367,7 @@ static int pl011_can_receive(void *opaque) return r; } -static void pl011_put_fifo(void *opaque, uint32_t value) +static void pl011_fifo_rx_put(void *opaque, uint32_t value) { PL011State *s = (PL011State *)opaque; int slot; @@ -378,9 +378,9 @@ static void pl011_put_fifo(void *opaque, uint32_t value) s->read_fifo[slot] = value; s->read_count++; s->flags &= ~PL011_FLAG_RXFE; - trace_pl011_put_fifo(value, s->read_count); + trace_pl011_fifo_rx_put(value, s->read_count); if (s->read_count == pipe_depth) { - trace_pl011_put_fifo_full(); + trace_pl011_fifo_rx_full(); s->flags |= PL011_FLAG_RXFF; } if (s->read_count == s->read_trigger) { @@ -391,13 +391,13 @@ static void pl011_put_fifo(void *opaque, uint32_t value) static void pl011_receive(void *opaque, const uint8_t *buf, int size) { - pl011_put_fifo(opaque, *buf); + pl011_fifo_rx_put(opaque, *buf); } static void pl011_event(void *opaque, QEMUChrEvent event) { if (event == CHR_EVENT_BREAK) { - pl011_put_fifo(opaque, DR_BE); + pl011_fifo_rx_put(opaque, DR_BE); } } diff --git a/hw/char/trace-events b/hw/char/trace-events index babf4d35ea..9fd40e3aae 100644 --- a/hw/char/trace-events +++ b/hw/char/trace-events @@ -58,8 +58,8 @@ pl011_read(uint32_t addr, uint32_t value, const char *regname) "addr 0x%03x valu pl011_read_fifo(int read_count) "FIFO read, read_count now %d" pl011_write(uint32_t addr, uint32_t value, const char *regname) "addr 0x%03x value 0x%08x reg %s" pl011_can_receive(uint32_t lcr, int read_count, int r) "LCR 0x%08x read_count %d returning %d" -pl011_put_fifo(uint32_t c, int read_count) "new char 0x%x read_count now %d" -pl011_put_fifo_full(void) "FIFO now full, RXFF set" +pl011_fifo_rx_put(uint32_t c, int read_count) "new char 0x%02x read_count now %d" +pl011_fifo_rx_full(void) "RX FIFO now full, RXFF set" pl011_baudrate_change(unsigned int baudrate, uint64_t clock, uint32_t ibrd, uint32_t fbrd) "new baudrate %u (clk: %" PRIu64 "hz, ibrd: %" PRIu32 ", fbrd: %" PRIu32 ")" # cmsdk-apb-uart.c From patchwork Mon Jul 10 17:51:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 701044 Delivered-To: patch@linaro.org Received: by 2002:adf:fcc5:0:0:0:0:0 with SMTP id f5csp5305082wrs; Mon, 10 Jul 2023 10:53:10 -0700 (PDT) X-Google-Smtp-Source: APBJJlH/JfcqULbcUzVMiHew2rHN6wYvOxnKvW9asGuRwsM1egVD1UOknkflhlz03Hv4SJwNQrqP X-Received: by 2002:a05:620a:c50:b0:765:758d:5be8 with SMTP id u16-20020a05620a0c5000b00765758d5be8mr12434289qki.0.1689011590268; Mon, 10 Jul 2023 10:53:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689011590; cv=none; d=google.com; s=arc-20160816; b=j0ae17VVaXfj7SlHQSYhefJaOubuQPffMlAtCP0SS641ivUfrTIiP0RXHP/aifTPoa iCCIeF4FGn98xKnY4zuaiCl+pqULmxLa7XZKA35N527887PUVfehpEHls0qxx85jwZLj 163IpcHhtBapPmhKKWUI0sSBf1QMRVIzQcd3ZF6vwMG0Y/pkjS7mQJ597oKqVbjsTefp Ev+sXWy1UOYM1rnjAJ7Gu+t8zQG8bkKYUcEute5vb2XMmA2LxWVB2SgNPfE74C8TMScq 31vBF1M4zveLJghI5HfC62GB9jCZeK1asAkVGgbc1sI29XvNR1bLa6JsTGZ8yIi0ix8H GvXA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=qOM6YlvdwPEkIJATvf5aWwHQXWtlyzUZX4uuGNKyOYI=; fh=h2ztgUZ2XV+ir99uJ/APPfzm77wVDZASNC4DoaahShk=; b=vv4BkyRmqSLl8BEEzsHuBYXR7Q2kaJZ78bS9GczBKmcJod/naz18O7PZyW/UlMnexu zcbzx394a/kTjL418NhnBTweeqQR3Rju6THHhQ0gtxM0ywNcROqYPJjOO5xFSzu0G1NR zP1RpNswIYJiR1V+cGq+tjvyoqxYzBbPAnIc4/QgSMKhCGExnyeZo315mXQYghr0R4wo ST6s6VQHC26fHIazdEveGN55DoUEsRFcv6UmORqGmHEXBSixEqgjkB3OhDvI8iqojLuP 4/eILAgSzD3JziuRWTOBnbXQMJDhLKCfCFiMZOM7jWiHIb6Fy2slnaQEW66zOWqM+6BI pu+Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pQpdtX2F; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.184.47.225]) by smtp.gmail.com with ESMTPSA id m20-20020a7bcb94000000b003fbfea1afffsm461613wmi.27.2023.07.10.10.52.07 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 10 Jul 2023 10:52:09 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , Peter Maydell , Evgeny Iakovlev , =?utf-8?q?Alex_Benn=C3=A9e?= , Gavin Shan , Paolo Bonzini , qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Mikko Rapeli Subject: [RFC PATCH v2 11/11] hw/char/pl011: Implement TX FIFO Date: Mon, 10 Jul 2023 19:51:02 +0200 Message-Id: <20230710175102.32429-12-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230710175102.32429-1-philmd@linaro.org> References: <20230710175102.32429-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org If the UART back-end chardev doesn't drain data as fast as stdout does or blocks, buffer in the TX FIFO to try again later. This avoids having the IO-thread busy waiting on chardev back-ends, reported recently when testing the Trusted Reference Stack and using the socket backend: https://linaro.atlassian.net/browse/TRS-149?focusedCommentId=149574 Implement registering a front-end 'watch' callback on back-end events, so we can resume transmitting when the back-end is writable again, not blocking the main loop. Similarly to the RX FIFO path, FIFO level selection is not implemented (interrupt is triggered when a single byte is available in the FIFO). We only migrate the TX FIFO if it is in use. Reported-by: Mikko Rapeli Suggested-by: Alex Bennée Signed-off-by: Philippe Mathieu-Daudé --- RFC: Again for the migration part. --- include/hw/char/pl011.h | 2 + hw/char/pl011.c | 108 ++++++++++++++++++++++++++++++++++++++-- hw/char/trace-events | 4 ++ 3 files changed, 109 insertions(+), 5 deletions(-) diff --git a/include/hw/char/pl011.h b/include/hw/char/pl011.h index d853802132..20898f43a6 100644 --- a/include/hw/char/pl011.h +++ b/include/hw/char/pl011.h @@ -18,6 +18,7 @@ #include "hw/sysbus.h" #include "chardev/char-fe.h" #include "qom/object.h" +#include "qemu/fifo8.h" #define TYPE_PL011 "pl011" OBJECT_DECLARE_SIMPLE_TYPE(PL011State, PL011) @@ -53,6 +54,7 @@ struct PL011State { Clock *clk; bool migrate_clk; const unsigned char *id; + Fifo8 xmit_fifo; }; DeviceState *pl011_create(hwaddr addr, qemu_irq irq, Chardev *chr); diff --git a/hw/char/pl011.c b/hw/char/pl011.c index 7c785e7bb0..4392773327 100644 --- a/hw/char/pl011.c +++ b/hw/char/pl011.c @@ -57,6 +57,9 @@ DeviceState *pl011_create(hwaddr addr, qemu_irq irq, Chardev *chr) /* Data Register, UARTDR */ #define DR_BE (1 << 10) +/* Receive Status Register/Error Clear Register, UARTRSR/UARTECR */ +#define RSR_OE (1 << 3) + /* Interrupt status bits in UARTRIS, UARTMIS, UARTIMSC */ #define INT_OE (1 << 10) #define INT_BE (1 << 9) @@ -152,6 +155,59 @@ static inline void pl011_reset_tx_fifo(PL011State *s) /* Reset FIFO flags */ s->flags &= ~PL011_FLAG_TXFF; s->flags |= PL011_FLAG_TXFE; + + fifo8_reset(&s->xmit_fifo); +} + +static gboolean pl011_drain_tx(PL011State *s) +{ + trace_pl011_fifo_tx_drain(fifo8_num_used(&s->xmit_fifo)); + pl011_reset_tx_fifo(s); + s->rsr &= ~RSR_OE; + return G_SOURCE_REMOVE; +} + +static gboolean pl011_xmit(void *do_not_use, GIOCondition cond, void *opaque) +{ + PL011State *s = opaque; + int ret; + const uint8_t *buf; + uint32_t buflen; + uint32_t count; + bool tx_enabled; + + if (!qemu_chr_fe_backend_connected(&s->chr)) { + /* Instant drain the fifo when there's no back-end */ + return pl011_drain_tx(s); + } + + tx_enabled = s->cr & CR_UARTEN; + /* Allow completing the current FIFO character before stopping. */ + count = tx_enabled ? fifo8_num_used(&s->xmit_fifo) : 1; /* current only */ + if (count) { + /* Transmit as much data as we can */ + buf = fifo8_peek_buf(&s->xmit_fifo, count, &buflen); + ret = qemu_chr_fe_write(&s->chr, buf, buflen); + if (ret >= 0) { + /* Pop the data we could transmit */ + trace_pl011_fifo_tx_xmit(ret); + fifo8_pop_buf(&s->xmit_fifo, ret, NULL); + s->int_level |= INT_TX; + } + + if (tx_enabled && !fifo8_is_empty(&s->xmit_fifo)) { + /* Reschedule another transmission if we couldn't transmit all */ + guint r = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP, + pl011_xmit, s); + if (!r) { + return pl011_drain_tx(s); + } + } + + pl011_update(s); + } + + return G_SOURCE_REMOVE; } static void pl011_write_txdata(PL011State *s, const uint8_t *buf, int length) @@ -162,12 +218,32 @@ static void pl011_write_txdata(PL011State *s, const uint8_t *buf, int length) if (!(s->cr & CR_TXE)) { qemu_log_mask(LOG_GUEST_ERROR, "PL011 write data but TX disabled\n"); } + if (!fifo8_is_empty(&s->xmit_fifo)) { + /* + * If the UART is disabled in the middle of transmission + * or reception, it completes the current character before + * stopping. + */ + pl011_xmit(NULL, G_IO_OUT, s); + return; + } - /* XXX this blocks entire thread. Rewrite to use - * qemu_chr_fe_write and background I/O callbacks */ - qemu_chr_fe_write_all(&s->chr, buf, 1); - s->int_level |= INT_TX; - pl011_update(s); + if (length > fifo8_num_free(&s->xmit_fifo)) { + /* + * The FIFO contents remain valid because no more data is + * written when the FIFO is full, only the contents of the + * shift register are overwritten. The CPU must now read + * the data, to empty the FIFO. + */ + trace_pl011_fifo_tx_overrun(); + s->rsr |= RSR_OE; + return; + } + + trace_pl011_fifo_tx_put(length); + fifo8_push_all(&s->xmit_fifo, buf, length); + + pl011_xmit(NULL, G_IO_OUT, s); } static uint32_t pl011_read_rxdata(PL011State *s) @@ -434,6 +510,13 @@ static const VMStateDescription vmstate_pl011_clock = { } }; +static bool pl011_xmit_fifo_state_needed(void *opaque, int version_id) +{ + PL011State* s = opaque; + + return pl011_is_fifo_enabled(s) && !fifo8_is_empty(&s->xmit_fifo); +} + static int pl011_post_load(void *opaque, int version_id) { PL011State* s = opaque; @@ -455,6 +538,11 @@ static int pl011_post_load(void *opaque, int version_id) s->read_pos = 0; } + if (pl011_xmit_fifo_state_needed(s, version_id)) { + /* Reschedule another transmission */ + qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP, pl011_xmit, s); + } + return 0; } @@ -473,6 +561,7 @@ static const VMStateDescription vmstate_pl011 = { VMSTATE_UINT32(int_enabled, PL011State), VMSTATE_UINT32(int_level, PL011State), VMSTATE_UINT32_ARRAY(read_fifo, PL011State, PL011_FIFO_DEPTH), + VMSTATE_FIFO8_TEST(xmit_fifo, PL011State, pl011_xmit_fifo_state_needed), VMSTATE_UINT32(ilpr, PL011State), VMSTATE_UINT32(ibrd, PL011State), VMSTATE_UINT32(fbrd, PL011State), @@ -500,6 +589,7 @@ static void pl011_init(Object *obj) PL011State *s = PL011(obj); int i; + fifo8_create(&s->xmit_fifo, PL011_FIFO_DEPTH); memory_region_init_io(&s->iomem, OBJECT(s), &pl011_ops, s, "pl011", 0x1000); sysbus_init_mmio(sbd, &s->iomem); for (i = 0; i < ARRAY_SIZE(s->irq); i++) { @@ -512,6 +602,13 @@ static void pl011_init(Object *obj) s->id = pl011_id_arm; } +static void pl011_finalize(Object *obj) +{ + PL011State *s = PL011(obj); + + fifo8_destroy(&s->xmit_fifo); +} + static void pl011_realize(DeviceState *dev, Error **errp) { PL011State *s = PL011(dev); @@ -555,6 +652,7 @@ static const TypeInfo pl011_arm_info = { .parent = TYPE_SYS_BUS_DEVICE, .instance_size = sizeof(PL011State), .instance_init = pl011_init, + .instance_finalize = pl011_finalize, .class_init = pl011_class_init, }; diff --git a/hw/char/trace-events b/hw/char/trace-events index 9fd40e3aae..4c25564066 100644 --- a/hw/char/trace-events +++ b/hw/char/trace-events @@ -60,6 +60,10 @@ pl011_write(uint32_t addr, uint32_t value, const char *regname) "addr 0x%03x val pl011_can_receive(uint32_t lcr, int read_count, int r) "LCR 0x%08x read_count %d returning %d" pl011_fifo_rx_put(uint32_t c, int read_count) "new char 0x%02x read_count now %d" pl011_fifo_rx_full(void) "RX FIFO now full, RXFF set" +pl011_fifo_tx_put(int count) "TX FIFO push %d" +pl011_fifo_tx_xmit(int count) "TX FIFO pop %d" +pl011_fifo_tx_overrun(void) "TX FIFO overrun" +pl011_fifo_tx_drain(unsigned drained) "TX FIFO draining %u" pl011_baudrate_change(unsigned int baudrate, uint64_t clock, uint32_t ibrd, uint32_t fbrd) "new baudrate %u (clk: %" PRIu64 "hz, ibrd: %" PRIu32 ", fbrd: %" PRIu32 ")" # cmsdk-apb-uart.c