From patchwork Wed Jul 12 11:35:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Praveenkumar I X-Patchwork-Id: 702012 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 51F1EC04A94 for ; Wed, 12 Jul 2023 11:36:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232215AbjGLLgn (ORCPT ); Wed, 12 Jul 2023 07:36:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55430 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231407AbjGLLgl (ORCPT ); Wed, 12 Jul 2023 07:36:41 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C304B173C; Wed, 12 Jul 2023 04:36:39 -0700 (PDT) Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 36CBKr5k022041; Wed, 12 Jul 2023 11:36:33 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=lSVYweG+1iyXPoWcryC7PWa2xXmh7bxu4CPY4+blMek=; b=l63iKdt0DOqY+vEfqVozrmCPsxED15eUdQ1iLpPVefoA1QnIPn8daApBuQDKAutsn0z1 JppPMeGwya8S9/pjfrZBN6NdTqPw+Qe3SMR+OXBWpAx6B4fWy0cabfaeWhpj6NvMiQ1u icSt1+m/M8myLemFWVjTxCdGtwbq810Z0y++9zq0vnlgCHaDrn6MAAeW0e17AoQvNkuE 9uJP0vhEjgwea7rQCEs5N9Pw7pO0nD1cAOruOFovTt0kQx5OaIWve/c1r7Rd5V+iyZ1x pSfD9r2sOrSShI2UEjDx3fex+16ogyjEYVBfCWnpBqm0U5Vh1az8usYGrcgVujJAuy78 FA== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3rshyu92uk-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 12 Jul 2023 11:36:33 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 36CBaWpi007983 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 12 Jul 2023 11:36:32 GMT Received: from hu-ipkumar-blr.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Wed, 12 Jul 2023 04:36:01 -0700 From: Praveenkumar I To: , , , , , , , , , , , , , , CC: Subject: [PATCH v2 1/5] thermal/drivers/tsens: Add TSENS enable and calibration support for V2 Date: Wed, 12 Jul 2023 17:05:35 +0530 Message-ID: <20230712113539.4029941-2-quic_ipkumar@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230712113539.4029941-1-quic_ipkumar@quicinc.com> References: <20230712113539.4029941-1-quic_ipkumar@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 2kC3u8vEZj_q29R40xkkFwroyV7Ghewa X-Proofpoint-ORIG-GUID: 2kC3u8vEZj_q29R40xkkFwroyV7Ghewa X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-12_06,2023-07-11_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 malwarescore=0 bulkscore=0 spamscore=0 mlxlogscore=999 phishscore=0 clxscore=1015 mlxscore=0 adultscore=0 suspectscore=0 lowpriorityscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2307120103 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org SoCs without RPM have to enable sensors and calibrate from the kernel. Though TSENS IP supports 16 sensors, not all are used. So used hw_id to enable the relevant sensors. Added new calibration function for V2 as the tsens.c calib function only supports V1. Signed-off-by: Praveenkumar I --- [v2]: Added separate init function for tsens v2 which calls init_common and initialize the remaining fields. Reformatted calibrate function and used hw_ids for sensors to enable. drivers/thermal/qcom/tsens-v2.c | 144 ++++++++++++++++++++++++++++++++ drivers/thermal/qcom/tsens.c | 2 +- drivers/thermal/qcom/tsens.h | 3 + 3 files changed, 148 insertions(+), 1 deletion(-) diff --git a/drivers/thermal/qcom/tsens-v2.c b/drivers/thermal/qcom/tsens-v2.c index 29a61d2d6ca3..ba74d971fe95 100644 --- a/drivers/thermal/qcom/tsens-v2.c +++ b/drivers/thermal/qcom/tsens-v2.c @@ -6,11 +6,23 @@ #include #include +#include #include "tsens.h" /* ----- SROT ------ */ #define SROT_HW_VER_OFF 0x0000 #define SROT_CTRL_OFF 0x0004 +#define SROT_MEASURE_PERIOD 0x0008 +#define SROT_Sn_CONVERSION 0x0060 +#define V2_SHIFT_DEFAULT 0x0003 +#define V2_SLOPE_DEFAULT 0x0cd0 +#define V2_CZERO_DEFAULT 0x016a +#define ONE_PT_SLOPE 0x0cd0 +#define TWO_PT_SHIFTED_GAIN 921600 +#define ONE_PT_CZERO_CONST 94 +#define SENSOR_CONVERSION(n) (((n) * 4) + SROT_Sn_CONVERSION) +#define CONVERSION_SLOPE_SHIFT 10 +#define CONVERSION_SHIFT_SHIFT 23 /* ----- TM ------ */ #define TM_INT_EN_OFF 0x0004 @@ -59,6 +71,11 @@ static const struct reg_field tsens_v2_regfields[MAX_REGFIELDS] = { /* CTRL_OFF */ [TSENS_EN] = REG_FIELD(SROT_CTRL_OFF, 0, 0), [TSENS_SW_RST] = REG_FIELD(SROT_CTRL_OFF, 1, 1), + [SENSOR_EN] = REG_FIELD(SROT_CTRL_OFF, 3, 18), + [CODE_OR_TEMP] = REG_FIELD(SROT_CTRL_OFF, 21, 21), + + /* MAIN_MEASURE_PERIOD */ + [MAIN_MEASURE_PERIOD] = REG_FIELD(SROT_MEASURE_PERIOD, 0, 7), /* ----- TM ------ */ /* INTERRUPT ENABLE */ @@ -104,6 +121,133 @@ static const struct reg_field tsens_v2_regfields[MAX_REGFIELDS] = { [TRDY] = REG_FIELD(TM_TRDY_OFF, 0, 0), }; +static int tsens_v2_calibrate_sensor(struct device *dev, struct tsens_sensor *sensor, + struct regmap *map, u32 mode, u32 base0, u32 base1) +{ + u32 slope, czero, val; + char name[15]; + int ret; + + /* Read offset value */ + ret = snprintf(name, sizeof(name), "s%d", sensor->hw_id); + if (ret < 0) + return ret; + + ret = nvmem_cell_read_variable_le_u32(dev, name, &sensor->offset); + if (ret) + return ret; + + /* Based on calib mode, program SHIFT, SLOPE and CZERO */ + switch (mode) { + case TWO_PT_CALIB: + slope = (TWO_PT_SHIFTED_GAIN / (base1 - base0)); + + czero = (base0 + sensor->offset - ((base1 - base0) / 3)); + + val = (V2_SHIFT_DEFAULT << CONVERSION_SHIFT_SHIFT) | + (slope << CONVERSION_SLOPE_SHIFT) | czero; + + fallthrough; + case ONE_PT_CALIB2: + czero = base0 + sensor->offset - ONE_PT_CZERO_CONST; + + val = (V2_SHIFT_DEFAULT << CONVERSION_SHIFT_SHIFT) | + (ONE_PT_SLOPE << CONVERSION_SLOPE_SHIFT) | czero; + + break; + default: + dev_dbg(dev, "calibrationless mode\n"); + + val = (V2_SHIFT_DEFAULT << CONVERSION_SHIFT_SHIFT) | + (V2_SLOPE_DEFAULT << CONVERSION_SLOPE_SHIFT) | V2_CZERO_DEFAULT; + } + + regmap_write(map, SENSOR_CONVERSION(sensor->hw_id), val); + + return 0; +} + +static int tsens_v2_calibration(struct tsens_priv *priv) +{ + struct device *dev = priv->dev; + u32 mode, base0, base1; + int i, ret; + + if (priv->num_sensors > MAX_SENSORS) + return -EINVAL; + + ret = nvmem_cell_read_variable_le_u32(priv->dev, "mode", &mode); + if (ret == -ENOENT) + dev_warn(priv->dev, "Calibration data not present in DT\n"); + if (ret < 0) + return ret; + + dev_dbg(priv->dev, "calibration mode is %d\n", mode); + + ret = nvmem_cell_read_variable_le_u32(priv->dev, "base0", &base0); + if (ret < 0) + return ret; + + ret = nvmem_cell_read_variable_le_u32(priv->dev, "base1", &base1); + if (ret < 0) + return ret; + + /* Calibrate each sensor */ + for (i = 0; i < priv->num_sensors; i++) { + ret = tsens_v2_calibrate_sensor(dev, &priv->sensor[i], priv->srot_map, + mode, base0, base1); + if (ret < 0) + return ret; + } + + return 0; +} + +static int __init init_tsens_v2(struct tsens_priv *priv) +{ + int i, ret; + u32 val = 0; + struct device *dev = priv->dev; + + ret = init_common(priv); + if (ret < 0) + return ret; + + if (priv->feat->ver_major != VER_2_X_NO_RPM) + return 0; + + priv->rf[CODE_OR_TEMP] = devm_regmap_field_alloc(dev, priv->srot_map, + priv->fields[CODE_OR_TEMP]); + if (IS_ERR(priv->rf[CODE_OR_TEMP])) + return PTR_ERR(priv->rf[CODE_OR_TEMP]); + + priv->rf[MAIN_MEASURE_PERIOD] = devm_regmap_field_alloc(dev, priv->srot_map, + priv->fields[MAIN_MEASURE_PERIOD]); + if (IS_ERR(priv->rf[MAIN_MEASURE_PERIOD])) + return PTR_ERR(priv->rf[MAIN_MEASURE_PERIOD]); + + regmap_field_write(priv->rf[TSENS_SW_RST], 0x1); + + /* Update measure period to 2ms */ + regmap_field_write(priv->rf[MAIN_MEASURE_PERIOD], 0x1); + + /* Enable available sensors */ + for (i = 0; i < priv->num_sensors; i++) + val |= 1 << priv->sensor[i].hw_id; + + regmap_field_write(priv->rf[SENSOR_EN], val); + + /* Real temperature format */ + regmap_field_write(priv->rf[CODE_OR_TEMP], 0x1); + + regmap_field_write(priv->rf[TSENS_SW_RST], 0x0); + + /* Enable TSENS */ + regmap_field_write(priv->rf[TSENS_EN], 0x1); + + return 0; +} + static const struct tsens_ops ops_generic_v2 = { .init = init_common, .get_temp = get_temp_tsens_valid, diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index 98c356acfe98..5d2ad3b155ec 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -974,7 +974,7 @@ int __init init_common(struct tsens_priv *priv) ret = regmap_field_read(priv->rf[TSENS_EN], &enabled); if (ret) goto err_put_device; - if (!enabled) { + if (!enabled && !VER_2_X_NO_RPM) { dev_err(dev, "%s: device not enabled\n", __func__); ret = -ENODEV; goto err_put_device; diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index 2805de1c6827..b2e8f0f2b466 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -35,6 +35,7 @@ enum tsens_ver { VER_0_1, VER_1_X, VER_2_X, + VER_2_X_NO_RPM, }; enum tsens_irq_type { @@ -168,6 +169,8 @@ enum regfield_ids { TSENS_SW_RST, SENSOR_EN, CODE_OR_TEMP, + /* MEASURE_PERIOD */ + MAIN_MEASURE_PERIOD, /* ----- TM ------ */ /* TRDY */ From patchwork Wed Jul 12 11:35:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Praveenkumar I X-Patchwork-Id: 702462 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 36A8FEB64DA for ; Wed, 12 Jul 2023 11:36:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231221AbjGLLgk (ORCPT ); Wed, 12 Jul 2023 07:36:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55412 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229506AbjGLLgj (ORCPT ); Wed, 12 Jul 2023 07:36:39 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9641B8F; Wed, 12 Jul 2023 04:36:38 -0700 (PDT) Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 36CB1Av5027631; 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Wed, 12 Jul 2023 11:36:32 GMT Received: from hu-ipkumar-blr.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Wed, 12 Jul 2023 04:36:06 -0700 From: Praveenkumar I To: , , , , , , , , , , , , , , CC: Subject: [PATCH v2 2/5] dt-bindings: thermal: tsens: Add ipq5332 compatible Date: Wed, 12 Jul 2023 17:05:36 +0530 Message-ID: <20230712113539.4029941-3-quic_ipkumar@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230712113539.4029941-1-quic_ipkumar@quicinc.com> References: <20230712113539.4029941-1-quic_ipkumar@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: CwXYnLK828oQWJFms9AE1j6L2Iug0r1V X-Proofpoint-GUID: CwXYnLK828oQWJFms9AE1j6L2Iug0r1V X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-12_06,2023-07-11_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxscore=0 bulkscore=0 lowpriorityscore=0 clxscore=1015 phishscore=0 malwarescore=0 mlxlogscore=999 impostorscore=0 spamscore=0 suspectscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2307120103 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org IPQ5332 uses TSENS v2.3.3 with combined interrupt. RPM is not available in the SoC, hence adding new compatible to have the sensor enablement and calibration function. This patch also adds nvmem-cell-names for ipq5332 Signed-off-by: Praveenkumar I --- [v2]: Followed the order for ipq5332 and added nvmem-cell-names. .../devicetree/bindings/thermal/qcom-tsens.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml index 27e9e16e6455..cca115906762 100644 --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml +++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml @@ -69,6 +69,7 @@ properties: - description: v2 of TSENS with combined interrupt enum: + - qcom,ipq5332-tsens - qcom,ipq8074-tsens - description: v2 of TSENS with combined interrupt @@ -205,6 +206,15 @@ properties: - const: s9_p2_backup - const: s10_p1_backup - const: s10_p2_backup + - items: + - const: mode + - const: base0 + - const: base1 + - pattern: '^s[0-9]+$' + - pattern: '^s[0-9]+$' + - pattern: '^s[0-9]+$' + - pattern: '^s[0-9]+$' + - pattern: '^s[0-9]+$' "#qcom,sensors": description: @@ -266,6 +276,7 @@ allOf: compatible: contains: enum: + - qcom,ipq5332-tsens - qcom,ipq8074-tsens then: properties: @@ -281,6 +292,7 @@ allOf: compatible: contains: enum: + - qcom,ipq5332-tsens - qcom,ipq8074-tsens - qcom,tsens-v0_1 - qcom,tsens-v1 From patchwork Wed Jul 12 11:35:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Praveenkumar I X-Patchwork-Id: 702461 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1F2C9C04FE0 for ; Wed, 12 Jul 2023 11:36:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232271AbjGLLgn (ORCPT ); Wed, 12 Jul 2023 07:36:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55436 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232139AbjGLLgl (ORCPT ); Wed, 12 Jul 2023 07:36:41 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E77D08F; Wed, 12 Jul 2023 04:36:40 -0700 (PDT) Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 36C9MJXc018622; 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Wed, 12 Jul 2023 11:36:32 GMT Received: from hu-ipkumar-blr.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Wed, 12 Jul 2023 04:36:12 -0700 From: Praveenkumar I To: , , , , , , , , , , , , , , CC: Subject: [PATCH v2 3/5] arm64: dts: qcom: ipq5332: Add tsens node Date: Wed, 12 Jul 2023 17:05:37 +0530 Message-ID: <20230712113539.4029941-4-quic_ipkumar@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230712113539.4029941-1-quic_ipkumar@quicinc.com> References: <20230712113539.4029941-1-quic_ipkumar@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: mRJ593EmXTnqxdu5xLYW48zdpZxQvTk0 X-Proofpoint-ORIG-GUID: mRJ593EmXTnqxdu5xLYW48zdpZxQvTk0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-12_06,2023-07-11_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 malwarescore=0 adultscore=0 impostorscore=0 mlxscore=0 suspectscore=0 phishscore=0 bulkscore=0 lowpriorityscore=0 mlxlogscore=720 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2307120103 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org IPQ5332 has tsens v2.3.3 peripheral. This patch adds the tsense node with nvmem cells for calibration data. Signed-off-by: Praveenkumar I --- [v2]: Included qfprom nodes only for available sensors and removed the offset suffix. arch/arm64/boot/dts/qcom/ipq5332.dtsi | 66 +++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi index 8bfc2db44624..0eef77e36609 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -150,6 +150,46 @@ qfprom: efuse@a4000 { reg = <0x000a4000 0x721>; #address-cells = <1>; #size-cells = <1>; + + tsens_mode: mode@3e1 { + reg = <0x3e1 0x1>; + bits = <0 3>; + }; + + tsens_base0: base0@3e1 { + reg = <0x3e1 0x2>; + bits = <3 10>; + }; + + tsens_base1: base1@3e2 { + reg = <0x3e2 0x2>; + bits = <5 10>; + }; + + s11: s11@3a5 { + reg = <0x3a5 0x1>; + bits = <4 4>; + }; + + s12: s12@3a6 { + reg = <0x3a6 0x1>; + bits = <0 4>; + }; + + s13: s13@3a6 { + reg = <0x3a6 0x1>; + bits = <4 4>; + }; + + s14: s14@3ad { + reg = <0x3ad 0x2>; + bits = <7 4>; + }; + + s15: s15@3ae { + reg = <0x3ae 0x1>; + bits = <3 4>; + }; }; rng: rng@e3000 { @@ -159,6 +199,32 @@ rng: rng@e3000 { clock-names = "core"; }; + tsens: thermal-sensor@4a9000 { + compatible = "qcom,ipq5332-tsens"; + reg = <0x4a9000 0x1000>, + <0x4a8000 0x1000>; + nvmem-cells = <&tsens_mode>, + <&tsens_base0>, + <&tsens_base1>, + <&s11>, + <&s12>, + <&s13>, + <&s14>, + <&s15>; + nvmem-cell-names = "mode", + "base0", + "base1", + "s11", + "s12", + "s13", + "s14", + "s15"; + interrupts = ; + interrupt-names = "combined"; + #qcom,sensors = <5>; + #thermal-sensor-cells = <1>; + }; + tlmm: pinctrl@1000000 { compatible = "qcom,ipq5332-tlmm"; reg = <0x01000000 0x300000>; From patchwork Wed Jul 12 11:35:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Praveenkumar I X-Patchwork-Id: 702014 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D49E8C001DD for ; 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Wed, 12 Jul 2023 04:36:17 -0700 From: Praveenkumar I To: , , , , , , , , , , , , , , CC: Subject: [PATCH v2 4/5] arm64: dts: qcom: ipq5332: Add thermal zone nodes Date: Wed, 12 Jul 2023 17:05:38 +0530 Message-ID: <20230712113539.4029941-5-quic_ipkumar@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230712113539.4029941-1-quic_ipkumar@quicinc.com> References: <20230712113539.4029941-1-quic_ipkumar@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: ZG_wMW4E8I61g8WeP7Plon5EkzW6fXoi X-Proofpoint-ORIG-GUID: ZG_wMW4E8I61g8WeP7Plon5EkzW6fXoi X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-12_06,2023-07-11_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 lowpriorityscore=0 bulkscore=0 suspectscore=0 phishscore=0 mlxlogscore=999 clxscore=1015 impostorscore=0 adultscore=0 malwarescore=0 priorityscore=1501 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2307120103 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch adds thermal zone nodes for sensors present in IPQ5332. Signed-off-by: Praveenkumar I --- [v2]: Added passive trips and alignment change. arch/arm64/boot/dts/qcom/ipq5332.dtsi | 78 +++++++++++++++++++++++++++ 1 file changed, 78 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi index 0eef77e36609..a1f59af97ee8 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -480,4 +480,82 @@ timer { , ; }; + + thermal-zones { + rfa-0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 11>; + + trips { + rfa-0-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + rfa-1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 12>; + + trips { + rfa-1-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + misc-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 13>; + + trips { + misc-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-top-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 14>; + + trips { + cpu-top-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + + cpu-passive { + temperature = <105000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + top-glue-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens 15>; + + trips { + top-glue-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + }; }; From patchwork Wed Jul 12 11:35:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Praveenkumar I X-Patchwork-Id: 702013 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 47407C00528 for ; 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Wed, 12 Jul 2023 04:36:22 -0700 From: Praveenkumar I To: , , , , , , , , , , , , , , CC: Subject: [PATCH v2 5/5] thermal/drivers/tsens: Add IPQ5332 support Date: Wed, 12 Jul 2023 17:05:39 +0530 Message-ID: <20230712113539.4029941-6-quic_ipkumar@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230712113539.4029941-1-quic_ipkumar@quicinc.com> References: <20230712113539.4029941-1-quic_ipkumar@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: ij9PXJv6ST4wFbXB8EKmzd7WgDOwiwgz X-Proofpoint-ORIG-GUID: ij9PXJv6ST4wFbXB8EKmzd7WgDOwiwgz X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-12_06,2023-07-11_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 spamscore=0 suspectscore=0 lowpriorityscore=0 clxscore=1015 phishscore=0 mlxlogscore=999 mlxscore=0 impostorscore=0 priorityscore=1501 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2307120103 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org IPQ5332 uses tsens v2.3.3 IP and it is having combined interrupt. It does not have RPM and kernel needs to take care of sensor enablement, calibration. Hence introduced new feature_config, ops and data for IPQ5332. Signed-off-by: Praveenkumar I --- [v2]: Added tsens_features for ipq5332 with VER_2_X_NO_RPM. Used hw_ids to mention the available sensors. Dropped v2 in ops_ipq5332. drivers/thermal/qcom/tsens-v2.c | 25 +++++++++++++++++++++++++ drivers/thermal/qcom/tsens.c | 3 +++ drivers/thermal/qcom/tsens.h | 2 +- 3 files changed, 29 insertions(+), 1 deletion(-) diff --git a/drivers/thermal/qcom/tsens-v2.c b/drivers/thermal/qcom/tsens-v2.c index ba74d971fe95..f95dce04fb17 100644 --- a/drivers/thermal/qcom/tsens-v2.c +++ b/drivers/thermal/qcom/tsens-v2.c @@ -62,6 +62,17 @@ static struct tsens_features ipq8074_feat = { .trip_max_temp = 204000, }; +static struct tsens_features ipq5332_feat = { + .ver_major = VER_2_X_NO_RPM, + .crit_int = 1, + .combo_int = 1, + .adc = 0, + .srot_split = 1, + .max_sensors = 16, + .trip_min_temp = 0, + .trip_max_temp = 204000, +}; + static const struct reg_field tsens_v2_regfields[MAX_REGFIELDS] = { /* ----- SROT ------ */ /* VERSION */ @@ -265,6 +276,20 @@ struct tsens_plat_data data_ipq8074 = { .fields = tsens_v2_regfields, }; +static const struct tsens_ops ops_ipq5332 = { + .init = init_tsens_v2, + .get_temp = get_temp_tsens_valid, + .calibrate = tsens_v2_calibration, +}; + +struct tsens_plat_data data_ipq5332 = { + .num_sensors = 5, + .ops = &ops_ipq5332, + .hw_ids = (unsigned int []){11, 12, 13, 14, 15}, + .feat = &ipq5332_feat, + .fields = tsens_v2_regfields, +}; + /* Kept around for backward compatibility with old msm8996.dtsi */ struct tsens_plat_data data_8996 = { .num_sensors = 13, diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index 5d2ad3b155ec..7d3b29bf14d4 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -1106,6 +1106,9 @@ static const struct of_device_id tsens_table[] = { }, { .compatible = "qcom,ipq8074-tsens", .data = &data_ipq8074, + }, { + .compatible = "qcom,ipq5332-tsens", + .data = &data_ipq5332, }, { .compatible = "qcom,mdm9607-tsens", .data = &data_9607, diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index b2e8f0f2b466..1dde363914cd 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -648,6 +648,6 @@ extern struct tsens_plat_data data_8226, data_8909, data_8916, data_8939, data_8 extern struct tsens_plat_data data_tsens_v1, data_8976, data_8956; /* TSENS v2 targets */ -extern struct tsens_plat_data data_8996, data_ipq8074, data_tsens_v2; +extern struct tsens_plat_data data_8996, data_ipq8074, data_ipq5332, data_tsens_v2; #endif /* __QCOM_TSENS_H__ */