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[209.51.188.17]) by mx.google.com with ESMTPS id u20-20020a05622a199400b00403b398c7a4si4545711qtc.311.2023.07.14.08.49.43 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 14 Jul 2023 08:49:43 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tpB8rFst; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qKL0T-0007Bp-M9; Fri, 14 Jul 2023 11:46:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qKL0S-0007Ae-DC for qemu-devel@nongnu.org; Fri, 14 Jul 2023 11:46:56 -0400 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qKL0P-000751-I1 for qemu-devel@nongnu.org; Fri, 14 Jul 2023 11:46:56 -0400 Received: by mail-wm1-x32c.google.com with SMTP id 5b1f17b1804b1-3fbea14700bso19207085e9.3 for ; Fri, 14 Jul 2023 08:46:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1689349612; x=1691941612; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=CiH9E7mBgPKZNIpdmx/tPxEyFtaNkc5RvSs8kkQDWdc=; b=tpB8rFstuTaj78dYKDrQspXQtsizJgJ7WV8QOo2zvitmtF1J9ZH66aMCgaSA2AkKh2 dS6mEpwAN633lp2na70fjxlvG7zHv+ZmKDo5ByWGOvZOv2bjvaRJmJZHGEeY4rXY0eSw aW/Drf/wwutJP5GsWx+oM1Eh5HrJqL2Y4mbbaSGBeavhH2F90k4lIzVyIOQbxhlwZTKd F4Y/v4r6HIvlL1ETInKGNlW8P7jYj07omVAgRWkN7+OkHSFDAOVQdNn67Cq68TRTYeox RrPihxoH929hsils3WgrhsaeKNZ8K1jKQJTKy0KLl9zmwZFvIQ2U54WN8nSeNSrMfD7q 6u0Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689349612; x=1691941612; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CiH9E7mBgPKZNIpdmx/tPxEyFtaNkc5RvSs8kkQDWdc=; b=AHoydbjyA6kmt7OAVpxq8+3zaW2/rF9T4z+v4qaHlzZxS6zDAqjYsiWM3R19Rx+iap S82kJ0M682EmOD9pczJXsN8fR0rg3PpRc8AlOyS+WzxUh2AvEaoxOKCNXWXDHa3svd6e 30AIcrxYSvAdaW0n2Gj4yDLgzU7WR5v9A9Zb6gTIQOYsXOPBqBDR4HjeJ/PwpMOncnVY 4wlJk+X99DJhrR77jpS39x09B2Gs4LeEPvpC9/Jmf9O05DkrktG6n5Y/JOmdpkG6ltmE T9oQpwabsTWGCUexUtLIA/4qmT3PCOWF0YB8kjYBOhoCxC9t9XYdzsjb9aTPKh6KEzfM Y3zA== X-Gm-Message-State: ABy/qLaE5Es6y/OkSbPonaLqg/xXFGSGAwybF6wSdkvPV3NGJ2uiN6WJ aYyQCCHAmNO1aO5mk08BegiocA== X-Received: by 2002:adf:de12:0:b0:314:30ed:9b55 with SMTP id b18-20020adfde12000000b0031430ed9b55mr4580983wrm.15.1689349611418; Fri, 14 Jul 2023 08:46:51 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id t16-20020a5d49d0000000b003143bb5ecd5sm11214025wrs.69.2023.07.14.08.46.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Jul 2023 08:46:51 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 01/14] target/arm/ptw: Don't set fi->s1ptw for UnsuppAtomicUpdate fault Date: Fri, 14 Jul 2023 16:46:35 +0100 Message-Id: <20230714154648.327466-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230714154648.327466-1-peter.maydell@linaro.org> References: <20230714154648.327466-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org For an Unsupported Atomic Update fault where the stage 1 translation table descriptor update can't be done because it's to an unsupported memory type, this is a stage 1 abort (per the Arm ARM R_VSXXT). This means we should not set fi->s1ptw, because this will cause the code in the get_phys_addr_lpae() error-exit path to mark it as stage 2. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/ptw.c | 1 - 1 file changed, 1 deletion(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 8f94100c61f..bafeb876ad7 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -701,7 +701,6 @@ static uint64_t arm_casq_ptw(CPUARMState *env, uint64_t old_val, if (unlikely(!host)) { fi->type = ARMFault_UnsuppAtomicUpdate; - fi->s1ptw = true; return 0; } From patchwork Fri Jul 14 15:46:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 702739 Delivered-To: patch@linaro.org Received: by 2002:adf:db4e:0:b0:314:25da:8dc4 with SMTP id f14csp1162247wrj; Fri, 14 Jul 2023 08:50:10 -0700 (PDT) X-Google-Smtp-Source: APBJJlG0G8W/YWxoJt3ibTJMB35fHdEUNI93qkMHCDMTRtMDK5pjozcFmVC+xa6rvLPpNJHtO0MM X-Received: by 2002:a05:620a:2591:b0:767:1c73:6a06 with SMTP id x17-20020a05620a259100b007671c736a06mr6256000qko.0.1689349809828; Fri, 14 Jul 2023 08:50:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689349809; cv=none; d=google.com; s=arc-20160816; b=E6ruq2GZxLoqBO+fnHBU1g08Aq+gT3kMY7LBt4GOpUqvvtTaFBb3/kGJukYd5gYobq a1bJm3190Q9mfOWI2Njb2hqKpfkGXLya6AFfXCdppVEK9nDXS/FgAJE4dqmekF71N1qD VUpnBPMtByQ3PHYLhOqYLUEOGCbea7N7O2iuMIz3TTh+FQMD8v8Ot8e5QZ0eeWN9gYX6 uw04NQXHi4jmVoF0UZIjM/MzGCefAnydfm5P46HnVb3kzBW86Qm4aKdX1TC6LTcmoYO+ UUnAzPGJiusRJ0vUaW5njCsEiB8h2D3wreqOBGPUpOi8bBa3dmVdzSXBtSUK63TpusgX I3jg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=eumrElobNKY7spGfBeTnnGIQlpKlfLkNgQIpTApqm4A=; fh=jvpdohKmRoZMO537s6xMKXXtj7EZws1LOMQI/oP4vXs=; b=L4/vxjAi7nsfsOA/MZ0hUVQVLMwGsaEfmFIZrVoe9CiJVy2+9VjeqVDzjGWR9mNDbL 4qa4ogyI7mhGL1gxnjxJegZwMeSLxUUc5Ai/LL5LXz/bmzUswp+MGvCYrefN/IkzwEVk TrKRvJqiEf/4Bd+3LVR4WMz+3XAl+t3PofozlimR3lhUXslhsok4hBTXGnmLfwD88V1x umqcv8UqtjZEHi+VUBABkJwzg6bra6wzlzL/pdlOZx6RIxqYjixxV1HxroHR2fpKfFqs oCFV9Z2jn2pvQAp/Jt6ss5TdwJzp/lnfiNOO+01d2sys3uGpsFKz9OsaGoyRHvP0F4/7 WRsQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cOMxZxTZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id t16-20020a5d49d0000000b003143bb5ecd5sm11214025wrs.69.2023.07.14.08.46.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Jul 2023 08:46:51 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 02/14] target/arm/ptw: Don't report GPC faults on stage 1 ptw as stage2 faults Date: Fri, 14 Jul 2023 16:46:36 +0100 Message-Id: <20230714154648.327466-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230714154648.327466-1-peter.maydell@linaro.org> References: <20230714154648.327466-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In S1_ptw_translate() we set up the ARMMMUFaultInfo if the attempt to translate the page descriptor address into a physical address fails. This used to only be possible if we are doing a stage 2 ptw for that descriptor address, and so the code always sets fi->stage2 and fi->s1ptw to true. However, with FEAT_RME it is also possible for the lookup of the page descriptor address to fail because of a Granule Protection Check fault. These should not be reported as stage 2, otherwise arm_deliver_fault() will incorrectly set HPFAR_EL2. Similarly the s1ptw bit should only be set for stage 2 faults on stage 1 translation table walks, i.e. not for GPC faults. Add a comment to the the other place where we might detect a stage2-fault-on-stage-1-ptw, in arm_casq_ptw(), noting why we know in that case that it must really be a stage 2 fault and not a GPC fault. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/ptw.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index bafeb876ad7..eb57ebd897b 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -600,8 +600,8 @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, fi->type = ARMFault_GPCFOnWalk; } fi->s2addr = addr; - fi->stage2 = true; - fi->s1ptw = true; + fi->stage2 = regime_is_stage2(s2_mmu_idx); + fi->s1ptw = fi->stage2; fi->s1ns = !is_secure; return false; } @@ -719,6 +719,12 @@ static uint64_t arm_casq_ptw(CPUARMState *env, uint64_t old_val, env->tlb_fi = NULL; if (unlikely(flags & TLB_INVALID_MASK)) { + /* + * We know this must be a stage 2 fault because the granule + * protection table does not separately track read and write + * permission, so all GPC faults are caught in S1_ptw_translate(): + * we only get here for "readable but not writeable". + */ assert(fi->type != ARMFault_None); fi->s2addr = ptw->out_virt; fi->stage2 = true; From patchwork Fri Jul 14 15:46:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 702734 Delivered-To: patch@linaro.org Received: by 2002:adf:db4e:0:b0:314:25da:8dc4 with SMTP id f14csp1161487wrj; Fri, 14 Jul 2023 08:48:29 -0700 (PDT) X-Google-Smtp-Source: APBJJlEaHDB01AZcBEjFJh9iwcvKXv9GrAe7kZ8J2KYF/xRcJVhrQa2s0zXBkiliFGVpY2zHb3Rm X-Received: by 2002:a05:622a:1a82:b0:403:b3a2:820f with SMTP id s2-20020a05622a1a8200b00403b3a2820fmr3510113qtc.31.1689349708912; Fri, 14 Jul 2023 08:48:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689349708; cv=none; d=google.com; s=arc-20160816; b=Iozr/nAsu52GdRaqeXKafiViOpcZ61WYX3NUGm7yNo1gUmoJmo95SGdEQ+DtlF+vSb 2wX77L/DW10WoNFuBM39X4Kf1jQ2jcansBFjXU0yrSIdiXvDy1QmqOwIAhWeSomCJYe4 I5F/rqFnzzEjyeFGJ4iO/igTzzzRl65mJcLxU5fRyLLfFvZUuBrsHB0tCUvQBJa2IPqf fxtBh7Y3l4OVhvsD0cm0ePBp5968DLX8Ur2Md3QrOxEHcReIYfOxrmaJZzyVU1zkOA7u sHRU50OsJTp7DxpQyRfXJEABv5wIRML6MHEykfxF7LhFkJsDXC+bdE6YzuaZgTA3vU2o m4JA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=wjXax+BQ/9wUzLTNVvfXm39pxSfddxOCMcJwUt+OkWM=; fh=jvpdohKmRoZMO537s6xMKXXtj7EZws1LOMQI/oP4vXs=; b=TM09Ntex0MXEmdem0Um7shX7kr3hUoNkL84u8GuaYWlXpBX3fbRuaxAg/KBJP4FLy1 7CF1iWs+KNiObwAp9oggU0y+dUZZEL1PmpIm1COKRlGKGj8oBnaqXYrF0VVfbZLeETn0 tgAx1K8/aBmMBZ1nASfqPTYEXbZ/gnuEyKL/31lgW8rmhLA3Lq2UVxOvrD7NvD9EmYCy wTcn/6vsx/lE1o6USrUwY5oG15r4iIZzqLxOVbzLAPMXEqlQLR8PlzKe+qz7D5hrBTjg Hn0O0010wyHF5XN/NNRraEWh5eHRYU9jJJU72mzlG8gGxTxpXFeHRv/PGbyHkNM7P3LK +bEA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CoNTr4QX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id t16-20020a5d49d0000000b003143bb5ecd5sm11214025wrs.69.2023.07.14.08.46.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Jul 2023 08:46:52 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 03/14] target/arm/ptw: Set s1ns bit in fault info more consistently Date: Fri, 14 Jul 2023 16:46:37 +0100 Message-Id: <20230714154648.327466-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230714154648.327466-1-peter.maydell@linaro.org> References: <20230714154648.327466-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The s1ns bit in ARMMMUFaultInfo is documented as "true if we faulted on a non-secure IPA while in secure state". Both the places which look at this bit only do so after having confirmed that this is a stage 2 fault and we're dealing with Secure EL2, which leaves the ptw.c code free to set the bit to any random value in the other cases. Instead of taking advantage of that freedom, consistently make the bit be set to false for the "not a stage 2 fault for Secure EL2" cases. This removes some cases where we were using an 'is_secure' boolean and leaving the reader guessing about whether that was the right thing for Realm and Root cases. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/ptw.c | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index eb57ebd897b..67078ae3509 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -514,6 +514,17 @@ static ARMSecuritySpace S2_security_space(ARMSecuritySpace s1_space, } } +static bool fault_s1ns(ARMSecuritySpace space, ARMMMUIdx s2_mmu_idx) +{ + /* + * For stage 2 faults in Secure EL22, S1NS indicates + * whether the faulting IPA is in the Secure or NonSecure + * IPA space. For all other kinds of fault, it is false. + */ + return space == ARMSS_Secure && regime_is_stage2(s2_mmu_idx) + && s2_mmu_idx == ARMMMUIdx_Stage2_S; +} + /* Translate a S1 pagetable walk through S2 if needed. */ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, hwaddr addr, ARMMMUFaultInfo *fi) @@ -586,7 +597,7 @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, fi->s2addr = addr; fi->stage2 = true; fi->s1ptw = true; - fi->s1ns = !is_secure; + fi->s1ns = fault_s1ns(ptw->in_space, s2_mmu_idx); return false; } } @@ -602,7 +613,7 @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, fi->s2addr = addr; fi->stage2 = regime_is_stage2(s2_mmu_idx); fi->s1ptw = fi->stage2; - fi->s1ns = !is_secure; + fi->s1ns = fault_s1ns(ptw->in_space, s2_mmu_idx); return false; } @@ -729,7 +740,7 @@ static uint64_t arm_casq_ptw(CPUARMState *env, uint64_t old_val, fi->s2addr = ptw->out_virt; fi->stage2 = true; fi->s1ptw = true; - fi->s1ns = !ptw->in_secure; + fi->s1ns = fault_s1ns(ptw->in_space, ptw->in_ptw_idx); return 0; } @@ -2030,7 +2041,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, fi->level = level; /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */ fi->stage2 = fi->s1ptw || regime_is_stage2(mmu_idx); - fi->s1ns = mmu_idx == ARMMMUIdx_Stage2; + fi->s1ns = fault_s1ns(ptw->in_space, mmu_idx); return true; } From patchwork Fri Jul 14 15:46:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 702729 Delivered-To: patch@linaro.org Received: by 2002:adf:db4e:0:b0:314:25da:8dc4 with SMTP id f14csp1161259wrj; Fri, 14 Jul 2023 08:48:01 -0700 (PDT) X-Google-Smtp-Source: APBJJlEhDSd2vTKa/gGzKUuOowfMyyeFg0r6VtN9ajJHLvkp9G4YGt+t1qDiNqZ6DbdDndlwLE4E X-Received: by 2002:a05:620a:44c9:b0:767:fe52:d13c with SMTP id y9-20020a05620a44c900b00767fe52d13cmr4852666qkp.22.1689349681118; Fri, 14 Jul 2023 08:48:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689349681; cv=none; d=google.com; s=arc-20160816; b=zH+xAR/vSInjx+vjTDcpQV+LD9eZRH+AwL9DhtmXKjVTI8rMPtGXTZ8HU7Rh4ABq0L UymsneG2mS7fCNpbeSGn9yXaSMBgAj9EoE6exEe7fJsWSZX8p/S52ot8mgsqKZwa+fTF kouckVw0pQbBFXJ86EOeEdtyT69HU3n33yf0VYyeS7qhPULLGYYtEkKzou4LrvoPMsX+ wV4a8RMoLBkNqmBmj1JGbgKyWt1A7t0mpm0F4cgZvHtbQPvq8SmHfEQ3W3UgqXT8cjcu KAaWSH9ALENHTbcAdA+9g/I4IBUQMe67jbpHaa1mYSvG8ZWdbQJwxoGYbn7z8loHFLP1 YAvQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=F6lmvGSCSTya37L8EMZF/NmWegbCLw9mDbZjRhmFpRA=; fh=jvpdohKmRoZMO537s6xMKXXtj7EZws1LOMQI/oP4vXs=; b=LMXelwJaHV4aH5l6fpQLfWY1tsO/09jrrbbMsFXQOLxH5YEZzm2YojJLVNM1GHhLU2 OW+Z3HxzK+p8p7OgGDapjdRQcx/P5IWP9sln43C/x/OEASkBuCE0vZryibeb897XqnVl SJA42jQjSMsmFZ2sQtpCVimcisGXa6cpzF0uHKTf2XfPiXyWupL3pG0hsaC0smjCBGT0 OsUON9zZbBXO8m1i/j8tNv8nPAeaxhycq0TS3uGEi74AEPVJa2ibnVv40NrvFiLAZKEG nKPlgtlD0sXhPo+ftsxGtoaVpL3VT4NlxwuJkSzVWrloZ0KyeVuzZJXEXlS95OZrCc60 00+g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="G/V++jxF"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id t16-20020a5d49d0000000b003143bb5ecd5sm11214025wrs.69.2023.07.14.08.46.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Jul 2023 08:46:52 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 04/14] target/arm/ptw: Pass ptw into get_phys_addr_pmsa*() and get_phys_addr_disabled() Date: Fri, 14 Jul 2023 16:46:38 +0100 Message-Id: <20230714154648.327466-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230714154648.327466-1-peter.maydell@linaro.org> References: <20230714154648.327466-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In commit 6d2654ffacea813916176 we created the S1Translate struct and used it to plumb through various arguments that we were previously passing one-at-a-time to get_phys_addr_v5(), get_phys_addr_v6(), and get_phys_addr_lpae(). Extend that pattern to get_phys_addr_pmsav5(), get_phys_addr_pmsav7(), get_phys_addr_pmsav8() and get_phys_addr_disabled(), so that all the get_phys_addr_* functions we call from get_phys_addr_nogpc() take the S1Translate struct rather than the mmu_idx and is_secure bool. (This refactoring is a prelude to having the called functions look at ptw->is_space rather than using an is_secure boolean.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/ptw.c | 57 ++++++++++++++++++++++++++++++------------------ 1 file changed, 36 insertions(+), 21 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 67078ae3509..a873fbe0239 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2045,15 +2045,19 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, return true; } -static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, - bool is_secure, GetPhysAddrResult *result, +static bool get_phys_addr_pmsav5(CPUARMState *env, + S1Translate *ptw, + uint32_t address, + MMUAccessType access_type, + GetPhysAddrResult *result, ARMMMUFaultInfo *fi) { int n; uint32_t mask; uint32_t base; + ARMMMUIdx mmu_idx = ptw->in_mmu_idx; bool is_user = regime_is_user(env, mmu_idx); + bool is_secure = arm_space_is_secure(ptw->in_space); if (regime_translation_disabled(env, mmu_idx, is_secure)) { /* MPU disabled. */ @@ -2210,14 +2214,18 @@ static bool pmsav7_use_background_region(ARMCPU *cpu, ARMMMUIdx mmu_idx, return regime_sctlr(env, mmu_idx) & SCTLR_BR; } -static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, - bool secure, GetPhysAddrResult *result, +static bool get_phys_addr_pmsav7(CPUARMState *env, + S1Translate *ptw, + uint32_t address, + MMUAccessType access_type, + GetPhysAddrResult *result, ARMMMUFaultInfo *fi) { ARMCPU *cpu = env_archcpu(env); int n; + ARMMMUIdx mmu_idx = ptw->in_mmu_idx; bool is_user = regime_is_user(env, mmu_idx); + bool secure = arm_space_is_secure(ptw->in_space); result->f.phys_addr = address; result->f.lg_page_size = TARGET_PAGE_BITS; @@ -2736,12 +2744,16 @@ void v8m_security_lookup(CPUARMState *env, uint32_t address, } } -static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, - bool secure, GetPhysAddrResult *result, +static bool get_phys_addr_pmsav8(CPUARMState *env, + S1Translate *ptw, + uint32_t address, + MMUAccessType access_type, + GetPhysAddrResult *result, ARMMMUFaultInfo *fi) { V8M_SAttributes sattrs = {}; + ARMMMUIdx mmu_idx = ptw->in_mmu_idx; + bool secure = arm_space_is_secure(ptw->in_space); bool ret; if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { @@ -3045,12 +3057,15 @@ static ARMCacheAttrs combine_cacheattrs(uint64_t hcr, * MMU disabled. S1 addresses within aa64 translation regimes are * still checked for bounds -- see AArch64.S1DisabledOutput(). */ -static bool get_phys_addr_disabled(CPUARMState *env, target_ulong address, +static bool get_phys_addr_disabled(CPUARMState *env, + S1Translate *ptw, + target_ulong address, MMUAccessType access_type, - ARMMMUIdx mmu_idx, bool is_secure, GetPhysAddrResult *result, ARMMMUFaultInfo *fi) { + ARMMMUIdx mmu_idx = ptw->in_mmu_idx; + bool is_secure = arm_space_is_secure(ptw->in_space); uint8_t memattr = 0x00; /* Device nGnRnE */ uint8_t shareability = 0; /* non-shareable */ int r_el; @@ -3252,8 +3267,8 @@ static bool get_phys_addr_nogpc(CPUARMState *env, S1Translate *ptw, case ARMMMUIdx_Phys_Root: case ARMMMUIdx_Phys_Realm: /* Checking Phys early avoids special casing later vs regime_el. */ - return get_phys_addr_disabled(env, address, access_type, mmu_idx, - is_secure, result, fi); + return get_phys_addr_disabled(env, ptw, address, access_type, + result, fi); case ARMMMUIdx_Stage1_E0: case ARMMMUIdx_Stage1_E1: @@ -3321,16 +3336,16 @@ static bool get_phys_addr_nogpc(CPUARMState *env, S1Translate *ptw, if (arm_feature(env, ARM_FEATURE_V8)) { /* PMSAv8 */ - ret = get_phys_addr_pmsav8(env, address, access_type, mmu_idx, - is_secure, result, fi); + ret = get_phys_addr_pmsav8(env, ptw, address, access_type, + result, fi); } else if (arm_feature(env, ARM_FEATURE_V7)) { /* PMSAv7 */ - ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx, - is_secure, result, fi); + ret = get_phys_addr_pmsav7(env, ptw, address, access_type, + result, fi); } else { /* Pre-v7 MPU */ - ret = get_phys_addr_pmsav5(env, address, access_type, mmu_idx, - is_secure, result, fi); + ret = get_phys_addr_pmsav5(env, ptw, address, access_type, + result, fi); } qemu_log_mask(CPU_LOG_MMU, "PMSA MPU lookup for %s at 0x%08" PRIx32 " mmu_idx %u -> %s (prot %c%c%c)\n", @@ -3348,8 +3363,8 @@ static bool get_phys_addr_nogpc(CPUARMState *env, S1Translate *ptw, /* Definitely a real MMU, not an MPU */ if (regime_translation_disabled(env, mmu_idx, is_secure)) { - return get_phys_addr_disabled(env, address, access_type, mmu_idx, - is_secure, result, fi); + return get_phys_addr_disabled(env, ptw, address, access_type, + result, fi); } if (regime_using_lpae_format(env, mmu_idx)) { From patchwork Fri Jul 14 15:46:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 702738 Delivered-To: patch@linaro.org Received: by 2002:adf:db4e:0:b0:314:25da:8dc4 with SMTP id f14csp1162111wrj; Fri, 14 Jul 2023 08:49:53 -0700 (PDT) X-Google-Smtp-Source: APBJJlGcG4MU37bgDeLyMIth1hwPgRSaYLwJ12Mwtaae7jOOmEqiaxtwvl1cq1StRwYysOOsGCxR X-Received: by 2002:a05:620a:199c:b0:75b:23a1:d847 with SMTP id bm28-20020a05620a199c00b0075b23a1d847mr3986776qkb.9.1689349793203; Fri, 14 Jul 2023 08:49:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689349793; cv=none; d=google.com; s=arc-20160816; b=R1HjucqxKntBX9ydqzBiGpI+KZ9zzrjEiFk+nXqNBiRhcINsJJmrXxIqmR7PtJy6Zn bvKLbeZ80WysB380jAQTSeFyRlK6i9eZBuazIYE14eWpXmx7lYTw7czT/yhUOcwL7vMI cfmI9/CsGaszUOHtLHC5CqVx+ipn+pXK3s2M2j+wwWHbohHS2udE9oqG5DDNQOUeJzOK jY+DFm/ui+U6QuA2b8+gCj5X3aBKF8HDJ++CqLzm1gOY2xPaelok6IW4uV2GcKAkpxnp cM4w+p96cRdtxVgQpleWEBbMQUDgmYTGEGoDbwkcMa2KM8UsyAEBv9WQQhpOsUlxWMhX Hwsw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=q234a2QZpJLMfs9OiY+sBy9QxJhtbu9OJpiuspwmwC0=; fh=jvpdohKmRoZMO537s6xMKXXtj7EZws1LOMQI/oP4vXs=; b=DXKj7vhtGO30cn4/PnG40ZN1b1Rs4rN/lJ6zFUu5TyyrAHRSafSfmt/5Fxb6Zi92/S NhxG+UVx2Py5i5yuergBFrspidfhCv11NobOf3cYKRFV9iY7+Wk0Vd47nHYKlZF8XWbn cCwHFiA6p79GbLStV0ER5zqiL39bhT7riQRhBBwrW9FFXAljpL5kvZUv0ecWB6dOH5uT kJBRZvDAQNqgYIMnVFPyG/XozqFo/En87IhskyfobT/Pzu5Z8DSagOG+QTXWXjX5xC41 IH8Y9FnJjuVgsEA4w/22XhSmgOGwYlAg/x8q+0aZJ6IgRmX9FujhLfehfHT5vI2F05LV t4BA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=d2aC1z2Z; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id t16-20020a5d49d0000000b003143bb5ecd5sm11214025wrs.69.2023.07.14.08.46.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Jul 2023 08:46:53 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 05/14] target/arm/ptw: Pass ARMSecurityState to regime_translation_disabled() Date: Fri, 14 Jul 2023 16:46:39 +0100 Message-Id: <20230714154648.327466-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230714154648.327466-1-peter.maydell@linaro.org> References: <20230714154648.327466-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Plumb the ARMSecurityState through to regime_translation_disabled() rather than just a bool is_secure. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/ptw.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index a873fbe0239..63dd8e3cbe1 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -206,9 +206,10 @@ static uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx, int ttbrn) /* Return true if the specified stage of address translation is disabled */ static bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx, - bool is_secure) + ARMSecuritySpace space) { uint64_t hcr_el2; + bool is_secure = arm_space_is_secure(space); if (arm_feature(env, ARM_FEATURE_M)) { switch (env->v7m.mpu_ctrl[is_secure] & @@ -2057,9 +2058,8 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t base; ARMMMUIdx mmu_idx = ptw->in_mmu_idx; bool is_user = regime_is_user(env, mmu_idx); - bool is_secure = arm_space_is_secure(ptw->in_space); - if (regime_translation_disabled(env, mmu_idx, is_secure)) { + if (regime_translation_disabled(env, mmu_idx, ptw->in_space)) { /* MPU disabled. */ result->f.phys_addr = address; result->f.prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; @@ -2231,7 +2231,7 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, result->f.lg_page_size = TARGET_PAGE_BITS; result->f.prot = 0; - if (regime_translation_disabled(env, mmu_idx, secure) || + if (regime_translation_disabled(env, mmu_idx, ptw->in_space) || m_is_ppb_region(env, address)) { /* * MPU disabled or M profile PPB access: use default memory map. @@ -2475,7 +2475,8 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, * are done in arm_v7m_load_vector(), which always does a direct * read using address_space_ldl(), rather than going via this function. */ - if (regime_translation_disabled(env, mmu_idx, secure)) { /* MPU disabled */ + if (regime_translation_disabled(env, mmu_idx, arm_secure_to_space(secure))) { + /* MPU disabled */ hit = true; } else if (m_is_ppb_region(env, address)) { hit = true; @@ -3303,7 +3304,7 @@ static bool get_phys_addr_nogpc(CPUARMState *env, S1Translate *ptw, */ ptw->in_mmu_idx = mmu_idx = s1_mmu_idx; if (arm_feature(env, ARM_FEATURE_EL2) && - !regime_translation_disabled(env, ARMMMUIdx_Stage2, is_secure)) { + !regime_translation_disabled(env, ARMMMUIdx_Stage2, ptw->in_space)) { return get_phys_addr_twostage(env, ptw, address, access_type, result, fi); } @@ -3362,7 +3363,7 @@ static bool get_phys_addr_nogpc(CPUARMState *env, S1Translate *ptw, /* Definitely a real MMU, not an MPU */ - if (regime_translation_disabled(env, mmu_idx, is_secure)) { + if (regime_translation_disabled(env, mmu_idx, ptw->in_space)) { return get_phys_addr_disabled(env, ptw, address, access_type, result, fi); } From patchwork Fri Jul 14 15:46:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 702728 Delivered-To: patch@linaro.org Received: by 2002:adf:db4e:0:b0:314:25da:8dc4 with SMTP id f14csp1161125wrj; Fri, 14 Jul 2023 08:47:44 -0700 (PDT) X-Google-Smtp-Source: APBJJlGCtr0wZ2ULsBJFVxxNGDgZtXHcmENn2llt4gsd/psEbwRdz8Iis1uL1XIeu01ocVu1rvRZ X-Received: by 2002:a0c:e591:0:b0:635:b4e7:1859 with SMTP id t17-20020a0ce591000000b00635b4e71859mr4425453qvm.49.1689349664053; Fri, 14 Jul 2023 08:47:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689349664; cv=none; d=google.com; s=arc-20160816; b=SqLt2MLdPlWM1HVCS1r6wWEyVhDr0zjjg9wSrIXWWZmLMn84nfOQu9Ch8u14Z4OyAL ExjxDDkCzt9IQUTOxvpa1VjQjY3Cnb6mWBhbHIYF0U1kP7dt8kgHk0py3TdQ+4xPiewx X6jTrciTnkii3tbe46Vcvi/iUB1C1PuMt4K+Aa8Fd2TSCCjB2W1ps0ZEkFJk7xVVxh5e 3QCselSnMMGWFPMCB9hB4dJjEbjW/uxSNEP3vc9KDa458VcFobOcdSGaOl7q1K4CTZG6 WDv9kcFBxdXHuSKGW3/O1BDeFGQ9mm5GlVLiYbD9wHZpiuJTtU+g5dFtlrgzKR5QkuR+ kM+Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=NaxZtJ/Zz22f09eQWd/e/ljK+9HRxTBlYQ6KBcsfIVM=; fh=jvpdohKmRoZMO537s6xMKXXtj7EZws1LOMQI/oP4vXs=; b=lGR2CHUYq88pgQuQkzQAfnIgh2/Zcf4GxTDsfdBzhwq27a9Q3xAESfpyUJAfwPfskN wNALICKFE7t6MAdaydX3SzIWcTAZNEMK0Azm51CFo4jcLaejm62qamgftkCjGXd0j2fm bAsncIaVw8hzpZsOzlg9g6+KmoECiro3uNWfhIN8I0fkt1e8dX4zrOtC8Iho2MHkIcLx l01ijhbZq0RFJtvqIzILYKpHxmbgvFQWFL8TIo7q97rysIXR5HjP11fKsaGeNCPErE9I CAdKxghwT0SqqS2A23Arhg9dGVWMCVm5FtyHAJX5IDjYkyRmtpiZEGQT6avH8bCKgGUt cmmA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=W+KiEeRb; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id t16-20020a5d49d0000000b003143bb5ecd5sm11214025wrs.69.2023.07.14.08.46.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Jul 2023 08:46:53 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 06/14] target/arm/ptw: Pass an ARMSecuritySpace to arm_hcr_el2_eff_secstate() Date: Fri, 14 Jul 2023 16:46:40 +0100 Message-Id: <20230714154648.327466-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230714154648.327466-1-peter.maydell@linaro.org> References: <20230714154648.327466-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org arm_hcr_el2_eff_secstate() takes a bool secure, which it uses to determine whether EL2 is enabled in the current security state. With the advent of FEAT_RME this is no longer sufficient, because EL2 can be enabled for Secure state but not for Root, and both of those will pass 'secure == true' in the callsites in ptw.c. As it happens in all of our callsites in ptw.c we either avoid making the call or else avoid using the returned value if we're doing a translation for Root, so this is not a behaviour change even if the experimental FEAT_RME is enabled. But it is less confusing in the ptw.c code if we avoid the use of a bool secure that duplicates some of the information in the ArmSecuritySpace argument. Make arm_hcr_el2_eff_secstate() take an ARMSecuritySpace argument instead. Note that since arm_hcr_el2_eff() uses the return value from arm_security_space_below_el3() for the 'space' argument, its behaviour does not change even when at EL3 (Root security state) and it continues to tell you what EL2 would be if you were in it. Signed-off-by: Peter Maydell --- target/arm/cpu.h | 2 +- target/arm/helper.c | 7 ++++--- target/arm/ptw.c | 13 +++++-------- 3 files changed, 10 insertions(+), 12 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 4d6c0f95d59..3743a9e2f8a 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2555,7 +2555,7 @@ static inline bool arm_is_el2_enabled(CPUARMState *env) * "for all purposes other than a direct read or write access of HCR_EL2." * Not included here is HCR_RW. */ -uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, bool secure); +uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, ARMSecuritySpace space); uint64_t arm_hcr_el2_eff(CPUARMState *env); uint64_t arm_hcrx_el2_eff(CPUARMState *env); diff --git a/target/arm/helper.c b/target/arm/helper.c index d08c058e424..1e45fdb47c9 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5731,11 +5731,12 @@ static void hcr_writelow(CPUARMState *env, const ARMCPRegInfo *ri, * Bits that are not included here: * RW (read from SCR_EL3.RW as needed) */ -uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, bool secure) +uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, ARMSecuritySpace space) { uint64_t ret = env->cp15.hcr_el2; - if (!arm_is_el2_enabled_secstate(env, secure)) { + if (space == ARMSS_Root || + !arm_is_el2_enabled_secstate(env, arm_space_is_secure(space))) { /* * "This register has no effect if EL2 is not enabled in the * current Security state". This is ARMv8.4-SecEL2 speak for @@ -5799,7 +5800,7 @@ uint64_t arm_hcr_el2_eff(CPUARMState *env) if (arm_feature(env, ARM_FEATURE_M)) { return 0; } - return arm_hcr_el2_eff_secstate(env, arm_is_secure_below_el3(env)); + return arm_hcr_el2_eff_secstate(env, arm_security_space_below_el3(env)); } /* diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 63dd8e3cbe1..9e45160e1ba 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -209,9 +209,9 @@ static bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx, ARMSecuritySpace space) { uint64_t hcr_el2; - bool is_secure = arm_space_is_secure(space); if (arm_feature(env, ARM_FEATURE_M)) { + bool is_secure = arm_space_is_secure(space); switch (env->v7m.mpu_ctrl[is_secure] & (R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK)) { case R_V7M_MPU_CTRL_ENABLE_MASK: @@ -230,7 +230,7 @@ static bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx, } } - hcr_el2 = arm_hcr_el2_eff_secstate(env, is_secure); + hcr_el2 = arm_hcr_el2_eff_secstate(env, space); switch (mmu_idx) { case ARMMMUIdx_Stage2: @@ -530,7 +530,6 @@ static bool fault_s1ns(ARMSecuritySpace space, ARMMMUIdx s2_mmu_idx) static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, hwaddr addr, ARMMMUFaultInfo *fi) { - bool is_secure = ptw->in_secure; ARMMMUIdx mmu_idx = ptw->in_mmu_idx; ARMMMUIdx s2_mmu_idx = ptw->in_ptw_idx; uint8_t pte_attrs; @@ -587,7 +586,7 @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, } if (regime_is_stage2(s2_mmu_idx)) { - uint64_t hcr = arm_hcr_el2_eff_secstate(env, is_secure); + uint64_t hcr = arm_hcr_el2_eff_secstate(env, ptw->in_space); if ((hcr & HCR_PTW) && S2_attrs_are_device(hcr, pte_attrs)) { /* @@ -3066,7 +3065,6 @@ static bool get_phys_addr_disabled(CPUARMState *env, ARMMMUFaultInfo *fi) { ARMMMUIdx mmu_idx = ptw->in_mmu_idx; - bool is_secure = arm_space_is_secure(ptw->in_space); uint8_t memattr = 0x00; /* Device nGnRnE */ uint8_t shareability = 0; /* non-shareable */ int r_el; @@ -3112,7 +3110,7 @@ static bool get_phys_addr_disabled(CPUARMState *env, /* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */ if (r_el == 1) { - uint64_t hcr = arm_hcr_el2_eff_secstate(env, is_secure); + uint64_t hcr = arm_hcr_el2_eff_secstate(env, ptw->in_space); if (hcr & HCR_DC) { if (hcr & HCR_DCT) { memattr = 0xf0; /* Tagged, Normal, WB, RWA */ @@ -3149,7 +3147,6 @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw, { hwaddr ipa; int s1_prot, s1_lgpgsz; - bool is_secure = ptw->in_secure; ARMSecuritySpace in_space = ptw->in_space; bool ret, ipa_secure; ARMCacheAttrs cacheattrs1; @@ -3212,7 +3209,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw, } /* Combine the S1 and S2 cache attributes. */ - hcr = arm_hcr_el2_eff_secstate(env, is_secure); + hcr = arm_hcr_el2_eff_secstate(env, in_space); if (hcr & HCR_DC) { /* * HCR.DC forces the first stage attributes to From patchwork Fri Jul 14 15:46:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 702741 Delivered-To: patch@linaro.org Received: by 2002:adf:db4e:0:b0:314:25da:8dc4 with SMTP id f14csp1162612wrj; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id t16-20020a5d49d0000000b003143bb5ecd5sm11214025wrs.69.2023.07.14.08.46.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Jul 2023 08:46:54 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 07/14] target/arm/ptw: Only fold in NSTable bit effects in Secure state Date: Fri, 14 Jul 2023 16:46:41 +0100 Message-Id: <20230714154648.327466-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230714154648.327466-1-peter.maydell@linaro.org> References: <20230714154648.327466-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org When we do a translation in Secure state, the NSTable bits in table descriptors may downgrade us to NonSecure; we update ptw->in_secure and ptw->in_space accordingly. We guard that check correctly with a conditional that means it's only applied for Secure stage 1 translations. However, later on in get_phys_addr_lpae() we fold the effects of the NSTable bits into the final descriptor attributes bits, and there we do it unconditionally regardless of the CPU state. That means that in Realm state (where in_secure is false) we will set bit 5 in attrs, and later use it to decide to output to non-secure space. We don't in fact need to do this folding in at all any more (since commit 2f1ff4e7b9f30c): if an NSTable bit was set then we have already set ptw->in_space to ARMSS_NonSecure, and in that situation we don't look at attrs bit 5. The only thing we still need to deal with is the real NS bit in the final descriptor word, so we can just drop the code that ORed in the NSTable bit. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/ptw.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 9e45160e1ba..c30d3fe69a0 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1884,11 +1884,10 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, * Extract attributes from the (modified) descriptor, and apply * table descriptors. Stage 2 table descriptors do not include * any attribute fields. HPD disables all the table attributes - * except NSTable. + * except NSTable (which we have already handled). */ attrs = new_descriptor & (MAKE_64BIT_MASK(2, 10) | MAKE_64BIT_MASK(50, 14)); if (!regime_is_stage2(mmu_idx)) { - attrs |= !ptw->in_secure << 5; /* NS */ if (!param.hpd) { attrs |= extract64(tableattrs, 0, 2) << 53; /* XN, PXN */ /* From patchwork Fri Jul 14 15:46:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 702737 Delivered-To: patch@linaro.org Received: by 2002:adf:db4e:0:b0:314:25da:8dc4 with SMTP id f14csp1162078wrj; Fri, 14 Jul 2023 08:49:48 -0700 (PDT) X-Google-Smtp-Source: APBJJlHcfZjp0GdPSE5US3EcwD6mNgUPWKdgZfRAbOR7zjyBYOXA8SLV3h2lXJDWQ4iw5UloerQD X-Received: by 2002:a1f:5e07:0:b0:481:3721:7811 with SMTP id s7-20020a1f5e07000000b0048137217811mr3597052vkb.0.1689349787856; Fri, 14 Jul 2023 08:49:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689349787; cv=none; d=google.com; s=arc-20160816; b=EhwL7wM2/JmNOgqC5W3XsmKy49aENfxSShotuwyJLtjNuckYtNH5slWBYx4+uX9wFY sKg15mvsSHBP6eT+Ts8E8SeF+QlEKc2cNIhPWjwzBsLY7AzMi8kELgbt37ms4R5Cniau hqdeQSSOM/0esvQdVUDbncfixM78TEELpEeiNLlOqBLttnvczW1MwQ2wAfYlo30AfI5S xXbP15nhr4xNRhM9O6Ah6jT/3rv6F38+XqG2aSmv4z5QpjZnxdRVLYFsOo1yTgoW09LX p+WZe2/XO8ryEcGxBMjGPaHKsExvwZ3rKT2kzvodAQkjCH2eKgUDx2fDZUgK5Zbi8xvx cOsA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=FCSU4FtaO/3zeArkUS9xQ1e+FjPheX63usjZ65/2/SU=; fh=jvpdohKmRoZMO537s6xMKXXtj7EZws1LOMQI/oP4vXs=; b=m2pVqZsycZAgII82sFbl558nJy0+EhhhCOohI0jDelxRvmmbwKI5h5YQZgzPCSDPIa S5UCOJM3YQQ1oZoNP/lp4R6X6m4ZXtgwa7NTXAUOkNdISuzxC6K69RW7r2uYAE+bH+e8 NfcdQ7rJ3s7pziQWxvBEQc/JXGu7RbcgiF6WKeRdOSQTOJzb9Jby+KNQJEV148+Fqqzq L96Maqy9OspxYMFpr4LsjX7Zjl3ZcMpiGKX2xWJBL87xN1C5Xry9YO2N41iyD9uVBL9x yUgCW8/6PFs+Z9Z+VElsOCvfPV1RtQNOkEKLxz4WuOp41nmG21LBc7WVAnMoyZXskrtc dhBQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=I40HmBU3; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id t16-20020a5d49d0000000b003143bb5ecd5sm11214025wrs.69.2023.07.14.08.46.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Jul 2023 08:46:54 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 08/14] target/arm/ptw: Remove last uses of ptw->in_secure Date: Fri, 14 Jul 2023 16:46:42 +0100 Message-Id: <20230714154648.327466-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230714154648.327466-1-peter.maydell@linaro.org> References: <20230714154648.327466-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Replace the last uses of ptw->in_secure with appropriate checks on ptw->in_space. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/ptw.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index c30d3fe69a0..bc834675fb2 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -3247,7 +3247,6 @@ static bool get_phys_addr_nogpc(CPUARMState *env, S1Translate *ptw, ARMMMUFaultInfo *fi) { ARMMMUIdx mmu_idx = ptw->in_mmu_idx; - bool is_secure = ptw->in_secure; ARMMMUIdx s1_mmu_idx; /* @@ -3255,8 +3254,8 @@ static bool get_phys_addr_nogpc(CPUARMState *env, S1Translate *ptw, * cannot upgrade a NonSecure translation regime's attributes * to Secure or Realm. */ - result->f.attrs.secure = is_secure; result->f.attrs.space = ptw->in_space; + result->f.attrs.secure = arm_space_is_secure(ptw->in_space); switch (mmu_idx) { case ARMMMUIdx_Phys_S: @@ -3270,8 +3269,12 @@ static bool get_phys_addr_nogpc(CPUARMState *env, S1Translate *ptw, case ARMMMUIdx_Stage1_E0: case ARMMMUIdx_Stage1_E1: case ARMMMUIdx_Stage1_E1_PAN: - /* First stage lookup uses second stage for ptw. */ - ptw->in_ptw_idx = is_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2; + /* + * First stage lookup uses second stage for ptw; only + * Secure has both S and NS IPA and starts with Stage2_S. + */ + ptw->in_ptw_idx = (ptw->in_space == ARMSS_Secure) ? + ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2; break; case ARMMMUIdx_Stage2: From patchwork Fri Jul 14 15:46:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 702733 Delivered-To: patch@linaro.org Received: by 2002:adf:db4e:0:b0:314:25da:8dc4 with SMTP id f14csp1161420wrj; Fri, 14 Jul 2023 08:48:21 -0700 (PDT) X-Google-Smtp-Source: APBJJlFkb0wEz/oYMOv3JcSGCZdcG30I5TeQftGCUyg52UZ9BIRhll1ECKghegMsoAyHp7E9dkks X-Received: by 2002:a05:620a:4256:b0:765:a7d9:7085 with SMTP id w22-20020a05620a425600b00765a7d97085mr5624948qko.51.1689349701404; Fri, 14 Jul 2023 08:48:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689349701; cv=none; d=google.com; s=arc-20160816; b=J0cJulqKaWx2d264c8/d5wgy0TyTf6pcGLfVgWEOD33Kc2BZRYxuTkiZvXpuc/EDv/ +wj27GqkTuLcAgzzfWaDiuRp03IcmylXSDMaySHeAkRUR99lInkqgTvXq/tj6IZlsszm kkgIXP6UZp52zjRwPYpV85FXs48Wh8dzPXellrct0Ip2cFp72kHuUDEONSIskz2Dciiu osI41ozL6AMe1XYnVQi8GRpc9qGFHI9X1uWL3RVTyCALlzDIk9svs0rk+lTKz86fdZxE Jy2DI/dxeSjDoB6IXPEYNc/PuBYyjuJFZ3ifM0BdnkwznF2GpnVPf9OV14GyvAtRC1XF Q4CA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=TpDMhnEcDgkB2wr6VipjcrDus/OWGCdiCk/KPC7Pdx8=; fh=jvpdohKmRoZMO537s6xMKXXtj7EZws1LOMQI/oP4vXs=; b=Ev2qWzcKed1Ou57oOlGLJizRyuiwvZdn8TCCNI8slzn2yWtd/XElHz7Bg+JDWCaZiK 4h8AR4sIuLj0FSo70yULv50uSh6Z1fkgrtCgyU25H9RIOsGJ7M75R4NYie5B6gehLLfh Vbbn/Hy6f4XnNXtpS6vUGbZU4GXj6nl4KLvYzj6vmUxXRoPaely1XD1dFfDrBUncjtDp yfb9iwvyiyqnoGPY0rL7C9wj793u3d9gaFq5DX5+OlobxBTcFhviUMiBY9q0Hrl3b8x3 1OYtWOSS7M96cdljkpoEJkn1NknKWNoAHuHC7N6NLx0PLsVAMjw4VGOa1GXaZ3ZZkdI7 szeQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CdX1X31W; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id t16-20020a5d49d0000000b003143bb5ecd5sm11214025wrs.69.2023.07.14.08.46.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Jul 2023 08:46:54 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 09/14] target/arm/ptw: Remove S1Translate::in_secure Date: Fri, 14 Jul 2023 16:46:43 +0100 Message-Id: <20230714154648.327466-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230714154648.327466-1-peter.maydell@linaro.org> References: <20230714154648.327466-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org We no longer look at the in_secure field of the S1Translate struct anyway, so we can remove it and all the code which sets it. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/ptw.c | 13 ------------- 1 file changed, 13 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index bc834675fb2..77b8382ceff 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -51,13 +51,6 @@ typedef struct S1Translate { * value being Stage2 vs Stage2_S distinguishes those. */ ARMSecuritySpace in_space; - /* - * in_secure: whether the translation regime is a Secure one. - * This is always equal to arm_space_is_secure(in_space). - * If a Secure ptw is "downgraded" to NonSecure by an NSTable bit, - * this field is updated accordingly. - */ - bool in_secure; /* * in_debug: is this a QEMU debug access (gdbstub, etc)? Debug * accesses will not update the guest page table access flags @@ -545,7 +538,6 @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, S1Translate s2ptw = { .in_mmu_idx = s2_mmu_idx, .in_ptw_idx = ptw_idx_for_stage_2(env, s2_mmu_idx), - .in_secure = arm_space_is_secure(s2_space), .in_space = s2_space, .in_debug = true, }; @@ -1782,7 +1774,6 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_S + 1 != ARMMMUIdx_Phys_NS); QEMU_BUILD_BUG_ON(ARMMMUIdx_Stage2_S + 1 != ARMMMUIdx_Stage2); ptw->in_ptw_idx += 1; - ptw->in_secure = false; ptw->in_space = ARMSS_NonSecure; } @@ -3165,7 +3156,6 @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw, ptw->in_s1_is_el0 = ptw->in_mmu_idx == ARMMMUIdx_Stage1_E0; ptw->in_mmu_idx = ipa_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2; - ptw->in_secure = ipa_secure; ptw->in_space = ipa_space; ptw->in_ptw_idx = ptw_idx_for_stage_2(env, ptw->in_mmu_idx); @@ -3401,7 +3391,6 @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address, { S1Translate ptw = { .in_mmu_idx = mmu_idx, - .in_secure = is_secure, .in_space = arm_secure_to_space(is_secure), }; return get_phys_addr_gpc(env, &ptw, address, access_type, result, fi); @@ -3473,7 +3462,6 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, } ptw.in_space = ss; - ptw.in_secure = arm_space_is_secure(ss); return get_phys_addr_gpc(env, &ptw, address, access_type, result, fi); } @@ -3487,7 +3475,6 @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, S1Translate ptw = { .in_mmu_idx = mmu_idx, .in_space = ss, - .in_secure = arm_space_is_secure(ss), .in_debug = true, }; GetPhysAddrResult res = {}; From patchwork Fri Jul 14 15:46:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 702735 Delivered-To: patch@linaro.org Received: by 2002:adf:db4e:0:b0:314:25da:8dc4 with SMTP id f14csp1161626wrj; Fri, 14 Jul 2023 08:48:46 -0700 (PDT) X-Google-Smtp-Source: APBJJlECH9JpoF46jrXq5d0no4vBA/nlZUnP9CxTm8Y3dd/kFGqvLklhFMk+lhNeSzHbZxjGnGjH X-Received: by 2002:a05:620a:8f83:b0:767:494f:4ab5 with SMTP id ri3-20020a05620a8f8300b00767494f4ab5mr4959047qkn.39.1689349726099; Fri, 14 Jul 2023 08:48:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689349726; cv=none; d=google.com; s=arc-20160816; b=dhhh2RHocotkmb380J1tnf1XVJo1MXWOq1PuqAWzAqwN/OcMZBWO9dXrQcLzYL7ZYf OjH2EwghKK4vCSl/04aexIuYXn83tNT+X1HRhixtepRXerLw8B52H58K6S9jqpAEZSO8 ezMnJDakVT5xVKiuuZo2USVVGylWtt8QrMO9on/3hs7YdVa2Xd65an9Xj1X3+uEoU02d Yv3rL1FgVwoQuWWu6vFt4dLGo4MQTtpoLEMv9JiElZYUZJQt9qaoH3/lAgu/1HN6MBs0 m3n5MMcS9lFMSdv3HC3t1mryrRfeRnKWL57Bktz/0bdG9tOuat6kiF/ht4SPY0fc8Fl2 OOCg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=mAzSZlytbR1t1ZIQhjeYZyBJFO870QY6aIUEWQM1ovA=; fh=jvpdohKmRoZMO537s6xMKXXtj7EZws1LOMQI/oP4vXs=; b=QNwT67IWQuSbVus52GvOHSiIxWqe4aeQjAc4VYcPxl3eYVHDlQDzulS93eR+VVPS6l tCjgwY7pRMTC2I7MnPxrBIHGBIEZ2SVE1BhlYm9rZKXG9XAXkgqfj3cOxVezrCDGhOy0 bnrCzWcYs2EPui0xH56/ncYMSGj82cxxQ2ONamPmQlnAdDdypVKzOL4CY9B15agxseH0 dM9/p5Qi235V5yWxhCOg/xpH0cAjPBxgRAv0p2juw07r4lczbnzxpJ62uu5c3ihh0kRI FPZy7T8V/r+Eg4jWobH8YZRJmwyPt3ZKJuBSjS3NdsPnI2JVyb2gNbWxsoyOqby04ie6 bytg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=M6KVwi48; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id t16-20020a5d49d0000000b003143bb5ecd5sm11214025wrs.69.2023.07.14.08.46.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Jul 2023 08:46:55 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 10/14] target/arm/ptw: Drop S1Translate::out_secure Date: Fri, 14 Jul 2023 16:46:44 +0100 Message-Id: <20230714154648.327466-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230714154648.327466-1-peter.maydell@linaro.org> References: <20230714154648.327466-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org We only use S1Translate::out_secure in two places, where we are setting up MemTxAttrs for a page table load. We can use arm_space_is_secure(ptw->out_space) instead, which guarantees that we're setting the MemTxAttrs secure and space fields consistently, and allows us to drop the out_secure field in S1Translate entirely. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/ptw.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 77b8382ceff..2be6bf302b0 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -63,7 +63,6 @@ typedef struct S1Translate { * Stage 2 is indicated by in_mmu_idx set to ARMMMUIdx_Stage2{,_S}. */ bool in_s1_is_el0; - bool out_secure; bool out_rw; bool out_be; ARMSecuritySpace out_space; @@ -551,7 +550,6 @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, pte_attrs = s2.cacheattrs.attrs; ptw->out_host = NULL; ptw->out_rw = false; - ptw->out_secure = s2.f.attrs.secure; ptw->out_space = s2.f.attrs.space; } else { #ifdef CONFIG_TCG @@ -570,7 +568,6 @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, ptw->out_phys = full->phys_addr | (addr & ~TARGET_PAGE_MASK); ptw->out_rw = full->prot & PAGE_WRITE; pte_attrs = full->pte_attrs; - ptw->out_secure = full->attrs.secure; ptw->out_space = full->attrs.space; #else g_assert_not_reached(); @@ -628,8 +625,8 @@ static uint32_t arm_ldl_ptw(CPUARMState *env, S1Translate *ptw, } else { /* Page tables are in MMIO. */ MemTxAttrs attrs = { - .secure = ptw->out_secure, .space = ptw->out_space, + .secure = arm_space_is_secure(ptw->out_space), }; AddressSpace *as = arm_addressspace(cs, attrs); MemTxResult result = MEMTX_OK; @@ -674,8 +671,8 @@ static uint64_t arm_ldq_ptw(CPUARMState *env, S1Translate *ptw, } else { /* Page tables are in MMIO. */ MemTxAttrs attrs = { - .secure = ptw->out_secure, .space = ptw->out_space, + .secure = arm_space_is_secure(ptw->out_space), }; AddressSpace *as = arm_addressspace(cs, attrs); MemTxResult result = MEMTX_OK; From patchwork Fri Jul 14 15:46:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 702731 Delivered-To: patch@linaro.org Received: by 2002:adf:db4e:0:b0:314:25da:8dc4 with SMTP id f14csp1161378wrj; Fri, 14 Jul 2023 08:48:15 -0700 (PDT) X-Google-Smtp-Source: APBJJlFHxFopz3aaV9PPi9YHGJ2QcI9WVr4N5DqSziD7YvOqOnDyqx5/FzVZ9PSVBWFgigxOAPwB X-Received: by 2002:a0c:ca85:0:b0:62d:e3d7:5b89 with SMTP id a5-20020a0cca85000000b0062de3d75b89mr4722857qvk.38.1689349695525; Fri, 14 Jul 2023 08:48:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689349695; cv=none; d=google.com; s=arc-20160816; b=PSgH+8ex73Fs5nLyvWe6YNfPLSFX65HV43RtChe9YTp6qXZ80z5K4tpWc4G6gPsedk G0t2bjN/6Xgf91Jm9A7uzQGK6BI4DJekZuDMJ9bzOEAhKhqaC8OO6AbIOEMIBlFvrP75 1P/39PzsLjaoRHgAlyHcgetvZx8oNiqg0iFCbnnqjIxuBJt7zFGVoG82dd4Vr45enxUd 2XtHha2NHfJfMwRNcOYno+Ieb4J1I68nza2F1jXwAhXOVl0cLKMrvUQAcg2S+/glxhLG 3w8DrbNKRg1GDECcytXRZNdhmOhtm+eVAr+UIjrjMRytFaH6S3oZV1uzPsekoEM9R2Gs 9qGQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=KTXC6GkpQIvSes2vuxm04/9pQF6G3CB656Q7X8rE+8M=; fh=jvpdohKmRoZMO537s6xMKXXtj7EZws1LOMQI/oP4vXs=; b=K0eoGDs8ENoXeOK+9FahoyanDuA0SKQ1Q1JHthTeZxHj8qDqHjCoImPaIjfbFfv2/A y0eOXhtnM2IM/IbOS6pz3eRsAvN9qyKG21r+/v9zPOLms5Y88hHlG/8ANhxOGGDa4BJj 0oDocAntX2J+OntN6o0xiXSLOcR4QllK6Wqp/Gh1u/SmKOTSJ7DUz6gidphK+jusi/gN mzyRPRxTu0jtDVPrqnJkf8Kuq2dldxilG1OH0f3Kh2rrLY3iIFSedGHR4jslBa8GRZpi jYstkIS0RAlQyEVPNMJC08f6gcHq16mMeQppdHV+d/jJzzoYW7XybRpzw5IW6+1Ok1O5 cIYQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QwTvGJfl; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id t16-20020a5d49d0000000b003143bb5ecd5sm11214025wrs.69.2023.07.14.08.46.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Jul 2023 08:46:55 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 11/14] target/arm/ptw: Set attributes correctly for MMU disabled data accesses Date: Fri, 14 Jul 2023 16:46:45 +0100 Message-Id: <20230714154648.327466-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230714154648.327466-1-peter.maydell@linaro.org> References: <20230714154648.327466-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org When the MMU is disabled, data accesses should be Device nGnRnE, Outer Shareable, Untagged. We handle the other cases from AArch64.S1DisabledOutput() correctly but missed this one. Device nGnRnE is memattr == 0, so the only part we were missing was that shareability should be set to 2 for both insn fetches and data accesses. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/ptw.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 2be6bf302b0..e4210abc148 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -3106,11 +3106,13 @@ static bool get_phys_addr_disabled(CPUARMState *env, } } } - if (memattr == 0 && access_type == MMU_INST_FETCH) { - if (regime_sctlr(env, mmu_idx) & SCTLR_I) { - memattr = 0xee; /* Normal, WT, RA, NT */ - } else { - memattr = 0x44; /* Normal, NC, No */ + if (memattr == 0) { + if (access_type == MMU_INST_FETCH) { + if (regime_sctlr(env, mmu_idx) & SCTLR_I) { + memattr = 0xee; /* Normal, WT, RA, NT */ + } else { + memattr = 0x44; /* Normal, NC, No */ + } } shareability = 2; /* outer shareable */ } From patchwork Fri Jul 14 15:46:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 702732 Delivered-To: patch@linaro.org Received: by 2002:adf:db4e:0:b0:314:25da:8dc4 with SMTP id f14csp1161408wrj; Fri, 14 Jul 2023 08:48:20 -0700 (PDT) X-Google-Smtp-Source: APBJJlFW26HQrwLalpOlHXy/rLaVmPyuNuOYe0jYqk2A2EbYkUwtBtcop5RYTws9atIgpK4X+uLw X-Received: by 2002:a05:620a:133c:b0:767:156e:ddaa with SMTP id p28-20020a05620a133c00b00767156eddaamr3120352qkj.35.1689349700277; Fri, 14 Jul 2023 08:48:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689349700; cv=none; d=google.com; s=arc-20160816; b=Ty/GACxJx2BZY3TiuGTd3T0xDzI64U/v8bB3RPFBZJUdHDYTx+jJyTz6i5UR2tBjm8 /3acU6mfilU7fdzmhIiGTkccdOQBzB4LtZwQvTBptDJcrLbfsXusUw49E7dVRhRfSfY4 jV7KcK00W6vYWEnzJb72PjPV5uMAF0eUw2H7ZfVnAwmNgmQUDhh3r1QqYlm3ZS+OYDct JjhBUldrSDNTt6jzMvumv2AvVgjimJ6Jcq1U3uGFeW24NieIgBLZnRlYDPJ+F6e7pDI0 HYioAQGdowjV4dID68A3Rm0QKP7/zp4IwHLZaPAvaZ+qTiKcNsl0US9nbg/I0wWKngmL RFWA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=zHxdCpbn/xikj26GCA5/nQ2FBBTjRyE6yEPZb7eG12g=; fh=jvpdohKmRoZMO537s6xMKXXtj7EZws1LOMQI/oP4vXs=; b=oRLbddb9rHqo6Baq0RcFWmCuM6EPN+6izdFtl8sETQ1rNSHJO59zYKVcWfFqbVXA5D 1BiNfIc55hFykCQB77mtEQ91j4zpjFdeYuxHINqlQZ1oGjX5enN7qKMIfDeaUJ7PwvrQ uRH6lRIgL1L2CnSdjG8/4dPYZVahUGDvARfUHNiwpFts6+mUejvxf3kkuDt5OEkXBx8l /JuClrYe24yd6M6RkyRVezdFDegDUFMrN/Ji7Z0SfjL5T38s97o3cslcLDWbrkNq5K8k HF0GuF24BWXIbmnh9PiEXhGA2LdFRYwd/0HumSNRcjIkCX5gmng4NEjEJlgNi5eT7ogn LmOA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ipnxl87x; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id t16-20020a5d49d0000000b003143bb5ecd5sm11214025wrs.69.2023.07.14.08.46.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Jul 2023 08:46:56 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 12/14] target/arm/ptw: Check for block descriptors at invalid levels Date: Fri, 14 Jul 2023 16:46:46 +0100 Message-Id: <20230714154648.327466-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230714154648.327466-1-peter.maydell@linaro.org> References: <20230714154648.327466-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The architecture doesn't permit block descriptors at any arbitrary level of the page table walk; it depends on the granule size which levels are permitted. We implemented only a partial version of this check which assumes that block descriptors are valid at all levels except level 3, which meant that we wouldn't deliver the Translation fault for all cases of this sort of guest page table error. Implement the logic corresponding to the pseudocode AArch64.DecodeDescriptorType() and AArch64.BlockDescSupported(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/ptw.c | 25 +++++++++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index e4210abc148..ed46bb82a75 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1549,6 +1549,25 @@ static int check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, uint64_t tcr, return INT_MIN; } +static bool lpae_block_desc_valid(ARMCPU *cpu, bool ds, + ARMGranuleSize gran, int level) +{ + /* + * See pseudocode AArch46.BlockDescSupported(): block descriptors + * are not valid at all levels, depending on the page size. + */ + switch (gran) { + case Gran4K: + return (level == 0 && ds) || level == 1 || level == 2; + case Gran16K: + return (level == 1 && ds) || level == 2; + case Gran64K: + return (level == 1 && arm_pamax(cpu) == 52) || level == 2; + default: + g_assert_not_reached(); + } +} + /** * get_phys_addr_lpae: perform one stage of page table walk, LPAE format * @@ -1784,8 +1803,10 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, new_descriptor = descriptor; restart_atomic_update: - if (!(descriptor & 1) || (!(descriptor & 2) && (level == 3))) { - /* Invalid, or the Reserved level 3 encoding */ + if (!(descriptor & 1) || + (!(descriptor & 2) && + !lpae_block_desc_valid(cpu, param.ds, param.gran, level))) { + /* Invalid, or a block descriptor at an invalid level */ goto do_translation_fault; } From patchwork Fri Jul 14 15:46:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 702727 Delivered-To: patch@linaro.org Received: by 2002:adf:db4e:0:b0:314:25da:8dc4 with SMTP id f14csp1161121wrj; Fri, 14 Jul 2023 08:47:43 -0700 (PDT) X-Google-Smtp-Source: APBJJlF4iI0qWaEgFgpRRGzkeAl+f3t32tqFssyuf9hZDXR11MOutAcIoZMTo4lZy5OZR1Ajosw+ X-Received: by 2002:ac8:57c3:0:b0:403:b052:7f58 with SMTP id w3-20020ac857c3000000b00403b0527f58mr6572936qta.39.1689349663255; Fri, 14 Jul 2023 08:47:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689349663; cv=none; d=google.com; s=arc-20160816; b=XKhJmc92DmMhF6ALhiFRDGHS2ZWOM44QZQHU13YVVsk8hgUz0ez85VzWHrffHnpH5r VrbbtXG8ucgwx7p2LV+pA+RO5Uom0I7frT4/j0pAXKpp4LYVq0Jedr0zqGSkNZYzxtU/ 2duM+Ra/wMbmGaPXmClPi2J7Z+3fa/w4jO+Jafy1AF5ms8o4wjqXdBnajWgY5Idyi2eV t8XjLfMo5cWhzlJSrhYAOceV12qIvZqAVF4IZP92ITKPglUuGncJjAskh6QdGsgURFL1 HPMTPxWF/OqA4kdwijLP8yIjruJSVjNFUdKdSrDW8OvUk+3g+8/ngFOkltmnXOd/uN+E L8VQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=MCCxEvnOoEn5P3Xa8BG9DaZmOIjYscf+/hErEQPjuEY=; fh=jvpdohKmRoZMO537s6xMKXXtj7EZws1LOMQI/oP4vXs=; b=aIKJ99ztwNYhCdecXhyb+nnIrW5iVWX5YA+jX50tbWN+Iodr0ykpUfSJ+GJnzUaK+D ybSUsA3vhoKcDXJ7RH2rIJA9+vGc9yhPGLws20oLHQo8/OC57TwNBjDajcYWL2Xqci3S 9mXWFR5/5M1SoCs7UL/tGSvMHJRiX6ZSEcMCIiemo8T5a3EJbFSSffQC9F4HvjIg0bjo a9uooC29HGo+reI4KfVamotshOwEOwQkhnwJxjiav9sHSfxZcSWuhkJAK8HOmJUFf+jT 5EypnWDhmeOMngFih7Cntw0iIyul0nggiLCz4JU/ORg4Csiv3piIP1lAd5PDZANPp/PG 7GiQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=bVKjxHGj; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id t16-20020a5d49d0000000b003143bb5ecd5sm11214025wrs.69.2023.07.14.08.46.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Jul 2023 08:46:57 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 13/14] target/arm/ptw: Report stage 2 fault level for stage 2 faults on stage 1 ptw Date: Fri, 14 Jul 2023 16:46:47 +0100 Message-Id: <20230714154648.327466-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230714154648.327466-1-peter.maydell@linaro.org> References: <20230714154648.327466-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org When we report faults due to stage 2 faults during a stage 1 page table walk, the 'level' parameter should be the level of the walk in stage 2 that faulted, not the level of the walk in stage 1. Correct the reporting of these faults. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/ptw.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index ed46bb82a75..d1de934702d 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2046,9 +2046,13 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, do_translation_fault: fi->type = ARMFault_Translation; do_fault: - fi->level = level; - /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */ - fi->stage2 = fi->s1ptw || regime_is_stage2(mmu_idx); + if (fi->s1ptw) { + /* Retain the existing stage 2 fi->level */ + assert(fi->stage2); + } else { + fi->level = level; + fi->stage2 = regime_is_stage2(mmu_idx); + } fi->s1ns = fault_s1ns(ptw->in_space, mmu_idx); return true; } From patchwork Fri Jul 14 15:46:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 702740 Delivered-To: patch@linaro.org Received: by 2002:adf:db4e:0:b0:314:25da:8dc4 with SMTP id f14csp1162296wrj; Fri, 14 Jul 2023 08:50:15 -0700 (PDT) X-Google-Smtp-Source: APBJJlEGHEaGlzo/t13KelWqrRacp+onSqEXWu0Hyidc8il1oJyI9dXsU5S7u5h+W9qr180JfSlC X-Received: by 2002:aca:de02:0:b0:3a1:ddc1:e25 with SMTP id v2-20020acade02000000b003a1ddc10e25mr4582284oig.58.1689349815723; Fri, 14 Jul 2023 08:50:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689349815; cv=none; d=google.com; s=arc-20160816; b=v2mu24e8xMAk353TX1Q5FsmQe74rk5h84cPHOw6JJZlfMX+BIUeYqg2pEVHX9XC0Ri fEynni7sfSGBMl6WjH5lQ03+3f/hqCt04UxRRq019SOOjWgu0PM3BI82DHvyo3qWL3BM lHqSTpuiJ722MvO7QAUhwAbvUlAb77cNTtplgNI/zK50+G4nz62svCTQtR4Vc8xC5GZR o2/aXaCBgSlvqpPM7btBTE6LFvZxAkMQg4P3zZgR4o5upm5o6h4KdSjb6DeviGupf2RI PYKMxreazibKzKfwaXarexNk4VI/Z4t7e2ds7NDkCpbT7t3g+1xxf8xGl+XH3YY5JpsH smDw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=BuUwbulU5zL9tN4hCYlIE1gc3ZvqjDoeI3CgFmuY05s=; fh=jvpdohKmRoZMO537s6xMKXXtj7EZws1LOMQI/oP4vXs=; b=CE4VdUaUs1Dt3GFqggLVO/fb6KAItcCMHHufdpiXckdQodikZ4pesY86jHn7F403BH TwI1RPyKP5HP41I5jqoVw/7NmHrB63GBWkF/mUkxeljTFeltuo//ztFqYHnURnR7IQSV pe5D+4TyVMJNUGe/cdfyKlXo4htthWdZv5iIOPkFTgbAJfbZIdkcZJtz8NP/etHg2vMJ tGOpce1P58qWQ0L59RfTIAntZ9/2ycgEFmkN1aVHTTeEXABG4TBswrypc6ahIMIye2tZ N/ua/1uJpaIMT9TL6OCL0AnLTNkdY/hY1W4rxHajtSSIoPxMjUN2Fapy3JTVgh5RSwmk a9Dw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=K1xbhVUA; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id t16-20020a5d49d0000000b003143bb5ecd5sm11214025wrs.69.2023.07.14.08.46.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Jul 2023 08:46:57 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 14/14] target/arm: Adjust PAR_EL1.SH for Device and Normal-NC memory types Date: Fri, 14 Jul 2023 16:46:48 +0100 Message-Id: <20230714154648.327466-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230714154648.327466-1-peter.maydell@linaro.org> References: <20230714154648.327466-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The PAR_EL1.SH field documents that for the cases of: * Device memory * Normal memory with both Inner and Outer Non-Cacheable the field should be 0b10 rather than whatever was in the translation table descriptor field. (In the pseudocode this is handled by PAREncodeShareability().) Perform this adjustment when assembling a PAR value. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 1e45fdb47c9..f9c00827018 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3342,6 +3342,19 @@ static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri, } #ifdef CONFIG_TCG +static int par_el1_shareability(GetPhysAddrResult *res) +{ + /* + * The PAR_EL1.SH field must be 0b10 for Device or Normal-NC + * memory -- see pseudocode PAREncodeShareability(). + */ + if (((res->cacheattrs.attrs & 0xf0) == 0) || + res->cacheattrs.attrs == 0x44 || res->cacheattrs.attrs == 0x40) { + return 2; + } + return res->cacheattrs.shareability; +} + static uint64_t do_ats_write(CPUARMState *env, uint64_t value, MMUAccessType access_type, ARMMMUIdx mmu_idx, bool is_secure) @@ -3470,7 +3483,7 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value, par64 |= (1 << 9); /* NS */ } par64 |= (uint64_t)res.cacheattrs.attrs << 56; /* ATTR */ - par64 |= res.cacheattrs.shareability << 7; /* SH */ + par64 |= par_el1_shareability(&res) << 7; /* SH */ } else { uint32_t fsr = arm_fi_to_lfsc(&fi);