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Sun, 23 Jul 2023 01:28:04 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz 0FA4FF80153 Authentication-Results: alsa1.perex.cz; dkim=pass (2048-bit key, unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20201202 header.b=p79CDN4a Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 6A3BA60BBD; Sat, 22 Jul 2023 23:28:00 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id D2B9EC433C8; Sat, 22 Jul 2023 23:27:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1690068479; bh=4Rzq1YvQj5lkcsTj0h4z35hXfooOcCsSwzHWSviixF4=; h=From:Date:Subject:To:Cc:From; b=p79CDN4asme4HdUunkCbjeVgN2yWdSE7BvtdSIw4Qc5DfBUhaMlI1qFqak3pxdSSV t8Kn9HbNsjVHMH4tZW/B3DL4qo6tYFS2iI3fcXYSHy/PGBQA3guAZ5FqdkOZN7Ys7D l9XK7cgmm+1djMOE70ixbnTKLORdeLR069tMVMeBNjsCvgcVau7RITNPXmpvynkRbF +IdNqWjGA4EcuX4VKbwO6x0r9jfMFbrcc7N0Ad2S0+De4QI8rSf8i7MK2kVxtExjB1 FFAIY+YMZqoZYtgGejGkT+vPNGZKJX7ohtB1/a80koMZncKpOC0KlrXfWNT4W8nU4/ WgRAM7VtXBhTA== From: Mark Brown Date: Sun, 23 Jul 2023 00:27:22 +0100 Subject: [PATCH] ASoC: wm8904: Fill the cache for WM8904_ADC_TEST_0 register MIME-Version: 1.0 Message-Id: <20230723-asoc-fix-wm8904-adc-test-read-v1-1-2cdf2edd83fd@kernel.org> X-B4-Tracking: v=1; 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no-senders; approved; emergency; loop; banned-address; member-moderation; header-match-alsa-devel.alsa-project.org-0; header-match-alsa-devel.alsa-project.org-1; nonmember-moderation; administrivia; implicit-dest; max-recipients; max-size; news-moderation; no-subject; digests; suspicious-header X-Mailman-Version: 3.3.8 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" Archived-At: List-Archive: List-Help: List-Owner: List-Post: List-Subscribe: List-Unsubscribe: The WM8904_ADC_TEST_0 register is modified as part of updating the OSR controls but does not have a cache default, leading to errors when we try to modify these controls in cache only mode with no prior read: wm8904 3-001a: ASoC: error at snd_soc_component_update_bits on wm8904.3-001a for register: [0x000000c6] -16 Add a read of the register to probe() to fill the cache and avoid both the error messages and the misconfiguration of the chip which will result. Signed-off-by: Mark Brown Acked-by: Charles Keepax --- sound/soc/codecs/wm8904.c | 3 +++ 1 file changed, 3 insertions(+) --- base-commit: fdf0eaf11452d72945af31804e2a1048ee1b574c change-id: 20230722-asoc-fix-wm8904-adc-test-read-5a0051264a0b Best regards, diff --git a/sound/soc/codecs/wm8904.c b/sound/soc/codecs/wm8904.c index 068e610b1b4c..f2baee7c332e 100644 --- a/sound/soc/codecs/wm8904.c +++ b/sound/soc/codecs/wm8904.c @@ -2308,6 +2308,9 @@ static int wm8904_i2c_probe(struct i2c_client *i2c) regmap_update_bits(wm8904->regmap, WM8904_BIAS_CONTROL_0, WM8904_POBCTRL, 0); + /* Fill the cache for the ADC test register */ + regmap_read(wm8904->regmap, WM8904_ADC_TEST_0, &val); + /* Can leave the device powered off until we need it */ regcache_cache_only(wm8904->regmap, true); regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), wm8904->supplies);