From patchwork Mon Jul 24 06:01:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huqiang Qin X-Patchwork-Id: 705914 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 79D65C001B0 for ; Mon, 24 Jul 2023 06:02:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229768AbjGXGCO (ORCPT ); Mon, 24 Jul 2023 02:02:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46060 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229546AbjGXGCN (ORCPT ); Mon, 24 Jul 2023 02:02:13 -0400 Received: from mail-sh.amlogic.com (mail-sh.amlogic.com [58.32.228.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AF919CF; Sun, 23 Jul 2023 23:02:11 -0700 (PDT) Received: from rd02-sz.amlogic.software (10.28.11.83) by mail-sh.amlogic.com (10.18.11.5) with Microsoft SMTP Server id 15.1.2507.13; Mon, 24 Jul 2023 14:01:54 +0800 From: Huqiang Qin To: , , , , , , , CC: , , , , , Huqiang Qin Subject: [PATCH V2 1/3] dt-bindings: interrupt-controller: Add header file for Amlogic Meson-G12A SoCs Date: Mon, 24 Jul 2023 14:01:06 +0800 Message-ID: <20230724060108.1403662-2-huqiang.qin@amlogic.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20230724060108.1403662-1-huqiang.qin@amlogic.com> References: <20230724060108.1403662-1-huqiang.qin@amlogic.com> MIME-Version: 1.0 X-Originating-IP: [10.28.11.83] Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add a new dt-binding header that details the interrupt number of the GPIO. Signed-off-by: Huqiang Qin --- V1 -> V2: Rename irq-meson-g12a-gpio.h to amlogic,meson-g12a-gpio-intc.h .../amlogic,meson-g12a-gpio-intc.h | 126 ++++++++++++++++++ 1 file changed, 126 insertions(+) create mode 100644 include/dt-bindings/interrupt-controller/amlogic,meson-g12a-gpio-intc.h diff --git a/include/dt-bindings/interrupt-controller/amlogic,meson-g12a-gpio-intc.h b/include/dt-bindings/interrupt-controller/amlogic,meson-g12a-gpio-intc.h new file mode 100644 index 000000000000..bd415cb7b669 --- /dev/null +++ b/include/dt-bindings/interrupt-controller/amlogic,meson-g12a-gpio-intc.h @@ -0,0 +1,126 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (c) 2023 Amlogic, Inc. All rights reserved. + * Author: Huqiang Qin + */ + +#ifndef _DT_BINDINGS_IRQ_MESON_G12A_GPIO_H +#define _DT_BINDINGS_IRQ_MESON_G12A_GPIO_H + +/* IRQID[11:0] - GPIOAO[11:0] */ +#define IRQID_GPIOAO_0 0 +#define IRQID_GPIOAO_1 1 +#define IRQID_GPIOAO_2 2 +#define IRQID_GPIOAO_3 3 +#define IRQID_GPIOAO_4 4 +#define IRQID_GPIOAO_5 5 +#define IRQID_GPIOAO_6 6 +#define IRQID_GPIOAO_7 7 +#define IRQID_GPIOAO_8 8 +#define IRQID_GPIOAO_9 9 +#define IRQID_GPIOAO_10 10 +#define IRQID_GPIOAO_11 11 + +/* IRQID[27:12] - GPIOZ[15:0] */ +#define IRQID_GPIOZ_0 12 +#define IRQID_GPIOZ_1 13 +#define IRQID_GPIOZ_2 14 +#define IRQID_GPIOZ_3 15 +#define IRQID_GPIOZ_4 16 +#define IRQID_GPIOZ_5 17 +#define IRQID_GPIOZ_6 18 +#define IRQID_GPIOZ_7 19 +#define IRQID_GPIOZ_8 20 +#define IRQID_GPIOZ_9 21 +#define IRQID_GPIOZ_10 22 +#define IRQID_GPIOZ_11 23 +#define IRQID_GPIOZ_12 24 +#define IRQID_GPIOZ_13 25 +#define IRQID_GPIOZ_14 26 +#define IRQID_GPIOZ_15 27 + +/* IRQID[36:28] - GPIOH[8:0] */ +#define IRQID_GPIOH_0 28 +#define IRQID_GPIOH_1 29 +#define IRQID_GPIOH_2 30 +#define IRQID_GPIOH_3 31 +#define IRQID_GPIOH_4 32 +#define IRQID_GPIOH_5 33 +#define IRQID_GPIOH_6 34 +#define IRQID_GPIOH_7 35 +#define IRQID_GPIOH_8 36 + +/* IRQID[52:37] - BOOT[15:0] */ +#define IRQID_BOOT_0 37 +#define IRQID_BOOT_1 38 +#define IRQID_BOOT_2 39 +#define IRQID_BOOT_3 40 +#define IRQID_BOOT_4 41 +#define IRQID_BOOT_5 42 +#define IRQID_BOOT_6 43 +#define IRQID_BOOT_7 44 +#define IRQID_BOOT_8 45 +#define IRQID_BOOT_9 46 +#define IRQID_BOOT_10 47 +#define IRQID_BOOT_11 48 +#define IRQID_BOOT_12 49 +#define IRQID_BOOT_13 50 +#define IRQID_BOOT_14 51 +#define IRQID_BOOT_15 52 + +/* IRQID[60:53] - GPIOC[7:0] */ +#define IRQID_GPIOC_0 53 +#define IRQID_GPIOC_1 54 +#define IRQID_GPIOC_2 55 +#define IRQID_GPIOC_3 56 +#define IRQID_GPIOC_4 57 +#define IRQID_GPIOC_5 58 +#define IRQID_GPIOC_6 59 +#define IRQID_GPIOC_7 60 + +/* IRQID[76:61] - GPIOA[15:0] */ +#define IRQID_GPIOA_0 61 +#define IRQID_GPIOA_1 62 +#define IRQID_GPIOA_2 63 +#define IRQID_GPIOA_3 64 +#define IRQID_GPIOA_4 65 +#define IRQID_GPIOA_5 66 +#define IRQID_GPIOA_6 67 +#define IRQID_GPIOA_7 68 +#define IRQID_GPIOA_8 69 +#define IRQID_GPIOA_9 70 +#define IRQID_GPIOA_10 71 +#define IRQID_GPIOA_11 72 +#define IRQID_GPIOA_12 73 +#define IRQID_GPIOA_13 74 +#define IRQID_GPIOA_14 75 +#define IRQID_GPIOA_15 76 + +/* IRQID[96:77] - GPIOX[19:0] */ +#define IRQID_GPIOX_0 77 +#define IRQID_GPIOX_1 78 +#define IRQID_GPIOX_2 79 +#define IRQID_GPIOX_3 80 +#define IRQID_GPIOX_4 81 +#define IRQID_GPIOX_5 82 +#define IRQID_GPIOX_6 83 +#define IRQID_GPIOX_7 84 +#define IRQID_GPIOX_8 85 +#define IRQID_GPIOX_9 86 +#define IRQID_GPIOX_10 87 +#define IRQID_GPIOX_11 88 +#define IRQID_GPIOX_12 89 +#define IRQID_GPIOX_13 90 +#define IRQID_GPIOX_14 91 +#define IRQID_GPIOX_15 92 +#define IRQID_GPIOX_16 93 +#define IRQID_GPIOX_17 94 +#define IRQID_GPIOX_18 95 +#define IRQID_GPIOX_19 96 + +/* IRQID[99:97] - GPIOE[2:0] */ +#define IRQID_GPIOE_0 97 +#define IRQID_GPIOE_1 98 +#define IRQID_GPIOE_2 99 + +#endif /* _DT_BINDINGS_IRQ_MESON_G12A_GPIO_H */ From patchwork Mon Jul 24 06:01:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huqiang Qin X-Patchwork-Id: 705913 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6FDE2C001DE for ; Mon, 24 Jul 2023 06:03:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230196AbjGXGDG (ORCPT ); Mon, 24 Jul 2023 02:03:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46066 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230177AbjGXGDD (ORCPT ); Mon, 24 Jul 2023 02:03:03 -0400 Received: from mail-sh.amlogic.com (mail-sh.amlogic.com [58.32.228.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 54D7B1AD; Sun, 23 Jul 2023 23:02:13 -0700 (PDT) Received: from rd02-sz.amlogic.software (10.28.11.83) by mail-sh.amlogic.com (10.18.11.5) with Microsoft SMTP Server id 15.1.2507.13; Mon, 24 Jul 2023 14:01:54 +0800 From: Huqiang Qin To: , , , , , , , CC: , , , , , Huqiang Qin Subject: [PATCH V2 2/3] pinctrl: Replace the IRQ number in the driver with the IRQID macro definition Date: Mon, 24 Jul 2023 14:01:07 +0800 Message-ID: <20230724060108.1403662-3-huqiang.qin@amlogic.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20230724060108.1403662-1-huqiang.qin@amlogic.com> References: <20230724060108.1403662-1-huqiang.qin@amlogic.com> MIME-Version: 1.0 X-Originating-IP: [10.28.11.83] Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Replacing IRQ numbers with IRQID macro definitions makes driver code easier to understand. Associated platforms: - Amlogic Meson-G12A - Amlogic Meson-G12B - Amlogic Meson-SM1 Signed-off-by: Huqiang Qin Acked-by: Linus Walleij --- V1 -> V2: Include header file changed to amlogic,meson-g12a-gpio-intc.h drivers/pinctrl/meson/pinctrl-meson-g12a.c | 35 +++++++++++----------- 1 file changed, 18 insertions(+), 17 deletions(-) diff --git a/drivers/pinctrl/meson/pinctrl-meson-g12a.c b/drivers/pinctrl/meson/pinctrl-meson-g12a.c index d182a575981e..3cd86d6a0a60 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-g12a.c +++ b/drivers/pinctrl/meson/pinctrl-meson-g12a.c @@ -8,6 +8,7 @@ */ #include +#include #include "pinctrl-meson.h" #include "pinctrl-meson-axg-pmx.h" @@ -1318,31 +1319,31 @@ static struct meson_pmx_func meson_g12a_aobus_functions[] = { static struct meson_bank meson_g12a_periphs_banks[] = { /* name first last irq pullen pull dir out in ds */ - BANK_DS("Z", GPIOZ_0, GPIOZ_15, 12, 27, - 4, 0, 4, 0, 12, 0, 13, 0, 14, 0, 5, 0), - BANK_DS("H", GPIOH_0, GPIOH_8, 28, 36, - 3, 0, 3, 0, 9, 0, 10, 0, 11, 0, 4, 0), - BANK_DS("BOOT", BOOT_0, BOOT_15, 37, 52, - 0, 0, 0, 0, 0, 0, 1, 0, 2, 0, 0, 0), - BANK_DS("C", GPIOC_0, GPIOC_7, 53, 60, - 1, 0, 1, 0, 3, 0, 4, 0, 5, 0, 1, 0), - BANK_DS("A", GPIOA_0, GPIOA_15, 61, 76, - 5, 0, 5, 0, 16, 0, 17, 0, 18, 0, 6, 0), - BANK_DS("X", GPIOX_0, GPIOX_19, 77, 96, - 2, 0, 2, 0, 6, 0, 7, 0, 8, 0, 2, 0), + BANK_DS("Z", GPIOZ_0, GPIOZ_15, IRQID_GPIOZ_0, IRQID_GPIOZ_15, + 4, 0, 4, 0, 12, 0, 13, 0, 14, 0, 5, 0), + BANK_DS("H", GPIOH_0, GPIOH_8, IRQID_GPIOH_0, IRQID_GPIOH_8, + 3, 0, 3, 0, 9, 0, 10, 0, 11, 0, 4, 0), + BANK_DS("BOOT", BOOT_0, BOOT_15, IRQID_BOOT_0, IRQID_BOOT_15, + 0, 0, 0, 0, 0, 0, 1, 0, 2, 0, 0, 0), + BANK_DS("C", GPIOC_0, GPIOC_7, IRQID_GPIOC_0, IRQID_GPIOC_7, + 1, 0, 1, 0, 3, 0, 4, 0, 5, 0, 1, 0), + BANK_DS("A", GPIOA_0, GPIOA_15, IRQID_GPIOA_0, IRQID_GPIOA_15, + 5, 0, 5, 0, 16, 0, 17, 0, 18, 0, 6, 0), + BANK_DS("X", GPIOX_0, GPIOX_19, IRQID_GPIOX_0, IRQID_GPIOX_19, + 2, 0, 2, 0, 6, 0, 7, 0, 8, 0, 2, 0), }; static struct meson_bank meson_g12a_aobus_banks[] = { /* name first last irq pullen pull dir out in ds */ - BANK_DS("AO", GPIOAO_0, GPIOAO_11, 0, 11, 3, 0, 2, 0, 0, 0, 4, 0, 1, 0, - 0, 0), + BANK_DS("AO", GPIOAO_0, GPIOAO_11, IRQID_GPIOAO_0, IRQID_GPIOAO_11, + 3, 0, 2, 0, 0, 0, 4, 0, 1, 0, 0, 0), /* GPIOE actually located in the AO bank */ - BANK_DS("E", GPIOE_0, GPIOE_2, 97, 99, 3, 16, 2, 16, 0, 16, 4, 16, 1, - 16, 1, 0), + BANK_DS("E", GPIOE_0, GPIOE_2, IRQID_GPIOE_0, IRQID_GPIOE_2, + 3, 16, 2, 16, 0, 16, 4, 16, 1, 16, 1, 0), }; static struct meson_pmx_bank meson_g12a_periphs_pmx_banks[] = { - /* name first lask reg offset */ + /* name first last reg offset */ BANK_PMX("Z", GPIOZ_0, GPIOZ_15, 0x6, 0), BANK_PMX("H", GPIOH_0, GPIOH_8, 0xb, 0), BANK_PMX("BOOT", BOOT_0, BOOT_15, 0x0, 0),