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Mon, 24 Jul 2023 03:46:16 -0500 Received: from xhdlakshmis40.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2507.27 via Frontend Transport; Mon, 24 Jul 2023 03:46:12 -0500 From: Sai Krishna Potthuri To: Linus Walleij , Michal Simek , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mathieu Poirier , Tanmay Shah , Ben Levinsky , Marek Vasut , Roman Gushchin , Arnd Bergmann CC: , , , , , , Sai Krishna Potthuri Subject: [PATCH v2 1/4] firmware: xilinx: Add support to get platform information Date: Mon, 24 Jul 2023 14:15:51 +0530 Message-ID: <20230724084554.1924378-2-sai.krishna.potthuri@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230724084554.1924378-1-sai.krishna.potthuri@amd.com> References: <20230724084554.1924378-1-sai.krishna.potthuri@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT078:EE_|SA0PR12MB4590:EE_ X-MS-Office365-Filtering-Correlation-Id: 446bdba2-0ad1-4bd7-f4e5-08db8c22720e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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SFS:(13230028)(4636009)(136003)(346002)(396003)(376002)(39860400002)(451199021)(82310400008)(36840700001)(46966006)(40470700004)(6666004)(478600001)(4326008)(316002)(40480700001)(70206006)(70586007)(110136005)(41300700001)(54906003)(103116003)(36756003)(36860700001)(8676002)(8936002)(7416002)(40460700003)(26005)(186003)(1076003)(336012)(5660300002)(86362001)(82740400003)(2616005)(426003)(81166007)(921005)(356005)(2906002)(47076005)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Jul 2023 08:46:17.2947 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 446bdba2-0ad1-4bd7-f4e5-08db8c22720e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT078.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4590 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Dhaval Shah Add function to get family code and sub family code from the idcode. This family code and sub family code helps to identify the platform. Family code of any platform is on bits 21 to 27 and Sub family code is on bits 19 and 20. Signed-off-by: Dhaval Shah Signed-off-by: Sai Krishna Potthuri --- drivers/firmware/xilinx/zynqmp.c | 42 ++++++++++++++++++++++++++++ include/linux/firmware/xlnx-zynqmp.h | 13 +++++++++ 2 files changed, 55 insertions(+) diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c index a736db4a5825..f9498e7ea694 100644 --- a/drivers/firmware/xilinx/zynqmp.c +++ b/drivers/firmware/xilinx/zynqmp.c @@ -339,6 +339,8 @@ int zynqmp_pm_invoke_fn(u32 pm_api_id, u32 arg0, u32 arg1, static u32 pm_api_version; static u32 pm_tz_version; +static u32 pm_family_code; +static u32 pm_sub_family_code; int zynqmp_pm_register_sgi(u32 sgi_num, u32 reset) { @@ -404,6 +406,41 @@ int zynqmp_pm_get_chipid(u32 *idcode, u32 *version) } EXPORT_SYMBOL_GPL(zynqmp_pm_get_chipid); +/** + * zynqmp_pm_get_family_info() - Get family info of platform + * @family: Returned family code value + * @subfamily: Returned sub-family code value + * + * Return: Returns status, either success or error+reason + */ +static int zynqmp_pm_get_family_info(u32 *family, u32 *subfamily) +{ + u32 ret_payload[PAYLOAD_ARG_CNT]; + u32 idcode; + int ret; + + /* Check is family or sub-family code already received */ + if (pm_family_code && pm_sub_family_code) { + *family = pm_family_code; + *subfamily = pm_sub_family_code; + return 0; + } + + ret = zynqmp_pm_invoke_fn(PM_GET_CHIPID, 0, 0, 0, 0, ret_payload); + if (ret < 0) + return ret; + + idcode = ret_payload[1]; + pm_family_code = FIELD_GET(GENMASK(FAMILY_CODE_MSB, FAMILY_CODE_LSB), + idcode); + pm_sub_family_code = FIELD_GET(GENMASK(SUB_FAMILY_CODE_MSB, + SUB_FAMILY_CODE_LSB), idcode); + *family = pm_family_code; + *subfamily = pm_sub_family_code; + + return 0; +} + /** * zynqmp_pm_get_trustzone_version() - Get secure trustzone firmware version * @version: Returned version value @@ -1911,6 +1948,11 @@ static int zynqmp_firmware_probe(struct platform_device *pdev) pr_info("%s Platform Management API v%d.%d\n", __func__, pm_api_version >> 16, pm_api_version & 0xFFFF); + /* Get the Family code and sub family code of platform */ + ret = zynqmp_pm_get_family_info(&pm_family_code, &pm_sub_family_code); + if (ret < 0) + return ret; + /* Check trustzone version number */ ret = zynqmp_pm_get_trustzone_version(&pm_tz_version); if (ret) diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h index f5da51677069..d7f94b42ad4c 100644 --- a/include/linux/firmware/xlnx-zynqmp.h +++ b/include/linux/firmware/xlnx-zynqmp.h @@ -34,6 +34,19 @@ /* PM API versions */ #define PM_API_VERSION_2 2 +#define ZYNQMP_FAMILY_CODE 0x23 +#define VERSAL_FAMILY_CODE 0x26 + +/* When all subfamily of platform need to support */ +#define ALL_SUB_FAMILY_CODE 0x00 +#define VERSAL_SUB_FAMILY_CODE 0x01 +#define VERSALNET_SUB_FAMILY_CODE 0x03 + +#define FAMILY_CODE_LSB 21 +#define FAMILY_CODE_MSB 27 +#define SUB_FAMILY_CODE_LSB 19 +#define SUB_FAMILY_CODE_MSB 20 + /* ATF only commands */ #define TF_A_PM_REGISTER_SGI 0xa04 #define PM_GET_TRUSTZONE_VERSION 0xa03 From patchwork Mon Jul 24 08:45:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sai Krishna Potthuri X-Patchwork-Id: 705924 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6A16CC0015E for ; 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Using these pinctrl properties observed hang issues with older Xilinx ZynqMP Platform Management Firmware, hence reverted the patch previously. Commit ff8356060e3a5e126abb ("Revert "dt-bindings: pinctrl-zynqmp: Add output-enable configuration""). Support for configuring these properties added in Xilinx ZynqMP Platform Management firmware(PMUFW) Configuration Set version 2.0. Linux firmware driver checks if the configuration is supported by the PMUFW when it gets request for TRISTATE configuration from pinctrl driver. If it supports, then calls will be made otherwise it returns error. Signed-off-by: Sai Krishna Potthuri Acked-by: Conor Dooley --- .../devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml index 2722dc7bb03d..1e2b9b627b12 100644 --- a/Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml @@ -274,6 +274,10 @@ patternProperties: slew-rate: enum: [0, 1] + output-enable: + description: + This will internally disable the tri-state for MIO pins. + drive-strength: description: Selects the drive strength for MIO pins, in mA.