From patchwork Mon Jul 31 05:25:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohit Agarwal X-Patchwork-Id: 708503 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 47651C04E69 for ; Mon, 31 Jul 2023 05:25:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229591AbjGaFZZ (ORCPT ); Mon, 31 Jul 2023 01:25:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49138 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229963AbjGaFZY (ORCPT ); Mon, 31 Jul 2023 01:25:24 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 46CA0E7C; Sun, 30 Jul 2023 22:25:21 -0700 (PDT) Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 36V4J7lI021076; Mon, 31 Jul 2023 05:25:14 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references; s=qcppdkim1; bh=Vt14ovzPT5cuYr7v5GPtjgGhVyc5Q1hVycwfTc1p7nQ=; b=ncgB4GqIGVz+repPG6vMacmaY3XuxFh6Xg49OyM+SxxN/uUXf2ub42agZoGlwqCyXuRc xQsbOvD/x/0GnyRBuBaYs62rF8gdPu54EnNatu1KbOu3KJZgSpLbHW0isB33yYoXJMZO GvLPFe1htfecHVnOWzrmUmbN/epulKG2CCOQmBmkQADIFsbhMjZDIpimoKw6LxnMeyNN IG/VQlLBOxO5WfW8NT0mVDvMIZWd3RenRX7dUIiWXl/T8t/k3IWRsOd7vgCkAZanN/rF mtO9Gi/j1tElZW3+JvI2fn/ae02UQqwAfhf/Qnvl7LBZ8WH2oRZ2Xzkm+MG4bdVzbz+Y NQ== Received: from apblrppmta02.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3s4uxsamgn-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 31 Jul 2023 05:25:13 +0000 Received: from pps.filterd (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 36V5PA2A017582; Mon, 31 Jul 2023 05:25:10 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 3s4uuk6gxp-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Mon, 31 Jul 2023 05:25:10 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 36V5P9M4017573; Mon, 31 Jul 2023 05:25:10 GMT Received: from hu-sgudaval-hyd.qualcomm.com (hu-rohiagar-hyd.qualcomm.com [10.213.106.138]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 36V5P9lq017569; Mon, 31 Jul 2023 05:25:09 +0000 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3970568) id 45AAF1AA0; Mon, 31 Jul 2023 10:55:09 +0530 (+0530) From: Rohit Agarwal To: agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: cros-qcom-dts-watchers@chromium.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rohit Agarwal Subject: [PATCH 1/4] dt-bindings: power: qcom, rpmhpd: Add the regulator levels for RPMHPD Date: Mon, 31 Jul 2023 10:55:01 +0530 Message-Id: <1690781104-2290-2-git-send-email-quic_rohiagar@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1690781104-2290-1-git-send-email-quic_rohiagar@quicinc.com> References: <1690781104-2290-1-git-send-email-quic_rohiagar@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: muG-d0KQyB23NTeji3d1FoeWUW8nNdLK X-Proofpoint-GUID: muG-d0KQyB23NTeji3d1FoeWUW8nNdLK X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-27_10,2023-07-26_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 priorityscore=1501 malwarescore=0 clxscore=1015 impostorscore=0 mlxlogscore=527 suspectscore=0 bulkscore=0 lowpriorityscore=0 spamscore=0 adultscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2307310048 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add the regulator levels for RPMHPD for Qualcomm SoCs having RPMH. Signed-off-by: Rohit Agarwal --- include/dt-bindings/power/qcom,rpmhpd.h | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/include/dt-bindings/power/qcom,rpmhpd.h b/include/dt-bindings/power/qcom,rpmhpd.h index 7c201a6..578243f 100644 --- a/include/dt-bindings/power/qcom,rpmhpd.h +++ b/include/dt-bindings/power/qcom,rpmhpd.h @@ -27,4 +27,30 @@ #define RPMHPD_DDR 17 #define RPMHPD_XO 18 +/* RPMHPD performance levels */ +#define RPMH_REGULATOR_LEVEL_RETENTION 16 +#define RPMH_REGULATOR_LEVEL_MIN_SVS 48 +#define RPMH_REGULATOR_LEVEL_LOW_SVS_D2 52 +#define RPMH_REGULATOR_LEVEL_LOW_SVS_D1 56 +#define RPMH_REGULATOR_LEVEL_LOW_SVS_D0 60 +#define RPMH_REGULATOR_LEVEL_LOW_SVS 64 +#define RPMH_REGULATOR_LEVEL_LOW_SVS_P1 72 +#define RPMH_REGULATOR_LEVEL_LOW_SVS_L1 80 +#define RPMH_REGULATOR_LEVEL_LOW_SVS_L2 96 +#define RPMH_REGULATOR_LEVEL_SVS 128 +#define RPMH_REGULATOR_LEVEL_SVS_L0 144 +#define RPMH_REGULATOR_LEVEL_SVS_L1 192 +#define RPMH_REGULATOR_LEVEL_SVS_L2 224 +#define RPMH_REGULATOR_LEVEL_NOM 256 +#define RPMH_REGULATOR_LEVEL_NOM_L0 288 +#define RPMH_REGULATOR_LEVEL_NOM_L1 320 +#define RPMH_REGULATOR_LEVEL_NOM_L2 336 +#define RPMH_REGULATOR_LEVEL_TURBO 384 +#define RPMH_REGULATOR_LEVEL_TURBO_L0 400 +#define RPMH_REGULATOR_LEVEL_TURBO_L1 416 +#define RPMH_REGULATOR_LEVEL_TURBO_L2 432 +#define RPMH_REGULATOR_LEVEL_TURBO_L3 448 +#define RPMH_REGULATOR_LEVEL_SUPER_TURBO 464 +#define RPMH_REGULATOR_LEVEL_SUPER_TURBO_NO_CPR 480 + #endif From patchwork Mon Jul 31 05:25:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohit Agarwal X-Patchwork-Id: 708889 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 82A40C04A94 for ; Mon, 31 Jul 2023 05:25:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229972AbjGaFZZ (ORCPT ); Mon, 31 Jul 2023 01:25:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49132 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229955AbjGaFZY (ORCPT ); Mon, 31 Jul 2023 01:25:24 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 163C2E79; Sun, 30 Jul 2023 22:25:20 -0700 (PDT) Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 36V4c47k011505; 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Mon, 31 Jul 2023 05:25:10 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 3s4uuk6gxw-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Mon, 31 Jul 2023 05:25:10 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 36V5PAiQ017584; Mon, 31 Jul 2023 05:25:10 GMT Received: from hu-sgudaval-hyd.qualcomm.com (hu-rohiagar-hyd.qualcomm.com [10.213.106.138]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 36V5PAjk017581; Mon, 31 Jul 2023 05:25:10 +0000 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3970568) id 93E4F1AA6; Mon, 31 Jul 2023 10:55:09 +0530 (+0530) From: Rohit Agarwal To: agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: cros-qcom-dts-watchers@chromium.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rohit Agarwal Subject: [PATCH 2/4] arm: dts: qcom: Add the rpmhpd header Date: Mon, 31 Jul 2023 10:55:02 +0530 Message-Id: <1690781104-2290-3-git-send-email-quic_rohiagar@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1690781104-2290-1-git-send-email-quic_rohiagar@quicinc.com> References: <1690781104-2290-1-git-send-email-quic_rohiagar@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 4ACK-CKMPXf-YT5CDwSgTzHk5FFk9L_l X-Proofpoint-ORIG-GUID: 4ACK-CKMPXf-YT5CDwSgTzHk5FFk9L_l X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-27_10,2023-07-26_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 suspectscore=0 clxscore=1015 impostorscore=0 bulkscore=0 phishscore=0 adultscore=0 mlxlogscore=302 malwarescore=0 priorityscore=1501 mlxscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2307310048 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add the rpmhpd header having the definition of the regulator levels for Qualcomm SoCs. Signed-off-by: Rohit Agarwal --- arch/arm/boot/dts/qcom/qcom-sdx55.dtsi | 1 + arch/arm/boot/dts/qcom/qcom-sdx65.dtsi | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi index df3cd9c..8ffb2a0 100644 --- a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi @@ -12,6 +12,7 @@ #include #include #include +#include #include / { diff --git a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi index 1a35830..f990f5d 100644 --- a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi @@ -11,6 +11,7 @@ #include #include #include +#include #include #include From patchwork Mon Jul 31 05:25:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohit Agarwal X-Patchwork-Id: 708502 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CE273C04FE2 for ; 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Signed-off-by: Rohit Agarwal --- arch/arm64/boot/dts/qcom/qdu1000.dtsi | 1 + arch/arm64/boot/dts/qcom/sa8775p.dtsi | 1 + arch/arm64/boot/dts/qcom/sc7180.dtsi | 1 + arch/arm64/boot/dts/qcom/sc7280.dtsi | 1 + arch/arm64/boot/dts/qcom/sc8180x.dtsi | 1 + arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 1 + arch/arm64/boot/dts/qcom/sdm670.dtsi | 1 + arch/arm64/boot/dts/qcom/sdm845.dtsi | 1 + arch/arm64/boot/dts/qcom/sm6350.dtsi | 1 + arch/arm64/boot/dts/qcom/sm8150.dtsi | 1 + arch/arm64/boot/dts/qcom/sm8250.dtsi | 1 - arch/arm64/boot/dts/qcom/sm8350.dtsi | 1 - arch/arm64/boot/dts/qcom/sm8450.dtsi | 1 - arch/arm64/boot/dts/qcom/sm8550.dtsi | 1 - 14 files changed, 10 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi index 1c0e5d2..2210447 100644 --- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include #include / { diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index b130136..a17dffdb 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -11,6 +11,7 @@ #include #include #include +#include #include / { diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index e25dc2b..ed77e04 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index a0e8db8..e35a73e 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index d3ae185..8482437 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -12,6 +12,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index ac0596d..a579716 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi index a1c207c..898831c 100644 --- a/arch/arm64/boot/dts/qcom/sdm670.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi @@ -14,6 +14,7 @@ #include #include #include +#include #include / { diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 02a6ea0..0156460 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 30e7701..46b3ea5 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -16,6 +16,7 @@ #include #include #include +#include #include / { diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 18c822a..dc75d28 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 22bf99c..fe04d25 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -15,7 +15,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index edc072e..07779c6 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -14,7 +14,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 6bd6a6c..3f86b2c 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -13,7 +13,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 59bd1c7..c316ba8 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -14,7 +14,6 @@ #include #include #include -#include #include #include #include From patchwork Mon Jul 31 05:25:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohit Agarwal X-Patchwork-Id: 708888 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 374ABC04FE1 for ; Mon, 31 Jul 2023 05:25:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229987AbjGaFZ0 (ORCPT ); Mon, 31 Jul 2023 01:25:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49136 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229962AbjGaFZY (ORCPT ); Mon, 31 Jul 2023 01:25:24 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8C954E7A; Sun, 30 Jul 2023 22:25:20 -0700 (PDT) Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 36V3ICOp026456; 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Mon, 31 Jul 2023 05:25:11 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 3s4uuk6gy8-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Mon, 31 Jul 2023 05:25:11 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 36V5PBbt017614; Mon, 31 Jul 2023 05:25:11 GMT Received: from hu-sgudaval-hyd.qualcomm.com (hu-rohiagar-hyd.qualcomm.com [10.213.106.138]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 36V5PBTW017608; Mon, 31 Jul 2023 05:25:11 +0000 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3970568) id 72A051A08; Mon, 31 Jul 2023 10:55:10 +0530 (+0530) From: Rohit Agarwal To: agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: cros-qcom-dts-watchers@chromium.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rohit Agarwal Subject: [PATCH 4/4] dt-bindings: power: qcom,rpmpd: Remove unused SoC specific bindings Date: Mon, 31 Jul 2023 10:55:04 +0530 Message-Id: <1690781104-2290-5-git-send-email-quic_rohiagar@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1690781104-2290-1-git-send-email-quic_rohiagar@quicinc.com> References: <1690781104-2290-1-git-send-email-quic_rohiagar@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: yQfSdzeQW-0KJIuJp3gUdDaabEXuJyzU X-Proofpoint-GUID: yQfSdzeQW-0KJIuJp3gUdDaabEXuJyzU X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-27_10,2023-07-26_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 bulkscore=0 phishscore=0 mlxlogscore=540 malwarescore=0 clxscore=1015 spamscore=0 priorityscore=1501 mlxscore=0 impostorscore=0 suspectscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2307310048 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Remove the unused bindings as these bindings are moved to a generic bindings defined in rpmhpd.h. Even the regulator levels are moved to rpmhpd so that new SoC need to only use rpmhpd.h. Signed-off-by: Rohit Agarwal --- include/dt-bindings/power/qcom-rpmpd.h | 84 ---------------------------------- 1 file changed, 84 deletions(-) diff --git a/include/dt-bindings/power/qcom-rpmpd.h b/include/dt-bindings/power/qcom-rpmpd.h index 83be996..6447df0 100644 --- a/include/dt-bindings/power/qcom-rpmpd.h +++ b/include/dt-bindings/power/qcom-rpmpd.h @@ -99,64 +99,6 @@ #define SA8155P_MX SM8150_MX #define SA8155P_MX_AO SM8150_MX_AO -/* SM8250 Power Domain Indexes */ -#define SM8250_CX 0 -#define SM8250_CX_AO 1 -#define SM8250_EBI 2 -#define SM8250_GFX 3 -#define SM8250_LCX 4 -#define SM8250_LMX 5 -#define SM8250_MMCX 6 -#define SM8250_MMCX_AO 7 -#define SM8250_MX 8 -#define SM8250_MX_AO 9 - -/* SM8350 Power Domain Indexes */ -#define SM8350_CX 0 -#define SM8350_CX_AO 1 -#define SM8350_EBI 2 -#define SM8350_GFX 3 -#define SM8350_LCX 4 -#define SM8350_LMX 5 -#define SM8350_MMCX 6 -#define SM8350_MMCX_AO 7 -#define SM8350_MX 8 -#define SM8350_MX_AO 9 -#define SM8350_MXC 10 -#define SM8350_MXC_AO 11 -#define SM8350_MSS 12 - -/* SM8450 Power Domain Indexes */ -#define SM8450_CX 0 -#define SM8450_CX_AO 1 -#define SM8450_EBI 2 -#define SM8450_GFX 3 -#define SM8450_LCX 4 -#define SM8450_LMX 5 -#define SM8450_MMCX 6 -#define SM8450_MMCX_AO 7 -#define SM8450_MX 8 -#define SM8450_MX_AO 9 -#define SM8450_MXC 10 -#define SM8450_MXC_AO 11 -#define SM8450_MSS 12 - -/* SM8550 Power Domain Indexes */ -#define SM8550_CX 0 -#define SM8550_CX_AO 1 -#define SM8550_EBI 2 -#define SM8550_GFX 3 -#define SM8550_LCX 4 -#define SM8550_LMX 5 -#define SM8550_MMCX 6 -#define SM8550_MMCX_AO 7 -#define SM8550_MX 8 -#define SM8550_MX_AO 9 -#define SM8550_MXC 10 -#define SM8550_MXC_AO 11 -#define SM8550_MSS 12 -#define SM8550_NSP 13 - /* QDU1000/QRU1000 Power Domain Indexes */ #define QDU1000_EBI 0 #define QDU1000_MSS 1 @@ -215,32 +157,6 @@ #define SC8280XP_QPHY 14 #define SC8280XP_XO 15 -/* SDM845 Power Domain performance levels */ -#define RPMH_REGULATOR_LEVEL_RETENTION 16 -#define RPMH_REGULATOR_LEVEL_MIN_SVS 48 -#define RPMH_REGULATOR_LEVEL_LOW_SVS_D2 52 -#define RPMH_REGULATOR_LEVEL_LOW_SVS_D1 56 -#define RPMH_REGULATOR_LEVEL_LOW_SVS_D0 60 -#define RPMH_REGULATOR_LEVEL_LOW_SVS 64 -#define RPMH_REGULATOR_LEVEL_LOW_SVS_P1 72 -#define RPMH_REGULATOR_LEVEL_LOW_SVS_L1 80 -#define RPMH_REGULATOR_LEVEL_LOW_SVS_L2 96 -#define RPMH_REGULATOR_LEVEL_SVS 128 -#define RPMH_REGULATOR_LEVEL_SVS_L0 144 -#define RPMH_REGULATOR_LEVEL_SVS_L1 192 -#define RPMH_REGULATOR_LEVEL_SVS_L2 224 -#define RPMH_REGULATOR_LEVEL_NOM 256 -#define RPMH_REGULATOR_LEVEL_NOM_L0 288 -#define RPMH_REGULATOR_LEVEL_NOM_L1 320 -#define RPMH_REGULATOR_LEVEL_NOM_L2 336 -#define RPMH_REGULATOR_LEVEL_TURBO 384 -#define RPMH_REGULATOR_LEVEL_TURBO_L0 400 -#define RPMH_REGULATOR_LEVEL_TURBO_L1 416 -#define RPMH_REGULATOR_LEVEL_TURBO_L2 432 -#define RPMH_REGULATOR_LEVEL_TURBO_L3 448 -#define RPMH_REGULATOR_LEVEL_SUPER_TURBO 464 -#define RPMH_REGULATOR_LEVEL_SUPER_TURBO_NO_CPR 480 - /* MDM9607 Power Domains */ #define MDM9607_VDDCX 0 #define MDM9607_VDDCX_AO 1