From patchwork Tue Jul 9 09:20:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 168731 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp8295220ilk; Tue, 9 Jul 2019 02:23:06 -0700 (PDT) X-Google-Smtp-Source: APXvYqxAtdpIEwBl4IqyR0A9QiKGKETOTyoTYzMGfHlh+7AcFQg38d8J0GodGW68v30/H+aDD2R7 X-Received: by 2002:a17:906:7281:: with SMTP id b1mr20718561ejl.63.1562664186384; Tue, 09 Jul 2019 02:23:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1562664186; cv=none; d=google.com; s=arc-20160816; b=IiQEoVMzmtozFaPoT9KA7Bp/VS/SaSo+Qa18Poz0EWkCTBhTnWnZQJfyx2L73CmMGW 790P78RI2/b2k4vt5dqJLWta8KQOQxP93AGO3AFy0rF1AdGx7EQ9qZO6UJjkhwjTk6Ix wryUarT+Pm24SatUR1vCvaERvby9kiYiK8S5cUGtDp/kyS2sNbaDbkS0Rpgot2MK7uQ4 xYWx83UkPumY5fFwF9yskWkoLVNP4zZ2jRE0YgAvtftHAnbo+wncwbyE7Su6m84aYhQ5 3OvmDLgErgmhP8lqdqcTgPLIjW23BErBAst/jLfca8iRFe2SDwyEy6TZNkqUlNGu0Cjr keNw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=pFoay7GNwEUZQB8Jr0UsvPyxNWVYPlqTjcJEEwVExaY=; b=p48JNBOWkxgF4Br3C01sGQl/shdQ19PNPIv5wN1ngPHK/LnXdwf7ZOihJVYvCgWjZS o9G2CJ6o9q9sAwJUVWdyWPaiyG+TP2fsdy9GjLRTPRk3yG+Rf4cpPk5L0q6Jl1vB60eI ZVN+mT8qtbeRr6QHHtWtRMBEv5ec2/qekEqJzQ1KTS9tV+CNWr5rnxmEndQUvugnBSp0 u1Mw6bfIQgVoygG1a9B+GcPzKt0YxMOmT/gc4jvNNehmwqlh+W/fggIXWIu+tQJWISg2 URlh9kXowYZ6HDjlIBtcfPjv19hKgU9bKN8875mij4dxlaU0v21MifrE2eF04dd+5bzO Ud6Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=zud4XPcZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id h18si15234503edb.3.2019.07.09.02.23.06 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 09 Jul 2019 02:23:06 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=zud4XPcZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:48076 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hkmL3-0000vT-8h for patch@linaro.org; Tue, 09 Jul 2019 05:23:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43403) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hkmJA-0006qC-Mw for qemu-devel@nongnu.org; Tue, 09 Jul 2019 05:21:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hkmJ8-0001mu-Ng for qemu-devel@nongnu.org; Tue, 09 Jul 2019 05:21:08 -0400 Received: from mail-io1-xd42.google.com ([2607:f8b0:4864:20::d42]:37371) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hkmJ8-0001mR-9q for qemu-devel@nongnu.org; Tue, 09 Jul 2019 05:21:06 -0400 Received: by mail-io1-xd42.google.com with SMTP id q22so19834010iog.4 for ; Tue, 09 Jul 2019 02:21:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=pFoay7GNwEUZQB8Jr0UsvPyxNWVYPlqTjcJEEwVExaY=; b=zud4XPcZjkg3qLwJfacPY/UrNy72sXWazemnvyWdT7kcJwisiQhcP9GCwnaLfa1KUV jQYBNRfykwriAewJCJ4CF9x0Ip3rIUioQQkLcmgnW3q5jzs+Gt8tPDruYFuegUstpxq5 ZmjM+SO9CPWFljrBCjzn1U1wi7HLy8xJIuHIS7bj02n8zPIUeCUCS4EcfGb5WbguyuK9 pU4aIMEJMGLDqFtUgXeiV904DXy1zJj27XaX1VhtQXDw+eCIzpae1uJ1YuD5Ny2PBJJO bD5AGjPAKUO2eog2p4aGd5dIEp0c7N3DuEBq8GwvNB82f40UIfHhSrvnJ5NIRLWj6V4P vqgg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=pFoay7GNwEUZQB8Jr0UsvPyxNWVYPlqTjcJEEwVExaY=; b=crmD3IKV29Tcd20lNIPntl5PJzUqKz5Fo5rthNfNyE/eK6eCDH3hBXg9VYcPKg5zPv Kxt+3zy7AwdcQbXTixtjm4R9/0sVkJzx1nP+mJf3YHSxX8hAnAZ6D4rOVfXlRrx7rirO jUBrxAS2KZm9r8RJ/FsT5hAP4pV/rrFBKe9c61PgNGyn7udg6kGL4fe/7h7UgG5RjQpY DXDRqjzTMd0bCfzZ3OjS9N/2OIOmyEcxr5RqzzP9KXvtRHYktzDlR9oYjxZ2xl+BYPYz o1neggBoB2rkVBMXipboM5ZngKlTD5K/6Hra53n5Zef/XfHwqpjRpl8VioLTJXHPi5Od NBLw== X-Gm-Message-State: APjAAAV7h70RlMkZ0zc4W4s7N0Kas5aztG7CaSPeJTh7IDhTr6K4I//x 9iXlCUrS1Ype9FFa/lexALsdbVJmjO8= X-Received: by 2002:a02:c549:: with SMTP id g9mr18876778jaj.14.1562664065166; Tue, 09 Jul 2019 02:21:05 -0700 (PDT) Received: from localhost.localdomain ([172.56.12.212]) by smtp.gmail.com with ESMTPSA id c17sm17613817ioo.82.2019.07.09.02.21.01 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Tue, 09 Jul 2019 02:21:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 9 Jul 2019 11:20:45 +0200 Message-Id: <20190709092049.13771-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190709092049.13771-1-richard.henderson@linaro.org> References: <20190709092049.13771-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::d42 Subject: [Qemu-devel] [PATCH 1/5] include/qemu/atomic.h: Add signal_barrier X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, peter.maydell@linaro.org, alex.bennee@linaro.org, pbonzini@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We have some potential race conditions vs our user-exec signal handler that will be solved with this barrier. Signed-off-by: Richard Henderson --- include/qemu/atomic.h | 11 +++++++++++ 1 file changed, 11 insertions(+) -- 2.17.1 Reviewed-by: Alex Bennée diff --git a/include/qemu/atomic.h b/include/qemu/atomic.h index a6ac188188..f9cd24c899 100644 --- a/include/qemu/atomic.h +++ b/include/qemu/atomic.h @@ -88,6 +88,13 @@ #define smp_read_barrier_depends() barrier() #endif +/* + * A signal barrier forces all pending local memory ops to be observed before + * a SIGSEGV is delivered to the *same* thread. In practice this is exactly + * the same as barrier(), but since we have the correct builtin, use it. + */ +#define signal_barrier() __atomic_signal_fence(__ATOMIC_SEQ_CST) + /* Sanity check that the size of an atomic operation isn't "overly large". * Despite the fact that e.g. i686 has 64-bit atomic operations, we do not * want to use them because we ought not need them, and this lets us do a @@ -308,6 +315,10 @@ #define smp_read_barrier_depends() barrier() #endif +#ifndef signal_barrier +#define signal_barrier() barrier() +#endif + /* These will only be atomic if the processor does the fetch or store * in a single issue memory operation */ From patchwork Tue Jul 9 09:20:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 168732 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp8296532ilk; Tue, 9 Jul 2019 02:24:31 -0700 (PDT) X-Google-Smtp-Source: APXvYqziw7yEOa6HU1nYQyWP2CO81FDWz1/GQbrkft+O7FoqnfDKDjzf0pZZKl5V6nu17zv5apXF X-Received: by 2002:a17:906:6557:: with SMTP id u23mr20047511ejn.186.1562664271296; Tue, 09 Jul 2019 02:24:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1562664271; cv=none; d=google.com; s=arc-20160816; b=blKoXnDAb+wxjasMsWjgsRfr3v1M706CEQD14Dpd0BQDTJS0NIfoNj4p+x7my6duQx l0JW3MSpJdNnfsOc/xmtgUTn9YL64EHA6nt9hW1XfD7puZnN3SVVVSxAmInR12V5EsOW +4wCRDKzt+XQIiCiUM+5DBt4dq/y/erta7Qg4TtYSwSHuykDFt8CrnFdm6ooBfuslkb/ BPphNAcnhHJgPoTlpXKOn9kYvdte5GG4bkDMD9iT4Toq833PR59Mv2M8LDICjRkiI2+X TNvZG8o2eAk77qpSnzjt+3vjKO+f/9fj7+CKGDeX8AHPFt6woYRruXmCsz64AUfaGf7U T/CQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=dbK9HyZ7CrS/6xw2w7TzA9aDBiINtJqhGyy8umr2lq4=; b=dSNhlXIAiX/zWPIX3lUvDiBZY6zCRHXRlkDJTWuOKIFFMf85FioU1AnHkNXG8v6mmk epF4xOtwPGkj3B5r61P8wMyqG3zdHqltp8Etu2UjFUo7mlANa5O8CWVAT5i/6usejS2S 33GBpu1Rn+hRA7/Fx6yeHJ3BI/aKlyoWcDlEpg041nRoLXxMKf3C3XXw16Qu+BMOzBg6 gNviLFZgM7o+XReC16N0cGbUl0p4cO0QyPb0rLPlH8S6Fo4l7M8UZXKheIqQYizQSgiC +/jtX+tWYniJdi74eQJtLGAhqxC8mF3Kl4qWGmUMWP6iu2B8eA9a6N+gMgp/rUzBGCY6 kNwA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=trkqt1kP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id s18si16811660edd.291.2019.07.09.02.24.30 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 09 Jul 2019 02:24:31 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=trkqt1kP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:48090 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hkmMQ-000351-7C for patch@linaro.org; Tue, 09 Jul 2019 05:24:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43436) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hkmJP-0006vw-2F for qemu-devel@nongnu.org; Tue, 09 Jul 2019 05:21:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hkmJG-0001rf-9u for qemu-devel@nongnu.org; Tue, 09 Jul 2019 05:21:18 -0400 Received: from mail-io1-xd42.google.com ([2607:f8b0:4864:20::d42]:36394) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hkmJE-0001qA-EI for qemu-devel@nongnu.org; Tue, 09 Jul 2019 05:21:13 -0400 Received: by mail-io1-xd42.google.com with SMTP id o9so26057535iom.3 for ; Tue, 09 Jul 2019 02:21:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=dbK9HyZ7CrS/6xw2w7TzA9aDBiINtJqhGyy8umr2lq4=; b=trkqt1kPmMKQLRaasTj1fzewMkw7nS4Js9xD9izCmpbx/j2WZV60vLcqedForf2ukm ZPz1M8D4rMxSxXdefUnLldepZhf9yuZDudjF4wL3yjqn/PCkAFx1eBDQHnT0XMn59qpX NTaBuzn3v51FX3mQMUkL75/ZwUYPSTgFpLly7ulWhOImpHgue/os9EK8jIYjTQ09HrWe j2bmM0cr4enxaXFtvbtm3J8NvZ6zqizqDU4TxhzF6nN1SNXc0Crnp5BWcdSQFRJvOUig JNtQczUvrEQZHWKS7eKnMo9RvMr527N8Ap1hSs3p81HEr/R7pmZnV/ZEFSvbs21rE/sz oHVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=dbK9HyZ7CrS/6xw2w7TzA9aDBiINtJqhGyy8umr2lq4=; b=e3r1y+u8Lzu1ny/fbiHkyLUd4RnJAqmAKQ1Fq+xrcl8Zp2Fw7DckNt+nXlUy+ozKV/ qGVG7MUC/HboEH71tdROrO/yseOS9DnZycR3IxRyeK5VeHjCM0w8B8aAoRZzWS3QhrDx NxGMjJ/v6haC7BK8JCVA54zvG+/fJu8BmUxRPi35FNqylxddqfcHOQJiCloFugw4Zypj Kz7edTnCQ8nJbGw8yDOLaazDugzVC5Uv6G+/D166rcHwZ59JkX6m/1y6lwV8AI5OClfB 7WEdcgxyQ9zKdpsNpGzgZFIGCIJnweQn2y9KtNKCTxDyVnei9nIKfsOxqdy18Xnd8AMb hJkQ== X-Gm-Message-State: APjAAAXmqIE3z7ge8SFCZJAovO5jDNktTirbdXrME7J2d0Vuk/1UOhXK JxKGGYlVj4W25gsy93Yy4Nt1HJsaXK4= X-Received: by 2002:a02:77d4:: with SMTP id g203mr21312915jac.144.1562664071412; Tue, 09 Jul 2019 02:21:11 -0700 (PDT) Received: from localhost.localdomain ([172.56.12.212]) by smtp.gmail.com with ESMTPSA id c17sm17613817ioo.82.2019.07.09.02.21.05 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Tue, 09 Jul 2019 02:21:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 9 Jul 2019 11:20:46 +0200 Message-Id: <20190709092049.13771-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190709092049.13771-1-richard.henderson@linaro.org> References: <20190709092049.13771-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::d42 Subject: [Qemu-devel] [PATCH 2/5] tcg: Introduce set/clear_helper_retaddr X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, peter.maydell@linaro.org, alex.bennee@linaro.org, pbonzini@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" At present we have a potential error in that helper_retaddr contains data for handle_cpu_signal, but we have not ensured that those stores will be scheduled properly before the operation that may fault. It might be that these races are not in practice observable, due to our use of -fno-strict-aliasing, but better safe than sorry. Adjust all of the setters of helper_retaddr. Signed-off-by: Richard Henderson --- include/exec/cpu_ldst.h | 20 +++++++++++ include/exec/cpu_ldst_useronly_template.h | 12 +++---- accel/tcg/user-exec.c | 11 +++--- target/arm/helper-a64.c | 8 ++--- target/arm/sve_helper.c | 43 +++++++++++------------ 5 files changed, 57 insertions(+), 37 deletions(-) -- 2.17.1 Reviewed-by: Alex Bennée diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index a08b11bd2c..9de8c93303 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -89,6 +89,26 @@ typedef target_ulong abi_ptr; extern __thread uintptr_t helper_retaddr; +static inline void set_helper_retaddr(uintptr_t ra) +{ + helper_retaddr = ra; + /* + * Ensure that this write is visible to the SIGSEGV handler that + * may be invoked due to a subsequent invalid memory operation. + */ + signal_barrier(); +} + +static inline void clear_helper_retaddr(void) +{ + /* + * Ensure that previous memory operations have succeeded before + * removing the data visible to the signal handler. + */ + signal_barrier(); + helper_retaddr = 0; +} + /* In user-only mode we provide only the _code and _data accessors. */ #define MEMSUFFIX _data diff --git a/include/exec/cpu_ldst_useronly_template.h b/include/exec/cpu_ldst_useronly_template.h index bc45e2b8d4..e65733f7e2 100644 --- a/include/exec/cpu_ldst_useronly_template.h +++ b/include/exec/cpu_ldst_useronly_template.h @@ -78,9 +78,9 @@ glue(glue(glue(cpu_ld, USUFFIX), MEMSUFFIX), _ra)(CPUArchState *env, uintptr_t retaddr) { RES_TYPE ret; - helper_retaddr = retaddr; + set_helper_retaddr(retaddr); ret = glue(glue(cpu_ld, USUFFIX), MEMSUFFIX)(env, ptr); - helper_retaddr = 0; + clear_helper_retaddr(); return ret; } @@ -102,9 +102,9 @@ glue(glue(glue(cpu_lds, SUFFIX), MEMSUFFIX), _ra)(CPUArchState *env, uintptr_t retaddr) { int ret; - helper_retaddr = retaddr; + set_helper_retaddr(retaddr); ret = glue(glue(cpu_lds, SUFFIX), MEMSUFFIX)(env, ptr); - helper_retaddr = 0; + clear_helper_retaddr(); return ret; } #endif @@ -128,9 +128,9 @@ glue(glue(glue(cpu_st, SUFFIX), MEMSUFFIX), _ra)(CPUArchState *env, RES_TYPE v, uintptr_t retaddr) { - helper_retaddr = retaddr; + set_helper_retaddr(retaddr); glue(glue(cpu_st, SUFFIX), MEMSUFFIX)(env, ptr, v); - helper_retaddr = 0; + clear_helper_retaddr(); } #endif diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index cb5f4b19c5..4384b59a4d 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -134,7 +134,7 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, * currently executing TB was modified and must be exited * immediately. Clear helper_retaddr for next execution. */ - helper_retaddr = 0; + clear_helper_retaddr(); cpu_exit_tb_from_sighandler(cpu, old_set); /* NORETURN */ @@ -152,7 +152,7 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, * an exception. Undo signal and retaddr state prior to longjmp. */ sigprocmask(SIG_SETMASK, old_set, NULL); - helper_retaddr = 0; + clear_helper_retaddr(); cc = CPU_GET_CLASS(cpu); access_type = is_write ? MMU_DATA_STORE : MMU_DATA_LOAD; @@ -682,14 +682,15 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr, if (unlikely(addr & (size - 1))) { cpu_loop_exit_atomic(env_cpu(env), retaddr); } - helper_retaddr = retaddr; - return g2h(addr); + void *ret = g2h(addr); + set_helper_retaddr(retaddr); + return ret; } /* Macro to call the above, with local variables from the use context. */ #define ATOMIC_MMU_DECLS do {} while (0) #define ATOMIC_MMU_LOOKUP atomic_mmu_lookup(env, addr, DATA_SIZE, GETPC()) -#define ATOMIC_MMU_CLEANUP do { helper_retaddr = 0; } while (0) +#define ATOMIC_MMU_CLEANUP do { clear_helper_retaddr(); } while (0) #define ATOMIC_NAME(X) HELPER(glue(glue(atomic_ ## X, SUFFIX), END)) #define EXTRA_ARGS diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 44e45a8037..060699b901 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -554,7 +554,7 @@ uint64_t HELPER(paired_cmpxchg64_le)(CPUARMState *env, uint64_t addr, /* ??? Enforce alignment. */ uint64_t *haddr = g2h(addr); - helper_retaddr = ra; + set_helper_retaddr(ra); o0 = ldq_le_p(haddr + 0); o1 = ldq_le_p(haddr + 1); oldv = int128_make128(o0, o1); @@ -564,7 +564,7 @@ uint64_t HELPER(paired_cmpxchg64_le)(CPUARMState *env, uint64_t addr, stq_le_p(haddr + 0, int128_getlo(newv)); stq_le_p(haddr + 1, int128_gethi(newv)); } - helper_retaddr = 0; + clear_helper_retaddr(); #else int mem_idx = cpu_mmu_index(env, false); TCGMemOpIdx oi0 = make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx); @@ -624,7 +624,7 @@ uint64_t HELPER(paired_cmpxchg64_be)(CPUARMState *env, uint64_t addr, /* ??? Enforce alignment. */ uint64_t *haddr = g2h(addr); - helper_retaddr = ra; + set_helper_retaddr(ra); o1 = ldq_be_p(haddr + 0); o0 = ldq_be_p(haddr + 1); oldv = int128_make128(o0, o1); @@ -634,7 +634,7 @@ uint64_t HELPER(paired_cmpxchg64_be)(CPUARMState *env, uint64_t addr, stq_be_p(haddr + 0, int128_gethi(newv)); stq_be_p(haddr + 1, int128_getlo(newv)); } - helper_retaddr = 0; + clear_helper_retaddr(); #else int mem_idx = cpu_mmu_index(env, false); TCGMemOpIdx oi0 = make_memop_idx(MO_BEQ | MO_ALIGN_16, mem_idx); diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index fd434c66ea..fc0c1755d2 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -4125,12 +4125,11 @@ static intptr_t max_for_page(target_ulong base, intptr_t mem_off, return MIN(split, mem_max - mem_off) + mem_off; } -static inline void set_helper_retaddr(uintptr_t ra) -{ -#ifdef CONFIG_USER_ONLY - helper_retaddr = ra; +#ifndef CONFIG_USER_ONLY +/* These are normally defined only for CONFIG_USER_ONLY in */ +static inline void set_helper_retaddr(uintptr_t ra) { } +static inline void clear_helper_retaddr(void) { } #endif -} /* * The result of tlb_vaddr_to_host for user-only is just g2h(x), @@ -4188,7 +4187,7 @@ static void sve_ld1_r(CPUARMState *env, void *vg, const target_ulong addr, if (test_host_page(host)) { mem_off = host_fn(vd, vg, host - mem_off, mem_off, mem_max); tcg_debug_assert(mem_off == mem_max); - set_helper_retaddr(0); + clear_helper_retaddr(); /* After having taken any fault, zero leading inactive elements. */ swap_memzero(vd, reg_off); return; @@ -4239,7 +4238,7 @@ static void sve_ld1_r(CPUARMState *env, void *vg, const target_ulong addr, } #endif - set_helper_retaddr(0); + clear_helper_retaddr(); memcpy(vd, &scratch, reg_max); } @@ -4312,7 +4311,7 @@ static void sve_ld2_r(CPUARMState *env, void *vg, target_ulong addr, addr += 2 * size; } while (i & 15); } - set_helper_retaddr(0); + clear_helper_retaddr(); /* Wait until all exceptions have been raised to write back. */ memcpy(&env->vfp.zregs[rd], &scratch[0], oprsz); @@ -4341,7 +4340,7 @@ static void sve_ld3_r(CPUARMState *env, void *vg, target_ulong addr, addr += 3 * size; } while (i & 15); } - set_helper_retaddr(0); + clear_helper_retaddr(); /* Wait until all exceptions have been raised to write back. */ memcpy(&env->vfp.zregs[rd], &scratch[0], oprsz); @@ -4372,7 +4371,7 @@ static void sve_ld4_r(CPUARMState *env, void *vg, target_ulong addr, addr += 4 * size; } while (i & 15); } - set_helper_retaddr(0); + clear_helper_retaddr(); /* Wait until all exceptions have been raised to write back. */ memcpy(&env->vfp.zregs[rd], &scratch[0], oprsz); @@ -4494,7 +4493,7 @@ static void sve_ldff1_r(CPUARMState *env, void *vg, const target_ulong addr, if (test_host_page(host)) { mem_off = host_fn(vd, vg, host - mem_off, mem_off, mem_max); tcg_debug_assert(mem_off == mem_max); - set_helper_retaddr(0); + clear_helper_retaddr(); /* After any fault, zero any leading inactive elements. */ swap_memzero(vd, reg_off); return; @@ -4537,7 +4536,7 @@ static void sve_ldff1_r(CPUARMState *env, void *vg, const target_ulong addr, } #endif - set_helper_retaddr(0); + clear_helper_retaddr(); record_fault(env, reg_off, reg_max); } @@ -4740,7 +4739,7 @@ static void sve_st1_r(CPUARMState *env, void *vg, target_ulong addr, addr += msize; } while (i & 15); } - set_helper_retaddr(0); + clear_helper_retaddr(); } static void sve_st2_r(CPUARMState *env, void *vg, target_ulong addr, @@ -4766,7 +4765,7 @@ static void sve_st2_r(CPUARMState *env, void *vg, target_ulong addr, addr += 2 * msize; } while (i & 15); } - set_helper_retaddr(0); + clear_helper_retaddr(); } static void sve_st3_r(CPUARMState *env, void *vg, target_ulong addr, @@ -4794,7 +4793,7 @@ static void sve_st3_r(CPUARMState *env, void *vg, target_ulong addr, addr += 3 * msize; } while (i & 15); } - set_helper_retaddr(0); + clear_helper_retaddr(); } static void sve_st4_r(CPUARMState *env, void *vg, target_ulong addr, @@ -4824,7 +4823,7 @@ static void sve_st4_r(CPUARMState *env, void *vg, target_ulong addr, addr += 4 * msize; } while (i & 15); } - set_helper_retaddr(0); + clear_helper_retaddr(); } #define DO_STN_1(N, NAME, ESIZE) \ @@ -4932,7 +4931,7 @@ static void sve_ld1_zs(CPUARMState *env, void *vd, void *vg, void *vm, i += 4, pg >>= 4; } while (i & 15); } - set_helper_retaddr(0); + clear_helper_retaddr(); /* Wait until all exceptions have been raised to write back. */ memcpy(vd, &scratch, oprsz); @@ -4955,7 +4954,7 @@ static void sve_ld1_zd(CPUARMState *env, void *vd, void *vg, void *vm, tlb_fn(env, &scratch, i * 8, base + (off << scale), oi, ra); } } - set_helper_retaddr(0); + clear_helper_retaddr(); /* Wait until all exceptions have been raised to write back. */ memcpy(vd, &scratch, oprsz * 8); @@ -5133,7 +5132,7 @@ static inline void sve_ldff1_zs(CPUARMState *env, void *vd, void *vg, void *vm, tlb_fn(env, vd, reg_off, addr, oi, ra); /* The rest of the reads will be non-faulting. */ - set_helper_retaddr(0); + clear_helper_retaddr(); } /* After any fault, zero the leading predicated false elements. */ @@ -5175,7 +5174,7 @@ static inline void sve_ldff1_zd(CPUARMState *env, void *vd, void *vg, void *vm, tlb_fn(env, vd, reg_off, addr, oi, ra); /* The rest of the reads will be non-faulting. */ - set_helper_retaddr(0); + clear_helper_retaddr(); } /* After any fault, zero the leading predicated false elements. */ @@ -5299,7 +5298,7 @@ static void sve_st1_zs(CPUARMState *env, void *vd, void *vg, void *vm, i += 4, pg >>= 4; } while (i & 15); } - set_helper_retaddr(0); + clear_helper_retaddr(); } static void sve_st1_zd(CPUARMState *env, void *vd, void *vg, void *vm, @@ -5318,7 +5317,7 @@ static void sve_st1_zd(CPUARMState *env, void *vd, void *vg, void *vm, tlb_fn(env, vd, i * 8, base + (off << scale), oi, ra); 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X-Received-From: 2607:f8b0:4864:20::d41 Subject: [Qemu-devel] [PATCH 3/5] tcg: Remove cpu_ld*_code_ra X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, peter.maydell@linaro.org, alex.bennee@linaro.org, pbonzini@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" These functions are not used, and are not usable in the context of code generation, because we never have a helper return address to pass in to them. Signed-off-by: Richard Henderson --- include/exec/cpu_ldst_useronly_template.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) -- 2.17.1 Reviewed-by: Alex Bennée diff --git a/include/exec/cpu_ldst_useronly_template.h b/include/exec/cpu_ldst_useronly_template.h index e65733f7e2..8c7a2c6cd7 100644 --- a/include/exec/cpu_ldst_useronly_template.h +++ b/include/exec/cpu_ldst_useronly_template.h @@ -72,6 +72,7 @@ glue(glue(cpu_ld, USUFFIX), MEMSUFFIX)(CPUArchState *env, abi_ptr ptr) return glue(glue(ld, USUFFIX), _p)(g2h(ptr)); } +#ifndef CODE_ACCESS static inline RES_TYPE glue(glue(glue(cpu_ld, USUFFIX), MEMSUFFIX), _ra)(CPUArchState *env, abi_ptr ptr, @@ -83,6 +84,7 @@ glue(glue(glue(cpu_ld, USUFFIX), MEMSUFFIX), _ra)(CPUArchState *env, clear_helper_retaddr(); return ret; } +#endif #if DATA_SIZE <= 2 static inline int @@ -96,6 +98,7 @@ glue(glue(cpu_lds, SUFFIX), MEMSUFFIX)(CPUArchState *env, abi_ptr ptr) return glue(glue(lds, SUFFIX), _p)(g2h(ptr)); } +#ifndef CODE_ACCESS static inline int glue(glue(glue(cpu_lds, SUFFIX), MEMSUFFIX), _ra)(CPUArchState *env, abi_ptr ptr, @@ -107,7 +110,8 @@ glue(glue(glue(cpu_lds, SUFFIX), MEMSUFFIX), _ra)(CPUArchState *env, clear_helper_retaddr(); return ret; } -#endif +#endif /* CODE_ACCESS */ +#endif /* DATA_SIZE <= 2 */ #ifndef CODE_ACCESS static inline void From patchwork Tue Jul 9 09:20:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 168734 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp8297349ilk; Tue, 9 Jul 2019 02:25:23 -0700 (PDT) X-Google-Smtp-Source: APXvYqwXOtdT5mj1C5BJGhxm7AnUNOC7Z6+F4+ChzAYn63GXmUJrK86HlNyanq4STMXE5GTaOk6j X-Received: by 2002:a50:b635:: with SMTP id b50mr24426567ede.293.1562664323413; Tue, 09 Jul 2019 02:25:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1562664323; cv=none; d=google.com; s=arc-20160816; b=056+KUCI4GdNRFa4iS5d6UeOMHn29d8Ib2QJbw3IG1PE+rpEjZJ125q4SrJH+kDdKr GjYxjS6WzkqdFc7HCBxYY6C53YCo0lKj7Iji8cXAco7v5N4K+HKw1e4AV1zpeRZbomk3 bhjNoQ+1i1TIn6y0sh9NVgYY20B4UX0fjqK7CqqoRsLaDdKTspRtJKQKv1YEx8WME+Eq 1pgljz9RHWYdeX7hNp9NDTcYFOskmYEcOPEPNaqHMQ1TsBeM0dnEkgV5whmJSV4sLhWT R7lIHLSEnDdXy5WCqcSt4cOX30GI5qWGYU59qE03/b6wByMd7ImvV25OrQgm6fMMF2am 5a0g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=RngKFqfhqHf/c/CCpGl+L7AgkqksgPe6OGO3ZGF2urY=; b=ixaJba/wlnkHqr4nduolFACiCyurTCgSEYni1JQWQPB605MQK7HeSN1FYghy/j3rQQ dFNdHpGXngiSypce00JPBP6IesFd7yuDv9XSVxwmvrAfofkpxz97LRr2TEFfhxSUSomB P7r0mqQOcXRFCBZjDcVBWSTxgAWTVD7rzflz6ElNR5jSB85MLDgezNreL/ioy5JsWOp5 ZQCg18UARO9LUOdNLF5L/1RJiB3HX31uyImhLxfMAUC6Buxh1fj+4jSiamLXV9UM//G3 Ceu/0yUaO6KOE9yTwx6E8xlbbobK1cc31TvOPkpugdt9mFM6NnuXpxjSQ1UE4fTgPVeP l2PA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=saez24hH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::d32 Subject: [Qemu-devel] [PATCH 4/5] tcg: Remove duplicate #if !defined(CODE_ACCESS) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, peter.maydell@linaro.org, alex.bennee@linaro.org, pbonzini@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This code block is already surrounded by #ifndef CODE_ACCESS. Signed-off-by: Richard Henderson --- include/exec/cpu_ldst_useronly_template.h | 2 -- 1 file changed, 2 deletions(-) -- 2.17.1 Reviewed-by: Alex Bennée diff --git a/include/exec/cpu_ldst_useronly_template.h b/include/exec/cpu_ldst_useronly_template.h index 8c7a2c6cd7..d663826ac2 100644 --- a/include/exec/cpu_ldst_useronly_template.h +++ b/include/exec/cpu_ldst_useronly_template.h @@ -118,11 +118,9 @@ static inline void glue(glue(cpu_st, SUFFIX), MEMSUFFIX)(CPUArchState *env, abi_ptr ptr, RES_TYPE v) { -#if !defined(CODE_ACCESS) trace_guest_mem_before_exec( env_cpu(env), ptr, trace_mem_build_info(SHIFT, false, MO_TE, true)); -#endif glue(glue(st, SUFFIX), _p)(g2h(ptr), v); } From patchwork Tue Jul 9 09:20:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 168735 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp8298250ilk; Tue, 9 Jul 2019 02:26:15 -0700 (PDT) X-Google-Smtp-Source: APXvYqxbvWp1cUs76XatRHuIKq3havGkP4lKoG0r4zSuXnezVzrXe+DPpKhFTcPrboQ3wG7rofhK X-Received: by 2002:a17:906:af54:: with SMTP id ly20mr15539342ejb.194.1562664375702; Tue, 09 Jul 2019 02:26:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1562664375; cv=none; d=google.com; s=arc-20160816; b=IXa0ca5JuviEFAJ1h7zJKqI31qHDf/RMbcEKCaTK4gtkk94QOSqYA5i1hvv34sR72Z BKKOGFst7qnnIe3DhYAX3Ei2o6OqQNCmY+yX12oO+E/JW7bFrBfrKsnpH6ylmvTh5nlj NCpnMzQLTiHY28aIexZj3UNLQz1dkM7Q/youZiYqZJ6dKd26+ec9nqAl58YuZQPFbr89 8fJhs2hxlFdKL20eVuWoUQ2WSHwWVbibQ73kOuHm3MRUVlhET8T+lohy7PeRvo7CM+I8 j7xzOZ4eBkUdYKBqTcj8T5floDQNvQ8jiIuIAQY+/Aqf3DBumKTcKMnZcGd00PUojaSU cCuQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=kUYtEVCtbbNfYNqyJu/DwHfi1v5PGfant7R2M4Nf9u8=; b=pOwKSTna3tNjepokU57jbDknrb4Gpe1kXlcu9OtSjJhKVrmfnz2mV0BUO9MtBLaLjp DW8n5HalDCbEwaR72B7kev/wL/3OaiNqGchx4vmtMJhFiXvVngJadGEotR6S8nXeDmdT xBFTZeirh986ttXLnjjRTT5olOWGdB/FRxF1SYmcakENSANurgAv3ASJbjCJz9A5hqTg 4QD5OcQYP0Xn9DdZrMPWGO7MuFB7r6xn21TUJSVJeuWkqVrcIRsDriaFHMv0P9c9JdoK jiFF6zV5GNaEDEcSyXy85nqQ1vJg4N+x34OkXDyqglcUSt1xpKIQXEz5Xee+3ykzwyYH q1Lw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=PXqwmcqI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id y18si11260192ejg.127.2019.07.09.02.26.15 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 09 Jul 2019 02:26:15 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=PXqwmcqI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:48100 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hkmO6-00042E-Lw for patch@linaro.org; Tue, 09 Jul 2019 05:26:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43506) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hkmJW-00072R-Oi for qemu-devel@nongnu.org; Tue, 09 Jul 2019 05:21:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hkmJV-00024Z-3t for qemu-devel@nongnu.org; Tue, 09 Jul 2019 05:21:30 -0400 Received: from mail-io1-xd44.google.com ([2607:f8b0:4864:20::d44]:34861) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hkmJS-000210-V3 for qemu-devel@nongnu.org; Tue, 09 Jul 2019 05:21:28 -0400 Received: by mail-io1-xd44.google.com with SMTP id m24so32166341ioo.2 for ; Tue, 09 Jul 2019 02:21:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=kUYtEVCtbbNfYNqyJu/DwHfi1v5PGfant7R2M4Nf9u8=; b=PXqwmcqId/ArQolYsEqS2pncOb0V2THv1ejejqPpn4Jcf0f5St0oe9uIjiBfWgC+wC 1uc6dGyI2fnLp6ywHdLzbeTXpowSV+v9RZZCeFMOsBGjNz5rkinlxeP2FHCOhVrA9jVl aPfDs3zUZhBEOHY+eOohvIsoPvaQqBTd7LE3AHCF0BVd65PCUoQYA7opghOkc6DmUuS3 zMcpjuAVr+MKUxMtHbK4opUnoE48vK1DL8vCZmd7X6YNfJBDtBLcy/s01eMWIxMwJgWl +rqZ3G8SqP6kgGxidc5nQ3v/slS5Zzd5KVM9098ehdEw8zdfDEG0B+o88vCd2BfSEFqI Y/PA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=kUYtEVCtbbNfYNqyJu/DwHfi1v5PGfant7R2M4Nf9u8=; b=PYV56qTyGNoMX11vRMFaANKPALeVrcs3pTWpiA8R/LXN2C8N3WTOc4PTSb6qE1Z8Af zarcCp3OmxeUlHCRAMwRh5HVQqE274ZxPnNNfcEQJh2L0vDIgwGLyl+ACD31KlYUVK8Z eLtYcBfvjFSxs0Z7kWWkPakZ4njR1pxitGTcXAz3fWj2Ocyua290TNu07fvWEYhhPhou SIipNs/gL33f/DpjVI6Zb7NZ0xWJLvKiCsj788VpcFOgKsHm19Dkj8at4KmLcbmqddqZ NxxFuhs0mwxeVAaIlYCiy3tq9JGIG9Qf+Kl9Yxwa3dXE/AqjJZ/ziJJ1kx83FiRz50H1 i2oQ== X-Gm-Message-State: APjAAAUaphUpire/afQkrcaYt2ScO/UZ/oiriztNeHASF96Johl12BM9 j97j1FAuNKmsiBOWrSWiG0Vh4eL6hdk= X-Received: by 2002:a02:6616:: with SMTP id k22mr27315822jac.100.1562664085043; Tue, 09 Jul 2019 02:21:25 -0700 (PDT) Received: from localhost.localdomain ([172.56.12.212]) by smtp.gmail.com with ESMTPSA id c17sm17613817ioo.82.2019.07.09.02.21.20 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Tue, 09 Jul 2019 02:21:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 9 Jul 2019 11:20:49 +0200 Message-Id: <20190709092049.13771-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190709092049.13771-1-richard.henderson@linaro.org> References: <20190709092049.13771-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::d44 Subject: [Qemu-devel] [PATCH 5/5] tcg: Release mmap_lock on translation fault X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, peter.maydell@linaro.org, alex.bennee@linaro.org, pbonzini@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Turn helper_retaddr into a multi-state flag that may now also indicate when we're performing a read on behalf of the translator. In this case, release the mmap_lock before the longjmp back to the main cpu loop, and thereby avoid a failing assert therein. Fixes: https://bugs.launchpad.net/qemu/+bug/1832353 Signed-off-by: Richard Henderson --- include/exec/cpu_ldst_useronly_template.h | 20 +++++-- accel/tcg/user-exec.c | 65 ++++++++++++++++------- 2 files changed, 62 insertions(+), 23 deletions(-) -- 2.17.1 Reviewed-by: Alex Bennée Tested-by: Alex Bennée diff --git a/include/exec/cpu_ldst_useronly_template.h b/include/exec/cpu_ldst_useronly_template.h index d663826ac2..35caae8ca6 100644 --- a/include/exec/cpu_ldst_useronly_template.h +++ b/include/exec/cpu_ldst_useronly_template.h @@ -64,12 +64,18 @@ static inline RES_TYPE glue(glue(cpu_ld, USUFFIX), MEMSUFFIX)(CPUArchState *env, abi_ptr ptr) { -#if !defined(CODE_ACCESS) +#ifdef CODE_ACCESS + RES_TYPE ret; + set_helper_retaddr(1); + ret = glue(glue(ld, USUFFIX), _p)(g2h(ptr)); + clear_helper_retaddr(); + return ret; +#else trace_guest_mem_before_exec( env_cpu(env), ptr, trace_mem_build_info(SHIFT, false, MO_TE, false)); -#endif return glue(glue(ld, USUFFIX), _p)(g2h(ptr)); +#endif } #ifndef CODE_ACCESS @@ -90,12 +96,18 @@ glue(glue(glue(cpu_ld, USUFFIX), MEMSUFFIX), _ra)(CPUArchState *env, static inline int glue(glue(cpu_lds, SUFFIX), MEMSUFFIX)(CPUArchState *env, abi_ptr ptr) { -#if !defined(CODE_ACCESS) +#ifdef CODE_ACCESS + int ret; + set_helper_retaddr(1); + ret = glue(glue(ld, USUFFIX), _p)(g2h(ptr)); + clear_helper_retaddr(); + return ret; +#else trace_guest_mem_before_exec( env_cpu(env), ptr, trace_mem_build_info(SHIFT, true, MO_TE, false)); -#endif return glue(glue(lds, SUFFIX), _p)(g2h(ptr)); +#endif } #ifndef CODE_ACCESS diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 4384b59a4d..5adea629de 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -64,27 +64,55 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, CPUState *cpu = current_cpu; CPUClass *cc; unsigned long address = (unsigned long)info->si_addr; - MMUAccessType access_type; + MMUAccessType access_type = is_write ? MMU_DATA_STORE : MMU_DATA_LOAD; - /* We must handle PC addresses from two different sources: - * a call return address and a signal frame address. - * - * Within cpu_restore_state_from_tb we assume the former and adjust - * the address by -GETPC_ADJ so that the address is within the call - * insn so that addr does not accidentally match the beginning of the - * next guest insn. - * - * However, when the PC comes from the signal frame, it points to - * the actual faulting host insn and not a call insn. Subtracting - * GETPC_ADJ in that case may accidentally match the previous guest insn. - * - * So for the later case, adjust forward to compensate for what - * will be done later by cpu_restore_state_from_tb. - */ - if (helper_retaddr) { + switch (helper_retaddr) { + default: + /* + * Fault during host memory operation within a helper function. + * The helper's host return address, saved here, gives us a + * pointer into the generated code that will unwind to the + * correct guest pc. + */ pc = helper_retaddr; - } else { + break; + + case 0: + /* + * Fault during host memory operation within generated code. + * (Or, a unrelated bug within qemu, but we can't tell from here). + * + * We take the host pc from the signal frame. However, we cannot + * use that value directly. Within cpu_restore_state_from_tb, we + * assume PC comes from GETPC(), as used by the helper functions, + * so we adjust the address by -GETPC_ADJ to form an address that + * is within the call insn, so that the address does not accidentially + * match the beginning of the next guest insn. However, when the + * pc comes fromt he signal frame it points to the actual faulting + * host memory insn and not a call insn. + * + * Therefore, adjust to compensate for what will be done later + * by cpu_restore_state_from_tb. + */ pc += GETPC_ADJ; + break; + + case 1: + /* + * Fault during host read for translation, or loosely, "execution". + * + * The guest pc is already pointing to the start of the TB for which + * code is being generated. If the guest translator manages the + * page crossings correctly, this is exactly the correct address + * (and if it doesn't there's little we can do about that here). + * Therefore, do not trigger the unwinder. + * + * Like tb_gen_code, release the memory lock before cpu_loop_exit. + */ + pc = 0; + access_type = MMU_INST_FETCH; + mmap_unlock(); + break; } /* For synchronous signals we expect to be coming from the vCPU @@ -155,7 +183,6 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info, clear_helper_retaddr(); cc = CPU_GET_CLASS(cpu); - access_type = is_write ? MMU_DATA_STORE : MMU_DATA_LOAD; cc->tlb_fill(cpu, address, 0, access_type, MMU_USER_IDX, false, pc); g_assert_not_reached(); }