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Sun, 6 Aug 2023 22:52:28 -0700 Received: from xhdradheys41.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2507.27 via Frontend Transport; Mon, 7 Aug 2023 00:52:24 -0500 From: Radhey Shyam Pandey To: , , , , , , , , , CC: , , , , , , Radhey Shyam Pandey Subject: [PATCH net-next v5 04/10] dmaengine: xilinx_dma: Increase AXI DMA transaction segment count Date: Mon, 7 Aug 2023 11:21:43 +0530 Message-ID: <1691387509-2113129-5-git-send-email-radhey.shyam.pandey@amd.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1691387509-2113129-1-git-send-email-radhey.shyam.pandey@amd.com> References: <1691387509-2113129-1-git-send-email-radhey.shyam.pandey@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D2:EE_|PH8PR12MB7326:EE_ X-MS-Office365-Filtering-Correlation-Id: 2b348bc0-c58c-4cd1-8cf7-08db970a84da X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Signed-off-by: Radhey Shyam Pandey --- Changes for v5: - New patch in this series. Just a note that dmaengine series was earlier sent as separate series[1] and now it's merged with axiethernet series[2]. [1]: https://lore.kernel.org/all/20221124102745.2620370-1-sarath.babu.naidu.gaddam@amd.com [2]: https://lore.kernel.org/all/20230630053844.1366171-1-sarath.babu.naidu.gaddam@amd.com - Switch to amd.com email address. --- drivers/dma/xilinx/xilinx_dma.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c index d526e472b905..7f3c57fbe1e3 100644 --- a/drivers/dma/xilinx/xilinx_dma.c +++ b/drivers/dma/xilinx/xilinx_dma.c @@ -178,7 +178,7 @@ #define XILINX_DMA_BD_SOP BIT(27) #define XILINX_DMA_BD_EOP BIT(26) #define XILINX_DMA_COALESCE_MAX 255 -#define XILINX_DMA_NUM_DESCS 255 +#define XILINX_DMA_NUM_DESCS 512 #define XILINX_DMA_NUM_APP_WORDS 5 /* AXI CDMA Specific Registers/Offsets */ From patchwork Mon Aug 7 05:51:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Pandey, Radhey Shyam" X-Patchwork-Id: 711345 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 83AC4C001DE for ; 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Mon, 7 Aug 2023 00:52:41 -0500 From: Radhey Shyam Pandey To: , , , , , , , , , CC: , , , , , , Radhey Shyam Pandey Subject: [PATCH net-next v5 06/10] dmaengine: xilinx_dma: Use tasklet_hi_schedule for timing critical usecase Date: Mon, 7 Aug 2023 11:21:45 +0530 Message-ID: <1691387509-2113129-7-git-send-email-radhey.shyam.pandey@amd.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1691387509-2113129-1-git-send-email-radhey.shyam.pandey@amd.com> References: <1691387509-2113129-1-git-send-email-radhey.shyam.pandey@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044EE:EE_|CY5PR12MB6526:EE_ X-MS-Office365-Filtering-Correlation-Id: 6391a4c5-f507-419e-3489-08db970a8868 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: SRZ70rxG5ykNrlUoUOA3Z5oBplZXBBWeDjdgot0YugGUruGf2Ns4QPf7eo9HMGNJqrsicLUPaZM4TzHdKohQK1MblnnyvtXCWymLqiRZF333t9NOErZYKMfUpOcUZ196tKfgEhswcP0G5jUjDjNQKeFvsEUSF0cJ7Tv6pLWH8ynrLyIty6nCDGpEXuYSnlvp52K20Gr+tmihuUKXUDwCczSTU1dWGq7jB9c1PLz7akKOjE0rG3elYSEKoaQEDEIUtVMIJFO8GfGHrcely5afrsNnEtCBRPIT+g7VfsT6Mb/0pfDj2dB611NK2BJPYJFQ3oOZs9LHRTxQ7+XaiU2mdC9yVUFQYwklYhTyeiXZiRpzYkzR8lpleF30zBihsURU8goSntkLZVx7lhKF9S3sWivU6G6tSVx7gp4POnALjw2tqaq/6QJ30fZS6oF8rL7wSdCvYPE5I8UE61squzu0aEI1arTy5HNcAx6LlyehNBSH53VK3RE7EUxGTb7QkDL5nFU2HQExMqtb5uQjephykZT0Hh07G1dJ6ZfLaumRhbJ/EUB6KED/6FaIuJJdXn+9sBVpEwyxmwxiKkuPD9LXFxOdCoksh4A6ZArAM0kvL3IS0aO4Ppbg69ubnuXdBXUJ9+KT+9aFsuDcOoStyyEfqd43XRvbxcrwPdHerTRr/MuCNL9hbcF3DdC/W2afPxRypdfBtMeSoADyAODjoHAGjOfINJwqgYwrpBbIjpXkJNEu50qa4A14wnBKHC5/cu/PHwa2bHmMlDWUUlj80a4+nwjQTEhRi2kLx68QS9VFmlji0CVy5uK5SEBcf7elSy+p X-Forefront-Antispam-Report: CIP:165.204.84.17; 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It improves throughput for netdev dma clients. Signed-off-by: Radhey Shyam Pandey --- Changes for v5: - New patch in this series. Just a note that dmaengine series was earlier sent as separate series[1] and now it's merged with axiethernet series[2]. [1]: https://lore.kernel.org/all/20221124102745.2620370-1-sarath.babu.naidu.gaddam@amd.com [2]: https://lore.kernel.org/all/20230630053844.1366171-1-sarath.babu.naidu.gaddam@amd.com - Switch to amd.com email address. --- drivers/dma/xilinx/xilinx_dma.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c index 3b721da827e0..6c1c63a38f70 100644 --- a/drivers/dma/xilinx/xilinx_dma.c +++ b/drivers/dma/xilinx/xilinx_dma.c @@ -1850,7 +1850,7 @@ static irqreturn_t xilinx_mcdma_irq_handler(int irq, void *data) spin_unlock(&chan->lock); } - tasklet_schedule(&chan->tasklet); + tasklet_hi_schedule(&chan->tasklet); return IRQ_HANDLED; } From patchwork Mon Aug 7 05:51:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Pandey, Radhey Shyam" X-Patchwork-Id: 711344 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 537E8C04A6A for ; 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Mon, 7 Aug 2023 00:52:46 -0500 From: Radhey Shyam Pandey To: , , , , , , , , , CC: , , , , , , Radhey Shyam Pandey Subject: [PATCH net-next v5 07/10] dmaengine: xilinx_dma: Program interrupt delay timeout Date: Mon, 7 Aug 2023 11:21:46 +0530 Message-ID: <1691387509-2113129-8-git-send-email-radhey.shyam.pandey@amd.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1691387509-2113129-1-git-send-email-radhey.shyam.pandey@amd.com> References: <1691387509-2113129-1-git-send-email-radhey.shyam.pandey@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044F5:EE_|DS0PR12MB8218:EE_ X-MS-Office365-Filtering-Correlation-Id: 9c558b65-d473-497b-d684-08db970a901d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: rd+gwZCgwjw7Ay2oflc8yU3V5YTx/tvaamwFbFIltpyjbvyumShHBRTeKrK+e2rSV1c0JZm63a+Ih6re3HEg4ML44snFs0oZLUfrfgwe2H7g5fDp+oTMniZ8yvgvDbnwm1f6waoiotwR9c3GdQ662xzcRqEyH0/MnA2RV3hPWYXKF0eFuvnJmyPRM4wzVUmA2bt+Lz+vpOSbCw8REKKC2GsRRN0PGD1AKbV7+Z7U8eNwRb88wzKhVwC34DKayNrBEP8AmysWe4TYYtrwFqu0f96cUiqyXdos7NOjynDw9A99RUO1wm0CgFNRznJess8W7vUJAq6r13AtINsOgpmavrs1NvLSrIeNQWOIuUvvIwohu5CAq7Mb0zhq3cTqwC1719ahvDa1Gu2a7DSGFhpFmWYWGBleLl8VzVkLiG7qDAyaK9LehV74WNPnVFfh9vk3MW3QkLoKHdVxyWtXCATSUBR3Jp3tk5L+Km3EVJv/EvLF3twvrWpZs1TzNJv8EDvOEz5IOFgKzByvzxSHg3BZi36pU/MPotT4e7TrSqoKlQLXTs5W0azoe9hYuJgQftdUr5unRS/yqpunB3wCU27/WAgxTeWSGBUm+DB9Ne5LdjCUpXglsOQF3bRI576teeZl9NmAPhLK0iMYgE4mXpkxb14rcCfcqP8Fy0cGwRUru1i36M6jzRilLznoTUxzISXShPbJt+HHrru53I8sSKP//lfkGTYzZO1LqMSv+ERxz+chcuClahwOmlnOrj4R8+T4Nn9nHo+EOBZHs61QfmR4RzxIdmLJF2WRF/aKVvSKgbIRcAh3dMXuN7Oj99MlU3c4 X-Forefront-Antispam-Report: CIP:165.204.84.17; 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The interrupt timeout mechanism causes the DMA engine to generate an interrupt after the delay time period has expired. It enables dmaengine to respond in real-time even though interrupt coalescing is configured. It also remove the placeholder for delay interrupt and merge it with frame completion interrupt. Since by default interrupt delay timeout is disabled this feature addition has no functional impact on VDMA, MCDMA and CDMA IP's. Signed-off-by: Radhey Shyam Pandey --- Changes for v5: - New patch in this series. Just a note that dmaengine series was earlier sent as separate series[1] and now it's merged with axiethernet series[2]. [1]: https://lore.kernel.org/all/20221124102745.2620370-1-sarath.babu.naidu.gaddam@amd.com [2]: https://lore.kernel.org/all/20230630053844.1366171-1-sarath.babu.naidu.gaddam@amd.com - Modified commit description to add "MCDMA" along with VDMA and CDMA IP. - Switch to amd.com email address. --- drivers/dma/xilinx/xilinx_dma.c | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c index 6c1c63a38f70..e9f70cad4934 100644 --- a/drivers/dma/xilinx/xilinx_dma.c +++ b/drivers/dma/xilinx/xilinx_dma.c @@ -173,8 +173,10 @@ #define XILINX_DMA_MAX_TRANS_LEN_MAX 23 #define XILINX_DMA_V2_MAX_TRANS_LEN_MAX 26 #define XILINX_DMA_CR_COALESCE_MAX GENMASK(23, 16) +#define XILINX_DMA_CR_DELAY_MAX GENMASK(31, 24) #define XILINX_DMA_CR_CYCLIC_BD_EN_MASK BIT(4) #define XILINX_DMA_CR_COALESCE_SHIFT 16 +#define XILINX_DMA_CR_DELAY_SHIFT 24 #define XILINX_DMA_BD_SOP BIT(27) #define XILINX_DMA_BD_EOP BIT(26) #define XILINX_DMA_BD_COMP_MASK BIT(31) @@ -411,6 +413,7 @@ struct xilinx_dma_tx_descriptor { * @stop_transfer: Differentiate b/w DMA IP's quiesce * @tdest: TDEST value for mcdma * @has_vflip: S2MM vertical flip + * @irq_delay: Interrupt delay timeout */ struct xilinx_dma_chan { struct xilinx_dma_device *xdev; @@ -449,6 +452,7 @@ struct xilinx_dma_chan { int (*stop_transfer)(struct xilinx_dma_chan *chan); u16 tdest; bool has_vflip; + u8 irq_delay; }; /** @@ -1561,6 +1565,9 @@ static void xilinx_dma_start_transfer(struct xilinx_dma_chan *chan) if (chan->has_sg) xilinx_write(chan, XILINX_DMA_REG_CURDESC, head_desc->async_tx.phys); + reg &= ~XILINX_DMA_CR_DELAY_MAX; + reg |= chan->irq_delay << XILINX_DMA_CR_DELAY_SHIFT; + dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg); xilinx_dma_start(chan); @@ -1898,15 +1905,8 @@ static irqreturn_t xilinx_dma_irq_handler(int irq, void *data) } } - if (status & XILINX_DMA_DMASR_DLY_CNT_IRQ) { - /* - * Device takes too long to do the transfer when user requires - * responsiveness. - */ - dev_dbg(chan->dev, "Inter-packet latency too long\n"); - } - - if (status & XILINX_DMA_DMASR_FRM_CNT_IRQ) { + if (status & (XILINX_DMA_DMASR_FRM_CNT_IRQ | + XILINX_DMA_DMASR_DLY_CNT_IRQ)) { spin_lock(&chan->lock); xilinx_dma_complete_descriptor(chan); chan->idle = true; @@ -2833,6 +2833,8 @@ static int xilinx_dma_chan_probe(struct xilinx_dma_device *xdev, /* Retrieve the channel properties from the device tree */ has_dre = of_property_read_bool(node, "xlnx,include-dre"); + of_property_read_u8(node, "xlnx,irq-delay", &chan->irq_delay); + chan->genlock = of_property_read_bool(node, "xlnx,genlock-mode"); err = of_property_read_u32(node, "xlnx,datawidth", &value); From patchwork Mon Aug 7 05:51:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Pandey, Radhey Shyam" X-Patchwork-Id: 711343 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7966AC001DE for ; Mon, 7 Aug 2023 05:55:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230465AbjHGFzw (ORCPT ); Mon, 7 Aug 2023 01:55:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56042 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229947AbjHGFzu (ORCPT ); Mon, 7 Aug 2023 01:55:50 -0400 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2079.outbound.protection.outlook.com [40.107.94.79]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7C9691989; 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Mon, 7 Aug 2023 00:53:39 -0500 From: Radhey Shyam Pandey To: , , , , , , , , , CC: , , , , , , Sarath Babu Naidu Gaddam , Radhey Shyam Pandey Subject: [PATCH net-next v5 09/10] net: axienet: Preparatory changes for dmaengine support Date: Mon, 7 Aug 2023 11:21:48 +0530 Message-ID: <1691387509-2113129-10-git-send-email-radhey.shyam.pandey@amd.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1691387509-2113129-1-git-send-email-radhey.shyam.pandey@amd.com> References: <1691387509-2113129-1-git-send-email-radhey.shyam.pandey@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002529E:EE_|SA1PR12MB6993:EE_ X-MS-Office365-Filtering-Correlation-Id: 43845fcf-756c-4a3e-de1e-08db970ab737 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: nsuv0rdP86pRvFIqXiZob5EsOq6isF2zskIPHErARc/HrRE0K05bKPdRCVIVDyPKB5Qs/A8fdjR/1g1nzE/XYhMsjn8bwvWvwot4s+zsszAI420MNf/2BdWmr4sg9zuPDs2b9biL1Mt2A+5dGx7BTktbDBwGKJj1ikGKO0kDToNCi+KCSgTQO9/1iLpeFcpMvIxPlUqnM+2oviHvIqIriEclySMmy1qDfHhz2Ei3m9zyTJeVPjBdQ/YrVXfvAV8okcDMdZlwXxzMlG74hEoV9Mc/hntPxSbMjwnQ0TZI+Ym7R41hIKQS5PYbgNuMX1rxF30GF9wUOaW/Cn9MgOJ6iKPSgUjOSnPGx3mif4c1axEfVu7VYAKF4S5IpXiC8rlNUaqQql6iy4gQjaOp3pRSL/lIQi0Nq1slDiFcYZXFU/2VFxea8Hsn6AlaAaHLvPmDkH9m1rGs3qFW/9+oHF3T++j5vQh1FL0MKm7oa2xkdMX9926yBEEL5mo2kzejyXCwf9KCNxMDe1yja4ZxZCWkbweTjPQoZpUyd+KpLyAoesogTpH+QgfJia6vz8gxbl8/H9oGtrLXD1P030csmVdak2u/GwMLNQwLiqz0ig0/DkHBlGcvRqJ5XPAUd/hLxOdRdwNmnWgG4X8cehnt16Isf9g49dwgLBF//WyJ+LHBOLlKrBiHiVy5Ks6X6Z7hm21kcR4Ag2qOHHcSYOvis7q46WsqznfbMlVUJUiPfprwvZi8g6Qa8F6GBzDmGR4IG6bP4A5Hshi8VfSj230YbwadYbMZzXTBzpWjd/wadFnHqRE= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230028)(4636009)(136003)(376002)(39860400002)(346002)(396003)(186006)(1800799003)(451199021)(82310400008)(40470700004)(46966006)(36840700001)(47076005)(4326008)(2906002)(70206006)(70586007)(336012)(6666004)(83380400001)(5660300002)(36860700001)(7416002)(41300700001)(8936002)(316002)(8676002)(30864003)(40480700001)(81166007)(921005)(356005)(2616005)(54906003)(110136005)(426003)(478600001)(82740400003)(36756003)(26005)(86362001)(40460700003)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Aug 2023 05:54:08.1791 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 43845fcf-756c-4a3e-de1e-08db970ab737 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002529E.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB6993 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Sarath Babu Naidu Gaddam The axiethernet driver has inbuilt dma programming. In order to add dmaengine support and make it's integration seamless the current axidma inbuilt programming code is put under use_dmaengine check. It also performs minor code reordering to minimize conditional use_dmaengine checks and there is no functional change. It uses "dmas" property to identify whether it should use a dmaengine framework or inbuilt axidma programming. Signed-off-by: Sarath Babu Naidu Gaddam Signed-off-by: Radhey Shyam Pandey --- Changes for v5: - Fix git apply failure due to commit f1bc9fc4a06de0108e0dca2a9a7e99ba1fc632f9 Changes for v4: - Renamed has_dmas to use_dmaegine. - Removed the AXIENET_USE_DMA. - Changed the start_xmit_** functions description. Changes for v3: - New patch --- drivers/net/ethernet/xilinx/xilinx_axienet.h | 2 + .../net/ethernet/xilinx/xilinx_axienet_main.c | 313 +++++++++++------- 2 files changed, 188 insertions(+), 127 deletions(-) diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet.h b/drivers/net/ethernet/xilinx/xilinx_axienet.h index 575ff9de8985..3ead0bac597b 100644 --- a/drivers/net/ethernet/xilinx/xilinx_axienet.h +++ b/drivers/net/ethernet/xilinx/xilinx_axienet.h @@ -435,6 +435,7 @@ struct axidma_bd { * @coalesce_usec_rx: IRQ coalesce delay for RX * @coalesce_count_tx: Store the irq coalesce on TX side. * @coalesce_usec_tx: IRQ coalesce delay for TX + * @use_dmaengine: flag to check dmaengine framework usage. */ struct axienet_local { struct net_device *ndev; @@ -499,6 +500,7 @@ struct axienet_local { u32 coalesce_usec_rx; u32 coalesce_count_tx; u32 coalesce_usec_tx; + u8 use_dmaengine; }; /** diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c index 8e32dc50a408..36c77248a55e 100644 --- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c +++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c @@ -588,10 +588,6 @@ static int axienet_device_reset(struct net_device *ndev) struct axienet_local *lp = netdev_priv(ndev); int ret; - ret = __axienet_device_reset(lp); - if (ret) - return ret; - lp->max_frm_size = XAE_MAX_VLAN_FRAME_SIZE; lp->options |= XAE_OPTION_VLAN; lp->options &= (~XAE_OPTION_JUMBO); @@ -605,11 +601,17 @@ static int axienet_device_reset(struct net_device *ndev) lp->options |= XAE_OPTION_JUMBO; } - ret = axienet_dma_bd_init(ndev); - if (ret) { - netdev_err(ndev, "%s: descriptor allocation failed\n", - __func__); - return ret; + if (!lp->use_dmaengine) { + ret = __axienet_device_reset(lp); + if (ret) + return ret; + + ret = axienet_dma_bd_init(ndev); + if (ret) { + netdev_err(ndev, "%s: descriptor allocation failed\n", + __func__); + return ret; + } } axienet_status = axienet_ior(lp, XAE_RCW1_OFFSET); @@ -775,20 +777,20 @@ static int axienet_tx_poll(struct napi_struct *napi, int budget) } /** - * axienet_start_xmit - Starts the transmission. + * axienet_start_xmit_legacy - Starts the transmission. * @skb: sk_buff pointer that contains data to be Txed. * @ndev: Pointer to net_device structure. * * Return: NETDEV_TX_OK, on success * NETDEV_TX_BUSY, if any of the descriptors are not free * - * This function is invoked from upper layers to initiate transmission. The + * This function is invoked from axienet_start_xmit to initiate transmission. The * function uses the next available free BDs and populates their fields to * start the transmission. Additionally if checksum offloading is supported, * it populates AXI Stream Control fields with appropriate values. */ static netdev_tx_t -axienet_start_xmit(struct sk_buff *skb, struct net_device *ndev) +axienet_start_xmit_legacy(struct sk_buff *skb, struct net_device *ndev) { u32 ii; u32 num_frag; @@ -890,6 +892,27 @@ axienet_start_xmit(struct sk_buff *skb, struct net_device *ndev) return NETDEV_TX_OK; } +/** + * axienet_start_xmit - Invoke the transmission function + * @skb: sk_buff pointer that contains data to be Txed. + * @ndev: Pointer to net_device structure. + * + * Return: NETDEV_TX_OK, on success + * NETDEV_TX_BUSY, if any of the descriptors are not free + * + * This function is invoked from upper layers to initiate transmission + */ +static netdev_tx_t +axienet_start_xmit(struct sk_buff *skb, struct net_device *ndev) +{ + struct axienet_local *lp = netdev_priv(ndev); + + if (!lp->use_dmaengine) + return axienet_start_xmit_legacy(skb, ndev); + else + return NETDEV_TX_BUSY; +} + /** * axienet_rx_poll - Triggered by RX ISR to complete the BD processing. * @napi: Pointer to NAPI structure. @@ -1124,41 +1147,22 @@ static irqreturn_t axienet_eth_irq(int irq, void *_ndev) static void axienet_dma_err_handler(struct work_struct *work); /** - * axienet_open - Driver open routine. - * @ndev: Pointer to net_device structure + * axienet_init_legacy_dma - init the dma legacy code. + * @ndev: Pointer to net_device structure * * Return: 0, on success. - * non-zero error value on failure + * non-zero error value on failure + * + * This is the dma initialization code. It also allocates interrupt + * service routines, enables the interrupt lines and ISR handling. * - * This is the driver open routine. It calls phylink_start to start the - * PHY device. - * It also allocates interrupt service routines, enables the interrupt lines - * and ISR handling. Axi Ethernet core is reset through Axi DMA core. Buffer - * descriptors are initialized. */ -static int axienet_open(struct net_device *ndev) + +static inline int axienet_init_legacy_dma(struct net_device *ndev) { int ret; struct axienet_local *lp = netdev_priv(ndev); - dev_dbg(&ndev->dev, "axienet_open()\n"); - - /* When we do an Axi Ethernet reset, it resets the complete core - * including the MDIO. MDIO must be disabled before resetting. - * Hold MDIO bus lock to avoid MDIO accesses during the reset. - */ - axienet_lock_mii(lp); - ret = axienet_device_reset(ndev); - axienet_unlock_mii(lp); - - ret = phylink_of_phy_connect(lp->phylink, lp->dev->of_node, 0); - if (ret) { - dev_err(lp->dev, "phylink_of_phy_connect() failed: %d\n", ret); - return ret; - } - - phylink_start(lp->phylink); - /* Enable worker thread for Axi DMA error handling */ INIT_WORK(&lp->dma_err_task, axienet_dma_err_handler); @@ -1192,13 +1196,62 @@ static int axienet_open(struct net_device *ndev) err_tx_irq: napi_disable(&lp->napi_tx); napi_disable(&lp->napi_rx); - phylink_stop(lp->phylink); - phylink_disconnect_phy(lp->phylink); cancel_work_sync(&lp->dma_err_task); dev_err(lp->dev, "request_irq() failed\n"); return ret; } +/** + * axienet_open - Driver open routine. + * @ndev: Pointer to net_device structure + * + * Return: 0, on success. + * non-zero error value on failure + * + * This is the driver open routine. It calls phylink_start to start the + * PHY device. + * It also allocates interrupt service routines, enables the interrupt lines + * and ISR handling. Axi Ethernet core is reset through Axi DMA core. Buffer + * descriptors are initialized. + */ +static int axienet_open(struct net_device *ndev) +{ + int ret; + struct axienet_local *lp = netdev_priv(ndev); + + dev_dbg(&ndev->dev, "%s\n", __func__); + + /* When we do an Axi Ethernet reset, it resets the complete core + * including the MDIO. MDIO must be disabled before resetting. + * Hold MDIO bus lock to avoid MDIO accesses during the reset. + */ + axienet_lock_mii(lp); + ret = axienet_device_reset(ndev); + axienet_unlock_mii(lp); + + ret = phylink_of_phy_connect(lp->phylink, lp->dev->of_node, 0); + if (ret) { + dev_err(lp->dev, "phylink_of_phy_connect() failed: %d\n", ret); + return ret; + } + + phylink_start(lp->phylink); + + if (!lp->use_dmaengine) { + ret = axienet_init_legacy_dma(ndev); + if (ret) + goto error_code; + } + + return 0; + +error_code: + phylink_stop(lp->phylink); + phylink_disconnect_phy(lp->phylink); + + return ret; +} + /** * axienet_stop - Driver stop routine. * @ndev: Pointer to net_device structure @@ -1215,8 +1268,10 @@ static int axienet_stop(struct net_device *ndev) dev_dbg(&ndev->dev, "axienet_close()\n"); - napi_disable(&lp->napi_tx); - napi_disable(&lp->napi_rx); + if (!lp->use_dmaengine) { + napi_disable(&lp->napi_tx); + napi_disable(&lp->napi_rx); + } phylink_stop(lp->phylink); phylink_disconnect_phy(lp->phylink); @@ -1224,18 +1279,18 @@ static int axienet_stop(struct net_device *ndev) axienet_setoptions(ndev, lp->options & ~(XAE_OPTION_TXEN | XAE_OPTION_RXEN)); - axienet_dma_stop(lp); + if (!lp->use_dmaengine) { + axienet_dma_stop(lp); + cancel_work_sync(&lp->dma_err_task); + free_irq(lp->tx_irq, ndev); + free_irq(lp->rx_irq, ndev); + axienet_dma_bd_release(ndev); + } axienet_iow(lp, XAE_IE_OFFSET, 0); - cancel_work_sync(&lp->dma_err_task); - if (lp->eth_irq > 0) free_irq(lp->eth_irq, ndev); - free_irq(lp->tx_irq, ndev); - free_irq(lp->rx_irq, ndev); - - axienet_dma_bd_release(ndev); return 0; } @@ -1411,14 +1466,16 @@ static void axienet_ethtools_get_regs(struct net_device *ndev, data[29] = axienet_ior(lp, XAE_FMI_OFFSET); data[30] = axienet_ior(lp, XAE_AF0_OFFSET); data[31] = axienet_ior(lp, XAE_AF1_OFFSET); - data[32] = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET); - data[33] = axienet_dma_in32(lp, XAXIDMA_TX_SR_OFFSET); - data[34] = axienet_dma_in32(lp, XAXIDMA_TX_CDESC_OFFSET); - data[35] = axienet_dma_in32(lp, XAXIDMA_TX_TDESC_OFFSET); - data[36] = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET); - data[37] = axienet_dma_in32(lp, XAXIDMA_RX_SR_OFFSET); - data[38] = axienet_dma_in32(lp, XAXIDMA_RX_CDESC_OFFSET); - data[39] = axienet_dma_in32(lp, XAXIDMA_RX_TDESC_OFFSET); + if (!lp->use_dmaengine) { + data[32] = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET); + data[33] = axienet_dma_in32(lp, XAXIDMA_TX_SR_OFFSET); + data[34] = axienet_dma_in32(lp, XAXIDMA_TX_CDESC_OFFSET); + data[35] = axienet_dma_in32(lp, XAXIDMA_TX_TDESC_OFFSET); + data[36] = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET); + data[37] = axienet_dma_in32(lp, XAXIDMA_RX_SR_OFFSET); + data[38] = axienet_dma_in32(lp, XAXIDMA_RX_CDESC_OFFSET); + data[39] = axienet_dma_in32(lp, XAXIDMA_RX_TDESC_OFFSET); + } } static void @@ -1879,9 +1936,6 @@ static int axienet_probe(struct platform_device *pdev) u64_stats_init(&lp->rx_stat_sync); u64_stats_init(&lp->tx_stat_sync); - netif_napi_add(ndev, &lp->napi_rx, axienet_rx_poll); - netif_napi_add(ndev, &lp->napi_tx, axienet_tx_poll); - lp->axi_clk = devm_clk_get_optional(&pdev->dev, "s_axi_lite_clk"); if (!lp->axi_clk) { /* For backward compatibility, if named AXI clock is not present, @@ -2007,80 +2061,85 @@ static int axienet_probe(struct platform_device *pdev) goto cleanup_clk; } - /* Find the DMA node, map the DMA registers, and decode the DMA IRQs */ - np = of_parse_phandle(pdev->dev.of_node, "axistream-connected", 0); - if (np) { - struct resource dmares; + if (!of_find_property(pdev->dev.of_node, "dmas", NULL)) { + /* Find the DMA node, map the DMA registers, and decode the DMA IRQs */ + np = of_parse_phandle(pdev->dev.of_node, "axistream-connected", 0); - ret = of_address_to_resource(np, 0, &dmares); - if (ret) { - dev_err(&pdev->dev, - "unable to get DMA resource\n"); + if (np) { + struct resource dmares; + + ret = of_address_to_resource(np, 0, &dmares); + if (ret) { + dev_err(&pdev->dev, + "unable to get DMA resource\n"); + of_node_put(np); + goto cleanup_clk; + } + lp->dma_regs = devm_ioremap_resource(&pdev->dev, + &dmares); + lp->rx_irq = irq_of_parse_and_map(np, 1); + lp->tx_irq = irq_of_parse_and_map(np, 0); of_node_put(np); + lp->eth_irq = platform_get_irq_optional(pdev, 0); + } else { + /* Check for these resources directly on the Ethernet node. */ + lp->dma_regs = devm_platform_get_and_ioremap_resource(pdev, 1, NULL); + lp->rx_irq = platform_get_irq(pdev, 1); + lp->tx_irq = platform_get_irq(pdev, 0); + lp->eth_irq = platform_get_irq_optional(pdev, 2); + } + if (IS_ERR(lp->dma_regs)) { + dev_err(&pdev->dev, "could not map DMA regs\n"); + ret = PTR_ERR(lp->dma_regs); + goto cleanup_clk; + } + if (lp->rx_irq <= 0 || lp->tx_irq <= 0) { + dev_err(&pdev->dev, "could not determine irqs\n"); + ret = -ENOMEM; goto cleanup_clk; } - lp->dma_regs = devm_ioremap_resource(&pdev->dev, - &dmares); - lp->rx_irq = irq_of_parse_and_map(np, 1); - lp->tx_irq = irq_of_parse_and_map(np, 0); - of_node_put(np); - lp->eth_irq = platform_get_irq_optional(pdev, 0); - } else { - /* Check for these resources directly on the Ethernet node. */ - lp->dma_regs = devm_platform_get_and_ioremap_resource(pdev, 1, NULL); - lp->rx_irq = platform_get_irq(pdev, 1); - lp->tx_irq = platform_get_irq(pdev, 0); - lp->eth_irq = platform_get_irq_optional(pdev, 2); - } - if (IS_ERR(lp->dma_regs)) { - dev_err(&pdev->dev, "could not map DMA regs\n"); - ret = PTR_ERR(lp->dma_regs); - goto cleanup_clk; - } - if ((lp->rx_irq <= 0) || (lp->tx_irq <= 0)) { - dev_err(&pdev->dev, "could not determine irqs\n"); - ret = -ENOMEM; - goto cleanup_clk; - } - /* Reset core now that clocks are enabled, prior to accessing MDIO */ - ret = __axienet_device_reset(lp); - if (ret) - goto cleanup_clk; + /* Reset core now that clocks are enabled, prior to accessing MDIO */ + ret = __axienet_device_reset(lp); + if (ret) + goto cleanup_clk; + + /* Autodetect the need for 64-bit DMA pointers. + * When the IP is configured for a bus width bigger than 32 bits, + * writing the MSB registers is mandatory, even if they are all 0. + * We can detect this case by writing all 1's to one such register + * and see if that sticks: when the IP is configured for 32 bits + * only, those registers are RES0. + * Those MSB registers were introduced in IP v7.1, which we check first. + */ + if ((axienet_ior(lp, XAE_ID_OFFSET) >> 24) >= 0x9) { + void __iomem *desc = lp->dma_regs + XAXIDMA_TX_CDESC_OFFSET + 4; - /* Autodetect the need for 64-bit DMA pointers. - * When the IP is configured for a bus width bigger than 32 bits, - * writing the MSB registers is mandatory, even if they are all 0. - * We can detect this case by writing all 1's to one such register - * and see if that sticks: when the IP is configured for 32 bits - * only, those registers are RES0. - * Those MSB registers were introduced in IP v7.1, which we check first. - */ - if ((axienet_ior(lp, XAE_ID_OFFSET) >> 24) >= 0x9) { - void __iomem *desc = lp->dma_regs + XAXIDMA_TX_CDESC_OFFSET + 4; - - iowrite32(0x0, desc); - if (ioread32(desc) == 0) { /* sanity check */ - iowrite32(0xffffffff, desc); - if (ioread32(desc) > 0) { - lp->features |= XAE_FEATURE_DMA_64BIT; - addr_width = 64; - dev_info(&pdev->dev, - "autodetected 64-bit DMA range\n"); - } iowrite32(0x0, desc); + if (ioread32(desc) == 0) { /* sanity check */ + iowrite32(0xffffffff, desc); + if (ioread32(desc) > 0) { + lp->features |= XAE_FEATURE_DMA_64BIT; + addr_width = 64; + dev_info(&pdev->dev, + "autodetected 64-bit DMA range\n"); + } + iowrite32(0x0, desc); + } + } + if (!IS_ENABLED(CONFIG_64BIT) && lp->features & XAE_FEATURE_DMA_64BIT) { + dev_err(&pdev->dev, "64-bit addressable DMA is not compatible with 32-bit archecture\n"); + ret = -EINVAL; + goto cleanup_clk; } - } - if (!IS_ENABLED(CONFIG_64BIT) && lp->features & XAE_FEATURE_DMA_64BIT) { - dev_err(&pdev->dev, "64-bit addressable DMA is not compatible with 32-bit archecture\n"); - ret = -EINVAL; - goto cleanup_clk; - } - ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(addr_width)); - if (ret) { - dev_err(&pdev->dev, "No suitable DMA available\n"); - goto cleanup_clk; + ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(addr_width)); + if (ret) { + dev_err(&pdev->dev, "No suitable DMA available\n"); + goto cleanup_clk; + } + netif_napi_add(ndev, &lp->napi_rx, axienet_rx_poll); + netif_napi_add(ndev, &lp->napi_tx, axienet_tx_poll); } /* Check for Ethernet core IRQ (optional) */ @@ -2098,8 +2157,8 @@ static int axienet_probe(struct platform_device *pdev) } lp->coalesce_count_rx = XAXIDMA_DFT_RX_THRESHOLD; - lp->coalesce_usec_rx = XAXIDMA_DFT_RX_USEC; lp->coalesce_count_tx = XAXIDMA_DFT_TX_THRESHOLD; + lp->coalesce_usec_rx = XAXIDMA_DFT_RX_USEC; lp->coalesce_usec_tx = XAXIDMA_DFT_TX_USEC; ret = axienet_mdio_setup(lp);