From patchwork Fri Jul 12 05:27:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 168860 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp394226ilk; Thu, 11 Jul 2019 22:29:02 -0700 (PDT) X-Google-Smtp-Source: APXvYqxGhexWvz9obc2d9UTMWjgHNvpZgdhBaNInVfU/9ebhIQDjd9Nj/V/loTeiySVS4Y86eXhG X-Received: by 2002:a63:2323:: with SMTP id j35mr8619136pgj.166.1562909342800; Thu, 11 Jul 2019 22:29:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1562909342; cv=none; d=google.com; s=arc-20160816; b=B4FW2GIyuVz56L6bsPeWGCyuuMMwz5ofz07SQb8WXUpImUzMtO748yQ/OuTjtD8kvz RD7wWh5yJvKkdFL5f74/KOzh33uzCXRghZPJlCR1sYIC7jG2F1kceJYFRnvdJD3FrkcT nqc8MhOMy3xikZLIAlIPcL8goP5TqM54enwxqVqpmaIxjkNksXqBVlyso/smnT7x/LcT zZjMtZbz6x5/GsmNpuS3nmBpOafAdCWbCSKI09i5NyCi9bVz8CvJr4uALFqg10GSibl3 N5P3AWSOTPy1GLjT54oX2+jP1kgL+bSKKlAw0uH1MVjC8yqQlfj2+jw5HQPTWcI0mc3b 6VpA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=t+8ZINgorfc9/vHqnYTLmiCH63MmZJ4ah1lcUclNBnY=; b=ylfhCLsuyx8izj0SWc+qh/AcsmLN/ld013WdxxDC4rEKAzMiBAUGhIAclD0lpwpjtY 6lBWzC7ab230yxrWy+nclruWulGEYpmZLrSupCUZ9cFeHrNyH/PkAt7Ewvc6C5wkToNk 0Zys6kTe7ueCTWm3QMWgyu6aVYGJDLB4zomDX5t/eAkKJRdNsXJ15QxhbXOs149RfOZP 8ussEHQOL9qSlbc3NXnTXYzs/Zmn3v3FWXBC0jaq8+F9TGltWdMCZiaOHCVq5anP/X9a LR8tULyN45NMQYWxb4b+5qHuilYGyxMRwil2Mdo9RGpTCQaCQM89u711FY3ewotk3+jm bi/Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vfEescdr; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e36si5303191pgm.17.2019.07.11.22.29.02; Thu, 11 Jul 2019 22:29:02 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vfEescdr; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725974AbfGLF3C (ORCPT + 13 others); Fri, 12 Jul 2019 01:29:02 -0400 Received: from mail-pl1-f196.google.com ([209.85.214.196]:45455 "EHLO mail-pl1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725791AbfGLF3C (ORCPT ); Fri, 12 Jul 2019 01:29:02 -0400 Received: by mail-pl1-f196.google.com with SMTP id y8so4188836plr.12 for ; Thu, 11 Jul 2019 22:29:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=t+8ZINgorfc9/vHqnYTLmiCH63MmZJ4ah1lcUclNBnY=; b=vfEescdrZk7PAf9yh6XRXZTOpIl94QL0p7zhy0G6HKN/L7stQNe0GsU83l1vABWalR 40VfcXPgBqpZUStl85FVtb6u/dee46kXlWli0J8BZJMc/renFQMKfN3432e0Oms2ll51 pytAaRdD5CFCthBLyq98D+cP1UBigqqFmAdgmKh1ceFPIVWWHQqCx1KlzrTb2n7DsfU3 NyK/2R2NVZXGHW7UREDpV2hTAOEJudmW8ho0hO1AB0/3ZNHTvMsiatNstJWM63A2mrWN RabQ7GQclnS5EVa/l/thl+giSH96sRyalPlp+7465G1t7yNFinTicVk75JqPNPn9cIaj pYyw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=t+8ZINgorfc9/vHqnYTLmiCH63MmZJ4ah1lcUclNBnY=; b=aoLker4Mpjbz1Iqt4MRYaLqEN3rrjPWZQpH4DXW46k8lDdK0yOWF+KeAKGItnSOdWc iSXbfxqeNHeRx9Ye3J9YIxUO/3sCq88l62EcTp0fC3um5nGxxfaiKoAn18upNMCI0Dju lqIEecBNZySSjAvhfNxl5c+IIwzRMGsBTWrMVK4i4fIoWaLOEYOyelhoL28Uzj4Fjba1 Pm0ZBI7ffqFdYGzwcWGRsAd33oiDNFK/QuL8KFAbShgxLrshOaj4J2q0Py5sr/z7INQS hz1SGW7egoOBPQPhMavHP6SFdYzhLNDJKnpaHqbVZYBV01RcGA3ieStyT/lit2UJo6ua cLKw== X-Gm-Message-State: APjAAAWzGI55evmwVTwCoZz1WhDCrBrMhbHqEYeV1Uwzvlnco3yyZzre fcB7sJlWm8Ztt34az7iOVDg4k/p3s4s= X-Received: by 2002:a17:902:2869:: with SMTP id e96mr8804681plb.203.1562909341172; Thu, 11 Jul 2019 22:29:01 -0700 (PDT) Received: from localhost ([122.172.28.117]) by smtp.gmail.com with ESMTPSA id l31sm13056963pgm.63.2019.07.11.22.29.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 11 Jul 2019 22:29:00 -0700 (PDT) From: Viresh Kumar To: stable@vger.kernel.org, Julien Thierry Cc: Viresh Kumar , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Marc Zyngier , Mark Rutland , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: [PATCH v4.4 V2 01/43] arm64: barrier: Add CSDB macros to control data-value prediction Date: Fri, 12 Jul 2019 10:57:49 +0530 Message-Id: X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Will Deacon commit 669474e772b952b14f4de4845a1558fd4c0414a4 upstream. For CPUs capable of data value prediction, CSDB waits for any outstanding predictions to architecturally resolve before allowing speculative execution to continue. Provide macros to expose it to the arch code. Reviewed-by: Mark Rutland Signed-off-by: Will Deacon Signed-off-by: Catalin Marinas Signed-off-by: Viresh Kumar --- arch/arm64/include/asm/assembler.h | 7 +++++++ arch/arm64/include/asm/barrier.h | 2 ++ 2 files changed, 9 insertions(+) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h index f68abb17aa4b..683c2875278f 100644 --- a/arch/arm64/include/asm/assembler.h +++ b/arch/arm64/include/asm/assembler.h @@ -95,6 +95,13 @@ dmb \opt .endm +/* + * Value prediction barrier + */ + .macro csdb + hint #20 + .endm + #define USER(l, x...) \ 9999: x; \ .section __ex_table,"a"; \ diff --git a/arch/arm64/include/asm/barrier.h b/arch/arm64/include/asm/barrier.h index f2d2c0bbe21b..574486634c62 100644 --- a/arch/arm64/include/asm/barrier.h +++ b/arch/arm64/include/asm/barrier.h @@ -28,6 +28,8 @@ #define dmb(opt) asm volatile("dmb " #opt : : : "memory") #define dsb(opt) asm volatile("dsb " #opt : : : "memory") +#define csdb() asm volatile("hint #20" : : : "memory") + #define mb() dsb(sy) #define rmb() dsb(ld) #define wmb() dsb(st) From patchwork Fri Jul 12 05:27:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 168861 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp394268ilk; Thu, 11 Jul 2019 22:29:05 -0700 (PDT) X-Google-Smtp-Source: APXvYqx7t/dstBJlCuLx04rgbEnNHkmOAnjm13KuN2JLym9pZihNGR/7iAPY06QYmdsQGXIpZ8/d X-Received: by 2002:a17:902:8f81:: with SMTP id z1mr8956689plo.290.1562909345865; Thu, 11 Jul 2019 22:29:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1562909345; cv=none; d=google.com; s=arc-20160816; b=soeirbilMkn/aKv2gBGUXo4lkjrDQr+7BsFiy3VYcMEgFeqldIqt1lcdvro+nVLzra U4RnSck3eGYWRr/LWSQsGGbbJmK16K78jgnAMXgho0pe1RLVn+sv+p9JXv7Cn2HGf+tG YPrEm8F8bfwZinbQl7G0eHZo3L7bQCfFuZ9TluP7EfoylRBZ73aeR1xZcKoS2+26jWth 1pj4Klnpgl+w0uu4h7NIOmPya0rZkdHTOCjHfKrUPq4Zie/laCdHPs0YapFy9oDiYpKX mQuyx6SHylz21tjEGgyz1+bNNlGTmTypwZD+Kkjxi6tjXnluvbI/zcf5uqXV7o48mN69 My7A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=QZmd1kVLh8a0enxFfoIC/p5hW82ft4CjkM7ASI4iKD4=; b=j5uCea7W+temlu3gXNjjbmtJ4xIErxqtK+CGZS/R9luMOlXGaUcyCYo4Kar2fD9+JZ 2o3D/KG4c7lhKw490jIxtvlu0C8okUdUZetz3816Pfd0THL0YHPzOt0VOqbtIR48F2Bf awExVyBYbBAItb7Fe01PJJW3Qi9jLVf/pXqsGcnAc+2D7mqYgy1q43/3e+6D2rTpeaZ2 eGe4vgDJEU2dBuASMRyKolDfIHyal0Sl6QmdjNeXV+K2peFf4jicoEmR+DcYpLWsRwln Ua0A+YIHCob9FaEaYP0BIVZmUlf4T2ZSVrwSm2KePkELAST6lCXwk4ImQw8j4FlMVuuo /xOg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JprPlE3j; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e36si5303191pgm.17.2019.07.11.22.29.05; Thu, 11 Jul 2019 22:29:05 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JprPlE3j; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725871AbfGLF3F (ORCPT + 13 others); Fri, 12 Jul 2019 01:29:05 -0400 Received: from mail-pl1-f195.google.com ([209.85.214.195]:44174 "EHLO mail-pl1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725791AbfGLF3E (ORCPT ); Fri, 12 Jul 2019 01:29:04 -0400 Received: by mail-pl1-f195.google.com with SMTP id t14so4186401plr.11 for ; Thu, 11 Jul 2019 22:29:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QZmd1kVLh8a0enxFfoIC/p5hW82ft4CjkM7ASI4iKD4=; b=JprPlE3jWUXLSHH6IEYKpZVLFEmbjwTJ1SlcNpUv0d1GSCe8JK/f0tNUq3RBbyxDEh YaDWpMtRy3kUkllP6k3WuFY7bT6cKPm4KygCT/04Oos2vO+SVgCzlgkPuZ6Xu86jBZYL +joRbYQT8HwYfhxbbhQOeFxZKodJnr7G//LB9Lgd6sS6X7pnWILRwWrvwv7pwn92phHu 2BN/4SfoVMRM1fdlzw8BG9jH+cYIHFnui69Xb6O7cq93/IiqXBB7NpgD6CYe2XA87Kb0 /vcznTUHRGLdUeHKNW20eSp7yGm7eew+5xU0ZVYuqZO7qU5Kqb4wNcP5DHcXhFQGpWi5 YpzQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QZmd1kVLh8a0enxFfoIC/p5hW82ft4CjkM7ASI4iKD4=; b=LZbVTkiTdDTvwVtCmkIw74gX9ve0ymqh4Moxka8OBhpCC3LhmqJofSC5jdwJxgaIoD mgnF4FDQtWGXjULE0SPTaHSdMHvSjBUKPmfNbhf3f71xcctuMWpbsRAcRyVzvkuy93g7 C7I0v3s8FKpkSOQWvx0C3ElXAKPHuVjYqd7+XbOztBD75GZS1gv2OHFV/DJ9yjgr0GWS PFSa/eaadpWEpD8u3cICteBxNAqKWdbtkN1DWw23wmBAyi6OFcwVgAFRy6uOBu60UnB8 OrHc8Nh2Q4XVWVRTteWKneu8jIfswmPZsUHC8CPKuNBPioYYUbWS0POWumVYRhJwoBdf qO6g== X-Gm-Message-State: APjAAAWKTa6Hc8W7jsZPM07AHiJGr4Ts9u/3RGC/HHt+UU6Ya2Mb3Iqc 9uhdBmbifLBN5LNC8mdkEtyFBY95csY= X-Received: by 2002:a17:902:7043:: with SMTP id h3mr9559497plt.10.1562909344101; Thu, 11 Jul 2019 22:29:04 -0700 (PDT) Received: from localhost ([122.172.28.117]) by smtp.gmail.com with ESMTPSA id b37sm14696355pjc.15.2019.07.11.22.29.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 11 Jul 2019 22:29:03 -0700 (PDT) From: Viresh Kumar To: stable@vger.kernel.org, Julien Thierry Cc: Viresh Kumar , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Marc Zyngier , Mark Rutland , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: [PATCH v4.4 V2 02/43] arm64: Implement array_index_mask_nospec() Date: Fri, 12 Jul 2019 10:57:50 +0530 Message-Id: <271b3de6a35cd1d184f8c0a21afc0d801bc0b250.1562908074.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Robin Murphy commit 022620eed3d0bc4bf2027326f599f5ad71c2ea3f upstream. Provide an optimised, assembly implementation of array_index_mask_nospec() for arm64 so that the compiler is not in a position to transform the code in ways which affect its ability to inhibit speculation (e.g. by introducing conditional branches). This is similar to the sequence used by x86, modulo architectural differences in the carry/borrow flags. Reviewed-by: Mark Rutland Signed-off-by: Robin Murphy Signed-off-by: Will Deacon Signed-off-by: Catalin Marinas Signed-off-by: Viresh Kumar --- arch/arm64/include/asm/barrier.h | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/include/asm/barrier.h b/arch/arm64/include/asm/barrier.h index 574486634c62..7c25e3e11b6d 100644 --- a/arch/arm64/include/asm/barrier.h +++ b/arch/arm64/include/asm/barrier.h @@ -37,6 +37,27 @@ #define dma_rmb() dmb(oshld) #define dma_wmb() dmb(oshst) +/* + * Generate a mask for array_index__nospec() that is ~0UL when 0 <= idx < sz + * and 0 otherwise. + */ +#define array_index_mask_nospec array_index_mask_nospec +static inline unsigned long array_index_mask_nospec(unsigned long idx, + unsigned long sz) +{ + unsigned long mask; + + asm volatile( + " cmp %1, %2\n" + " sbc %0, xzr, xzr\n" + : "=r" (mask) + : "r" (idx), "Ir" (sz) + : "cc"); + + csdb(); + return mask; +} + #define smp_mb() dmb(ish) #define smp_rmb() dmb(ishld) #define smp_wmb() dmb(ishst) From patchwork Fri Jul 12 05:27:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 168862 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp394351ilk; Thu, 11 Jul 2019 22:29:09 -0700 (PDT) X-Google-Smtp-Source: APXvYqzFlRFrsWpVRHDTzZmcC8Mi+WIwef5p9tKhMMrER4KXBtPtB14GnB2/9WC+qvBWQZFLfUVZ X-Received: by 2002:a17:902:1e7:: with SMTP id b94mr9324200plb.333.1562909349828; Thu, 11 Jul 2019 22:29:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1562909349; cv=none; d=google.com; s=arc-20160816; b=lp370Ior2hI5m1WqBGGLQwpzJfItn/dzjPMrNsjkFztydMusqeuPuC8b4vD41A8aRe x9Th4lJE034Mnl/gESl9xJOqVLP/NVX3+RuSQ0vb2Qei+mbyvd9o6Og+M4T2dd30rndd gggb6xfThDgc0DmxY3tYcmj36puqAXzcLvgu6p/RuDiVor5w4jbdszxzJ6JbOShBLZ9W lZM12dzP1koU9bmAI3VRBOFl6LUAIGf2221ZlxTU6EaxAsYgKdU3PSwaRtgC/s5zvOta 5EUcZt8NvrMS5EAISWXaB39eMqYBcPUj66Zhdc4mwWlNHe8XcFf75C8VDvaGu/RxtXOe 1cgA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ES6KJwQvdOYp/ZF0zdgUUsDi+h2pkDI/v1RQA0OQPVY=; b=SWq90apWG3zwKlw61Q9KbhSqrAk4xap242jTh9VRwJyA9Q34zoocxLo/NPUPxkQ13N j49qt5OupH5tOBkMob3yMXdRmVp2cV2WNG71rC+qcx+B3X+oP58Ap9tvDXu7yip5+ucX nlyzmKgSH532MGtXyvQBcV658Zz7LQyu7BcLGBpmEsZor8qLvUjQ1KtqEvZEvuESlnox tadyi3Rdwit+dsOowvT3RjLLlff6A94aVeNlz5pUM8XBhxEGg+MKJOrkvc3VqOB6QvNe ZnBJ6kj4IyyRla0S8KtCevaOP+7VGLDhWnW+HHU3s4XEFjr4Dmv5lnEy/gnGL5e2CqN3 FBTA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tmwltFcg; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e36si5303191pgm.17.2019.07.11.22.29.09; Thu, 11 Jul 2019 22:29:09 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tmwltFcg; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726025AbfGLF3J (ORCPT + 13 others); Fri, 12 Jul 2019 01:29:09 -0400 Received: from mail-pg1-f195.google.com ([209.85.215.195]:33239 "EHLO mail-pg1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725791AbfGLF3J (ORCPT ); Fri, 12 Jul 2019 01:29:09 -0400 Received: by mail-pg1-f195.google.com with SMTP id m4so4010527pgk.0 for ; Thu, 11 Jul 2019 22:29:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ES6KJwQvdOYp/ZF0zdgUUsDi+h2pkDI/v1RQA0OQPVY=; b=tmwltFcg11BComY5zOAw8U//kYuDnhwsBHYjvOdsbZqTgJ5Id3gL5+Ajk+Nf+99t0v cKAm1+okktz4oy5g8Y9Qt81vbaUbIQ7noZVvtk3HSxB72w6+rHQbtYFoPBtZRofPyPWm aqeqe59em/UaytGZ/SM2ScjksqxhmXmTvYgumAVaWkGB5Z3moF0IqDRMQ0GJOq+ZdauP fqSwueqQT5umFL1tyGAjyiRNH4En80WhQzaeubt+gxBunRvZlUql1u8KzNqFMCLgq5I7 sJ7C7MHmGv4nOeGxmoQgWcXAJ6eF4sgorFYTdfnY55ZMgGVDv3zTCHNCEnJsJUPoYtBh sGvw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ES6KJwQvdOYp/ZF0zdgUUsDi+h2pkDI/v1RQA0OQPVY=; b=frlIwpVFxitpz4AJZIiBTHwf78z0tLAnXNEM4h0A1TIyzv5LxVgq0TMxHgfHBBDxsN dUbnEZcUKGy8DYfLcXvHPSCBDvfESuOquWm1Qe15i9itkqplmc7Lfons2pcmfLTzSm4+ yP/wy3JTmpJCoJHQGYHCpMZ/A2MGCEY1NRc+onFLdIOQ4TeDg4sjJO3fJNMlfUyLQjYe /dmJhpniNKdgdB4SGvIZwXqA+ObopUZD8QQd64Ik+0QGHcoAPN8v9P6F8KTfr2eORf+E lRLQcvcPLJJI6hKUuCb59UzsJbbK3fi0NX13lb8s/yMrNXyABYicsCvmFwLUQFcwYCOJ CHag== X-Gm-Message-State: APjAAAWvNAn5Ez2L42jcW2ttyNUV5L28XqJU7Qhyv9mgHpZH99tSAWWF yYnEuOztLsxYspgYgCGgyg70pmZJwgQ= X-Received: by 2002:a17:90a:eb08:: with SMTP id j8mr9632470pjz.72.1562909347630; Thu, 11 Jul 2019 22:29:07 -0700 (PDT) Received: from localhost ([122.172.28.117]) by smtp.gmail.com with ESMTPSA id a25sm6920396pfn.1.2019.07.11.22.29.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 11 Jul 2019 22:29:06 -0700 (PDT) From: Viresh Kumar To: stable@vger.kernel.org, Julien Thierry Cc: Viresh Kumar , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Marc Zyngier , Mark Rutland , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: [PATCH v4.4 V2 03/43] arm64: move TASK_* definitions to Date: Fri, 12 Jul 2019 10:57:51 +0530 Message-Id: X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Yury Norov commit eef94a3d09aab437c8c254de942d8b1aa76455e2 upstream. ILP32 series [1] introduces the dependency on for TASK_SIZE macro. Which in turn requires , and include , giving a circular dependency, because TASK_SIZE is currently located in . In other architectures, TASK_SIZE is defined in , and moving TASK_SIZE there fixes the problem. Discussion: https://patchwork.kernel.org/patch/9929107/ [1] https://github.com/norov/linux/tree/ilp32-next CC: Will Deacon CC: Laura Abbott Cc: Ard Biesheuvel Cc: Catalin Marinas Cc: James Morse Suggested-by: Mark Rutland Signed-off-by: Yury Norov Signed-off-by: Will Deacon Signed-off-by: Viresh Kumar --- arch/arm64/include/asm/memory.h | 15 --------------- arch/arm64/include/asm/processor.h | 21 +++++++++++++++++++++ arch/arm64/kernel/entry.S | 2 +- 3 files changed, 22 insertions(+), 16 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/include/asm/memory.h b/arch/arm64/include/asm/memory.h index b42b930cc19a..959a1e9188fe 100644 --- a/arch/arm64/include/asm/memory.h +++ b/arch/arm64/include/asm/memory.h @@ -43,8 +43,6 @@ * (VA_BITS - 1)) * VA_BITS - the maximum number of bits for virtual addresses. * VA_START - the first kernel virtual address. - * TASK_SIZE - the maximum size of a user space task. - * TASK_UNMAPPED_BASE - the lower boundary of the mmap VM area. * The module space lives between the addresses given by TASK_SIZE * and PAGE_OFFSET - it must be within 128MB of the kernel text. */ @@ -58,19 +56,6 @@ #define PCI_IO_END (MODULES_VADDR - SZ_2M) #define PCI_IO_START (PCI_IO_END - PCI_IO_SIZE) #define FIXADDR_TOP (PCI_IO_START - SZ_2M) -#define TASK_SIZE_64 (UL(1) << VA_BITS) - -#ifdef CONFIG_COMPAT -#define TASK_SIZE_32 UL(0x100000000) -#define TASK_SIZE (test_thread_flag(TIF_32BIT) ? \ - TASK_SIZE_32 : TASK_SIZE_64) -#define TASK_SIZE_OF(tsk) (test_tsk_thread_flag(tsk, TIF_32BIT) ? \ - TASK_SIZE_32 : TASK_SIZE_64) -#else -#define TASK_SIZE TASK_SIZE_64 -#endif /* CONFIG_COMPAT */ - -#define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 4)) /* * Physical vs virtual RAM address space conversion. These are diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h index d08559528927..75d9ef6c457c 100644 --- a/arch/arm64/include/asm/processor.h +++ b/arch/arm64/include/asm/processor.h @@ -19,6 +19,10 @@ #ifndef __ASM_PROCESSOR_H #define __ASM_PROCESSOR_H +#define TASK_SIZE_64 (UL(1) << VA_BITS) + +#ifndef __ASSEMBLY__ + /* * Default implementation of macro that returns current * instruction pointer ("program counter"). @@ -36,6 +40,22 @@ #include #ifdef __KERNEL__ +/* + * TASK_SIZE - the maximum size of a user space task. + * TASK_UNMAPPED_BASE - the lower boundary of the mmap VM area. + */ +#ifdef CONFIG_COMPAT +#define TASK_SIZE_32 UL(0x100000000) +#define TASK_SIZE (test_thread_flag(TIF_32BIT) ? \ + TASK_SIZE_32 : TASK_SIZE_64) +#define TASK_SIZE_OF(tsk) (test_tsk_thread_flag(tsk, TIF_32BIT) ? \ + TASK_SIZE_32 : TASK_SIZE_64) +#else +#define TASK_SIZE TASK_SIZE_64 +#endif /* CONFIG_COMPAT */ + +#define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 4)) + #define STACK_TOP_MAX TASK_SIZE_64 #ifdef CONFIG_COMPAT #define AARCH32_VECTORS_BASE 0xffff0000 @@ -188,4 +208,5 @@ static inline void spin_lock_prefetch(const void *x) int cpu_enable_pan(void *__unused); +#endif /* __ASSEMBLY__ */ #endif /* __ASM_PROCESSOR_H */ diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index 586326981769..c849be9231bb 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S @@ -27,7 +27,7 @@ #include #include #include -#include +#include #include #include #include From patchwork Fri Jul 12 05:27:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 168863 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp394405ilk; Thu, 11 Jul 2019 22:29:12 -0700 (PDT) X-Google-Smtp-Source: APXvYqzWNRp682bPoMmNUKy6AoJ4GnYcX8a4/OvAPsJEicUSCITrGazA3s7UjMgH180r8pR1AO54 X-Received: by 2002:a63:9a41:: with SMTP id e1mr8795240pgo.210.1562909352587; Thu, 11 Jul 2019 22:29:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1562909352; cv=none; d=google.com; s=arc-20160816; b=hAgaR80GLXEEc0/SSdAjZQvvmBdjgrxR+7psDUir7FTKKlK6IMiG5Zu6ug9OCrG2El JbozQhztPoGIY1jn3TAl/0UEr83iZmPffWpI9M2GRJWCbKKkMm2abXhZLoo5QVYkSDfz zB/ZoV/9UPeL1tL9llxjtWHEQmQouUB+5qU8aOetW/o40Oo9PwYRCnM0ZRjg9ldiv0Aq YuoQX6FIopfD9Rb6gb8Cfdu5g5loruAwfNzyOJzcekE4FX9VkCywTz3lQVBDTclpz5rS 7FC36wxGEKXDPX14taMleWZaLQYD236wwPT13/kaf9SXV3Ueu+tRTp1127Sq0oIc0L4R r+Ag== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=kHvdeN9oObJ1DWOknB6wJwOgumkOXHrRy2jfFMpABJ8=; b=JhvLB3VGpx29PSdHNA1GbRkrFEguah4rHVo3K4FZt28LRquyO4f/NAtAW3hT5A6u25 2QfPbtlBz9Pkhd5fWrPoAt12p5JLXIeoyM7k3iOE8HjL2am+mJ65875kSR1eNRbfy9VP puijsAs5ffnBZo4Vz7cmz3JkIldO77nf5LiYhzON46HSvAL+TQD6aPspQY7kd9ptnycT qJbCf5/7AuqhCNn94eVshMOp0Nhy7wI7h85Wo0FQKXmqy283O7+L660OogfNmRu3bNX8 WOcoSFToWmzBEQzcJFb7NkN6fczJALCS6RDlfiGSljbrIEE5d/r7Lc58eMv3abl9IIpF fJxA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hM1jomak; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e36si5303191pgm.17.2019.07.11.22.29.12; Thu, 11 Jul 2019 22:29:12 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hM1jomak; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725913AbfGLF3M (ORCPT + 13 others); Fri, 12 Jul 2019 01:29:12 -0400 Received: from mail-pg1-f195.google.com ([209.85.215.195]:39418 "EHLO mail-pg1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725791AbfGLF3L (ORCPT ); Fri, 12 Jul 2019 01:29:11 -0400 Received: by mail-pg1-f195.google.com with SMTP id u17so4002137pgi.6 for ; Thu, 11 Jul 2019 22:29:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kHvdeN9oObJ1DWOknB6wJwOgumkOXHrRy2jfFMpABJ8=; b=hM1jomaku7YbTVsAoc4MF43HHAKnEowYYJJHt/ujVKG5+gImW/mKJgOiMQ3Bt1wvjx t72Kf3zjoxonK9qtPyFBV7PaBIvF1BLLUigcCeozquAUDEqkeEjOx72qr2XpJ2/LKQpE C9X5M+NPSvf3J7HwTmzqm6RsYFChmRfJyvkjWYOXkCgXPToCESKDVaHgbssqbdwrT0zW YeeqDKjniFcGnDv7qgTjBNhzpi/kvK1zKpa/FPZUGKNu/M4NhxLPOLjaGBmzGj2baKWS LRNXHssnuKnY8Z5pH7O8slUYXXAeWGvFvM353Gi/FDsoWnGa8Axw/prb+0MK346eafhJ AkKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kHvdeN9oObJ1DWOknB6wJwOgumkOXHrRy2jfFMpABJ8=; b=CkqqrajIREGfKe8Jr0FeVR9vaz20FR+1bo9gOAE+hi9OlnC7CmY3J4CTbcl4xcO2Mv SH8W6inIvWdDBPwIavsETgTL/pGyExHFuHCafCgrXPFsWTbgHG1Mec90mkR6efsirqhj 6Zip9BspQmeTtR+ZiKqgHE7oFdBsInm0vjvIfEHKp5Z2gO7eO7zBgmLEbSExwodygiFD 99bsoHnuVQZrFeCCIsu3UMeWe8/s7F2RFvRnKA8gAzPMBT9XuuCtSjH5JqH/R23wI0/S l5cP6mXcZJ+6aWjps8lIo+VsvUD9jC9Aig7wTCTJbTLjnMuGCQf7vdvslFFjEw7lk2B0 vj3w== X-Gm-Message-State: APjAAAUJ8SQh9PyqNCNBenI6a5d12tXlCKDC5qQcwZuT4/y2lIMyugdX djAEexDPVxps65o7cl2n6U4cw28B2i0= X-Received: by 2002:a17:90a:17a6:: with SMTP id q35mr9421112pja.118.1562909350473; Thu, 11 Jul 2019 22:29:10 -0700 (PDT) Received: from localhost ([122.172.28.117]) by smtp.gmail.com with ESMTPSA id f17sm6063670pgv.16.2019.07.11.22.29.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 11 Jul 2019 22:29:09 -0700 (PDT) From: Viresh Kumar To: stable@vger.kernel.org, Julien Thierry Cc: Viresh Kumar , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Marc Zyngier , Mark Rutland , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: [PATCH v4.4 V2 04/43] arm64: Make USER_DS an inclusive limit Date: Fri, 12 Jul 2019 10:57:52 +0530 Message-Id: X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Robin Murphy commit 51369e398d0d33e8f524314e672b07e8cf870e79 upstream. Currently, USER_DS represents an exclusive limit while KERNEL_DS is inclusive. In order to do some clever trickery for speculation-safe masking, we need them both to behave equivalently - there aren't enough bits to make KERNEL_DS exclusive, so we have precisely one option. This also happens to correct a longstanding false negative for a range ending on the very top byte of kernel memory. Mark Rutland points out that we've actually got the semantics of addresses vs. segments muddled up in most of the places we need to amend, so shuffle the {USER,KERNEL}_DS definitions around such that we can correct those properly instead of just pasting "-1"s everywhere. Signed-off-by: Robin Murphy Signed-off-by: Will Deacon Signed-off-by: Catalin Marinas [ 4.4: Dropped changes from fault.c and fixed minor rebase conflict ] Signed-off-by: Viresh Kumar --- arch/arm64/include/asm/processor.h | 3 ++ arch/arm64/include/asm/uaccess.h | 45 +++++++++++++++++------------- arch/arm64/kernel/entry.S | 4 +-- 3 files changed, 31 insertions(+), 21 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h index 75d9ef6c457c..ff1449c25bf4 100644 --- a/arch/arm64/include/asm/processor.h +++ b/arch/arm64/include/asm/processor.h @@ -21,6 +21,9 @@ #define TASK_SIZE_64 (UL(1) << VA_BITS) +#define KERNEL_DS UL(-1) +#define USER_DS (TASK_SIZE_64 - 1) + #ifndef __ASSEMBLY__ /* diff --git a/arch/arm64/include/asm/uaccess.h b/arch/arm64/include/asm/uaccess.h index 829fa6d3e561..c625cc5531fc 100644 --- a/arch/arm64/include/asm/uaccess.h +++ b/arch/arm64/include/asm/uaccess.h @@ -56,10 +56,7 @@ struct exception_table_entry extern int fixup_exception(struct pt_regs *regs); -#define KERNEL_DS (-1UL) #define get_ds() (KERNEL_DS) - -#define USER_DS TASK_SIZE_64 #define get_fs() (current_thread_info()->addr_limit) static inline void set_fs(mm_segment_t fs) @@ -87,22 +84,32 @@ static inline void set_fs(mm_segment_t fs) * Returns 1 if the range is valid, 0 otherwise. * * This is equivalent to the following test: - * (u65)addr + (u65)size <= current->addr_limit - * - * This needs 65-bit arithmetic. + * (u65)addr + (u65)size <= (u65)current->addr_limit + 1 */ -#define __range_ok(addr, size) \ -({ \ - unsigned long __addr = (unsigned long __force)(addr); \ - unsigned long flag, roksum; \ - __chk_user_ptr(addr); \ - asm("adds %1, %1, %3; ccmp %1, %4, #2, cc; cset %0, ls" \ - : "=&r" (flag), "=&r" (roksum) \ - : "1" (__addr), "Ir" (size), \ - "r" (current_thread_info()->addr_limit) \ - : "cc"); \ - flag; \ -}) +static inline unsigned long __range_ok(unsigned long addr, unsigned long size) +{ + unsigned long limit = current_thread_info()->addr_limit; + + __chk_user_ptr(addr); + asm volatile( + // A + B <= C + 1 for all A,B,C, in four easy steps: + // 1: X = A + B; X' = X % 2^64 + " adds %0, %0, %2\n" + // 2: Set C = 0 if X > 2^64, to guarantee X' > C in step 4 + " csel %1, xzr, %1, hi\n" + // 3: Set X' = ~0 if X >= 2^64. For X == 2^64, this decrements X' + // to compensate for the carry flag being set in step 4. For + // X > 2^64, X' merely has to remain nonzero, which it does. + " csinv %0, %0, xzr, cc\n" + // 4: For X < 2^64, this gives us X' - C - 1 <= 0, where the -1 + // comes from the carry in being clear. Otherwise, we are + // testing X' - C == 0, subject to the previous adjustments. + " sbcs xzr, %0, %1\n" + " cset %0, ls\n" + : "+r" (addr), "+r" (limit) : "Ir" (size) : "cc"); + + return addr; +} /* * When dealing with data aborts, watchpoints, or instruction traps we may end @@ -111,7 +118,7 @@ static inline void set_fs(mm_segment_t fs) */ #define untagged_addr(addr) sign_extend64(addr, 55) -#define access_ok(type, addr, size) __range_ok(addr, size) +#define access_ok(type, addr, size) __range_ok((unsigned long)(addr), size) #define user_addr_max get_fs /* diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index c849be9231bb..4c5013b09dcb 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S @@ -96,10 +96,10 @@ .else add x21, sp, #S_FRAME_SIZE get_thread_info tsk - /* Save the task's original addr_limit and set USER_DS (TASK_SIZE_64) */ + /* Save the task's original addr_limit and set USER_DS */ ldr x20, [tsk, #TI_ADDR_LIMIT] str x20, [sp, #S_ORIG_ADDR_LIMIT] - mov x20, #TASK_SIZE_64 + mov x20, #USER_DS str x20, [tsk, #TI_ADDR_LIMIT] .endif /* \el == 0 */ mrs x22, elr_el1 From patchwork Fri Jul 12 05:27:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 168864 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp394434ilk; Thu, 11 Jul 2019 22:29:15 -0700 (PDT) X-Google-Smtp-Source: APXvYqzo/IMVQIeBSK/BpEYbGF0zNvczHsNvZtAKlwBYv+YoAtZDjrU986DkTwO1ifct+XTkshem X-Received: by 2002:a63:4404:: with SMTP id r4mr8498985pga.245.1562909355128; Thu, 11 Jul 2019 22:29:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1562909355; cv=none; d=google.com; s=arc-20160816; b=GGfx3qa5E1lGgxe2lCETf6pCuHOc1uUOqVMXb3KmAaCsZ3vEIeOd7wIiA96G1ieImf +/Kvb7lq6LSLSkCgJSR770rrKF2vh5WfSbOWZ8Ua40FUQ5J6qurx/EqqOn2H4cEdt6RL /i6LKgwQPCQg30A8p55TKGsVpPyDtav7UHTvpwtZaLyti7+g2W4px6x8STZlLJdUFRrd rbW6f03DcqHoA7pY13tkm+24u9XJOuJEuIcXi4AApH1gW+lNTZVJk6Mbp89vS62eoAQB QrVS4wrPgFBZtqSJK5Hafvv4H/yUP/umSKdMm2j0TmDZ0FMHyoKOXR6QufqgJpV3KSbe Z3Jg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=oplH30x1zLW/kw5XTQuFI7s72sVvdi1RahKBb4zAIVI=; b=oAZSjwfAcUU73UsoY+KyKPmlQLyYoitGBzP3baoXrPYnFff2+X56qt7dHt6J46hOAe yWrxS1EwQkp/OOmHOxgPTQEBnUFWF6oHOQR7eeJcDHtvFN9EwKN1GAc7PrImA+3jtIOd S+d5UBMaORpRPY4AGSeVIX/RytpA0yPDjgO+7D7TOgvs/uf2PgtqGcAswSW9l7J1JNcr 2j3gJuqi9swLwc95PqUiy3I8A5TnaX20ulRgAKBYYqMtkBUXEx2LqRRpaa5M23FzRjfy w4wwsLeCO4cid8/nNZ8UYpod6q8ufXT4+LBmtxp9X9Ez6+cDMiFLI35WIBAuo8HtothE r+0A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=eaes5zcg; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Similarly to x86, mitigate speculation past an access_ok() check by masking the pointer against the address limit before use. Even if we don't expect speculative writes per se, it is plausible that a CPU may still speculate at least as far as fetching a cache line for writing, hence we also harden put_user() and clear_user() for peace of mind. Signed-off-by: Robin Murphy Signed-off-by: Will Deacon Signed-off-by: Catalin Marinas Signed-off-by: Viresh Kumar --- arch/arm64/include/asm/uaccess.h | 26 +++++++++++++++++++++++--- 1 file changed, 23 insertions(+), 3 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/include/asm/uaccess.h b/arch/arm64/include/asm/uaccess.h index c625cc5531fc..75363d723262 100644 --- a/arch/arm64/include/asm/uaccess.h +++ b/arch/arm64/include/asm/uaccess.h @@ -121,6 +121,26 @@ static inline unsigned long __range_ok(unsigned long addr, unsigned long size) #define access_ok(type, addr, size) __range_ok((unsigned long)(addr), size) #define user_addr_max get_fs +/* + * Sanitise a uaccess pointer such that it becomes NULL if above the + * current addr_limit. + */ +#define uaccess_mask_ptr(ptr) (__typeof__(ptr))__uaccess_mask_ptr(ptr) +static inline void __user *__uaccess_mask_ptr(const void __user *ptr) +{ + void __user *safe_ptr; + + asm volatile( + " bics xzr, %1, %2\n" + " csel %0, %1, xzr, eq\n" + : "=&r" (safe_ptr) + : "r" (ptr), "r" (current_thread_info()->addr_limit) + : "cc"); + + csdb(); + return safe_ptr; +} + /* * The "__xxx" versions of the user access functions do not verify the address * space - it must have been done previously with a separate "access_ok()" @@ -193,7 +213,7 @@ do { \ __typeof__(*(ptr)) __user *__p = (ptr); \ might_fault(); \ access_ok(VERIFY_READ, __p, sizeof(*__p)) ? \ - __get_user((x), __p) : \ + __p = uaccess_mask_ptr(__p), __get_user((x), __p) : \ ((x) = 0, -EFAULT); \ }) @@ -259,7 +279,7 @@ do { \ __typeof__(*(ptr)) __user *__p = (ptr); \ might_fault(); \ access_ok(VERIFY_WRITE, __p, sizeof(*__p)) ? \ - __put_user((x), __p) : \ + __p = uaccess_mask_ptr(__p), __put_user((x), __p) : \ -EFAULT; \ }) @@ -297,7 +317,7 @@ static inline unsigned long __must_check copy_in_user(void __user *to, const voi static inline unsigned long __must_check clear_user(void __user *to, unsigned long n) { if (access_ok(VERIFY_WRITE, to, n)) - n = __clear_user(to, n); + n = __clear_user(__uaccess_mask_ptr(to), n); return n; } From patchwork Fri Jul 12 05:27:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 168865 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp394465ilk; Thu, 11 Jul 2019 22:29:17 -0700 (PDT) X-Google-Smtp-Source: APXvYqy1kbK23BegyAVwiVgtFi2gzC2ZSIUI/spF9iHK6pzO7aKlntNYLB/GSVYmxI0WSF28FU2J X-Received: by 2002:a63:e953:: with SMTP id q19mr8673398pgj.313.1562909357626; Thu, 11 Jul 2019 22:29:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1562909357; cv=none; d=google.com; s=arc-20160816; b=DM0lEmj6Jk1PZ6NjeuYkO+3m6vxvjpKBWcIk3X5uv3khShDAV8Ut+7yASJDBCvHwzC /ofQq2IyF5GHjfnLsg4EhAa4G1DC1pQMr9+MRU44AY00oOSvtnBRfk+ETv+/pqB350iZ re8ezwU7QlpRDoExhZcPddJUN8001q1XbQyElYr3jWSAL6TJ6JYTW8sFweDCwoVhVREi lvIHvweepA4gZzPzNR4F3h8hdv8vPqzNzmHPxEYlFSi7nhTzOVH2fxgar7RE6GW6QSOi Y1ppvX+GqNDlDhcU/zdBoa/7tSsr4XLckNXsgZ+BuDXCL003A7ugZnJS/f9R9IqAWRYj p1+w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=1IdhsUs/fdllTh2EJ+ScRqWrO1uX9GsPUvP6PugnTR0=; b=kj+NV5Qc06d6qpJY3MBqQkJFwuyx/6G6EcZmM4sA+YliDrtxs1MN25cpbkgM11ixBG qHZgQcR7aIpmXvR5LVQPcM55u/F1m/EeI66RuzkROU3TWY8b9CchM3HcHvYHx8oZJ1l6 YXUKxdSS4G4+eZU3/F9Kpcgy5y41CtfdOrYlHRuK1/qIykIh57injejhrne6wUosjwUD 0CXQxFusqsP/R+FmmOxyHK4uZGG/Kcgbxdwa8roUWzIObRhlOCcqVlr0jpkERZdMispW UZN0/Sz9M0RSfmBMzc5ZshM49CDfDFuX+QcSKEShiyYghOtGF8DZsyIqn8vhxlsxB/Ox YP5g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NLbMjzAl; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e36si5303191pgm.17.2019.07.11.22.29.17; Thu, 11 Jul 2019 22:29:17 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NLbMjzAl; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726033AbfGLF3R (ORCPT + 13 others); Fri, 12 Jul 2019 01:29:17 -0400 Received: from mail-pf1-f195.google.com ([209.85.210.195]:41516 "EHLO mail-pf1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725791AbfGLF3Q (ORCPT ); Fri, 12 Jul 2019 01:29:16 -0400 Received: by mail-pf1-f195.google.com with SMTP id m30so3786611pff.8 for ; Thu, 11 Jul 2019 22:29:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1IdhsUs/fdllTh2EJ+ScRqWrO1uX9GsPUvP6PugnTR0=; b=NLbMjzAlqCBkT5p9dJVqb2Z5dGhi0jH/DelTojWG0Hk2jdOfuiefznDfWJuowL/Agl 9aokXDeJ+NvIotQEG7M9THxjw+tb4VCdkLg0zn5oOVf7UqOFxPmQNucZL3G6T4d34qB7 t4PnLhRDb1YvAtUJ64bQ3QYulrevKjRsE8L0fyxvWH95xDWSk9+Xh76mvSBfdlZUq6lQ XvmcFSoFmIX3B4BQMIZGp1/ew1VgB/sqXv79EloYkvfP3rnZvDNjRXbvP1Z+zMig52iB Dlq9x9DLYRFCXW8bKyADSSuKd2qCmMDKgLmgOmKouq+eU0jfATvKGuL0UJyP3z0HwRZu sM9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1IdhsUs/fdllTh2EJ+ScRqWrO1uX9GsPUvP6PugnTR0=; b=aVIOjgoCUVqCuOM+QhnEbFIfljTPoukFgFJBKDHRTDraR0EA8fG97XYLSre5a5/583 +L9CIzRFZCL+gRYFNQAaU8cErjXVcMooJsCc0mT5zFWZAhnSKHSHLg4HRVIP7r6zLbi7 cudPkw4dR6r+/cEjgbExdmMArihWcCUwBdhjVNjeZnKjHjO4nN45gh/uve6H+bDowcOx IdshdSQDKhXVwJF3up14s7Ob2R9N1wOzx/RMd8s/PC24cGdYcVSpkSSh1XExcx14eRMi Z+reOuCS+AYXpq0X3RHu5U+ThdZ+koY7xJDj9sJYwHlZp1RyjNfEyEY/i3CcZWdZ4WIi ToSw== X-Gm-Message-State: APjAAAVGCC//rsxytspA044y0+zaN7C1F/BU20zab3/g3DpKN2vxpG7y rzQLO6wbh8U+Y/NXLUuJLVoK1Uus1/A= X-Received: by 2002:a17:90a:a116:: with SMTP id s22mr9286580pjp.47.1562909355740; Thu, 11 Jul 2019 22:29:15 -0700 (PDT) Received: from localhost ([122.172.28.117]) by smtp.gmail.com with ESMTPSA id d23sm5914809pjv.18.2019.07.11.22.29.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 11 Jul 2019 22:29:15 -0700 (PDT) From: Viresh Kumar To: stable@vger.kernel.org, Julien Thierry Cc: Viresh Kumar , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Marc Zyngier , Mark Rutland , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: [PATCH v4.4 V2 06/43] arm64: entry: Ensure branch through syscall table is bounded under speculation Date: Fri, 12 Jul 2019 10:57:54 +0530 Message-Id: X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Will Deacon commit 6314d90e64936c584f300a52ef173603fb2461b5 upstream. In a similar manner to array_index_mask_nospec, this patch introduces an assembly macro (mask_nospec64) which can be used to bound a value under speculation. This macro is then used to ensure that the indirect branch through the syscall table is bounded under speculation, with out-of-range addresses speculating as calls to sys_io_setup (0). Reviewed-by: Mark Rutland Signed-off-by: Will Deacon Signed-off-by: Catalin Marinas [ v4.4: use existing scno & sc_nr definitions ] Signed-off-by: Viresh Kumar --- arch/arm64/include/asm/assembler.h | 11 +++++++++++ arch/arm64/kernel/entry.S | 1 + 2 files changed, 12 insertions(+) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h index 683c2875278f..2b30363a3a89 100644 --- a/arch/arm64/include/asm/assembler.h +++ b/arch/arm64/include/asm/assembler.h @@ -102,6 +102,17 @@ hint #20 .endm +/* + * Sanitise a 64-bit bounded index wrt speculation, returning zero if out + * of bounds. + */ + .macro mask_nospec64, idx, limit, tmp + sub \tmp, \idx, \limit + bic \tmp, \tmp, \idx + and \idx, \idx, \tmp, asr #63 + csdb + .endm + #define USER(l, x...) \ 9999: x; \ .section __ex_table,"a"; \ diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index 4c5013b09dcb..e6aec982dea9 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S @@ -697,6 +697,7 @@ el0_svc_naked: // compat entry point b.ne __sys_trace cmp scno, sc_nr // check upper syscall limit b.hs ni_sys + mask_nospec64 scno, sc_nr, x19 // enforce bounds for syscall number ldr x16, [stbl, scno, lsl #3] // address in the syscall table blr x16 // call sys_* routine b ret_fast_syscall From patchwork Fri Jul 12 05:27:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 168866 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp394488ilk; Thu, 11 Jul 2019 22:29:20 -0700 (PDT) X-Google-Smtp-Source: APXvYqxrvzt5w5bwEA24tCJeDzbKU/ili2+7JO64t3oiIi19Xi2nXV0NLzY9VhyquWnLoh8kcVBl X-Received: by 2002:a63:c34c:: with SMTP id e12mr8386102pgd.195.1562909359987; Thu, 11 Jul 2019 22:29:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1562909359; cv=none; d=google.com; s=arc-20160816; b=HAQc3RVdtWpt/L7+ke0yAvjxHvnMYhS6ccO7jxtDScND3087+ZUJ1mUGkpZ9jkmFAP +WDx+gHhE+r/y4xSjd+t0yFNrBWqBnmage1ALFRcnRSIUymOmBWUQib5oExzYJJ3Qplx sMP/glBYGGDG2pEWHJ64munZLzwZbl31uh2hYT4h3I3BVmK6AwfSlXxrLswD0aCIYhtj XboqMVpA5LJ3nj24Gs+Ng0MwRyxAAMTsqoBVA7apeQSbGl6FXvRloE+1nXVTsI8t5Lgh IzFcfFYmVZ5zX1Htv+GMaZguBGYhzySQu1SFH/BQOepViv3OQM8OSB2V+O/yImHaqC/D g15w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=gNlfncScxDREAT7VjTEXAFzdaeKYbTqQ4JYCBMZ7gaA=; b=QT01JvI7QihgIPKVzSWPBneJbRqcUp54ChHP/sui3EUWvDYZLeVQMGIfwn75WH6zqk 5QzqyElFifvNYlEpjnGeg43IYv38LlkzG2gZjek7E3egjFKC0MbQ479yIL0uIzdrul89 bOtGkv4t2b3fruLZq4vv2kLLTJFGCnNtVOGboM9iHdlPaPk7yvrAqUNerSPp8Uihf2Zp 0Hpn4qW5GRGevQ+37hRQY2X5ZQiv6cml4IYZGlMubkI1mrjgse+DMjJsM3yDSe9koQF1 7xZP91K1tTd57LyH87UOH+DU0TSdDkWa6uXeXrKHfFtbY4X7FWSsr9oAboVIv2mA7IPk W47Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cKXVVMIE; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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A mispredicted conditional call to set_fs could result in the wrong addr_limit being forwarded under speculation to a subsequent access_ok check, potentially forming part of a spectre-v1 attack using uaccess routines. This patch prevents this forwarding from taking place, but putting heavy barriers in set_fs after writing the addr_limit. Reviewed-by: Mark Rutland Signed-off-by: Will Deacon Signed-off-by: Catalin Marinas Signed-off-by: Viresh Kumar --- arch/arm64/include/asm/uaccess.h | 7 +++++++ 1 file changed, 7 insertions(+) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/include/asm/uaccess.h b/arch/arm64/include/asm/uaccess.h index 75363d723262..fc11c50af558 100644 --- a/arch/arm64/include/asm/uaccess.h +++ b/arch/arm64/include/asm/uaccess.h @@ -62,6 +62,13 @@ extern int fixup_exception(struct pt_regs *regs); static inline void set_fs(mm_segment_t fs) { current_thread_info()->addr_limit = fs; + + /* + * Prevent a mispredicted conditional call to set_fs from forwarding + * the wrong address limit to access_ok under speculation. + */ + dsb(nsh); + isb(); } #define segment_eq(a, b) ((a) == (b)) From patchwork Fri Jul 12 05:27:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 168867 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp394531ilk; Thu, 11 Jul 2019 22:29:22 -0700 (PDT) X-Google-Smtp-Source: APXvYqyc74PXQ56ViofrpzgukHzNwbodVorHzmnsxEDMPX2yAJI25jVW7o3zVUIbw7UhXYdASeSS X-Received: by 2002:a17:90a:3344:: with SMTP id m62mr9397433pjb.135.1562909362914; Thu, 11 Jul 2019 22:29:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1562909362; cv=none; d=google.com; s=arc-20160816; b=dJhAYK4r8QqBIA73QFV0pghD8Mn94moqeAEkyd4i+Bb2A4PeHZ6+t7LLm1Qr41txMJ ziBcrbK7ERfFVTeTHtvz7gdrgmC06MB2qgn95U2aecshBGxy4kzTW1gi1O6gb0PsmmGV o4BZE0egkleVEX4Pk/DaIl084Xw1L69tRBWr9sL7tAZ8eqBAcE6b7u3m3q2fWuU0LHxR 0k2I3jwPrMtrPiH4SgDB/KLMOBk/WgsEKMni8tVp/ugT7dji6Y5XodgI4kTp6KKBzoJP xGK5EcvyVzixiKgSxWNH2Q5PGLnRVJla53NH3Mn7a7QuGdaxx7kDMXUFydsMq+0kQiKe JnBg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Lt3w372XAiP2T5A3AE8p2nBAFVuCKsgxbI6J0UJSdP8=; b=o42z/fkHOom+QzummlrULx2fpGrxRLpDsyi6yCN5w22HdxYPHHOiGz5g1vK2fM9IWk qRjzXIjAdPN3yx95RFnSikzjy8VMLPNaCd9/oJUDZUmr6BoVsCGQanCfIpBidrdkqVw3 xS1fhKhM4sPXm5WU5Eco3PUmGo/4SnTe4ihwRiEANXmfFjgOTj5g5l5YB+fOhzObVdSF I9dUssgKai8GM7AWW9mFbNUad/Gc7b8R6DhiGz7DRgm20wPqeLt97gwMBVpDStjfCnQx R5qS5kCv09LWDvoFFcJxpC3QWrCAuEf04ND6lBjByQzz8QfkIKpz/rGuJ7+q9y3m1nu4 BmSQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="LaE/Kno7"; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e36si5303191pgm.17.2019.07.11.22.29.22; Thu, 11 Jul 2019 22:29:22 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="LaE/Kno7"; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726050AbfGLF3W (ORCPT + 13 others); Fri, 12 Jul 2019 01:29:22 -0400 Received: from mail-pl1-f196.google.com ([209.85.214.196]:42447 "EHLO mail-pl1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725791AbfGLF3W (ORCPT ); Fri, 12 Jul 2019 01:29:22 -0400 Received: by mail-pl1-f196.google.com with SMTP id ay6so4195749plb.9 for ; Thu, 11 Jul 2019 22:29:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Lt3w372XAiP2T5A3AE8p2nBAFVuCKsgxbI6J0UJSdP8=; b=LaE/Kno7nEObxeBKxYf9ds5SR/CXNWhXinMc3wcULfDJoYCm/+NNy5aliYFycyp/Pd xQjNCTX3R2Lq+L+RC/SMO5qnlzYoPN7ZrN0vVtlR6eZ+5ScFKAuQmQ3TO7j8mSsmt4Xd YlVHx3iK1DZkTJj5xP/b+JuDVFC6zP4989JLcd7xMAHJNgpFr3BPj89s9hC2xYMMV8up Aa7U2CtFy3VMya7CPReBDeY64SUW9PmXWPcFPrYDtu8vg5DZYAHcIBmCQyWoU3HVghK3 cMB2NDUennZ7lH8fyvKlDMyuCzU87oRy6E6zBmLCUtu5VqBlG9PrA3ZfPYCxqfgtFQwy qZAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Lt3w372XAiP2T5A3AE8p2nBAFVuCKsgxbI6J0UJSdP8=; b=HrPt6lo+NFUohSAosWXfwTzQ4PQf7dSfDWdfPch2P2zqSIq/EPCE8p6U9EO1R4yhPs 4l8a19m700r242cwTvPRC/lYH0dtNp6wQOOgRyLBGDeft5WWXfXSGt51xFxJmtGU67x5 WoIZRRIr1Rx7fpEMfQzQ09HQgvnlbRVZB5GGZnsZLXRFTt4ThbVoma9Lram3KtNSd/F8 F7Tm0ZpSsDMWg5Is69207BUluTtLV1ILD2bdx3lSF1AF/tS64FpsYQcjdac7Cn6qvn4w 6UZ0TM3MbCWvHGr6LEIjPJZlK5vW80oLZmtr2RaYOTgodm6sxbh6LoiJJL9WaJI7yFh+ ddnQ== X-Gm-Message-State: APjAAAVBC+qeMoRh3sXaKb9uR7rwW/eXoNiWu9ObX3SNtT1mNHBkWU+X uiNpd8qYG15qWls2x16tKDk70t30Vso= X-Received: by 2002:a17:902:8509:: with SMTP id bj9mr9229479plb.79.1562909360992; Thu, 11 Jul 2019 22:29:20 -0700 (PDT) Received: from localhost ([122.172.28.117]) by smtp.gmail.com with ESMTPSA id 196sm7991977pfy.167.2019.07.11.22.29.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 11 Jul 2019 22:29:20 -0700 (PDT) From: Viresh Kumar To: stable@vger.kernel.org, Julien Thierry Cc: Viresh Kumar , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Marc Zyngier , Mark Rutland , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: [PATCH v4.4 V2 08/43] arm64: uaccess: Don't bother eliding access_ok checks in __{get, put}_user Date: Fri, 12 Jul 2019 10:57:56 +0530 Message-Id: <61ec4192da912ef3c49e2e40670ddc76d9583683.1562908075.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Will Deacon commit 84624087dd7e3b482b7b11c170ebc1f329b3a218 upstream. access_ok isn't an expensive operation once the addr_limit for the current thread has been loaded into the cache. Given that the initial access_ok check preceding a sequence of __{get,put}_user operations will take the brunt of the miss, we can make the __* variants identical to the full-fat versions, which brings with it the benefits of address masking. The likely cost in these sequences will be from toggling PAN/UAO, which we can address later by implementing the *_unsafe versions. Reviewed-by: Robin Murphy Signed-off-by: Will Deacon Signed-off-by: Catalin Marinas [ v4.4: Fixed conflicts around {__get_user|__put_user}_unaligned macros ] Signed-off-by: Viresh Kumar --- arch/arm64/include/asm/uaccess.h | 62 ++++++++++++++++++-------------- 1 file changed, 36 insertions(+), 26 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/include/asm/uaccess.h b/arch/arm64/include/asm/uaccess.h index fc11c50af558..a34324436ce1 100644 --- a/arch/arm64/include/asm/uaccess.h +++ b/arch/arm64/include/asm/uaccess.h @@ -200,30 +200,35 @@ do { \ CONFIG_ARM64_PAN)); \ } while (0) -#define __get_user(x, ptr) \ +#define __get_user_check(x, ptr, err) \ ({ \ - int __gu_err = 0; \ - __get_user_err((x), (ptr), __gu_err); \ - __gu_err; \ + __typeof__(*(ptr)) __user *__p = (ptr); \ + might_fault(); \ + if (access_ok(VERIFY_READ, __p, sizeof(*__p))) { \ + __p = uaccess_mask_ptr(__p); \ + __get_user_err((x), __p, (err)); \ + } else { \ + (x) = 0; (err) = -EFAULT; \ + } \ }) #define __get_user_error(x, ptr, err) \ ({ \ - __get_user_err((x), (ptr), (err)); \ + __get_user_check((x), (ptr), (err)); \ (void)0; \ }) -#define __get_user_unaligned __get_user - -#define get_user(x, ptr) \ +#define __get_user(x, ptr) \ ({ \ - __typeof__(*(ptr)) __user *__p = (ptr); \ - might_fault(); \ - access_ok(VERIFY_READ, __p, sizeof(*__p)) ? \ - __p = uaccess_mask_ptr(__p), __get_user((x), __p) : \ - ((x) = 0, -EFAULT); \ + int __gu_err = 0; \ + __get_user_check((x), (ptr), __gu_err); \ + __gu_err; \ }) +#define __get_user_unaligned __get_user + +#define get_user __get_user + #define __put_user_asm(instr, reg, x, addr, err) \ asm volatile( \ "1: " instr " " reg "1, [%2]\n" \ @@ -266,30 +271,35 @@ do { \ CONFIG_ARM64_PAN)); \ } while (0) -#define __put_user(x, ptr) \ +#define __put_user_check(x, ptr, err) \ ({ \ - int __pu_err = 0; \ - __put_user_err((x), (ptr), __pu_err); \ - __pu_err; \ + __typeof__(*(ptr)) __user *__p = (ptr); \ + might_fault(); \ + if (access_ok(VERIFY_WRITE, __p, sizeof(*__p))) { \ + __p = uaccess_mask_ptr(__p); \ + __put_user_err((x), __p, (err)); \ + } else { \ + (err) = -EFAULT; \ + } \ }) #define __put_user_error(x, ptr, err) \ ({ \ - __put_user_err((x), (ptr), (err)); \ + __put_user_check((x), (ptr), (err)); \ (void)0; \ }) -#define __put_user_unaligned __put_user - -#define put_user(x, ptr) \ +#define __put_user(x, ptr) \ ({ \ - __typeof__(*(ptr)) __user *__p = (ptr); \ - might_fault(); \ - access_ok(VERIFY_WRITE, __p, sizeof(*__p)) ? \ - __p = uaccess_mask_ptr(__p), __put_user((x), __p) : \ - -EFAULT; \ + int __pu_err = 0; \ + __put_user_check((x), (ptr), __pu_err); \ + __pu_err; \ }) +#define __put_user_unaligned __put_user + +#define put_user __put_user + extern unsigned long __must_check __copy_from_user(void *to, const void __user *from, unsigned long n); extern unsigned long __must_check __copy_to_user(void __user *to, const void *from, unsigned long n); extern unsigned long __must_check __copy_in_user(void __user *to, const void __user *from, unsigned long n); From patchwork Fri Jul 12 05:27:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 168868 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp394575ilk; Thu, 11 Jul 2019 22:29:25 -0700 (PDT) X-Google-Smtp-Source: APXvYqy+BlxQ6Crze4g8Bd4L3WHs5oCc3KbUi93rc7aeSXZa+EOiGk00OvbIpfjwa3arnBrciuX9 X-Received: by 2002:a65:5687:: with SMTP id v7mr8786764pgs.263.1562909365512; Thu, 11 Jul 2019 22:29:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1562909365; cv=none; d=google.com; s=arc-20160816; b=UMZUAuc1+62GF5+JbWMxCk2dJ4e4O20TVbp8IRHkJlAG3/9lT50qCsromrD8B9V62k UG+6u8L9rSngzOFl6QhCLKyJzF0/zLp8fIpZswfdQBHFrB0YE1evb3Ef82hVl/2kV/sM pqhUjTfoHZxR4xFqHj2yDr11Y4eveLXtHALZZm3oDIRgHDbnNWKuZlvC8LmNQCoPEaYy ZZKjuI9t+rv8orBH3PjVdT73t8U9kruDt81ngUc54dX4BT4AjFm1Ndz4vgn3AVwaPnUl KIlOHRhheEJws46eoqXEK/o3OFtU1rGcRUiT5NCJ2FF8toXJCkJjIljuji2ZtqJHzecH Zqdw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=+i1PP70VM4gp+yGXoK79tVzWNeTCN5YHgyu+1fomQgA=; b=YMLYNmuXcskbmvlp3Zzb6XSeBUtLTi5ZWVAfgQ1tRSkqrS9cf2ssRhbpUCy6aLxc6G htXHkdlYIuyb3Rdyb43aD+Ye/mVNkJpyDgeTapuzNycBlsbDpWhzKFgcFWk8pBtwdzjz toqXaZxcnpbwIDd/uhnSIRYFhO7oFoikA5hLFbjsPoNUpIRjILTUrcw3o+v/OWdmaLKs y9Jr8PKowQtAhZGK7buxORrM7zIXI0bizYk3eeaHH4Y8Q91P2pejpG0gL8wIiP/S8rrD x3q3r4FQMquzZquBEOyiw2YGl7b/x9W6B43j1XK104Fm0XMF9E1qLWNbLL+rjAV/1LuN NcVA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=LtvPtrcr; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Memory access coded in an assembly won't be seen by KASAN as a compiler can instrument only C code. Add kasan_check_[read,write]() API which is going to be used to check a certain memory range. Link: http://lkml.kernel.org/r/1462538722-1574-3-git-send-email-aryabinin@virtuozzo.com Signed-off-by: Andrey Ryabinin Acked-by: Alexander Potapenko Cc: Dmitry Vyukov Cc: Ingo Molnar Cc: "H. Peter Anvin" Cc: Thomas Gleixner Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds [ v4.4: Fixed MAINTAINERS conflict and added whole kasan entry. Drop 4th argument to check_memory_region(). ] Signed-off-by: Viresh Kumar --- MAINTAINERS | 14 ++++++++++++++ include/linux/kasan-checks.h | 12 ++++++++++++ mm/kasan/kasan.c | 12 ++++++++++++ 3 files changed, 38 insertions(+) create mode 100644 include/linux/kasan-checks.h -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/MAINTAINERS b/MAINTAINERS index f4d4a5544dc1..2a8826732967 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -5982,6 +5982,20 @@ S: Maintained F: Documentation/hwmon/k8temp F: drivers/hwmon/k8temp.c +KASAN +M: Andrey Ryabinin +R: Alexander Potapenko +R: Dmitry Vyukov +L: kasan-dev@googlegroups.com +S: Maintained +F: arch/*/include/asm/kasan.h +F: arch/*/mm/kasan_init* +F: Documentation/kasan.txt +F: include/linux/kasan*.h +F: lib/test_kasan.c +F: mm/kasan/ +F: scripts/Makefile.kasan + KCONFIG M: "Yann E. MORIN" L: linux-kbuild@vger.kernel.org diff --git a/include/linux/kasan-checks.h b/include/linux/kasan-checks.h new file mode 100644 index 000000000000..b7f8aced7870 --- /dev/null +++ b/include/linux/kasan-checks.h @@ -0,0 +1,12 @@ +#ifndef _LINUX_KASAN_CHECKS_H +#define _LINUX_KASAN_CHECKS_H + +#ifdef CONFIG_KASAN +void kasan_check_read(const void *p, unsigned int size); +void kasan_check_write(const void *p, unsigned int size); +#else +static inline void kasan_check_read(const void *p, unsigned int size) { } +static inline void kasan_check_write(const void *p, unsigned int size) { } +#endif + +#endif diff --git a/mm/kasan/kasan.c b/mm/kasan/kasan.c index b7397b459960..1cdcab0c976a 100644 --- a/mm/kasan/kasan.c +++ b/mm/kasan/kasan.c @@ -274,6 +274,18 @@ static __always_inline void check_memory_region(unsigned long addr, void __asan_loadN(unsigned long addr, size_t size); void __asan_storeN(unsigned long addr, size_t size); +void kasan_check_read(const void *p, unsigned int size) +{ + check_memory_region((unsigned long)p, size, false); +} +EXPORT_SYMBOL(kasan_check_read); + +void kasan_check_write(const void *p, unsigned int size) +{ + check_memory_region((unsigned long)p, size, true); +} +EXPORT_SYMBOL(kasan_check_write); + #undef memset void *memset(void *addr, int c, size_t len) { From patchwork Fri Jul 12 05:27:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 168869 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp394604ilk; Thu, 11 Jul 2019 22:29:27 -0700 (PDT) X-Google-Smtp-Source: APXvYqzviaiKTtdo/vNHu3MWalBpvY6gy7S0/ANbVJxT/2SRl8uSAb09tHBzySkydv6BZhd6XM2Z X-Received: by 2002:a17:902:2d01:: with SMTP id o1mr9352075plb.105.1562909367722; Thu, 11 Jul 2019 22:29:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1562909367; cv=none; d=google.com; s=arc-20160816; b=v/5Efq6IA3WbTVgJMAswcgXFZn23ro1hydy9q9025cNsgsRv8X3Z1EU8iA0st7n2iC t4syNoyKmT118I0t53uHKDCu/0vg5veEEUoT7bfE1DA+0npzuVwPiLQCzTgAobIgo7jQ AnHEYCMuk4mYHZIBVrdhObcbdpKEeXTxwr2i9rXJd1NEnP8s5MUpBGgwkKshh74PsrEb 0qz30BwpiROg4NgHhCbSO900LVbZ7HS+5+ar/HkiaSBl+cFhA08vxpGgJPoRXe2HhaF1 VKeCxgX/0Cl73/H0+jaDPxjqPGQNRNsEnPxyPq2bRrHwh89D/rHExN6xnPw/7vbq1MwT 344w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=t0RCljGeD4tzeQJetzsGgy9r5JSUQjn098IzF6ZdUW0=; b=d+oDIPxLXozS20Dt9Z+RwlnTnJWjplVUEYp1uuIfS7CfzCcnCqBfjgT1on4UY+83R6 //AAe75bGL+kwF33RvAQ1TITiIrT+/nYulqw3c+v41ZfBWzbmc8qfrvFx87s625gDPV3 aEbLckLUuA10yN/LDqlJhNWda7dkiKc4FeNQ9XqBJF0TgnmL/aKvwlGw6hGPW4SFZ+DP zbFB4W+p07CAOAER+3BJWsdxFVx8DCMzQa1ns1fkE12uQ0qs5pdMKCx3VeIvjsX9MJ53 PAo6SdUUc09QmwBMpezOA+0F6lbWI+8BelHEdbyLWna9ZMiXnKXj362oHxlI4lfKFT8w wyfw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ulsmDQGt; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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The upstream commit 1771c6e1a567ea0ba2cccc0a4ffe68a1419fd8ef ("x86/kasan: instrument user memory access API") added KASAN instrument to x86 user memory access API, so added such instrument to ARM64 too. Define __copy_to/from_user in C in order to add kasan_check_read/write call, rename assembly implementation to __arch_copy_to/from_user. Tested by test_kasan module. Acked-by: Andrey Ryabinin Reviewed-by: Mark Rutland Tested-by: Mark Rutland Signed-off-by: Yang Shi Signed-off-by: Catalin Marinas Signed-off-by: Viresh Kumar --- arch/arm64/include/asm/uaccess.h | 25 +++++++++++++++++++++---- arch/arm64/kernel/arm64ksyms.c | 4 ++-- arch/arm64/lib/copy_from_user.S | 4 ++-- arch/arm64/lib/copy_to_user.S | 4 ++-- 4 files changed, 27 insertions(+), 10 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/include/asm/uaccess.h b/arch/arm64/include/asm/uaccess.h index a34324436ce1..693a0d784534 100644 --- a/arch/arm64/include/asm/uaccess.h +++ b/arch/arm64/include/asm/uaccess.h @@ -22,6 +22,7 @@ * User space memory access functions */ #include +#include #include #include @@ -300,15 +301,29 @@ do { \ #define put_user __put_user -extern unsigned long __must_check __copy_from_user(void *to, const void __user *from, unsigned long n); -extern unsigned long __must_check __copy_to_user(void __user *to, const void *from, unsigned long n); +extern unsigned long __must_check __arch_copy_from_user(void *to, const void __user *from, unsigned long n); +extern unsigned long __must_check __arch_copy_to_user(void __user *to, const void *from, unsigned long n); extern unsigned long __must_check __copy_in_user(void __user *to, const void __user *from, unsigned long n); extern unsigned long __must_check __clear_user(void __user *addr, unsigned long n); +static inline unsigned long __must_check __copy_from_user(void *to, const void __user *from, unsigned long n) +{ + kasan_check_write(to, n); + return __arch_copy_from_user(to, from, n); +} + +static inline unsigned long __must_check __copy_to_user(void __user *to, const void *from, unsigned long n) +{ + kasan_check_read(from, n); + return __arch_copy_to_user(to, from, n); +} + static inline unsigned long __must_check copy_from_user(void *to, const void __user *from, unsigned long n) { + kasan_check_write(to, n); + if (access_ok(VERIFY_READ, from, n)) - n = __copy_from_user(to, from, n); + n = __arch_copy_from_user(to, from, n); else /* security hole - plug it */ memset(to, 0, n); return n; @@ -316,8 +331,10 @@ static inline unsigned long __must_check copy_from_user(void *to, const void __u static inline unsigned long __must_check copy_to_user(void __user *to, const void *from, unsigned long n) { + kasan_check_read(from, n); + if (access_ok(VERIFY_WRITE, to, n)) - n = __copy_to_user(to, from, n); + n = __arch_copy_to_user(to, from, n); return n; } diff --git a/arch/arm64/kernel/arm64ksyms.c b/arch/arm64/kernel/arm64ksyms.c index 3b6d8cc9dfe0..c654df05b7d7 100644 --- a/arch/arm64/kernel/arm64ksyms.c +++ b/arch/arm64/kernel/arm64ksyms.c @@ -33,8 +33,8 @@ EXPORT_SYMBOL(copy_page); EXPORT_SYMBOL(clear_page); /* user mem (segment) */ -EXPORT_SYMBOL(__copy_from_user); -EXPORT_SYMBOL(__copy_to_user); +EXPORT_SYMBOL(__arch_copy_from_user); +EXPORT_SYMBOL(__arch_copy_to_user); EXPORT_SYMBOL(__clear_user); EXPORT_SYMBOL(__copy_in_user); diff --git a/arch/arm64/lib/copy_from_user.S b/arch/arm64/lib/copy_from_user.S index 4699cd74f87e..281e75db899a 100644 --- a/arch/arm64/lib/copy_from_user.S +++ b/arch/arm64/lib/copy_from_user.S @@ -66,7 +66,7 @@ .endm end .req x5 -ENTRY(__copy_from_user) +ENTRY(__arch_copy_from_user) ALTERNATIVE("nop", __stringify(SET_PSTATE_PAN(0)), ARM64_HAS_PAN, \ CONFIG_ARM64_PAN) add end, x0, x2 @@ -75,7 +75,7 @@ ALTERNATIVE("nop", __stringify(SET_PSTATE_PAN(1)), ARM64_HAS_PAN, \ CONFIG_ARM64_PAN) mov x0, #0 // Nothing to copy ret -ENDPROC(__copy_from_user) +ENDPROC(__arch_copy_from_user) .section .fixup,"ax" .align 2 diff --git a/arch/arm64/lib/copy_to_user.S b/arch/arm64/lib/copy_to_user.S index 7512bbbc07ac..db4d187de61f 100644 --- a/arch/arm64/lib/copy_to_user.S +++ b/arch/arm64/lib/copy_to_user.S @@ -65,7 +65,7 @@ .endm end .req x5 -ENTRY(__copy_to_user) +ENTRY(__arch_copy_to_user) ALTERNATIVE("nop", __stringify(SET_PSTATE_PAN(0)), ARM64_HAS_PAN, \ CONFIG_ARM64_PAN) add end, x0, x2 @@ -74,7 +74,7 @@ ALTERNATIVE("nop", __stringify(SET_PSTATE_PAN(1)), ARM64_HAS_PAN, \ CONFIG_ARM64_PAN) mov x0, #0 ret -ENDPROC(__copy_to_user) +ENDPROC(__arch_copy_to_user) .section .fixup,"ax" .align 2 From patchwork Fri Jul 12 05:27:59 2019 Content-Type: text/plain; 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Like we've done for get_user and put_user, ensure that user pointers are masked before invoking the underlying __arch_{clear,copy_*}_user operations. Signed-off-by: Will Deacon Signed-off-by: Catalin Marinas [ v4.4: fixup for v4.4 style uaccess primitives ] Signed-off-by: Viresh Kumar --- arch/arm64/include/asm/uaccess.h | 20 ++++++++++++-------- arch/arm64/kernel/arm64ksyms.c | 4 ++-- arch/arm64/lib/clear_user.S | 6 +++--- arch/arm64/lib/copy_in_user.S | 4 ++-- 4 files changed, 19 insertions(+), 15 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/include/asm/uaccess.h b/arch/arm64/include/asm/uaccess.h index 693a0d784534..a25b8726ffa9 100644 --- a/arch/arm64/include/asm/uaccess.h +++ b/arch/arm64/include/asm/uaccess.h @@ -303,19 +303,20 @@ do { \ extern unsigned long __must_check __arch_copy_from_user(void *to, const void __user *from, unsigned long n); extern unsigned long __must_check __arch_copy_to_user(void __user *to, const void *from, unsigned long n); -extern unsigned long __must_check __copy_in_user(void __user *to, const void __user *from, unsigned long n); -extern unsigned long __must_check __clear_user(void __user *addr, unsigned long n); +extern unsigned long __must_check __arch_copy_in_user(void __user *to, const void __user *from, unsigned long n); static inline unsigned long __must_check __copy_from_user(void *to, const void __user *from, unsigned long n) { kasan_check_write(to, n); - return __arch_copy_from_user(to, from, n); + return __arch_copy_from_user(to, __uaccess_mask_ptr(from), n); + } static inline unsigned long __must_check __copy_to_user(void __user *to, const void *from, unsigned long n) { kasan_check_read(from, n); - return __arch_copy_to_user(to, from, n); + return __arch_copy_to_user(__uaccess_mask_ptr(to), from, n); + } static inline unsigned long __must_check copy_from_user(void *to, const void __user *from, unsigned long n) @@ -338,22 +339,25 @@ static inline unsigned long __must_check copy_to_user(void __user *to, const voi return n; } -static inline unsigned long __must_check copy_in_user(void __user *to, const void __user *from, unsigned long n) +static inline unsigned long __must_check __copy_in_user(void __user *to, const void __user *from, unsigned long n) { if (access_ok(VERIFY_READ, from, n) && access_ok(VERIFY_WRITE, to, n)) - n = __copy_in_user(to, from, n); + n = __arch_copy_in_user(__uaccess_mask_ptr(to), __uaccess_mask_ptr(from), n); return n; } +#define copy_in_user __copy_in_user #define __copy_to_user_inatomic __copy_to_user #define __copy_from_user_inatomic __copy_from_user -static inline unsigned long __must_check clear_user(void __user *to, unsigned long n) +extern unsigned long __must_check __arch_clear_user(void __user *to, unsigned long n); +static inline unsigned long __must_check __clear_user(void __user *to, unsigned long n) { if (access_ok(VERIFY_WRITE, to, n)) - n = __clear_user(__uaccess_mask_ptr(to), n); + n = __arch_clear_user(__uaccess_mask_ptr(to), n); return n; } +#define clear_user __clear_user extern long strncpy_from_user(char *dest, const char __user *src, long count); diff --git a/arch/arm64/kernel/arm64ksyms.c b/arch/arm64/kernel/arm64ksyms.c index c654df05b7d7..abe4e0984dbb 100644 --- a/arch/arm64/kernel/arm64ksyms.c +++ b/arch/arm64/kernel/arm64ksyms.c @@ -35,8 +35,8 @@ EXPORT_SYMBOL(clear_page); /* user mem (segment) */ EXPORT_SYMBOL(__arch_copy_from_user); EXPORT_SYMBOL(__arch_copy_to_user); -EXPORT_SYMBOL(__clear_user); -EXPORT_SYMBOL(__copy_in_user); +EXPORT_SYMBOL(__arch_clear_user); +EXPORT_SYMBOL(__arch_copy_in_user); /* physical memory */ EXPORT_SYMBOL(memstart_addr); diff --git a/arch/arm64/lib/clear_user.S b/arch/arm64/lib/clear_user.S index a9723c71c52b..fc6bb0f83511 100644 --- a/arch/arm64/lib/clear_user.S +++ b/arch/arm64/lib/clear_user.S @@ -24,7 +24,7 @@ .text -/* Prototype: int __clear_user(void *addr, size_t sz) +/* Prototype: int __arch_clear_user(void *addr, size_t sz) * Purpose : clear some user memory * Params : addr - user memory address to clear * : sz - number of bytes to clear @@ -32,7 +32,7 @@ * * Alignment fixed up by hardware. */ -ENTRY(__clear_user) +ENTRY(__arch_clear_user) ALTERNATIVE("nop", __stringify(SET_PSTATE_PAN(0)), ARM64_HAS_PAN, \ CONFIG_ARM64_PAN) mov x2, x1 // save the size for fixup return @@ -57,7 +57,7 @@ USER(9f, strb wzr, [x0] ) ALTERNATIVE("nop", __stringify(SET_PSTATE_PAN(1)), ARM64_HAS_PAN, \ CONFIG_ARM64_PAN) ret -ENDPROC(__clear_user) +ENDPROC(__arch_clear_user) .section .fixup,"ax" .align 2 diff --git a/arch/arm64/lib/copy_in_user.S b/arch/arm64/lib/copy_in_user.S index 81c8fc93c100..0219aa85b3cc 100644 --- a/arch/arm64/lib/copy_in_user.S +++ b/arch/arm64/lib/copy_in_user.S @@ -67,7 +67,7 @@ .endm end .req x5 -ENTRY(__copy_in_user) +ENTRY(__arch_copy_in_user) ALTERNATIVE("nop", __stringify(SET_PSTATE_PAN(0)), ARM64_HAS_PAN, \ CONFIG_ARM64_PAN) add end, x0, x2 @@ -76,7 +76,7 @@ ALTERNATIVE("nop", __stringify(SET_PSTATE_PAN(1)), ARM64_HAS_PAN, \ CONFIG_ARM64_PAN) mov x0, #0 ret -ENDPROC(__copy_in_user) +ENDPROC(__arch_copy_in_user) .section .fixup,"ax" .align 2 From patchwork Fri Jul 12 05:28:00 2019 Content-Type: text/plain; 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[209.132.180.67]) by mx.google.com with ESMTP id e36si5303191pgm.17.2019.07.11.22.29.32; Thu, 11 Jul 2019 22:29:32 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cGmYhryo; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725877AbfGLF3c (ORCPT + 13 others); Fri, 12 Jul 2019 01:29:32 -0400 Received: from mail-pf1-f195.google.com ([209.85.210.195]:43502 "EHLO mail-pf1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725791AbfGLF3c (ORCPT ); Fri, 12 Jul 2019 01:29:32 -0400 Received: by mail-pf1-f195.google.com with SMTP id i189so3784679pfg.10 for ; Thu, 11 Jul 2019 22:29:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/kfHaZYBMHfOrWZM24aWUbS5m2tlkmGASsL26R9/1y0=; b=cGmYhryoCvANnaH4geFrp/J9iYbsc93CKBZgUMA9oUfaIiy5wdBhR4DlJmw3lRYYkA aVW9vCmzdn45ZIMZ1dMMq/N8JVs1GCVa8B89kv/v7c3FKhtB39xYSiG73QQR4kuM3JAb cL1tc5wyGgB1cEYzqSLcMKjG3Zfs2ngs3HKGI2Fy4Xyuya6kSkwu/P5920GkpBbj4Wk5 0q+nHiS2Ldbb8I+Wr9P0dryCEaZ2EiWQbjXGgDW2oeZoZQq2mF8seW0WrqTaTajMVkse GAdrTI0Kwc1mmnP0MN7Jp2dKsjRroebJ8GorFrfv+bWbEsgna60JLumwtDgx9vOMEbyA /O1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/kfHaZYBMHfOrWZM24aWUbS5m2tlkmGASsL26R9/1y0=; b=oc9m+7Gwzd57Vqbm0wXOkrw44ElTrILA5Z+vTfsu7N7vmv4LL+AAJIpaEPLS/lH5Mg Tjqd6HREcF46ns5ONXue0yOEVrD7pqpD1h1ies3eiYzRlRh0au4RqNvdCTCS2OiwXCuY TndjILNRSHQPNLLwm6na5Z1H3xh+FGSU1uOmDXOwFqBThe2ttUSz2VwI8i2LvTdipF6p hJerLulQjW9mAxxGEIPVLuVR/NyIsuwh+YomgTmiBngABk90UkF/8JMhkRAwdn6nQHoG HrhmVZ/QydL+AWfP9TUw+gUdqNTZW4KWXbiLWhGlRfZIrBpeadTv5/mKIOnDH/XHmRa/ 7S1Q== X-Gm-Message-State: APjAAAXoSNjVYTfwg+nGgGNtme8yxb+HgpbUVKdphNhiTCuL22rtI4hj l2vkjeRlInRPzjhvo/vmV09wozqJSvs= X-Received: by 2002:a63:6981:: with SMTP id e123mr8520931pgc.136.1562909371293; Thu, 11 Jul 2019 22:29:31 -0700 (PDT) Received: from localhost ([122.172.28.117]) by smtp.gmail.com with ESMTPSA id e6sm8850058pfn.71.2019.07.11.22.29.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 11 Jul 2019 22:29:30 -0700 (PDT) From: Viresh Kumar To: stable@vger.kernel.org, Julien Thierry Cc: Viresh Kumar , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Marc Zyngier , Mark Rutland , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: [PATCH v4.4 V2 12/43] arm64: cpufeature: Test 'matches' pointer to find the end of the list Date: Fri, 12 Jul 2019 10:58:00 +0530 Message-Id: <64c9f2c29cd2e63aecbd233aa96fd9d18e165330.1562908075.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: James Morse commit 644c2ae198412c956700e55a2acf80b2541f6aa5 upstream. CPU feature code uses the desc field as a test to find the end of the list, this means every entry must have a description. This generates noise for entries in the list that aren't really features, but combinations of them. e.g. > CPU features: detected feature: Privileged Access Never > CPU features: detected feature: PAN and not UAO These combination features are needed for corner cases with alternatives, where cpu features interact. Change all walkers of the arm64_features[] and arm64_hwcaps[] lists to test 'matches' not 'desc', and only print 'desc' if it is non-NULL. Signed-off-by: James Morse Reviewed-by : Suzuki K Poulose Signed-off-by: Catalin Marinas Signed-off-by: Viresh Kumar --- arch/arm64/kernel/cpufeature.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index c1eddc07d996..bdb4cd9ffccf 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -744,7 +744,7 @@ static void setup_cpu_hwcaps(void) int i; const struct arm64_cpu_capabilities *hwcaps = arm64_hwcaps; - for (i = 0; hwcaps[i].desc; i++) + for (i = 0; hwcaps[i].matches; i++) if (hwcaps[i].matches(&hwcaps[i])) cap_set_hwcap(&hwcaps[i]); } @@ -754,11 +754,11 @@ void update_cpu_capabilities(const struct arm64_cpu_capabilities *caps, { int i; - for (i = 0; caps[i].desc; i++) { + for (i = 0; caps[i].matches; i++) { if (!caps[i].matches(&caps[i])) continue; - if (!cpus_have_cap(caps[i].capability)) + if (!cpus_have_cap(caps[i].capability) && caps[i].desc) pr_info("%s %s\n", info, caps[i].desc); cpus_set_cap(caps[i].capability); } @@ -772,7 +772,7 @@ static void enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps) { int i; - for (i = 0; caps[i].desc; i++) + for (i = 0; caps[i].matches; i++) if (caps[i].enable && cpus_have_cap(caps[i].capability)) /* * Use stop_machine() as it schedules the work allowing @@ -884,7 +884,7 @@ void verify_local_cpu_capabilities(void) return; caps = arm64_features; - for (i = 0; caps[i].desc; i++) { + for (i = 0; caps[i].matches; i++) { if (!cpus_have_cap(caps[i].capability) || !caps[i].sys_reg) continue; /* @@ -897,7 +897,7 @@ void verify_local_cpu_capabilities(void) caps[i].enable(NULL); } - for (i = 0, caps = arm64_hwcaps; caps[i].desc; i++) { + for (i = 0, caps = arm64_hwcaps; caps[i].matches; i++) { if (!cpus_have_hwcap(&caps[i])) continue; if (!feature_matches(__raw_read_system_reg(caps[i].sys_reg), &caps[i])) From patchwork Fri Jul 12 05:28:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 168872 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp394713ilk; Thu, 11 Jul 2019 22:29:35 -0700 (PDT) X-Google-Smtp-Source: APXvYqzdNyPwXj/y4IzguKgJX0JW44hznQprgcl5aq7lGIiuIv7u0QRBKVH8w8kxPaJ1zfIao6fq X-Received: by 2002:a17:90a:3225:: with SMTP id k34mr9264654pjb.31.1562909375897; Thu, 11 Jul 2019 22:29:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1562909375; cv=none; d=google.com; s=arc-20160816; b=qBMK4wCo3Dscz285pe/J+DkXOFxifdhCzLcjcWGs/bSr3Op1uHb6zcAirm/Yb6hl68 /pQ7w1JqevCZ1UuQBgYZObJo2pah1mih6ZfYB+1HaSErWAp4wroBlAIPfsw+sHP7p/uv sOWiO+erucBJsqgZZ/RpUx720xhX2/nnpwLG3tV5JbWFIBjU9BkN5O7Y8uwFMCFkdl/B AhYpro2bu/S2Gm24Lkc8rbedrf1M6lXlQmYiK3WWgZ1+RQDoyk0MFFTl2CGP+mfJ2YYW RtVirYXP0ejPhiimULp2RGj85AlcRUc/ac3x5FyLrTw0BwBWh5jOGdf61ahnGjuDxLBe NT4g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=+8jS5wU9g41nb7lUYf6O/ux0jWphtxOIXXxsA7/oFkw=; b=X/7yUqB6L6Ml4RuQHKIlfOISYvr/ftx19Rs4ouKAZG7Dzu72Cn5MthHHf1ILt/yT9Y KEI3vudxemxsFVve4+NDilEZVV/G4Y3V55hqr1Y5XSr6doSAocvr1o8s/5p4UN7PPeLo zxzPgel2QS9AAFn15buJaPRul4XiRv3ZavbAybcE6FnyO8qa3FttB70wGtz0cqW7i38Y vMUMugcVRPB47DYimRp2TpYKFTtVuHryRRVqYoH0UfEjhWn/PfAoOvwFd8tR0dXMEB/b 0FmSS4tEkNQBiYvpVLUW2XjEyZ0Xkd3IrrGNu3Au6oJyDCCCA7dlw13IGxgvtLBU/yaw DiEw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=KNfBp1g7; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e36si5303191pgm.17.2019.07.11.22.29.35; Thu, 11 Jul 2019 22:29:35 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=KNfBp1g7; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725912AbfGLF3f (ORCPT + 13 others); Fri, 12 Jul 2019 01:29:35 -0400 Received: from mail-pl1-f193.google.com ([209.85.214.193]:44227 "EHLO mail-pl1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725791AbfGLF3f (ORCPT ); Fri, 12 Jul 2019 01:29:35 -0400 Received: by mail-pl1-f193.google.com with SMTP id t14so4187046plr.11 for ; Thu, 11 Jul 2019 22:29:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+8jS5wU9g41nb7lUYf6O/ux0jWphtxOIXXxsA7/oFkw=; b=KNfBp1g7S4eqR+RS92e7dLDP25RNS8lVmmr0lVF3A3MVIeuCHTEWx2dZYm3JSYgeOS +Jr6R2CWWlQU0MVR1YYad4On7zYD/qlaFG1j3LNdyrNLYoCKK6VE62z6/fzOI36xKcjK Eh6LTNogo1BK2DDZlAiBpgCYKHRxUwsZUsYhLO4jQmFkSPzUR5d8LG5ttCHhlC2U1kLZ j/7zXQgjvO/M701xXz0CZCTX1fBr3EGW+8PVZvc61QCjcElZY/tsei+BpoS1fk9EYCL6 UaVK+UFMou7Ej7D0NRLSAc8uHuHklSOAVHd02USXT1BBXe/kcxrJfHPeco+/wjGEx4Vc hkrA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+8jS5wU9g41nb7lUYf6O/ux0jWphtxOIXXxsA7/oFkw=; b=hl+jgj9fifcKU7/juYUBmOOrX2+Xkd/TZH5f8a/iTzRQoTWrtzZTZUYg/YYG17J8bt qVG2g6W5End+Zo+m/qHRwwXdn+DTU7jp7927a4kDyvABkZW7iNwy1Ptq6V7+lGIn4dK+ ZwxNUhPuP+vP6cVIRUBnZjZvacuoMuYoN/Z1C2kgL9oOnbssf04Z3BDl09DKkLnqbKOd +Qn3NpHn+paoZGD4Su84yPrmjvGn2f/T2qsUR3+vOfg/26JkM73eA++89lvfhSQ1RYjX /rXN4hZlKpvZi7JrOXT3Qdscw+FuFt/zGk+ongawX4fmwJEYCmnN5l4LLYsm513L6vm5 ry1w== X-Gm-Message-State: APjAAAWog/4sSAr844WorlcC8Amie4sWzK0c3BbLoZJxJQNMsoeiM+TO n+5M06HhDS470gyajO6OFks3tvOsrgQ= X-Received: by 2002:a17:902:ff05:: with SMTP id f5mr8894647plj.116.1562909373996; Thu, 11 Jul 2019 22:29:33 -0700 (PDT) Received: from localhost ([122.172.28.117]) by smtp.gmail.com with ESMTPSA id 33sm13035023pgy.22.2019.07.11.22.29.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 11 Jul 2019 22:29:33 -0700 (PDT) From: Viresh Kumar To: stable@vger.kernel.org, Julien Thierry Cc: Viresh Kumar , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Marc Zyngier , Mark Rutland , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: [PATCH v4.4 V2 13/43] arm64: cpufeature: Add scope for capability check Date: Fri, 12 Jul 2019 10:58:01 +0530 Message-Id: <6fbec5c89811c069dcfaaaf55ad708c5f0922020.1562908075.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Suzuki K Poulose commit 92406f0cc9e3d5cc77bf3de6d68c9c2373dcd701 upstream. Add scope parameter to the arm64_cpu_capabilities::matches(), so that this can be reused for checking the capability on a given CPU vs the system wide. The system uses the default scope associated with the capability for initialising the CPU_HWCAPs and ELF_HWCAPs. Cc: James Morse Cc: Marc Zyngier Cc: Andre Przywara Cc: Will Deacon Reviewed-by: Catalin Marinas Signed-off-by: Suzuki K Poulose Signed-off-by: Will Deacon [ v4.4: Changes made according to 4.4 codebase ] Signed-off-by: Viresh Kumar --- arch/arm64/include/asm/cpufeature.h | 9 ++- arch/arm64/kernel/cpu_errata.c | 5 +- arch/arm64/kernel/cpufeature.c | 105 +++++++++++++++------------- 3 files changed, 70 insertions(+), 49 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h index ad83c245781c..4c31e14c0f0e 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -74,10 +74,17 @@ struct arm64_ftr_reg { struct arm64_ftr_bits *ftr_bits; }; +/* scope of capability check */ +enum { + SCOPE_SYSTEM, + SCOPE_LOCAL_CPU, +}; + struct arm64_cpu_capabilities { const char *desc; u16 capability; - bool (*matches)(const struct arm64_cpu_capabilities *); + int def_scope; /* default scope */ + bool (*matches)(const struct arm64_cpu_capabilities *caps, int scope); int (*enable)(void *); /* Called on all active CPUs */ union { struct { /* To be used for erratum handling only */ diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index a3e846a28b05..0971d80d3623 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -29,10 +29,12 @@ MIDR_ARCHITECTURE_MASK) static bool __maybe_unused -is_affected_midr_range(const struct arm64_cpu_capabilities *entry) +is_affected_midr_range(const struct arm64_cpu_capabilities *entry, int scope) { u32 midr = read_cpuid_id(); + WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); + if ((midr & CPU_MODEL_MASK) != entry->midr_model) return false; @@ -42,6 +44,7 @@ is_affected_midr_range(const struct arm64_cpu_capabilities *entry) } #define MIDR_RANGE(model, min, max) \ + .def_scope = SCOPE_LOCAL_CPU, \ .matches = is_affected_midr_range, \ .midr_model = model, \ .midr_range_min = min, \ diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index bdb4cd9ffccf..d0c82bc02de4 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -589,6 +589,48 @@ u64 read_system_reg(u32 id) return regp->sys_val; } +/* + * __raw_read_system_reg() - Used by a STARTING cpu before cpuinfo is populated. + * Read the system register on the current CPU + */ +static u64 __raw_read_system_reg(u32 sys_id) +{ + switch (sys_id) { + case SYS_ID_PFR0_EL1: return (u64)read_cpuid(ID_PFR0_EL1); + case SYS_ID_PFR1_EL1: return (u64)read_cpuid(ID_PFR1_EL1); + case SYS_ID_DFR0_EL1: return (u64)read_cpuid(ID_DFR0_EL1); + case SYS_ID_MMFR0_EL1: return (u64)read_cpuid(ID_MMFR0_EL1); + case SYS_ID_MMFR1_EL1: return (u64)read_cpuid(ID_MMFR1_EL1); + case SYS_ID_MMFR2_EL1: return (u64)read_cpuid(ID_MMFR2_EL1); + case SYS_ID_MMFR3_EL1: return (u64)read_cpuid(ID_MMFR3_EL1); + case SYS_ID_ISAR0_EL1: return (u64)read_cpuid(ID_ISAR0_EL1); + case SYS_ID_ISAR1_EL1: return (u64)read_cpuid(ID_ISAR1_EL1); + case SYS_ID_ISAR2_EL1: return (u64)read_cpuid(ID_ISAR2_EL1); + case SYS_ID_ISAR3_EL1: return (u64)read_cpuid(ID_ISAR3_EL1); + case SYS_ID_ISAR4_EL1: return (u64)read_cpuid(ID_ISAR4_EL1); + case SYS_ID_ISAR5_EL1: return (u64)read_cpuid(ID_ISAR4_EL1); + case SYS_MVFR0_EL1: return (u64)read_cpuid(MVFR0_EL1); + case SYS_MVFR1_EL1: return (u64)read_cpuid(MVFR1_EL1); + case SYS_MVFR2_EL1: return (u64)read_cpuid(MVFR2_EL1); + + case SYS_ID_AA64PFR0_EL1: return (u64)read_cpuid(ID_AA64PFR0_EL1); + case SYS_ID_AA64PFR1_EL1: return (u64)read_cpuid(ID_AA64PFR0_EL1); + case SYS_ID_AA64DFR0_EL1: return (u64)read_cpuid(ID_AA64DFR0_EL1); + case SYS_ID_AA64DFR1_EL1: return (u64)read_cpuid(ID_AA64DFR0_EL1); + case SYS_ID_AA64MMFR0_EL1: return (u64)read_cpuid(ID_AA64MMFR0_EL1); + case SYS_ID_AA64MMFR1_EL1: return (u64)read_cpuid(ID_AA64MMFR1_EL1); + case SYS_ID_AA64ISAR0_EL1: return (u64)read_cpuid(ID_AA64ISAR0_EL1); + case SYS_ID_AA64ISAR1_EL1: return (u64)read_cpuid(ID_AA64ISAR1_EL1); + + case SYS_CNTFRQ_EL0: return (u64)read_cpuid(CNTFRQ_EL0); + case SYS_CTR_EL0: return (u64)read_cpuid(CTR_EL0); + case SYS_DCZID_EL0: return (u64)read_cpuid(DCZID_EL0); + default: + BUG(); + return 0; + } +} + #include static bool @@ -600,19 +642,24 @@ feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry) } static bool -has_cpuid_feature(const struct arm64_cpu_capabilities *entry) +has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) { u64 val; - val = read_system_reg(entry->sys_reg); + WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); + if (scope == SCOPE_SYSTEM) + val = read_system_reg(entry->sys_reg); + else + val = __raw_read_system_reg(entry->sys_reg); + return feature_matches(val, entry); } -static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry) +static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope) { bool has_sre; - if (!has_cpuid_feature(entry)) + if (!has_cpuid_feature(entry, scope)) return false; has_sre = gic_enable_sre(); @@ -627,6 +674,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { { .desc = "GIC system register CPU interface", .capability = ARM64_HAS_SYSREG_GIC_CPUIF, + .def_scope = SCOPE_SYSTEM, .matches = has_useable_gicv3_cpuif, .sys_reg = SYS_ID_AA64PFR0_EL1, .field_pos = ID_AA64PFR0_GIC_SHIFT, @@ -636,6 +684,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { { .desc = "Privileged Access Never", .capability = ARM64_HAS_PAN, + .def_scope = SCOPE_SYSTEM, .matches = has_cpuid_feature, .sys_reg = SYS_ID_AA64MMFR1_EL1, .field_pos = ID_AA64MMFR1_PAN_SHIFT, @@ -647,6 +696,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { { .desc = "LSE atomic instructions", .capability = ARM64_HAS_LSE_ATOMICS, + .def_scope = SCOPE_SYSTEM, .matches = has_cpuid_feature, .sys_reg = SYS_ID_AA64ISAR0_EL1, .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT, @@ -656,6 +706,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { { .desc = "32-bit EL0 Support", .capability = ARM64_HAS_32BIT_EL0, + .def_scope = SCOPE_SYSTEM, .matches = has_cpuid_feature, .sys_reg = SYS_ID_AA64PFR0_EL1, .field_pos = ID_AA64PFR0_EL0_SHIFT, @@ -667,6 +718,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { #define HWCAP_CAP(reg, field, min_value, type, cap) \ { \ .desc = #cap, \ + .def_scope = SCOPE_SYSTEM, \ .matches = has_cpuid_feature, \ .sys_reg = reg, \ .field_pos = field, \ @@ -745,7 +797,7 @@ static void setup_cpu_hwcaps(void) const struct arm64_cpu_capabilities *hwcaps = arm64_hwcaps; for (i = 0; hwcaps[i].matches; i++) - if (hwcaps[i].matches(&hwcaps[i])) + if (hwcaps[i].matches(&hwcaps[i], hwcaps[i].def_scope)) cap_set_hwcap(&hwcaps[i]); } @@ -755,7 +807,7 @@ void update_cpu_capabilities(const struct arm64_cpu_capabilities *caps, int i; for (i = 0; caps[i].matches; i++) { - if (!caps[i].matches(&caps[i])) + if (!caps[i].matches(&caps[i], caps[i].def_scope)) continue; if (!cpus_have_cap(caps[i].capability) && caps[i].desc) @@ -800,47 +852,6 @@ static inline void set_sys_caps_initialised(void) sys_caps_initialised = true; } -/* - * __raw_read_system_reg() - Used by a STARTING cpu before cpuinfo is populated. - */ -static u64 __raw_read_system_reg(u32 sys_id) -{ - switch (sys_id) { - case SYS_ID_PFR0_EL1: return (u64)read_cpuid(ID_PFR0_EL1); - case SYS_ID_PFR1_EL1: return (u64)read_cpuid(ID_PFR1_EL1); - case SYS_ID_DFR0_EL1: return (u64)read_cpuid(ID_DFR0_EL1); - case SYS_ID_MMFR0_EL1: return (u64)read_cpuid(ID_MMFR0_EL1); - case SYS_ID_MMFR1_EL1: return (u64)read_cpuid(ID_MMFR1_EL1); - case SYS_ID_MMFR2_EL1: return (u64)read_cpuid(ID_MMFR2_EL1); - case SYS_ID_MMFR3_EL1: return (u64)read_cpuid(ID_MMFR3_EL1); - case SYS_ID_ISAR0_EL1: return (u64)read_cpuid(ID_ISAR0_EL1); - case SYS_ID_ISAR1_EL1: return (u64)read_cpuid(ID_ISAR1_EL1); - case SYS_ID_ISAR2_EL1: return (u64)read_cpuid(ID_ISAR2_EL1); - case SYS_ID_ISAR3_EL1: return (u64)read_cpuid(ID_ISAR3_EL1); - case SYS_ID_ISAR4_EL1: return (u64)read_cpuid(ID_ISAR4_EL1); - case SYS_ID_ISAR5_EL1: return (u64)read_cpuid(ID_ISAR4_EL1); - case SYS_MVFR0_EL1: return (u64)read_cpuid(MVFR0_EL1); - case SYS_MVFR1_EL1: return (u64)read_cpuid(MVFR1_EL1); - case SYS_MVFR2_EL1: return (u64)read_cpuid(MVFR2_EL1); - - case SYS_ID_AA64PFR0_EL1: return (u64)read_cpuid(ID_AA64PFR0_EL1); - case SYS_ID_AA64PFR1_EL1: return (u64)read_cpuid(ID_AA64PFR0_EL1); - case SYS_ID_AA64DFR0_EL1: return (u64)read_cpuid(ID_AA64DFR0_EL1); - case SYS_ID_AA64DFR1_EL1: return (u64)read_cpuid(ID_AA64DFR0_EL1); - case SYS_ID_AA64MMFR0_EL1: return (u64)read_cpuid(ID_AA64MMFR0_EL1); - case SYS_ID_AA64MMFR1_EL1: return (u64)read_cpuid(ID_AA64MMFR1_EL1); - case SYS_ID_AA64ISAR0_EL1: return (u64)read_cpuid(ID_AA64ISAR0_EL1); - case SYS_ID_AA64ISAR1_EL1: return (u64)read_cpuid(ID_AA64ISAR1_EL1); - - case SYS_CNTFRQ_EL0: return (u64)read_cpuid(CNTFRQ_EL0); - case SYS_CTR_EL0: return (u64)read_cpuid(CTR_EL0); - case SYS_DCZID_EL0: return (u64)read_cpuid(DCZID_EL0); - default: - BUG(); - return 0; - } -} - /* * Park the CPU which doesn't have the capability as advertised * by the system. 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[209.132.180.67]) by mx.google.com with ESMTP id e36si5303191pgm.17.2019.07.11.22.29.38; Thu, 11 Jul 2019 22:29:38 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=LTGjy4Rb; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726062AbfGLF3h (ORCPT + 13 others); Fri, 12 Jul 2019 01:29:37 -0400 Received: from mail-pl1-f194.google.com ([209.85.214.194]:43940 "EHLO mail-pl1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725791AbfGLF3h (ORCPT ); Fri, 12 Jul 2019 01:29:37 -0400 Received: by mail-pl1-f194.google.com with SMTP id cl9so4183467plb.10 for ; Thu, 11 Jul 2019 22:29:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZERHer/S6V7v3IyXGHBRQXsjn5NA4nSXv7B2aoThKNw=; b=LTGjy4RbPjl9R3s4FBJE7KxiWqlXV2Jf5Pd7wO0KzlxPr4SUYEcUciTXuVXj7usHms PBQ0GacQJxLledV6d0cVnlYP7EdoN0ibucpvd5Ox2iDnM4lDcvrfAwBw9U3rins3V+uC C8hekJ0VKJ136OK57vbzVb/TQ2PkcO7zGjqhj+zavYVK/VEoiPLQXx5n5kxQm+P2TCHu QhCYjQR9YE9M+lQtk+SbouEYzEG5+J9vd5nBHptbGKNBegltTaQCKUt7YlzFwAelFi3i qFYfmRpohadOUJwGsZgQSyedLaAGEjxeLe/Fn5VrzZ0NCbgkUnncJO0AbbF5RRNRniql Ok3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZERHer/S6V7v3IyXGHBRQXsjn5NA4nSXv7B2aoThKNw=; b=JIx8lxTEXCoz0656elWgJ/CvVdXLXQgGVUhLXvCGMJ3c+VDJfoqPH6ZMNdg3HW3Ris Jkvyl/4lFFgTYEUtmOLUaQ6OBRAlDGnb2VRH+wXTDcR3tTdUj9QebLx/tIU3H8BB/Bgl GRQLKwHPBsYPSqIx91noHUz3pzCgZObNc/GPq31yw1RyeUaGO1xmCo9MHbJEXzkl3CtR mmWGGVCceGW9i/Q1vSK09YRWxXJWvziIBdr6/mIIQ6bHeE0lF7us+tclKCc2HqyEY+MM hFvHtmE9DBo+Vkgew/SRXb9ksfPhtbD9ALbBVUU2bR8fP5n9WwOERuWcHUTLGojx9lDh Kfmg== X-Gm-Message-State: APjAAAVXHfOqEwX1ZKHt9Zn256OoegjUyqKlZ4QtYD+kEUvhi8EAqwIi KwfEjKMOVAfk/Gsm4enGeTMQallSkpk= X-Received: by 2002:a17:902:8b88:: with SMTP id ay8mr8861169plb.139.1562909376770; Thu, 11 Jul 2019 22:29:36 -0700 (PDT) Received: from localhost ([122.172.28.117]) by smtp.gmail.com with ESMTPSA id n98sm6937170pjc.26.2019.07.11.22.29.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 11 Jul 2019 22:29:36 -0700 (PDT) From: Viresh Kumar To: stable@vger.kernel.org, Julien Thierry Cc: Viresh Kumar , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Marc Zyngier , Mark Rutland , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: [PATCH v4.4 V2 14/43] arm64: Introduce cpu_die_early Date: Fri, 12 Jul 2019 10:58:02 +0530 Message-Id: X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Suzuki K Poulose commit ee02a15919cf86c004142edaa05b43f7ff10edf0 upstream. Or in other words, make fail_incapable_cpu() reusable. We use fail_incapable_cpu() to kill a secondary CPU early during the bringup, which doesn't have the system advertised capabilities. This patch makes the routine more generic, to kill a secondary booting CPU, getting rid of the dependency on capability struct. This can be used by checks which are not necessarily attached to a capability struct (e.g, cpu ASIDBits). In that process, renames the function to cpu_die_early() to better match its functionality. This will be moved to arch/arm64/kernel/smp.c later. Cc: Mark Rutland Acked-by: Will Deacon Signed-off-by: Suzuki K Poulose Signed-off-by: Catalin Marinas Signed-off-by: Viresh Kumar --- arch/arm64/kernel/cpufeature.c | 24 +++++++++++++++--------- 1 file changed, 15 insertions(+), 9 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index d0c82bc02de4..b7f01bf47988 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -853,15 +853,15 @@ static inline void set_sys_caps_initialised(void) } /* - * Park the CPU which doesn't have the capability as advertised - * by the system. + * Kill the calling secondary CPU, early in bringup before it is turned + * online. */ -static void fail_incapable_cpu(char *cap_type, - const struct arm64_cpu_capabilities *cap) +void cpu_die_early(void) { int cpu = smp_processor_id(); - pr_crit("CPU%d: missing %s : %s\n", cpu, cap_type, cap->desc); + pr_crit("CPU%d: will not boot\n", cpu); + /* Mark this CPU absent */ set_cpu_present(cpu, 0); @@ -902,8 +902,11 @@ void verify_local_cpu_capabilities(void) * If the new CPU misses an advertised feature, we cannot proceed * further, park the cpu. */ - if (!feature_matches(__raw_read_system_reg(caps[i].sys_reg), &caps[i])) - fail_incapable_cpu("arm64_features", &caps[i]); + if (!feature_matches(__raw_read_system_reg(caps[i].sys_reg), &caps[i])) { + pr_crit("CPU%d: missing feature: %s\n", + smp_processor_id(), caps[i].desc); + cpu_die_early(); + } if (caps[i].enable) caps[i].enable(NULL); } @@ -911,8 +914,11 @@ void verify_local_cpu_capabilities(void) for (i = 0, caps = arm64_hwcaps; caps[i].matches; i++) { if (!cpus_have_hwcap(&caps[i])) continue; - if (!feature_matches(__raw_read_system_reg(caps[i].sys_reg), &caps[i])) - fail_incapable_cpu("arm64_hwcaps", &caps[i]); + if (!feature_matches(__raw_read_system_reg(caps[i].sys_reg), &caps[i])) { + pr_crit("CPU%d: missing HWCAP: %s\n", + smp_processor_id(), caps[i].desc); + cpu_die_early(); + } } } From patchwork Fri Jul 12 05:28:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 168874 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp394788ilk; Thu, 11 Jul 2019 22:29:41 -0700 (PDT) X-Google-Smtp-Source: APXvYqzxNR5V3OPirVA1E4zhOy/332efnqoMsTWp2k17s35kaGesHYbo4MYijatQ7YEN1kN51gQQ X-Received: by 2002:a65:5248:: with SMTP id q8mr8582620pgp.259.1562909381298; Thu, 11 Jul 2019 22:29:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1562909381; cv=none; d=google.com; s=arc-20160816; b=Broy3rCiLS0RTf637kzQWZKba6LLkmhVVZ/wxR7AhLQjnRVPfB5HSA1cFqHWGHiy85 dHrF1nF0qGwKmd7Yx8KXMSt6guL5x+Zxv2ie+1BfyW1w3AIFzRFA6lSanzOgXSqN+86Q ragPLotJ1kTE6ZuEjubKCsYgVQu5S7m12aAKOnGQe4pxl7GebYSlE6VtTn0hblQOYH+H QZI0uG+wXpXm3YWMQ4CYtbJ4pYbKGUQPsZEX1bCR2SpVewnpmFOFwRfvBWYAbIohk1LX d8VN/wK9j5zZer9n84myFfKCbNfx8w5GIL+YuGNlMjv0dV5arYTDkFE2/W1ocKS6QO6d wofw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=XsKw19fTFieNWoM6VpeUN2a175ttgnWqs3kt6rmh49I=; b=ejG4t1tjz6Y0ySS7iuIXhqMEY+xyPTCHbgF92zryOZOqrDY4z8ZAZVW9SFd59HkdMt 515LNmsgYVRWM0avvUYZGmgcVnvZzxuOC/79VL3SElZ37fo2T6oBIVy0MnMXjWlI1mi8 jVJPrHhoTIP4xlpfc4ZE6dNUnCblGECQ4yjLjFpVRHTar5SN2d5E0ixTxptceNLwcpCA P6MWM2UOUmqyh+CTcsyrtyIny8UU91NepxYsVFWCE8NIur1VpeUlxVE/NukJcLEqhUiW akjtpIyYdc1H9PhmGVo18BnjMkiSnbAW/a1uB/FuWhhjPh6fBPfCKEM+ZBeYvL5cnELa OIOw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iKPYCzvW; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e36si5303191pgm.17.2019.07.11.22.29.41; Thu, 11 Jul 2019 22:29:41 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iKPYCzvW; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725989AbfGLF3k (ORCPT + 13 others); Fri, 12 Jul 2019 01:29:40 -0400 Received: from mail-pl1-f196.google.com ([209.85.214.196]:34374 "EHLO mail-pl1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725791AbfGLF3k (ORCPT ); Fri, 12 Jul 2019 01:29:40 -0400 Received: by mail-pl1-f196.google.com with SMTP id i2so4215147plt.1 for ; Thu, 11 Jul 2019 22:29:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=XsKw19fTFieNWoM6VpeUN2a175ttgnWqs3kt6rmh49I=; b=iKPYCzvWW+66Pm/bOsNKrq5P7zLX7Gse55VsuCQJOKsYEXQJgYwZTl6ufTBi8ViuYK HVqUasJBncLGzqVq0OTEzoIpb21awZWXmMarGQg9BhWocyAf+boX3+XyZL9aO5fa20VQ NF1Qswif37U9oRv/De8zZokR8aXCAren/Vq91hDz3kBpLbpAV5sfYUHeSUrPRQaslkcz qVCNFXtFGaxFNIf+YJg1oWWhKMDwoYNEnadjNsjigTvmD1kqDDXndRa3Ktej+sBYoTaK /utuZ7pqW9y8QXFOKLw704iIzoo5Qarpys4miw0IMnmfvclAOvlmTL5awCM03/XljFsO +zIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XsKw19fTFieNWoM6VpeUN2a175ttgnWqs3kt6rmh49I=; b=of72YPMmPOcSehz5MXZPjADjBUKRqB6hKTLT1K+FNVMD5bToOiWZHdow8j8vbGKMMe N+ci6WwTIZI5ehghA2L1NBoZorRtLTVh4U+6DgUHjvHF0e8blEXuk9azn31oeaparbJf gt3Z5Bp6t3VJrMhSmuERegTxi9YlVrP3bEY1J5J0vHzh84HroifCn332TMfOiVycEn/8 0+UOSaUDCvNgUXnkxzp1sNxp4yImNEa2rramzDic73Wis6jdnv6GpPX7JMC7ttbCwv6H UG8bBKCseWpm3MK8pDaqRUAgyBHwYDuXTBMSvRLfKqfCDVHsNsbQ+7XznLA5VCdQjFhR MAzQ== X-Gm-Message-State: APjAAAWnl1qb2F7WE6SwJoOt/73A7KDA3kDuLurGDD8BVFQjWW4F6oFG sieUOswuHWTl9fYrSZm/x4jiBAuQ4fQ= X-Received: by 2002:a17:902:aa09:: with SMTP id be9mr8935831plb.52.1562909379536; Thu, 11 Jul 2019 22:29:39 -0700 (PDT) Received: from localhost ([122.172.28.117]) by smtp.gmail.com with ESMTPSA id 131sm10394940pfx.57.2019.07.11.22.29.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 11 Jul 2019 22:29:39 -0700 (PDT) From: Viresh Kumar To: stable@vger.kernel.org, Julien Thierry Cc: Viresh Kumar , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Marc Zyngier , Mark Rutland , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: [PATCH v4.4 V2 15/43] arm64: Move cpu_die_early to smp.c Date: Fri, 12 Jul 2019 10:58:03 +0530 Message-Id: X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Suzuki K Poulose commit fce6361fe9b0caeba0c05b7d72ceda406f8780df upstream. This patch moves cpu_die_early to smp.c, where it fits better. No functional changes, except for adding the necessary checks for CONFIG_HOTPLUG_CPU. Cc: Mark Rutland Acked-by: Will Deacon Signed-off-by: Suzuki K Poulose Signed-off-by: Catalin Marinas [ Viresh: Resolved rebase conflict ] Signed-off-by: Viresh Kumar --- arch/arm64/include/asm/smp.h | 1 + arch/arm64/kernel/cpufeature.c | 22 ---------------------- arch/arm64/kernel/smp.c | 25 +++++++++++++++++++++++++ 3 files changed, 26 insertions(+), 22 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/include/asm/smp.h b/arch/arm64/include/asm/smp.h index d9c3d6a6100a..13ce01fe6237 100644 --- a/arch/arm64/include/asm/smp.h +++ b/arch/arm64/include/asm/smp.h @@ -68,5 +68,6 @@ extern int __cpu_disable(void); extern void __cpu_die(unsigned int cpu); extern void cpu_die(void); +extern void cpu_die_early(void); #endif /* ifndef __ASM_SMP_H */ diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index b7f01bf47988..a0273cd8be51 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -852,28 +852,6 @@ static inline void set_sys_caps_initialised(void) sys_caps_initialised = true; } -/* - * Kill the calling secondary CPU, early in bringup before it is turned - * online. - */ -void cpu_die_early(void) -{ - int cpu = smp_processor_id(); - - pr_crit("CPU%d: will not boot\n", cpu); - - /* Mark this CPU absent */ - set_cpu_present(cpu, 0); - - /* Check if we can park ourselves */ - if (cpu_ops[cpu] && cpu_ops[cpu]->cpu_die) - cpu_ops[cpu]->cpu_die(cpu); - asm( - "1: wfe\n" - " wfi\n" - " b 1b"); -} - /* * Run through the enabled system capabilities and enable() it on this CPU. * The capabilities were decided based on the available CPUs at the boot time. diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c index 03c0946b79d2..752b53daac23 100644 --- a/arch/arm64/kernel/smp.c +++ b/arch/arm64/kernel/smp.c @@ -312,6 +312,31 @@ void cpu_die(void) } #endif +/* + * Kill the calling secondary CPU, early in bringup before it is turned + * online. + */ +void cpu_die_early(void) +{ + int cpu = smp_processor_id(); + + pr_crit("CPU%d: will not boot\n", cpu); + + /* Mark this CPU absent */ + set_cpu_present(cpu, 0); + +#ifdef CONFIG_HOTPLUG_CPU + /* Check if we can park ourselves */ + if (cpu_ops[cpu] && cpu_ops[cpu]->cpu_die) + cpu_ops[cpu]->cpu_die(cpu); +#endif + + asm( + "1: wfe\n" + " wfi\n" + " b 1b"); +} + static void __init hyp_mode_check(void) { if (is_hyp_mode_available()) From patchwork Fri Jul 12 05:28:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 168875 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp394817ilk; Thu, 11 Jul 2019 22:29:44 -0700 (PDT) X-Google-Smtp-Source: APXvYqySPhtCYOuxjuTsggZpqtCzFU9cwziWPKEvespn9gw6MrO0sNCkSr7BeP8Vg9FkHp3UlagP X-Received: by 2002:a17:902:968d:: with SMTP id n13mr9227216plp.257.1562909384185; Thu, 11 Jul 2019 22:29:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1562909384; cv=none; d=google.com; s=arc-20160816; b=N4eoCMdaixzuMvtxxHXMvR9WJrdqAJJlceDnXoxDiIVs40bWE7GnWqdQgIn0ou1w0u cK6ZGdXgaD7yQwOD6OChB5bTeTQ/5L23IpXxymYWuqMB8w+dGX2wi0T4GwTQfBImFiEz S0h8ZnwHWpL57RCHZOLTDe+aJLs/dpaJDo10QOWZ/G3HOsG12ZnOFZ5cpt8DxB18lWvG /eI0u9N1siK4PbywEF+3a9/VZqUeTT68Qrh25BwCZzTRoogJ+IC7AJV8c27On5Y32bDH dd4fcIb8VPzrDj02E92sOdr9pFupZs2gvTGWaKH/B3+WSiJreqjTfwbg0HQ1RlL1XHp1 MEuw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=NiMpS2GtyMwnZTpxG4MhAWhnIU6AXgssIk4MKZtthvc=; b=W1ghCyQ/hudq9V/+oKE3M8XmBTPmvUE3vEXVICPOGvhULXTPg3SeatzQ0F2vuWeZIB m9FNvBDprb5vchjZ2osNxI+z1AgyQHbUB5TKFswmumiKVdUYDrP8pydEarf1zSo56bvx nMRfaKpZVjzUmbtBsnbR0u0XZIRqKLaFkmGIM1MhrgBCrL2EWBJeKLLS0+DJwAE6P1wj Nc6xVRkg3YAnwqPVq9++cdq+M4Rwtx+Wpz7P8X2vUyrjeYvP8PnsvA0ml9bpeRk6Rgxs zkRUPdeGY/WTTuwdYKdpSXrJ8xGsSo6kfVEjmFwzbg1Ajqb5kaQKtNdhSLBgiJnM6KrT /RFg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="ZxWyb/8V"; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e36si5303191pgm.17.2019.07.11.22.29.43; Thu, 11 Jul 2019 22:29:44 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="ZxWyb/8V"; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726063AbfGLF3n (ORCPT + 13 others); Fri, 12 Jul 2019 01:29:43 -0400 Received: from mail-pg1-f196.google.com ([209.85.215.196]:44826 "EHLO mail-pg1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725791AbfGLF3n (ORCPT ); Fri, 12 Jul 2019 01:29:43 -0400 Received: by mail-pg1-f196.google.com with SMTP id i18so3990128pgl.11 for ; Thu, 11 Jul 2019 22:29:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NiMpS2GtyMwnZTpxG4MhAWhnIU6AXgssIk4MKZtthvc=; b=ZxWyb/8VZoLdoUn2uKUudf3sdZhjRD6a7pJM14TVwK7g/vHOIHZfykI1dtfLhHIfYn 3cSWJiC6CWJC6W1uMbsdf6OYsFlIxC64jvs4VHLK9L5lIWKJ8/JQAM/NV7qhXlQP4aMQ YY6r4gKLHQwZzJBywyvMiJPxbDmJ5WJF1z+CF5F8cyZRRtgISkKLkQ7pTx4QGi8Q9r/4 zas1OTYOclfwi531Lep+sfcTpCDvGycbUzp1Id0F1FOMJWc6d1ZrGlWDS8k9FXU1Rqvu rdQqv2AtNzI9gcxIvkDftOsnSlr139CUY3GegXmenTrJ9g96NbW2QGGTmBARNxkXD9my jzag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NiMpS2GtyMwnZTpxG4MhAWhnIU6AXgssIk4MKZtthvc=; b=fGafjCusM1pQREjpDNjgTsuUcql5/BvcK02pXPRk11i3IBhyAkpa8LcCQo026SG6ra QTfKWlBOYIW1SXmuFHOKTyB6yA+2MI1NgYa/BNa314EuIATw+iPIJZB8GqetuwxIZl2V bevnNeD2liaKUn0lNnqm6q66mm0mU5zlfEtaM284xJEjxTyGORKvx8YrkkX16tNZsZ5a 4ZBhWAndlXiKOI3tjEKcNv4odHT7232JI/GR699eOT8I8KKsJyDBBJnpLaW7E7egeJ3b 2BaFEPdfo0VUCCh6xQD2wfkSmoRJxSJ6+p/8Ns6bScJdKkl6Uuq8BfizYEpAKFS/u5un aprQ== X-Gm-Message-State: APjAAAVY/nxeW0wjghs+7fexG/85k16FFmad2wIlrOkm1SswIJcCDanj A4FpaHN1ZwsaoYhc6XJRa5CFLFoPr44= X-Received: by 2002:a63:4185:: with SMTP id o127mr8346896pga.82.1562909382331; Thu, 11 Jul 2019 22:29:42 -0700 (PDT) Received: from localhost ([122.172.28.117]) by smtp.gmail.com with ESMTPSA id r13sm8444561pfr.25.2019.07.11.22.29.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 11 Jul 2019 22:29:41 -0700 (PDT) From: Viresh Kumar To: stable@vger.kernel.org, Julien Thierry Cc: Viresh Kumar , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Marc Zyngier , Mark Rutland , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: [PATCH v4.4 V2 16/43] arm64: Verify CPU errata work arounds on hotplugged CPU Date: Fri, 12 Jul 2019 10:58:04 +0530 Message-Id: <69ba9cb57c88ef7c15651a3f474a209dabe9d89b.1562908075.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Suzuki K Poulose commit 6a6efbb45b7d95c84840010095367eb06a64f342 upstream. CPU Errata work arounds are detected and applied to the kernel code at boot time and the data is then freed up. If a new hotplugged CPU requires a work around which was not applied at boot time, there is nothing we can do but simply fail the booting. Cc: Will Deacon Cc: Mark Rutland Cc: Andre Przywara Reviewed-by: Catalin Marinas Signed-off-by: Suzuki K Poulose Signed-off-by: Will Deacon [ Viresh: Resolved rebase conflict ] Signed-off-by: Viresh Kumar --- arch/arm64/include/asm/cpufeature.h | 2 ++ arch/arm64/kernel/cpu_errata.c | 20 ++++++++++++++++++++ arch/arm64/kernel/cpufeature.c | 2 ++ 3 files changed, 24 insertions(+) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h index 4c31e14c0f0e..dd1aab8e52aa 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -173,6 +173,8 @@ void update_cpu_capabilities(const struct arm64_cpu_capabilities *caps, const char *info); void check_local_cpu_errata(void); +void verify_local_cpu_errata(void); + #ifdef CONFIG_HOTPLUG_CPU void verify_local_cpu_capabilities(void); #else diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index 0971d80d3623..a3567881c01b 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -116,6 +116,26 @@ const struct arm64_cpu_capabilities arm64_errata[] = { } }; +/* + * The CPU Errata work arounds are detected and applied at boot time + * and the related information is freed soon after. If the new CPU requires + * an errata not detected at boot, fail this CPU. + */ +void verify_local_cpu_errata(void) +{ + const struct arm64_cpu_capabilities *caps = arm64_errata; + + for (; caps->matches; caps++) + if (!cpus_have_cap(caps->capability) && + caps->matches(caps, SCOPE_LOCAL_CPU)) { + pr_crit("CPU%d: Requires work around for %s, not detected" + " at boot time\n", + smp_processor_id(), + caps->desc ? : "an erratum"); + cpu_die_early(); + } +} + void check_local_cpu_errata(void) { update_cpu_capabilities(arm64_errata, "enabling workaround for"); diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index a0273cd8be51..9a4b638b1c18 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -872,6 +872,8 @@ void verify_local_cpu_capabilities(void) if (!sys_caps_initialised) return; + verify_local_cpu_errata(); + caps = arm64_features; for (i = 0; caps[i].matches; i++) { if (!cpus_have_cap(caps[i].capability) || !caps[i].sys_reg) From patchwork Fri Jul 12 05:28:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 168876 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp394850ilk; Thu, 11 Jul 2019 22:29:46 -0700 (PDT) X-Google-Smtp-Source: APXvYqwObzkEf/iVofcDjQIZ/cG4Vtx9rY0LIzA8YbmQwQEmd5o2H6KQ/jTM0oDLnnscr/yI1Ckl X-Received: by 2002:a17:90a:37e9:: with SMTP id v96mr9230189pjb.10.1562909386709; Thu, 11 Jul 2019 22:29:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1562909386; cv=none; d=google.com; s=arc-20160816; b=AkwjR7i6kgUDG0LZja7pe0umquD6/MY5gJGv7TKUFEi5AN7/WWmJvPl7E32us1eUSs WLbVb7dgJyO5324RanIJeoHmwzRjDGyfhbhRzE0l0pvpnj0t3lZQQhytODVafG8QN0Xh NQW7+sBdFpnrTVFScTnHgd4WNspe//eeph7l+Z3VVEKP4fJ8HT8FLJMNyX9hAo5xAh/P KHa349/eiaBTCklM9GpsIAGae4l0aEsEv7x5EIkxTPude5hwNgvyaGMR1UHm58i1cvir fHsrm72mb9tbPGYhnYCbU+KPjhHX+fDSkpYj8eP7t0+bkUpjeRiyb/gs4XDYKenmYHGc tPYA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=dewjZZw0HbdCyicLrnA8hjXb53SKvhtBESHu+qhlc+Y=; b=tf5JfcuevAAI5fazT0muOIWEEm1/tAcePt4tdf2yF8ZpBDO+bKWbZWfhKr9XR5Lx+z KYAHhJvAF0Ch4M5Kh9HMtMrriKhHpIMyi9uSv4Y622pKVOSm1ZQ/Bx25T3qQKdWualSi fV2GhLQHLW92FSN9hTRiRY7vuSVzMExf9ZUyA2ayyQZ+OpBWzKdihYNDJgJSugiZGRT0 ypP8uQBJiro53B3BuTEZpLhxMQuLJ2sEGVZKVAbGV3a7W7DeqoHWDzJRGT9UxWap7crB RzeVrfy7GWNueloBTxbk+xCto2We/jn0aw14wWefeO5awF3EmTVC2prTHHAjT/KWLoCE nbLg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=RraxYDI8; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Currently we call the (optional) enable function for CPU _features_ only. As CPU _errata_ descriptions share the same data structure and having an enable function is useful for errata as well (for instance to set bits in SCTLR), lets call it when enumerating erratas too. Signed-off-by: Andre Przywara Reviewed-by: Suzuki K Poulose Signed-off-by: Catalin Marinas Signed-off-by: Viresh Kumar --- arch/arm64/include/asm/cpufeature.h | 2 ++ arch/arm64/kernel/cpu_errata.c | 5 +++++ arch/arm64/kernel/cpufeature.c | 3 ++- 3 files changed, 9 insertions(+), 1 deletion(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h index dd1aab8e52aa..0267bab6ac18 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -171,7 +171,9 @@ void __init setup_cpu_features(void); void update_cpu_capabilities(const struct arm64_cpu_capabilities *caps, const char *info); +void enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps); void check_local_cpu_errata(void); +void __init enable_errata_workarounds(void); void verify_local_cpu_errata(void); diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index a3567881c01b..d9f095439011 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -140,3 +140,8 @@ void check_local_cpu_errata(void) { update_cpu_capabilities(arm64_errata, "enabling workaround for"); } + +void __init enable_errata_workarounds(void) +{ + enable_cpu_capabilities(arm64_errata); +} diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 9a4b638b1c18..7773bea6927e 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -820,7 +820,7 @@ void update_cpu_capabilities(const struct arm64_cpu_capabilities *caps, * Run through the enabled capabilities and enable() it on all active * CPUs */ -static void enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps) +void enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps) { int i; @@ -923,6 +923,7 @@ void __init setup_cpu_features(void) /* Set the CPU feature capabilies */ setup_feature_capabilities(); + enable_errata_workarounds(); setup_cpu_hwcaps(); /* Advertise that we have computed the system capabilities */ From patchwork Fri Jul 12 05:28:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 168877 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp394887ilk; Thu, 11 Jul 2019 22:29:49 -0700 (PDT) X-Google-Smtp-Source: APXvYqy6ggSICFQVynYNr3/YanD0key2Cs4HtV1KXkoqVWEMYnqxCLsVQU3gwc5tm61crdgE0zDj X-Received: by 2002:a17:902:549:: with SMTP id 67mr9151481plf.86.1562909389350; Thu, 11 Jul 2019 22:29:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1562909389; cv=none; d=google.com; s=arc-20160816; b=zIpejx+7bEHXvaRgcmWuNKU47jo1OrLD+KraZvaHPSmxJjd5v3e7evE97Gca0x3uTn 4sxrdfp8WNPkz72HYnzrDPG93hZr/APIYiVs/srUgCLptuzdGaM8LPKw5QaJmiXqJzjK R9rH6gBRoYYoAjUbPmPL3RbnWUjTZIYqjEKn1svwmFQDDiyEYy3ABQVdUzT/jhOHPrzq XMRyvv03ihRpFuq8Bn7/NMJ8QhTF7zIORb1XcnRmoCXJpxUPeOJi/lNA/SFzut9Z+Lum yujoYXygtGKNLPo0aYoVBbB5UxVoN7w5u7wD9JlxX9qfgWOQ/DIJ/D1dS9uCR5L557kR wETQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ZUdOby9mUIJ5g7nxMiQ+DmGQefEZUa89WzEBGK5DmD0=; b=VNSUaLNv20tiuQ4XrGY7iNAM2AMmAZKqOkUAZyVAdUN/AsKVZr/sQm4JcYlkDHdvvC p2WQoKVR4gVZedA+a1WkPrRkj3m61NTgYOfsXcThZSkqX5SYaTD2byaBlbaT2b3cUXQO Q2380hutmFBWVPkN30IZCgrfm0PZvhDjEXbsQVlSxjqfHqqc+adOrD1xMmMf8LkGLck1 17HMQ328VvRgzu7wHQ/oL254G66nuIJTYruP3saJjuDVcKWBZDJUUW62aMSj9QyUB7vt RQ1wokoaDIQ/qJCGeNJsX+M4YOMqVnCMC6cnOHT2KMNFH/uKsY17VfXt8QIWmvWdb560 T9iw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=AboBRh8M; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Right now we run through the work around checks on a CPU from __cpuinfo_store_cpu. There are some problems with that: 1) We initialise the system wide CPU feature registers only after the Boot CPU updates its cpuinfo. Now, if a work around depends on the variance of a CPU ID feature (e.g, check for Cache Line size mismatch), we have no way of performing it cleanly for the boot CPU. 2) It is out of place, invoked from __cpuinfo_store_cpu() in cpuinfo.c. It is not an obvious place for that. This patch rearranges the CPU specific capability(aka work around) checks. 1) At the moment we use verify_local_cpu_capabilities() to check if a new CPU has all the system advertised features. Use this for the secondary CPUs to perform the work around check. For that we rename verify_local_cpu_capabilities() => check_local_cpu_capabilities() which: If the system wide capabilities haven't been initialised (i.e, the CPU is activated at the boot), update the system wide detected work arounds. Otherwise (i.e a CPU hotplugged in later) verify that this CPU conforms to the system wide capabilities. 2) Boot CPU updates the work arounds from smp_prepare_boot_cpu() after we have initialised the system wide CPU feature values. Cc: Mark Rutland Cc: Andre Przywara Cc: Will Deacon Cc: Catalin Marinas Signed-off-by: Suzuki K Poulose Signed-off-by: Will Deacon Signed-off-by: Viresh Kumar --- arch/arm64/include/asm/cpufeature.h | 8 +------- arch/arm64/kernel/cpufeature.c | 23 +++++++++++++++-------- arch/arm64/kernel/cpuinfo.c | 2 -- arch/arm64/kernel/smp.c | 8 +++++++- 4 files changed, 23 insertions(+), 18 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h index 0267bab6ac18..1bc51f8835e5 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -177,13 +177,7 @@ void __init enable_errata_workarounds(void); void verify_local_cpu_errata(void); -#ifdef CONFIG_HOTPLUG_CPU -void verify_local_cpu_capabilities(void); -#else -static inline void verify_local_cpu_capabilities(void) -{ -} -#endif +void check_local_cpu_capabilities(void); u64 read_system_reg(u32 id); diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 7773bea6927e..c74df3ca000e 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -860,18 +860,11 @@ static inline void set_sys_caps_initialised(void) * cannot do anything to fix it up and could cause unexpected failures. So * we park the CPU. */ -void verify_local_cpu_capabilities(void) +static void verify_local_cpu_capabilities(void) { int i; const struct arm64_cpu_capabilities *caps; - /* - * If we haven't computed the system capabilities, there is nothing - * to verify. - */ - if (!sys_caps_initialised) - return; - verify_local_cpu_errata(); caps = arm64_features; @@ -902,6 +895,20 @@ void verify_local_cpu_capabilities(void) } } +void check_local_cpu_capabilities(void) +{ + /* + * If we haven't finalised the system capabilities, this CPU gets + * a chance to update the errata work arounds. + * Otherwise, this CPU should verify that it has all the system + * advertised capabilities. + */ + if (!sys_caps_initialised) + check_local_cpu_errata(); + else + verify_local_cpu_capabilities(); +} + #else /* !CONFIG_HOTPLUG_CPU */ static inline void set_sys_caps_initialised(void) diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c index 0166cfbc866c..13e659fda04a 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c @@ -239,8 +239,6 @@ static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info) info->reg_mvfr2 = read_cpuid(MVFR2_EL1); cpuinfo_detect_icache_policy(info); - - check_local_cpu_errata(); } void cpuinfo_store_cpu(void) diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c index 752b53daac23..7a9eff0d1ebe 100644 --- a/arch/arm64/kernel/smp.c +++ b/arch/arm64/kernel/smp.c @@ -161,7 +161,7 @@ asmlinkage notrace void secondary_start_kernel(void) * this CPU ticks all of those. If it doesn't, the CPU will * fail to come online. */ - verify_local_cpu_capabilities(); + check_local_cpu_capabilities(); if (cpu_ops[cpu]->cpu_postboot) cpu_ops[cpu]->cpu_postboot(); @@ -360,6 +360,12 @@ void __init smp_prepare_boot_cpu(void) { set_my_cpu_offset(per_cpu_offset(smp_processor_id())); cpuinfo_store_boot_cpu(); + /* + * Run the errata work around checks on the boot CPU, once we have + * initialised the cpu feature infrastructure from + * cpuinfo_store_boot_cpu() above. + */ + check_local_cpu_errata(); } static u64 __init of_get_cpu_mpidr(struct device_node *dn) From patchwork Fri Jul 12 05:28:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 168878 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp394920ilk; Thu, 11 Jul 2019 22:29:52 -0700 (PDT) X-Google-Smtp-Source: APXvYqxWwClFBHSjiS6XSzvVWODDYg7ADR5sAV75UiMLQHxvkFcbylB4Y8nzCq9y3SB9Uvs1FUbG X-Received: by 2002:a63:4404:: with SMTP id r4mr8501266pga.245.1562909392000; Thu, 11 Jul 2019 22:29:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1562909391; cv=none; d=google.com; s=arc-20160816; b=IQm9sOJ20rZzMB8mp0TOp/lkLkrg0bI0hpvmMJjo0Mk2U1XT5Z6m4dCwPmAI2GKm5u W+NNR5+b6FQAkTWg2PN7eCNDkqIyjuWZQNcbkSCqFKY2vzkV6yicSVdr1c4X8oAQxeNb TRWhrM7VSw2Xz6Syv3A+1SaplbnSXBcKRkF/ZhjZNd62l0KdoWLgADCBP03TIlBK9NQ3 MIu5wad2iQy1YXSPVl6e3a/eORMv1wJOmEeZGYPBOv6d8rCbmQagLhnkPG25WXut9bTz TZkIOmoMY23UeSdMuG6iHhPDtkwf2zJwsbcb0tWX+bOwnllQmdJ/10t03AUkDcM68Fvz 5mJQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=j1PYP8TRl6+XUUI1RLnfOfH8okdoaEeO+GZk5UMu4vo=; b=eE/swjyHYhb2g2OrWG9W5tOfK8J08NtYs8Anh7B+HAACaYO9Ros8fivEaYKYniao+W AUvTLXLap+aFqJ9wMiPX+OXEOhCGNrBWKSnfFMrvq2xL+fYFwVzwoLaDsC4kvZeglwx8 jujK9Cu7cfcGM1NODAKddjBrlTpf4j0KDfaHbWJcC/JJswe8hIpyG6LLgMcTnVyvAD6s FyiDl4VyAhnPOuUiP1Q1X0hLyV+/89DHjbwUqt+pEO5IfAREWKKod8PrxqUVohFrudz9 a5aPbfgQoO1F+Bivmkla7evZdOYZf5GG5IHfEUdTydxiHC1LrEZK0C9RD0FUtSHaQbrB HbGQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Z1T5KKS7; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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When a CPU is brought up after we have finalised the system wide capabilities (i.e, features and errata), we make sure the new CPU doesn't need a new errata work around which has not been detected already. However we don't run enable() method on the new CPU for the errata work arounds already detected. This could cause the new CPU running without potential work arounds. It is upto the "enable()" method to decide if this CPU should do something about the errata. Fixes: commit 6a6efbb45b7d95c84 ("arm64: Verify CPU errata work arounds on hotplugged CPU") Cc: Will Deacon Cc: Mark Rutland Cc: Andre Przywara Cc: Dave Martin Signed-off-by: Suzuki K Poulose Signed-off-by: Catalin Marinas Signed-off-by: Viresh Kumar --- arch/arm64/kernel/cpu_errata.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index d9f095439011..047f1da59cb1 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -125,15 +125,18 @@ void verify_local_cpu_errata(void) { const struct arm64_cpu_capabilities *caps = arm64_errata; - for (; caps->matches; caps++) - if (!cpus_have_cap(caps->capability) && - caps->matches(caps, SCOPE_LOCAL_CPU)) { + for (; caps->matches; caps++) { + if (cpus_have_cap(caps->capability)) { + if (caps->enable) + caps->enable((void *)caps); + } else if (caps->matches(caps, SCOPE_LOCAL_CPU)) { pr_crit("CPU%d: Requires work around for %s, not detected" " at boot time\n", smp_processor_id(), caps->desc ? : "an erratum"); cpu_die_early(); } + } } void check_local_cpu_errata(void) From patchwork Fri Jul 12 05:28:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 168879 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp394956ilk; Thu, 11 Jul 2019 22:29:54 -0700 (PDT) X-Google-Smtp-Source: APXvYqz+og7B39ktsQYQrHtqm9MjFrvCsdPIzINBUoFQA4xKLCRj1a8LtGTTbR+nqhwnNANMRfNt X-Received: by 2002:a65:454c:: with SMTP id x12mr8636282pgr.354.1562909394669; Thu, 11 Jul 2019 22:29:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1562909394; cv=none; d=google.com; s=arc-20160816; b=smSaIdb5yH3BXbq+kizCd9Eu6OKl3pGuw5ncnGSROMdoG9YLKnDHOpNaULlnE/fpD/ qD7w7pgeiIImGv+8BhBuFb/dfo6DHZ8pYM3y8jKlSfTjcYXV5sWDyhvYGIlDogQZwb/0 t3BYoMG3/l86ZiGbLEXl53wS6v1G6MgPj5/MTHVkY03W70dSsOokvIRUNwA3hMMR0IRF ZMy4u8jHsTetXkgXgsnOyILPgr8B3gJLkRZMeCnNw4dzk9GZw/QhxUlj25E+cl7761zz FlQqAPReJxRn0Q4l2C9edQtjSU/6PxuRUkDjtnR5ycG511/nj3XMqwTzPBeXYgVcmKvX Q3fQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=L+Gdnz2jFF65J3PIUhAk0AHlnEqUM/+ROCtumKJNSeI=; b=B1KhdgqkkKFSJXr4kqkli41iosAlNMeHf4BZgH0WchEsA1Fg2A5eKFPnC2xmMozcaS wvhdBtBj/wQZFb2om+Jm/L1RtRn+cSj7B1WIBUoJcYc0pHdh64qm333ZHywP1/8pOR4M 0Wmd2mb9i4cAQzcDLk49D8/DbE+j0xnpE4vQZVXTARW2vjY/y3SDx5dyWppLsC7kkXxe AQfXFVEUpyVU9AQnRm8dZDE4jCiSgTRz6fnHZE8E2cyTv1ZtWx35pMDDxShDfxx6P3WG VavlPM/i1UZAhZX0RJCBs5bmO9aIylozP6YUvFsqnDif+zJohIcnBTyJAFF0K3hnvw0f SJHQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=O28H3hJb; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e36si5303191pgm.17.2019.07.11.22.29.54; Thu, 11 Jul 2019 22:29:54 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=O28H3hJb; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726074AbfGLF3y (ORCPT + 13 others); Fri, 12 Jul 2019 01:29:54 -0400 Received: from mail-pf1-f195.google.com ([209.85.210.195]:34657 "EHLO mail-pf1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725791AbfGLF3x (ORCPT ); Fri, 12 Jul 2019 01:29:53 -0400 Received: by mail-pf1-f195.google.com with SMTP id b13so3800253pfo.1 for ; Thu, 11 Jul 2019 22:29:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=L+Gdnz2jFF65J3PIUhAk0AHlnEqUM/+ROCtumKJNSeI=; b=O28H3hJbcm//HM+U/MWBuTNk2PRepOPX88YnoORFVdxZm09Mikdw3xD5PNVZAZcyJe SbkalfujGuflSOEKDuz9pC45lyZQhzbUFb7eZBEv5TnP6mQk8SvYOnFZ0TAHg6XgjTO1 M4vVkB+MqXqFKCP5J1/py2/4yb93120qicinbyThs1y/CAvkwHcoXZ4UWNASDaZYbr/o KYF1Zg1rmYn7w1Sp2W48nAkF5hIm0uUEOTg57A/O2D8Nr6d+6wXJNmGb5uKfNpzD01Ii iBwFDSQSY7S7s5vf8Mcz0jnUo5cUdJL1ne7hbWENSdlHLL+vqy0eyBtxP15jn46Jl6RI A0Hw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=L+Gdnz2jFF65J3PIUhAk0AHlnEqUM/+ROCtumKJNSeI=; b=dWLjpMmproeZeoqW+SLuWLZZHkHju0/3SY9dkCpXhTMLEY2u1h27QlZXzwvMDk0Uwt 5/FAgkhxs+VP1PxfWuELSxPWef8LT2SdXgPIO0I4BjO78kqjV++3gVMdpUNPcOCKcFID hQbvUlyN7br5S4Imnkv7qRZpJlyp2DuCsUu95Nu2N8K2ggnRb1QcYAfRg9HfiYNJGTN7 Xx7u3LjCP372IURTKd75DBlw1exS10YDFhAWMIl2UVyeZEpSjOtbJtcVsB58HelvpmAJ eddm/I7oK9WQwRhjddfFEirD3ihAnI4VC3Boq+MKI6bRZ/2AJLoHPvwR/KFdBDTzOsX+ Q7UQ== X-Gm-Message-State: APjAAAXXFqBsJJgR2+DZBAX3ol6PAVBwiLRSf3sqn8Lhs1o9aYPNfvjO /w0vwhDtJoyC46A84LYKVWkn0VTE/GI= X-Received: by 2002:a17:90a:fe5:: with SMTP id 92mr9537112pjz.35.1562909392738; Thu, 11 Jul 2019 22:29:52 -0700 (PDT) Received: from localhost ([122.172.28.117]) by smtp.gmail.com with ESMTPSA id p20sm11193369pgj.47.2019.07.11.22.29.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 11 Jul 2019 22:29:52 -0700 (PDT) From: Viresh Kumar To: stable@vger.kernel.org, Julien Thierry Cc: Viresh Kumar , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Marc Zyngier , Mark Rutland , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: [PATCH v4.4 V2 20/43] arm64: cpufeature: Pass capability structure to ->enable callback Date: Fri, 12 Jul 2019 10:58:08 +0530 Message-Id: X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Will Deacon commit 0a0d111d40fd1dc588cc590fab6b55d86ddc71d3 upstream. In order to invoke the CPU capability ->matches callback from the ->enable callback for applying local-CPU workarounds, we need a handle on the capability structure. This patch passes a pointer to the capability structure to the ->enable callback. Reviewed-by: Suzuki K Poulose Signed-off-by: Will Deacon Signed-off-by: Catalin Marinas [ v4.4: Use &caps[i] instead as caps isn't incremented ] Signed-off-by: Viresh Kumar --- arch/arm64/kernel/cpufeature.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index c74df3ca000e..474b34243521 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -832,7 +832,7 @@ void enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps) * uses an IPI, giving us a PSTATE that disappears when * we return. */ - stop_machine(caps[i].enable, NULL, cpu_online_mask); + stop_machine(caps[i].enable, (void *)&caps[i], cpu_online_mask); } #ifdef CONFIG_HOTPLUG_CPU @@ -881,7 +881,7 @@ static void verify_local_cpu_capabilities(void) cpu_die_early(); } if (caps[i].enable) - caps[i].enable(NULL); + caps[i].enable((void *)&caps[i]); } for (i = 0, caps = arm64_hwcaps; caps[i].matches; i++) { From patchwork Fri Jul 12 05:28:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 168880 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp395007ilk; Thu, 11 Jul 2019 22:29:57 -0700 (PDT) X-Google-Smtp-Source: APXvYqz54defiqJwNNbyGdSV1KpocO7UG94oct6UnKDo6LB/EirKExCOAJ0euTO7URVzNwNk2Hih X-Received: by 2002:a65:4489:: with SMTP id l9mr8879444pgq.207.1562909397342; Thu, 11 Jul 2019 22:29:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1562909397; cv=none; d=google.com; s=arc-20160816; b=t95ONGA/udWUHdjR3KzZs2nDkmrEQ4AlfZn7WxHPT3+eiE3TxCPoiV16lRQ72lSeZ/ vkUifbMh4Besj6557xfaJv55UnFaA+hnk87cBPPkwvRlrDIqa3QTG6UVGKnc59jE5bAS 3WlNpxt1sQxPOXsubYCM5PUaUjHZhGe4KRHK98HHjvB6Gzc85EHs2ZI9cm/Wl4hqWbVt kTdAKyYFqfGboax1ViXvrYXBHLuXJPywYO2Bxg4+WhDfUGmb3FKLV/8QcCrgAU4BaFIz uvYzVWYFk6UzYxKXDAQoNtx23GG3ZR04J/mrdQSWMNj1sazjBTZklRJ+H8eS8flvfxxp U6hw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=tUK8ETga6k61l9Q+/z8rY6SIV6XG+DcjRuCd/1NWAIQ=; b=mCaYTpmzv40yo127+FTIKrxLZxUifprAyQuV5wbJQdEUsuNjahImIDUrKn/2A8TeZH 4sx1OCzGaqMi0YqrZYQrEjjYvPdznt7TH+/xVDOZw9V89s7vJIqU1jK7EQn+umzP9LW5 KUtrPqYVjTVqgLQrhqddcSnD0NuGe+0LlBP6AIquVxLr69pdZbmCNMf+EDF0fGbelEsJ lRUb1h7MAL8g5AO6+4HxMCsunGuJJ3/JO1VTuWdT5dwGpziCqXXlAH/j0KAiUu6bDwPZ US7j/FL08VC5FfJNjL2Uu6oiXzp4s8K3taAGUiUUr3e7skTYzZMk13jjKODIsD5RThkq 1NoQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vcn+efFx; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e36si5303191pgm.17.2019.07.11.22.29.57; Thu, 11 Jul 2019 22:29:57 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vcn+efFx; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726078AbfGLF34 (ORCPT + 13 others); Fri, 12 Jul 2019 01:29:56 -0400 Received: from mail-pl1-f193.google.com ([209.85.214.193]:41578 "EHLO mail-pl1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725856AbfGLF34 (ORCPT ); Fri, 12 Jul 2019 01:29:56 -0400 Received: by mail-pl1-f193.google.com with SMTP id m9so4180534pls.8 for ; Thu, 11 Jul 2019 22:29:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tUK8ETga6k61l9Q+/z8rY6SIV6XG+DcjRuCd/1NWAIQ=; b=vcn+efFxVGF43UW996/RLB57/10XNju0qvaz5vdpRO72mRWLognFPo8qNtfpDPW9wZ +DUC8+warFb6QT7+oyWClKHjq1x7Wdfo/aWYabcKjOvy9OJC5YSJLHk+Llkcrc7PWLNw hEObSZdPSOj+qbesZy64H0GPnYB6dgzZRM2wUTE4OIVBekAlkk0plooX5qMEs3+kRGNP 9WoLlzDe3UrNFGBGNAdvAzewknxhut+DtRloIv+azJdI5Tv09g+h7znmIT8vJW20Vp58 lJCGPzQBWY/ou0OEARyGbcmhlPcwvASHjZQ8uArpijAbiTbcBAYX19zR0HC7G4vD6pmU s8FA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tUK8ETga6k61l9Q+/z8rY6SIV6XG+DcjRuCd/1NWAIQ=; b=UpPa7aPiLGoy3FN1kwNpZvfYqLzpVDTrUKHzU3dL1iBGqalZQdb9pkVleqfQ9nFSDj YJDekWh6jsVd93PbgWnNtJToFuYk0kFMEQGjCYQt3HBlj++VKGpE5KkSj4icIxxLBMAz SuDsDd4QE8Dn3olAv+HBpAqmA/MrRWM0KUChLBwEu9YrbIeq4ZV3DBFswvvLVjgwdnpT NltvJYpq0djB/1s0HJ+mzOVCSDhSjgaBOSSWm5ywfgQodfetnuHHFSDf4RWf7qXfm6yB CGPh8fymtBOqz1EK5uHYWXRv80E2ASNHoxmE4urfGig1Kv51vCImMR8G/fhINbsnIqEs ExGA== X-Gm-Message-State: APjAAAWBUvPEyhlxR1Gexj8rMWkvHHyXsFyPd2RLxd3nHlk97lCeS/NU o47MMRrN2jTmu2V3Iebeb4CNbN/uDCQ= X-Received: by 2002:a17:902:aa95:: with SMTP id d21mr8772502plr.185.1562909395725; Thu, 11 Jul 2019 22:29:55 -0700 (PDT) Received: from localhost ([122.172.28.117]) by smtp.gmail.com with ESMTPSA id f6sm7757419pga.50.2019.07.11.22.29.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 11 Jul 2019 22:29:55 -0700 (PDT) From: Viresh Kumar To: stable@vger.kernel.org, Julien Thierry Cc: Viresh Kumar , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Marc Zyngier , Mark Rutland , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: [PATCH v4.4 V2 21/43] drivers/firmware: Expose psci_get_version through psci_ops structure Date: Fri, 12 Jul 2019 10:58:09 +0530 Message-Id: X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Will Deacon commit d68e3ba5303f7e1099f51fdcd155f5263da8569b upstream. Entry into recent versions of ARM Trusted Firmware will invalidate the CPU branch predictor state in order to protect against aliasing attacks. This patch exposes the PSCI "VERSION" function via psci_ops, so that it can be invoked outside of the PSCI driver where necessary. Acked-by: Lorenzo Pieralisi Signed-off-by: Will Deacon Signed-off-by: Catalin Marinas Signed-off-by: Viresh Kumar --- drivers/firmware/psci.c | 2 ++ include/linux/psci.h | 1 + 2 files changed, 3 insertions(+) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/drivers/firmware/psci.c b/drivers/firmware/psci.c index ae70d2485ca1..290f8982e7b3 100644 --- a/drivers/firmware/psci.c +++ b/drivers/firmware/psci.c @@ -305,6 +305,8 @@ static void __init psci_init_migrate(void) static void __init psci_0_2_set_functions(void) { pr_info("Using standard PSCI v0.2 function IDs\n"); + psci_ops.get_version = psci_get_version; + psci_function_id[PSCI_FN_CPU_SUSPEND] = PSCI_FN_NATIVE(0_2, CPU_SUSPEND); psci_ops.cpu_suspend = psci_cpu_suspend; diff --git a/include/linux/psci.h b/include/linux/psci.h index 12c4865457ad..04b4d92c7791 100644 --- a/include/linux/psci.h +++ b/include/linux/psci.h @@ -25,6 +25,7 @@ bool psci_power_state_loses_context(u32 state); bool psci_power_state_is_valid(u32 state); struct psci_operations { + u32 (*get_version)(void); int (*cpu_suspend)(u32 state, unsigned long entry_point); int (*cpu_off)(u32 state); int (*cpu_on)(unsigned long cpuid, unsigned long entry_point); From patchwork Fri Jul 12 05:28:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 168881 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp395054ilk; Thu, 11 Jul 2019 22:30:00 -0700 (PDT) X-Google-Smtp-Source: APXvYqxGwQZzy6EM+KkUhDZsXN7cH1DHDYIMvskK6LD6JCCxICOUCKvskyttT97p+yHYFhXXZRPC X-Received: by 2002:a17:902:968d:: with SMTP id n13mr9228263plp.257.1562909400288; Thu, 11 Jul 2019 22:30:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1562909400; cv=none; d=google.com; s=arc-20160816; b=KbaTQZA433gz770bLIs6OI/8iwyqkEEGH5sVydUtieXGXr6ibMISYfdEwJArBhWkKh gPgMA6fWglsW1JBUYMOEcufn4NzfsMPZ7YdQTOCmWkexlI6BBw78WBVQWZgpcLRtGVAT ebhwIf+3kqiZDrNTKOEis6IMyrbFSYd1smdAPJP/qA4XxyIwvp25dEkqG93S14O+zj8J 0TlJ74ce1FQR90as2p4o13L8XWDso5xuCT/aYGz161H5bquF8sr7joU1bxrh+ROLMRKO TwbaDXpLpYYzhr1VkhCA1lGmRxhyObK2C1z4ImCslKRYDYGNLpdr9v4hBeBAqPPpdb4H r5CQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Cnuqc1YlBQBZ4RWPKzaqy9DfMXgSoNZrvvTdeydR7XY=; b=K5fMKNuxs+oxC9VEiaxCzbm633hemLjBSqhX9h2mNLWMmll4UUwMiNCmKRuWtyh+cy FmMJuWH20JprePneqFjjmQzkPaqcQc4URjOBhQFcnM2OOolN6kuN5gxvQSmbNeBs39OW nChhooSX6fM+hVMSURLb++Vi9J3oOPVTJKRlq+7n5ggoNp4xJqx0J8NnDtV8YD5z8Jbh t5E/fW0ABuXqjt1DFgWbOsKwLT3xsuB1VGPbx+qZM0VlY7cnfq+PKnawm3iF4Nl45J8w v5z836CFcIsI5AtbuZRki1nz6zUn1xkX7PuHXksmkXGwdhUxlO+JF9jWdUCqS9hUroxG iCDg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=yfJJZ5bu; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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This patch takes the errata workaround code out of cpu_do_switch_mm into a dedicated post_ttbr0_update_workaround macro which will be reused in a subsequent patch. Cc: Will Deacon Cc: James Morse Cc: Kees Cook Reviewed-by: Mark Rutland Signed-off-by: Catalin Marinas [ v4.4: Included cpufeature.h and adapted to use alternative_if_not ] Signed-off-by: Viresh Kumar --- arch/arm64/include/asm/assembler.h | 18 ++++++++++++++++++ arch/arm64/mm/proc.S | 11 +---------- 2 files changed, 19 insertions(+), 10 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h index 2b30363a3a89..8ab46508e836 100644 --- a/arch/arm64/include/asm/assembler.h +++ b/arch/arm64/include/asm/assembler.h @@ -23,6 +23,7 @@ #ifndef __ASM_ASSEMBLER_H #define __ASM_ASSEMBLER_H +#include #include #include #include @@ -282,4 +283,21 @@ lr .req x30 // link register .Ldone\@: .endm +/* + * Errata workaround post TTBR0_EL1 update. + */ + .macro post_ttbr0_update_workaround +#ifdef CONFIG_CAVIUM_ERRATUM_27456 +alternative_if_not ARM64_WORKAROUND_CAVIUM_27456 + ret + nop + nop + nop +alternative_else + ic iallu + dsb nsh + isb +#endif + .endm + #endif /* __ASM_ASSEMBLER_H */ diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S index f09636738007..4eb1084e203a 100644 --- a/arch/arm64/mm/proc.S +++ b/arch/arm64/mm/proc.S @@ -139,17 +139,8 @@ ENTRY(cpu_do_switch_mm) bfi x0, x1, #48, #16 // set the ASID msr ttbr0_el1, x0 // set TTBR0 isb -alternative_if_not ARM64_WORKAROUND_CAVIUM_27456 + post_ttbr0_update_workaround ret - nop - nop - nop -alternative_else - ic iallu - dsb nsh - isb - ret -alternative_endif ENDPROC(cpu_do_switch_mm) .section ".text.init", #alloc, #execinstr From patchwork Fri Jul 12 05:28:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 168882 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp395114ilk; Thu, 11 Jul 2019 22:30:03 -0700 (PDT) X-Google-Smtp-Source: APXvYqwA0PHqNLQhtUfQp3kmBF8BExGAsk67f5MqSzStCI1F0sPxiQhk22O0SWaEdb09AbLvdORy X-Received: by 2002:a17:90b:95:: with SMTP id bb21mr9538170pjb.8.1562909403164; Thu, 11 Jul 2019 22:30:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1562909403; cv=none; d=google.com; s=arc-20160816; b=AuXty3qlTq9F2T+smVxTuMuL3EeY4uZNqQtVY5JQJKdfWaiU3dF9g3HahOFVk4sEKX mep49lThmf0J0LWphKJEbiGIJPuUudZmG7ar2TvXhk7QVqtqvbsojS8VyUyKJ49ZE/oi Evl9UoBZWtnen+R85GseYBkbOwlkGeEZmFeAKlqyqAxXBlzOORRbPzzR3sDRLmyKC6XW LuyHtmmllpTeVuZxxjyYLzKiAP73qisOBfJyJqtLhkcNkpwNNdnR7qh6V96DD85wKmj6 mc4KA0annQTXpk7KL8m4ETM1mO3mbzXBlAKnep8LCEf0KXH5bk7yEiWTDorS6k0vBco+ HF4A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=FJU6AKZYmaWbov8SdJbQnRPRbYy33d5KJviuZzujVLk=; b=RlCLe4fxEIH5ptnJJF8CSbOUDtQZ/USy4pXJgFrxA6AxKwdPVBCr/q2nm7ORT9ve2I mQIf1ByU33vqBYFelX1IYTEyF++1v1KSBWoAN/cHWQmX0Ksdiw3L/ifxxq/iuj/aJwx8 TOJiLnvbw87C1hLUmbGwkqk+0E8ZwEUXtEoVETpwxCgpDH9smsfs4a9hM0JNl/xXvXWW HUl39lvRN6EvqwlqSYCaQC9jIMDVXNBpUHpmPG00Ul60q6fXNr1IGPb1xEJpYiyOWVpj Im19Q/9+kXe1WO1DISLvg7GKc2bFsUDGEyR1phZxnCdkxxtuQsV9p2jsXTYqRizSiE3I jRAg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=oTIW5muK; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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We will soon need to invoke a CPU-specific function pointer after changing page tables, so move post_ttbr_update_workaround out into C code to make this possible. Signed-off-by: Marc Zyngier Signed-off-by: Will Deacon Signed-off-by: Catalin Marinas [ v4.4: Removed cpufeature.h, included alternative.h, dropped entry.S changes and adapted to drop alternative_if_not ] Signed-off-by: Viresh Kumar --- arch/arm64/include/asm/assembler.h | 18 ------------------ arch/arm64/mm/context.c | 10 ++++++++++ arch/arm64/mm/proc.S | 3 +-- 3 files changed, 11 insertions(+), 20 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h index 8ab46508e836..2b30363a3a89 100644 --- a/arch/arm64/include/asm/assembler.h +++ b/arch/arm64/include/asm/assembler.h @@ -23,7 +23,6 @@ #ifndef __ASM_ASSEMBLER_H #define __ASM_ASSEMBLER_H -#include #include #include #include @@ -283,21 +282,4 @@ lr .req x30 // link register .Ldone\@: .endm -/* - * Errata workaround post TTBR0_EL1 update. - */ - .macro post_ttbr0_update_workaround -#ifdef CONFIG_CAVIUM_ERRATUM_27456 -alternative_if_not ARM64_WORKAROUND_CAVIUM_27456 - ret - nop - nop - nop -alternative_else - ic iallu - dsb nsh - isb -#endif - .endm - #endif /* __ASM_ASSEMBLER_H */ diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c index e87f53ff5f58..492d2968fa8f 100644 --- a/arch/arm64/mm/context.c +++ b/arch/arm64/mm/context.c @@ -22,6 +22,7 @@ #include #include +#include #include #include #include @@ -185,6 +186,15 @@ void check_and_switch_context(struct mm_struct *mm, unsigned int cpu) cpu_switch_mm(mm->pgd, mm); } +/* Errata workaround post TTBRx_EL1 update. */ +asmlinkage void post_ttbr_update_workaround(void) +{ + asm(ALTERNATIVE("nop; nop; nop", + "ic iallu; dsb nsh; isb", + ARM64_WORKAROUND_CAVIUM_27456, + CONFIG_CAVIUM_ERRATUM_27456)); +} + static int asids_init(void) { int fld = cpuid_feature_extract_field(read_cpuid(ID_AA64MMFR0_EL1), 4); diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S index 4eb1084e203a..a70b712ca94a 100644 --- a/arch/arm64/mm/proc.S +++ b/arch/arm64/mm/proc.S @@ -139,8 +139,7 @@ ENTRY(cpu_do_switch_mm) bfi x0, x1, #48, #16 // set the ASID msr ttbr0_el1, x0 // set TTBR0 isb - post_ttbr0_update_workaround - ret + b post_ttbr_update_workaround // Back to C code... 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Aliasing attacks against CPU branch predictors can allow an attacker to redirect speculative control flow on some CPUs and potentially divulge information from one context to another. This patch adds initial skeleton code behind a new Kconfig option to enable implementation-specific mitigations against these attacks for CPUs that are affected. Co-developed-by: Marc Zyngier Signed-off-by: Will Deacon Signed-off-by: Catalin Marinas [ v4.4: Changes made according to 4.4 codebase ] Signed-off-by: Viresh Kumar --- arch/arm64/Kconfig | 17 +++++++ arch/arm64/include/asm/cpufeature.h | 3 +- arch/arm64/include/asm/mmu.h | 39 +++++++++++++++ arch/arm64/include/asm/sysreg.h | 2 + arch/arm64/kernel/Makefile | 5 ++ arch/arm64/kernel/bpi.S | 55 +++++++++++++++++++++ arch/arm64/kernel/cpu_errata.c | 74 +++++++++++++++++++++++++++++ arch/arm64/kernel/cpufeature.c | 3 +- arch/arm64/kernel/entry.S | 8 ++-- arch/arm64/mm/context.c | 2 + arch/arm64/mm/fault.c | 16 +++++++ 11 files changed, 219 insertions(+), 5 deletions(-) create mode 100644 arch/arm64/kernel/bpi.S -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index f18b8c26a959..5fa01073566b 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -624,6 +624,23 @@ config FORCE_MAX_ZONEORDER However for 4K, we choose a higher default value, 11 as opposed to 10, giving us 4M allocations matching the default size used by generic code. +config HARDEN_BRANCH_PREDICTOR + bool "Harden the branch predictor against aliasing attacks" if EXPERT + default y + help + Speculation attacks against some high-performance processors rely on + being able to manipulate the branch predictor for a victim context by + executing aliasing branches in the attacker context. Such attacks + can be partially mitigated against by clearing internal branch + predictor state and limiting the prediction logic in some situations. + + This config option will take CPU-specific actions to harden the + branch predictor against aliasing attacks and may rely on specific + instruction sequences or control bits being set by the system + firmware. + + If unsure, say Y. + menuconfig ARMV8_DEPRECATED bool "Emulate deprecated/obsolete ARMv8 instructions" depends on COMPAT diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h index 1bc51f8835e5..93fb24d14d95 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -32,8 +32,9 @@ #define ARM64_WORKAROUND_834220 7 #define ARM64_WORKAROUND_CAVIUM_27456 8 #define ARM64_HAS_32BIT_EL0 9 +#define ARM64_HARDEN_BRANCH_PREDICTOR 10 -#define ARM64_NCAPS 10 +#define ARM64_NCAPS 11 #ifndef __ASSEMBLY__ diff --git a/arch/arm64/include/asm/mmu.h b/arch/arm64/include/asm/mmu.h index 990124a67eeb..8d0129210416 100644 --- a/arch/arm64/include/asm/mmu.h +++ b/arch/arm64/include/asm/mmu.h @@ -16,6 +16,8 @@ #ifndef __ASM_MMU_H #define __ASM_MMU_H +#include + typedef struct { atomic64_t id; void *vdso; @@ -28,6 +30,43 @@ typedef struct { */ #define ASID(mm) ((mm)->context.id.counter & 0xffff) +typedef void (*bp_hardening_cb_t)(void); + +struct bp_hardening_data { + int hyp_vectors_slot; + bp_hardening_cb_t fn; +}; + +#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR +extern char __bp_harden_hyp_vecs_start[], __bp_harden_hyp_vecs_end[]; + +DECLARE_PER_CPU_READ_MOSTLY(struct bp_hardening_data, bp_hardening_data); + +static inline struct bp_hardening_data *arm64_get_bp_hardening_data(void) +{ + return this_cpu_ptr(&bp_hardening_data); +} + +static inline void arm64_apply_bp_hardening(void) +{ + struct bp_hardening_data *d; + + if (!cpus_have_cap(ARM64_HARDEN_BRANCH_PREDICTOR)) + return; + + d = arm64_get_bp_hardening_data(); + if (d->fn) + d->fn(); +} +#else +static inline struct bp_hardening_data *arm64_get_bp_hardening_data(void) +{ + return NULL; +} + +static inline void arm64_apply_bp_hardening(void) { } +#endif /* CONFIG_HARDEN_BRANCH_PREDICTOR */ + extern void paging_init(void); extern void __iomem *early_io_map(phys_addr_t phys, unsigned long virt); extern void init_mem_pgprot(void); diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 50150320f80d..523b089fb408 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -95,6 +95,8 @@ #define ID_AA64ISAR0_AES_SHIFT 4 /* id_aa64pfr0 */ +#define ID_AA64PFR0_CSV2_SHIFT 56 +#define ID_AA64PFR0_SVE_SHIFT 32 #define ID_AA64PFR0_GIC_SHIFT 24 #define ID_AA64PFR0_ASIMD_SHIFT 20 #define ID_AA64PFR0_FP_SHIFT 16 diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile index 474691f8b13a..aa8f28210219 100644 --- a/arch/arm64/kernel/Makefile +++ b/arch/arm64/kernel/Makefile @@ -42,7 +42,12 @@ arm64-obj-$(CONFIG_PCI) += pci.o arm64-obj-$(CONFIG_ARMV8_DEPRECATED) += armv8_deprecated.o arm64-obj-$(CONFIG_ACPI) += acpi.o +ifeq ($(CONFIG_KVM),y) +arm64-obj-$(CONFIG_HARDEN_BRANCH_PREDICTOR) += bpi.o +endif + obj-y += $(arm64-obj-y) vdso/ + obj-m += $(arm64-obj-m) head-y := head.o extra-y += $(head-y) vmlinux.lds diff --git a/arch/arm64/kernel/bpi.S b/arch/arm64/kernel/bpi.S new file mode 100644 index 000000000000..06a931eb2673 --- /dev/null +++ b/arch/arm64/kernel/bpi.S @@ -0,0 +1,55 @@ +/* + * Contains CPU specific branch predictor invalidation sequences + * + * Copyright (C) 2018 ARM Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include + +.macro ventry target + .rept 31 + nop + .endr + b \target +.endm + +.macro vectors target + ventry \target + 0x000 + ventry \target + 0x080 + ventry \target + 0x100 + ventry \target + 0x180 + + ventry \target + 0x200 + ventry \target + 0x280 + ventry \target + 0x300 + ventry \target + 0x380 + + ventry \target + 0x400 + ventry \target + 0x480 + ventry \target + 0x500 + ventry \target + 0x580 + + ventry \target + 0x600 + ventry \target + 0x680 + ventry \target + 0x700 + ventry \target + 0x780 +.endm + + .align 11 +ENTRY(__bp_harden_hyp_vecs_start) + .rept 4 + vectors __kvm_hyp_vector + .endr +ENTRY(__bp_harden_hyp_vecs_end) diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index 047f1da59cb1..19c51d1cd302 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -43,6 +43,80 @@ is_affected_midr_range(const struct arm64_cpu_capabilities *entry, int scope) return (midr >= entry->midr_range_min && midr <= entry->midr_range_max); } +#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR +#include +#include + +DEFINE_PER_CPU_READ_MOSTLY(struct bp_hardening_data, bp_hardening_data); + +#ifdef CONFIG_KVM +static void __copy_hyp_vect_bpi(int slot, const char *hyp_vecs_start, + const char *hyp_vecs_end) +{ + void *dst = __bp_harden_hyp_vecs_start + slot * SZ_2K; + int i; + + for (i = 0; i < SZ_2K; i += 0x80) + memcpy(dst + i, hyp_vecs_start, hyp_vecs_end - hyp_vecs_start); + + flush_icache_range((uintptr_t)dst, (uintptr_t)dst + SZ_2K); +} + +static void __install_bp_hardening_cb(bp_hardening_cb_t fn, + const char *hyp_vecs_start, + const char *hyp_vecs_end) +{ + static int last_slot = -1; + static DEFINE_SPINLOCK(bp_lock); + int cpu, slot = -1; + + spin_lock(&bp_lock); + for_each_possible_cpu(cpu) { + if (per_cpu(bp_hardening_data.fn, cpu) == fn) { + slot = per_cpu(bp_hardening_data.hyp_vectors_slot, cpu); + break; + } + } + + if (slot == -1) { + last_slot++; + BUG_ON(((__bp_harden_hyp_vecs_end - __bp_harden_hyp_vecs_start) + / SZ_2K) <= last_slot); + slot = last_slot; + __copy_hyp_vect_bpi(slot, hyp_vecs_start, hyp_vecs_end); + } + + __this_cpu_write(bp_hardening_data.hyp_vectors_slot, slot); + __this_cpu_write(bp_hardening_data.fn, fn); + spin_unlock(&bp_lock); +} +#else +static void __install_bp_hardening_cb(bp_hardening_cb_t fn, + const char *hyp_vecs_start, + const char *hyp_vecs_end) +{ + __this_cpu_write(bp_hardening_data.fn, fn); +} +#endif /* CONFIG_KVM */ + +static void install_bp_hardening_cb(const struct arm64_cpu_capabilities *entry, + bp_hardening_cb_t fn, + const char *hyp_vecs_start, + const char *hyp_vecs_end) +{ + u64 pfr0; + + if (!entry->matches(entry, SCOPE_LOCAL_CPU)) + return; + + pfr0 = read_cpuid(ID_AA64PFR0_EL1); + if (cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_CSV2_SHIFT)) + return; + + __install_bp_hardening_cb(fn, hyp_vecs_start, hyp_vecs_end); +} +#endif /* CONFIG_HARDEN_BRANCH_PREDICTOR */ + #define MIDR_RANGE(model, min, max) \ .def_scope = SCOPE_LOCAL_CPU, \ .matches = is_affected_midr_range, \ diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 474b34243521..040a42d79990 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -83,7 +83,8 @@ static struct arm64_ftr_bits ftr_id_aa64isar0[] = { }; static struct arm64_ftr_bits ftr_id_aa64pfr0[] = { - ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 32, 0), + ARM64_FTR_BITS(FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 32, 28, 0), ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 4, 0), ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_GIC_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI), diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index e6aec982dea9..05bfc71639fc 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S @@ -495,13 +495,15 @@ ENDPROC(el1_irq) * Instruction abort handling */ mrs x26, far_el1 - // enable interrupts before calling the main handler - enable_dbg_and_irq + msr daifclr, #(8 | 4 | 1) +#ifdef CONFIG_TRACE_IRQFLAGS + bl trace_hardirqs_off +#endif ct_user_exit mov x0, x26 orr x1, x25, #1 << 24 // use reserved ISS bit for instruction aborts mov x2, sp - bl do_mem_abort + bl do_el0_ia_bp_hardening b ret_to_user el0_fpsimd_acc: /* diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c index 492d2968fa8f..be42bd3dca5c 100644 --- a/arch/arm64/mm/context.c +++ b/arch/arm64/mm/context.c @@ -193,6 +193,8 @@ asmlinkage void post_ttbr_update_workaround(void) "ic iallu; dsb nsh; isb", ARM64_WORKAROUND_CAVIUM_27456, CONFIG_CAVIUM_ERRATUM_27456)); + + arm64_apply_bp_hardening(); } static int asids_init(void) diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c index 89abdf9af4e6..1878c881a247 100644 --- a/arch/arm64/mm/fault.c +++ b/arch/arm64/mm/fault.c @@ -535,6 +535,22 @@ asmlinkage void __exception do_mem_abort(unsigned long addr, unsigned int esr, arm64_notify_die("", regs, &info, esr); } +asmlinkage void __exception do_el0_ia_bp_hardening(unsigned long addr, + unsigned int esr, + struct pt_regs *regs) +{ + /* + * We've taken an instruction abort from userspace and not yet + * re-enabled IRQs. If the address is a kernel address, apply + * BP hardening prior to enabling IRQs and pre-emption. + */ + if (addr > TASK_SIZE) + arm64_apply_bp_hardening(); + + local_irq_enable(); + do_mem_abort(addr, esr, regs); +} + /* * Handle stack alignment exceptions. */ From patchwork Fri Jul 12 05:28:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 168884 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp395191ilk; Thu, 11 Jul 2019 22:30:09 -0700 (PDT) X-Google-Smtp-Source: APXvYqyk3kfcDw1vFYosSlSFFhcK0JolP0d2KFqLg45CAUA6VMkrphBcqhvduOJ181qr0pRMii+t X-Received: by 2002:a17:90b:d8b:: with SMTP id bg11mr9410353pjb.30.1562909409071; Thu, 11 Jul 2019 22:30:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1562909409; cv=none; d=google.com; s=arc-20160816; b=l0XnxN/sapPHu/ROzRogGkDUccmI4ypKLadSZZf94BW1K0oesl9PNN4M56GBwYFfX8 O6Jo4W4wXyP1Xtoo6OQdg0Zw4Pfu373BSfNMb3OPQj/RTd5P1B6EPDKSdh1vjoGSD7z5 G5m9bRj4i6Cv229RBNGRJkH3xAz9MCqZLsGhA0XAz3AmdiCROt7qZrdWH58djmu5BZDY dL16V9yV/p7FXx5g/KGSmkTJ9vHS5LtMCNKJGNIS0+wKZBJhEjv8lsAvAP4N+MjsWphq p8lNpp0tzhsvE68eK5UIAyH8p8GrvoB5St+19EZdUYZ9tuNn3Qj6UoDr8aYzJ44NrGan UXeA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=7MRMdAKqkkU6zuM8WMZXIs4D8fug3sxafZUJy2Rr9SE=; b=Tk9IhOJ/KXQZe4rIyuVsveul/xIhmZeNJMOSKim8aRGksLjWwDoosuM7+jyZFwbVza O8CLI3+8KUr5DkC981GaruxhsEUDwCZTOBR5jt0dtusRdweVsI3B34+I591QxvfAMGSl EfNFSPwqnpy2R/+C6/uNec3ZlFN2o+p318/7i4/QWRANtKr4JhhFtjXRwpPja8AgjKKK VPYCRHe1FVZCCZyHBRwGeF3q3fR2YhxDM2W3Q/XGSJcNMeE3lJBuVR333EyjM5YqBWM+ EUqq1pQs50VehzvxnO/U9l0r+822IUfxevcQyHwtqZke2cE6ub+PnQvI5y5V7W9gbWmD AhFw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hdQErRJG; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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We call arm64_apply_bp_hardening() from post_ttbr_update_workaround, which has the unexpected consequence of being triggered on every exception return to userspace when ARM64_SW_TTBR0_PAN is selected, even if no context switch actually occured. This is a bit suboptimal, and it would be more logical to only invalidate the branch predictor when we actually switch to a different mm. In order to solve this, move the call to arm64_apply_bp_hardening() into check_and_switch_context(), where we're guaranteed to pick a different mm context. Acked-by: Will Deacon Signed-off-by: Marc Zyngier Signed-off-by: Catalin Marinas Signed-off-by: Viresh Kumar --- arch/arm64/mm/context.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c index be42bd3dca5c..de5afc27b4e6 100644 --- a/arch/arm64/mm/context.c +++ b/arch/arm64/mm/context.c @@ -183,6 +183,8 @@ void check_and_switch_context(struct mm_struct *mm, unsigned int cpu) raw_spin_unlock_irqrestore(&cpu_asid_lock, flags); switch_mm_fastpath: + arm64_apply_bp_hardening(); + cpu_switch_mm(mm->pgd, mm); } @@ -193,8 +195,6 @@ asmlinkage void post_ttbr_update_workaround(void) "ic iallu; dsb nsh; isb", ARM64_WORKAROUND_CAVIUM_27456, CONFIG_CAVIUM_ERRATUM_27456)); - - arm64_apply_bp_hardening(); } static int asids_init(void) From patchwork Fri Jul 12 05:28:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 168885 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp395248ilk; Thu, 11 Jul 2019 22:30:12 -0700 (PDT) X-Google-Smtp-Source: APXvYqxavjWUrhGArPiV6cDRFHQCb9dmLuuEOxxYrAgl29U3sn2GR0sJOStzCNLnYegD5nVMN8Qi X-Received: by 2002:a63:7e1d:: with SMTP id z29mr8624439pgc.346.1562909411870; Thu, 11 Jul 2019 22:30:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1562909411; cv=none; d=google.com; s=arc-20160816; b=PIW21m6z9Kf/2AWlcFu9cAlBZhYoGppo3EVMSz10IDJa86zleefMhlI2KdC6UO1OpK I70peX/c4bT7IVnxPbNG0PFJjO8IhM0Ie7gIP0e42vIuBUZGZa7q6N6BrkSUFCRXsUja 8NLv2DRy6yOw63/dgnpHfMRX/qIRrVODxKsRX3Buu4+UHGCpgb9+dYGBkDbHE3h2mTgQ C/Z3KRpQ+70vwC2HBWuCwNZ9oahV/ccnh6dg1X9sLqQ355apHlDKwZmfZux8GGoo6yVY RrQQaEm83DiVa/UAsMnkjqTg8NukG8Ta0GPz/fZawbApH+zJ/0DE3czHW17IZVE5q6e5 7FhA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=y6GazOWQm4IOOc6xrMbLHqM6mIdOvxmzg2BIOtMFGqg=; b=RPEJ/VhWtaLqJd2Hv3v8fLXDAVdshL4XxuLeB/1hM3YIwoFDcBFVtsA0iv81rDH5fS BR/M8QGJpI7L4QmTM65+Fek0S6VrkGqnuuQpRO8McTJhELFK4Ga/jSdgHCcNs7+Dll73 eHmHOpyx9yn2BU201K3zz7XS16yeFv6ovlZEv9J1vuRnKDTKrnGFg8H9U/bQaTKjfwA/ nePl0hdXmgg58xrKhNFrvkhx1MQbYVaymVRWsFzM+T1/b/ol00OzVp2tXqrw4ZQi+HGM Ui6GA2Fj+TRYUoNKf3UlDAFAgLxdFLVVDqsADHC2LVTun0+KwL9MwmTnKYKWwAaa2Wnw Ed9w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OLl7bCKk; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e36si5303191pgm.17.2019.07.11.22.30.11; Thu, 11 Jul 2019 22:30:11 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OLl7bCKk; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726083AbfGLFaL (ORCPT + 13 others); Fri, 12 Jul 2019 01:30:11 -0400 Received: from mail-pg1-f194.google.com ([209.85.215.194]:35628 "EHLO mail-pg1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725791AbfGLFaK (ORCPT ); Fri, 12 Jul 2019 01:30:10 -0400 Received: by mail-pg1-f194.google.com with SMTP id s27so4015177pgl.2 for ; Thu, 11 Jul 2019 22:30:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=y6GazOWQm4IOOc6xrMbLHqM6mIdOvxmzg2BIOtMFGqg=; b=OLl7bCKkpQB7HHEvi5BkF9G+nxhlHneSx/wcuVyx88Sh/2izv53KLpprn3OrcBdfxf rNFg7nrxIOlioyjKCxApisfUbELSBwZr8FRiz6ewJdbT5hEqRNMDqiss40SoU3mVFwRE c7SHuTjanEBu6AvXHj5GaCr7Io8wfrkPSE4NMD+LYrslHYcbLWIxj33eLl1x2SHE9Rzg RspIACQBzsDAu1P66ipaqShi11/DUXGPE+snfgWs+qLy9xumg4gra08TS7YU5fmNVtyc /Hqz4YLE9XVKKW6iAj9x8RrphBBu5/8GHIGeo8zNwQswhWG/JdJGSfLa9kEfhisnk4g5 sCIA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=y6GazOWQm4IOOc6xrMbLHqM6mIdOvxmzg2BIOtMFGqg=; b=cTunBfv/xazw1aG+Gy9lB/cQIm+xdx81SJArSDwpg0DqKTOAT4yhi12H0ImAvw72mj sAbAr6mMXfAzqvRUdXyk5Rka+ltMIKJHzZuKIL59NwwrmkqH8A/TbFihIT7Trny0oiGN EzF/ecIzgd+dbL1B/9DZ9gXp4VIcxh+E9wqueYn8ruP+yHxG+5rJfyNNvkO4L64avBu3 yF0TswGZ2LSd8SZcmNcsoL+9IKuXXo8heLMqBHjPRBKxqQECdwRXvHbBYRGEt4z/1W38 uZdVj6xRtxJKZvpLzQ3DrrgCSnLlAbkueU/aMDKcOYGdQlS1lG5zleA3/pg1DgOsYHwq dEyA== X-Gm-Message-State: APjAAAWoNgf/wNlftf1wU7hB6u752D1mSklfqAtuzioTGeRxv/V+6XdM MOnjUedeMN2CEIrnCXjAMTZcmrL0x+A= X-Received: by 2002:a63:6fcf:: with SMTP id k198mr8542676pgc.276.1562909409883; Thu, 11 Jul 2019 22:30:09 -0700 (PDT) Received: from localhost ([122.172.28.117]) by smtp.gmail.com with ESMTPSA id o14sm6910270pjp.29.2019.07.11.22.30.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 11 Jul 2019 22:30:09 -0700 (PDT) From: Viresh Kumar To: stable@vger.kernel.org, Julien Thierry Cc: Viresh Kumar , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Marc Zyngier , Mark Rutland , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: [PATCH v4.4 V2 26/43] arm64: entry: Apply BP hardening for high-priority synchronous exceptions Date: Fri, 12 Jul 2019 10:58:14 +0530 Message-Id: <3ce1670e749b99ec2ce2fcee330b06c65bf71474.1562908075.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Will Deacon commit 5dfc6ed27710c42cbc15db5c0d4475699991da0a upstream. Software-step and PC alignment fault exceptions have higher priority than instruction abort exceptions, so apply the BP hardening hooks there too if the user PC appears to reside in kernel space. Reported-by: Dan Hettena Reviewed-by: Marc Zyngier Signed-off-by: Will Deacon Signed-off-by: Catalin Marinas [ v4.4: Resolved rebase conflicts ] Signed-off-by: Viresh Kumar --- arch/arm64/kernel/entry.S | 6 ++++-- arch/arm64/mm/fault.c | 9 +++++++++ 2 files changed, 13 insertions(+), 2 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index 05bfc71639fc..42a141f01f3b 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S @@ -530,8 +530,10 @@ ENDPROC(el1_irq) * Stack or PC alignment exception handling */ mrs x26, far_el1 - // enable interrupts before calling the main handler - enable_dbg_and_irq + enable_dbg +#ifdef CONFIG_TRACE_IRQFLAGS + bl trace_hardirqs_off +#endif ct_user_exit mov x0, x26 mov x1, x25 diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c index 1878c881a247..082f385b6592 100644 --- a/arch/arm64/mm/fault.c +++ b/arch/arm64/mm/fault.c @@ -561,6 +561,12 @@ asmlinkage void __exception do_sp_pc_abort(unsigned long addr, struct siginfo info; struct task_struct *tsk = current; + if (user_mode(regs)) { + if (instruction_pointer(regs) > TASK_SIZE) + arm64_apply_bp_hardening(); + local_irq_enable(); + } + if (show_unhandled_signals && unhandled_signal(tsk, SIGBUS)) pr_info_ratelimited("%s[%d]: %s exception: pc=%p sp=%p\n", tsk->comm, task_pid_nr(tsk), @@ -621,6 +627,9 @@ asmlinkage int __exception do_debug_exception(unsigned long addr_if_watchpoint, if (interrupts_enabled(regs)) trace_hardirqs_off(); + if (user_mode(regs) && instruction_pointer(regs) > TASK_SIZE) + arm64_apply_bp_hardening(); + if (!inf->fn(addr_if_watchpoint, esr, regs)) { rv = 1; } else { From patchwork Fri Jul 12 05:28:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 168886 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp395308ilk; Thu, 11 Jul 2019 22:30:15 -0700 (PDT) X-Google-Smtp-Source: APXvYqx0vnQSVhfjc2ja+k+XFumJJzQuzUDnq7BTRPtzy8YHo7woPVoZ/cnEUhGvE0pwSY7QMjrD X-Received: by 2002:a17:902:1081:: with SMTP id c1mr9308191pla.200.1562909414706; Thu, 11 Jul 2019 22:30:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1562909414; cv=none; d=google.com; s=arc-20160816; b=obq+n1ZyTT9RY1t6zyE0XXWZaYQ83La83aTtG6WFIXx7En4NrvDMmYn9i1KuL00rcI e3tzoE4+/xL73a76JGCitMJLNBO/VDJaUYZU0eumexBf6Z6i7HOabZJqY+Drr1W5KSTq g/XNF8aRtOXXZWkNSXa7T8fCym4EvuJb5cU5Ryt8Z04Lhpm5Pk6sNFoUlkCE8KOWUqD2 c7rouKaMkvGf7vDZ2EtjU4onQcpknekyGwYmdoBMV6PmF/ynyuwUvJgUXEX18m6TjKdL OyHbB+TsTsxXD7/fBKxcSDdyZKifgwzb0V7gVge7SgWzXb3NdKVO73q13IMdrQ89D0Kz Y2Ww== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=kL4bvpTkIxzXH8Y5LirqPgKQFts/fgCJz2Uk/H1BBsA=; b=WusluHxfOyZlWkuJwqM4n0jINl4FrCYXxgZCx8eag/i3ZjcjRZkQbCIzr0hnT5iNvR RuqvS02JZIbl9gGdcAWX3pUZoxlvesBa79agtEB00SE6Ahhilx1QOquxpoWVU7ONEDzJ wSWokXJPznwpD053bYf5kGiLilSSnB763LpQUyJOUUjhv0TtOpZEMZ0j4BCZblvY5WWU LX55nVXY2mXPd1trxMgn5U5iwYVcRoAlcqtUL0QlDkjaMOm3VLb9L3vbNcRbP0NahZnR Tol1axn5Vt5RfSdhEcJVTy50aZeEITmbikwgV861AkejDqWMCG9P2W6kkOGOTpJh4YTz a9AA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=y9XIy3wT; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e36si5303191pgm.17.2019.07.11.22.30.14; Thu, 11 Jul 2019 22:30:14 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=y9XIy3wT; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726084AbfGLFaN (ORCPT + 13 others); Fri, 12 Jul 2019 01:30:13 -0400 Received: from mail-pl1-f195.google.com ([209.85.214.195]:43991 "EHLO mail-pl1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725791AbfGLFaN (ORCPT ); Fri, 12 Jul 2019 01:30:13 -0400 Received: by mail-pl1-f195.google.com with SMTP id cl9so4184234plb.10 for ; Thu, 11 Jul 2019 22:30:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kL4bvpTkIxzXH8Y5LirqPgKQFts/fgCJz2Uk/H1BBsA=; b=y9XIy3wTk60NXWrXhru0mUO9/FiIQPREsZdlokiU8JNb99L26GCt/yZIG2IBNB1WJg Kn89bWYn63fAPyCXVRrqjeEMRm+D73cSM1bBSF2Fpc+SGlMyBlN3M4u2xYr6pxEiIzLd 6Gv2JiHmZ5cDQF2BNlHUn62gP7cXHnpLypPt9ePeql3gi7+CzsagsMbfy1H721NCE0KK e878J9lQ1hyCCnI1gCkFdRECRGv0ZYVS+qNN5zmgumqJ+IBujvctwv3tIikLMsI0cP3O luRcEbquQ0y/S7UTqt9xwzfWjyT42vXfWK8WpJcBNXChxvHVMfw3c9m+up/a1itGbWyc DlTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kL4bvpTkIxzXH8Y5LirqPgKQFts/fgCJz2Uk/H1BBsA=; b=Jolz1qROAhARztd4ZTFwdrTsMuIvPn9Bx38c1AgPK/pj3m1wXQLq0g/97K+NT3OQQx IZC3iId0b6UxJfNy+wMd7kzwFS9f2nyXUtREl6Ova5Qt4KZksVJSnc5EgYKpoet2PSn6 TgwyU+D87cUWT+qokPvdXp6fNhoW7xKIOV0syUl0cbVlgzdzaiuuDrFXkdPjS6rX0AQR y3YL/z9my0qiU6jmBfgEOoIlLZT+zoNKtia1tE4U51X5tpP2VyeLyethT80OgglBsdN9 8x5/ZvEkaAPBCwbm+Uot7VRrXMg4JX7Nj7Ug2sXYDx1jiOJbvS6l/G7DL7W0qJminNOc qHDg== X-Gm-Message-State: APjAAAV3Yvk2d5hq8GOMy9cnUtKgHkuf/uS4T/o2I/lYbC3wL3I9yKOz 9NhPQwNLYkA3v2t65mTam6JRZhpPrjM= X-Received: by 2002:a17:902:4c88:: with SMTP id b8mr9462899ple.29.1562909412745; Thu, 11 Jul 2019 22:30:12 -0700 (PDT) Received: from localhost ([122.172.28.117]) by smtp.gmail.com with ESMTPSA id m9sm14607083pgr.24.2019.07.11.22.30.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 11 Jul 2019 22:30:12 -0700 (PDT) From: Viresh Kumar To: stable@vger.kernel.org, Julien Thierry Cc: Viresh Kumar , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Marc Zyngier , Mark Rutland , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: [PATCH v4.4 V2 27/43] arm64: entry: Apply BP hardening for suspicious interrupts from EL0 Date: Fri, 12 Jul 2019 10:58:15 +0530 Message-Id: <5de9501d4e24fe45bb5938c4eacad6ab56b1ae55.1562908075.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Will Deacon commit 30d88c0e3ace625a92eead9ca0ad94093a8f59fe upstream. It is possible to take an IRQ from EL0 following a branch to a kernel address in such a way that the IRQ is prioritised over the instruction abort. Whilst an attacker would need to get the stars to align here, it might be sufficient with enough calibration so perform BP hardening in the rare case that we see a kernel address in the ELR when handling an IRQ from EL0. Reported-by: Dan Hettena Reviewed-by: Marc Zyngier Signed-off-by: Will Deacon Signed-off-by: Catalin Marinas Signed-off-by: Viresh Kumar --- arch/arm64/kernel/entry.S | 5 +++++ arch/arm64/mm/fault.c | 6 ++++++ 2 files changed, 11 insertions(+) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index 42a141f01f3b..1548be9732ce 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S @@ -582,6 +582,11 @@ ENDPROC(el0_sync) #endif ct_user_exit +#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR + tbz x22, #55, 1f + bl do_el0_irq_bp_hardening +1: +#endif irq_handler #ifdef CONFIG_TRACE_IRQFLAGS diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c index 082f385b6592..9ff48d083c4c 100644 --- a/arch/arm64/mm/fault.c +++ b/arch/arm64/mm/fault.c @@ -535,6 +535,12 @@ asmlinkage void __exception do_mem_abort(unsigned long addr, unsigned int esr, arm64_notify_die("", regs, &info, esr); } +asmlinkage void __exception do_el0_irq_bp_hardening(void) +{ + /* PC has already been checked in entry.S */ + arm64_apply_bp_hardening(); +} + asmlinkage void __exception do_el0_ia_bp_hardening(unsigned long addr, unsigned int esr, struct pt_regs *regs) From patchwork Fri Jul 12 05:28:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 168887 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp395355ilk; Thu, 11 Jul 2019 22:30:18 -0700 (PDT) X-Google-Smtp-Source: APXvYqzXvaXwqOovKVTsgvan5hcg+Kt9nBL2v4MnVkqMK+pISVAG1lecPbYEM7mQBET6ZbQhOsYZ X-Received: by 2002:a63:6a81:: with SMTP id f123mr8833947pgc.348.1562909417696; Thu, 11 Jul 2019 22:30:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1562909417; cv=none; d=google.com; s=arc-20160816; b=YOQcX95jS72q+oQelAlX5EuqTaJDE38ilwcB/TFCWjnSt/U63kTN55x6SwSdV2yDSw 4shm/QqX6jLBWRApKNc0QZIRvuurd68vHwYIqra9HAuxxcBm+ggUKutWGcZWpgnkiSJF k++s9jzkTRYGVJjiIa/lf7ZAixvuNKlHpGfFYOyTQnN7Q3LY7R50yKJ0/6F7jIEZNbx+ M+BgMi2uZ5vvnnwHnGKnBf680lIUI2SZ0vt2k1oqcd5dqxA1u8RgJWThESbNv255eGZf 2hpw8LHqEEw7sWDQ3OJI7R+833FRWFG6T3dfILKtlVfX2RryWinuDbbltINgVicGxe/f /BQA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=D7dDso9mEizkFlSNIpcQXEVsYMAg+0dXCi9osCif4dQ=; b=lKRTC2ZVCYZ0YWMS2B5nJ4AIRckI2rsZM7j/vAsDr2fizU2oKwr4AEOk9iRiogDuPq TiQ5D92Sa+R5wKzplI8Fw3SG+HjQ0nfEWrw5PsZKoCakPxR+vBWl35QGj6J5h3JW1HmW RaQ+SxhL0A//ZeZJHMvVW752ZnHZmqm0Jd57rTj81+1EXpOw8q4r6UjRPB8IllEdhZNs 3BKqTsO7KrUn6tbNJcElKOXGyCgi1avEDRoaYJo9l7Deb5b/tPAAXOrMsd/IXGDS2Vm6 H0IEB3ru7g0PJuHJwJkeLa5VBGlYc0YFBjGzySIuGgXlQ3wPnP3aV0eoqeTdysYNGJPA Ck6g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SHX7e7Fu; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e36si5303191pgm.17.2019.07.11.22.30.16; Thu, 11 Jul 2019 22:30:17 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SHX7e7Fu; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726085AbfGLFaQ (ORCPT + 13 others); Fri, 12 Jul 2019 01:30:16 -0400 Received: from mail-pl1-f194.google.com ([209.85.214.194]:37243 "EHLO mail-pl1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725791AbfGLFaQ (ORCPT ); Fri, 12 Jul 2019 01:30:16 -0400 Received: by mail-pl1-f194.google.com with SMTP id b3so4207612plr.4 for ; Thu, 11 Jul 2019 22:30:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=D7dDso9mEizkFlSNIpcQXEVsYMAg+0dXCi9osCif4dQ=; b=SHX7e7FubaU7wyT+0UYJDMKcleNuApOH3nQjSdAAJSgKC8Q+xG65Uzre6wh+7Sf1o3 W+qVNTVWlECArHmOnif3X4WWMWuL5pI07rLChElsvGHJFDCihXEoQfg95FS4j5+Dr5bc c/ga9/JS/1+6kWpJGDkBOWcY54FXVwqT5/1S+bPCpOKqTwJjITMrmJByIWxeuuYKWq22 sm87pvXFxIDBVpEslQEvWHvl2pRxE+K0YB+gz5O8ECmtQYbNlMnE1fHDyJSwLTxraHym T6L/4VWus1+kiQFadEKTHBtw/FX2wmeSV3WzH4Gk0aNApRRHiO9JSPgUYP4UjP/QsgPq d+Pg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=D7dDso9mEizkFlSNIpcQXEVsYMAg+0dXCi9osCif4dQ=; b=c7uZqUZlimDZYouiywVpxV5jpJyZbpESc+B3tLfQraWr/JKBiPJBeOyBG+gd82Asuu mqj6m7cXjaOaABozry2xQ658EG9QYpm56vAI7qz5hzLoc3F6BHDqGR0fbialpMeAO9SS bm5lnAm+s7gHw1+ece9rUVG3mle5YNu9OmeMDCSjBbWASTAIq7c5DsChh0KCSRUv+mn6 DEnNTQId2yaIBx6PjSJ+kONrD+qPiABmiSZE5L1OYZO+4WtRC6JRBZgU9KXhj6+6dNqs Lq3SBnQa7aNg+qqfbOHbj25SiZLj1zSPmwc6Gn5TDOdIqFBRls5c0OkLFssmoCGC3GRk sYBg== X-Gm-Message-State: APjAAAUC/SjWMJGq/XGIz0DFFPLCQuQ02tZvluyC4Y4FRPAC4pAp5Tf1 UXXz86F6D89B4FKEY75RhBgj2sO+5zw= X-Received: by 2002:a17:902:8d97:: with SMTP id v23mr8886449plo.157.1562909415500; Thu, 11 Jul 2019 22:30:15 -0700 (PDT) Received: from localhost ([122.172.28.117]) by smtp.gmail.com with ESMTPSA id w2sm3669852pgc.32.2019.07.11.22.30.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 11 Jul 2019 22:30:15 -0700 (PDT) From: Viresh Kumar To: stable@vger.kernel.org, Julien Thierry Cc: Viresh Kumar , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Marc Zyngier , Mark Rutland , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: [PATCH v4.4 V2 28/43] arm64: cputype: Add missing MIDR values for Cortex-A72 and Cortex-A75 Date: Fri, 12 Jul 2019 10:58:16 +0530 Message-Id: <70bec6c6d4248724df18ac5b7a0719d7d9733e9b.1562908075.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Will Deacon commit a65d219fe5dc7887fd5ca04c2ac3e9a34feb8dfc upstream. Hook up MIDR values for the Cortex-A72 and Cortex-A75 CPUs, since they will soon need MIDR matches for hardening the branch predictor. Signed-off-by: Will Deacon Signed-off-by: Catalin Marinas [ v4.4: Add A73 values as well ] Signed-off-by: Viresh Kumar --- arch/arm64/include/asm/cputype.h | 6 ++++++ 1 file changed, 6 insertions(+) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index f43e10cfeda2..2a1f44646048 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -77,14 +77,20 @@ #define ARM_CPU_PART_AEM_V8 0xD0F #define ARM_CPU_PART_FOUNDATION 0xD00 #define ARM_CPU_PART_CORTEX_A57 0xD07 +#define ARM_CPU_PART_CORTEX_A72 0xD08 #define ARM_CPU_PART_CORTEX_A53 0xD03 #define ARM_CPU_PART_CORTEX_A55 0xD05 +#define ARM_CPU_PART_CORTEX_A73 0xD09 +#define ARM_CPU_PART_CORTEX_A75 0xD0A #define APM_CPU_PART_POTENZA 0x000 #define CAVIUM_CPU_PART_THUNDERX 0x0A1 #define MIDR_CORTEX_A55 MIDR_CPU_PART(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A55) +#define MIDR_CORTEX_A72 MIDR_CPU_PART(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72) +#define MIDR_CORTEX_A73 MIDR_CPU_PART(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A73) +#define MIDR_CORTEX_A75 MIDR_CPU_PART(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A75) #ifndef __ASSEMBLY__ From patchwork Fri Jul 12 05:28:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 168888 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp395409ilk; Thu, 11 Jul 2019 22:30:20 -0700 (PDT) X-Google-Smtp-Source: APXvYqyBhKwQ1vE+PPE9aCTnTRQIST9KPJkafPuzol7ineVG2NovZhwDXeVSO7L0ALNkl54+T6eU X-Received: by 2002:a17:90a:ac11:: with SMTP id o17mr9528120pjq.134.1562909420398; Thu, 11 Jul 2019 22:30:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1562909420; cv=none; d=google.com; s=arc-20160816; b=XUHjC54J7atAGB63u17jwAaN3JsKY6DiycK8RRxiUs01xEi2eNq7caF/93rScXhjOK a2K++yO01E3ZxP31l1t/H1F0776MXzYgm5i3WN6i9ME+o8KI6Ra/vlGWaR6KwezARYwp D2rH2h1P8iIBY765pECXQeSv49SlmJF7FY9qdJoq3coc43ZkoeVj8jXxVBdMToCdj9fe o/lQoUFlefLJ9iVVkzVpVEareinZDg+3MN1rhHaMXUwTw1Z12S9Gj575R2uc8kPNNya2 0kte3YKsnHALbx3NSXhcC0w/dO6RBzkxLTj//8hVqy76goG5IS2mwIZ0edfaYpXaQJR7 NIlA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=sqSfnQDS8sjUZN/3AxA8S/yruKf46+OQJxAy5E4hEak=; b=kMgrqTCgAw8wEXAT+xK8aW6wFSrXKA6uFihZ3AVGrmI1ixhAqolSnujEACw7bA2DlV jajfwCSC+nGXDH1rHJR128PBe66IH/ZN2iLCTPih4QaL2TUnMLMM5c2kWfP++oWh1b6S CK3PYnAoYlpweH91bhQG5HGU41+2KSA0ic0pCveG2m3i4UPtQwxDHek51anywvF+eGPY SlccHPOniKWn7U1iOzjuZrkdrAhMXl8aX7Qo3jdZ9NwKah99pG0KdGFGe0jh3cq4OzkE ZuKq7YPaRtiNZP16oqVft7IRCATaT2fp8ds+ubHd5KhplLvOFnguaZdvqOiDzPMr71nm 7dhA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="VyKNs/FI"; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e36si5303191pgm.17.2019.07.11.22.30.19; Thu, 11 Jul 2019 22:30:20 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="VyKNs/FI"; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726091AbfGLFaT (ORCPT + 13 others); Fri, 12 Jul 2019 01:30:19 -0400 Received: from mail-pg1-f193.google.com ([209.85.215.193]:44856 "EHLO mail-pg1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725791AbfGLFaS (ORCPT ); Fri, 12 Jul 2019 01:30:18 -0400 Received: by mail-pg1-f193.google.com with SMTP id i18so3990804pgl.11 for ; Thu, 11 Jul 2019 22:30:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=sqSfnQDS8sjUZN/3AxA8S/yruKf46+OQJxAy5E4hEak=; b=VyKNs/FIWF1WM+ek3qH+rFuK/9b+IRraNhUiCTZq+VByH2PDsFM+ZzVRunnTcmKPD8 rcT+7o4Q6LLKSt+hECJSfZsOnVxQksi9+G04j+7c9D+rwj9fSFy9Bpmcxoj9P9beID+B mFxmSs4x0uUuTqCK4SLHZYIB1fFHlEs+U0rFQUCAEsnq32OieHmCUChUPgxm3M8moBit f4d9vB5rosS/682Fu9nyRtWjXyU4dyNkeXfOzFPFtkpCQfw0HjV3lIgeGX/bsztZaCdB WmK7QSt3X2aL1zwLoYlC78RttynyAtWptxxt5zlcSvEcI64wkoyifVkVwoWtjr1lNAQ3 v6mQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sqSfnQDS8sjUZN/3AxA8S/yruKf46+OQJxAy5E4hEak=; b=Xeue+2zT1m39Kzxt3x/jLrzFYoo8LxgOHlQXf8/VdccPalzhmgQQqdhI1b9XdXO5PE wK/N0am/kqMnc7mXLdxaZFDDF2AeZ8THi5Mr3RqEyLwqSJ8IKIKV7yp9PyDkuwXbjUpS 4X9xs7Egg5mm0Nkdimf9TkwhMDPbhwO1N7D2E2L+RAp414D29rQyaWQUkFa4jp9QmQiW w0QL59UrpEP7eqhyuvs5KpN6uu5Yw0dzwSHbJhtKIBS+VznJE3TZeyr6Uf2fmqQJboW+ KiygA8cTAmSdpdYVFcz0Ooy9vT8JmoCUeqgRi9p7mtlr/WI2zxhTYIzmFflf3pxNty8n shCQ== X-Gm-Message-State: APjAAAV+LEG+aTm34NsIrbAQXN5pY+ailQNWAabHrrt78dPYAgzPZu/I 3fNdSvbHSd2kQTHonK7zlYr/kDktBz4= X-Received: by 2002:a17:90a:4f0e:: with SMTP id p14mr9130229pjh.40.1562909418024; Thu, 11 Jul 2019 22:30:18 -0700 (PDT) Received: from localhost ([122.172.28.117]) by smtp.gmail.com with ESMTPSA id n26sm8177303pfa.83.2019.07.11.22.30.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 11 Jul 2019 22:30:17 -0700 (PDT) From: Viresh Kumar To: stable@vger.kernel.org, Julien Thierry Cc: Viresh Kumar , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Marc Zyngier , Mark Rutland , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: [PATCH v4.4 V2 29/43] arm64: cpu_errata: Allow an erratum to be match for all revisions of a core Date: Fri, 12 Jul 2019 10:58:17 +0530 Message-Id: X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Marc Zyngier commit 06f1494f837da8997d670a1ba87add7963b08922 upstream. Some minor erratum may not be fixed in further revisions of a core, leading to a situation where the workaround needs to be updated each time an updated core is released. Introduce a MIDR_ALL_VERSIONS match helper that will work for all versions of that MIDR, once and for all. Acked-by: Thomas Gleixner Acked-by: Mark Rutland Acked-by: Daniel Lezcano Reviewed-by: Suzuki K Poulose Signed-off-by: Marc Zyngier Signed-off-by: Viresh Kumar --- arch/arm64/kernel/cpu_errata.c | 7 +++++++ 1 file changed, 7 insertions(+) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index 19c51d1cd302..80765feae955 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -124,6 +124,13 @@ static void install_bp_hardening_cb(const struct arm64_cpu_capabilities *entry, .midr_range_min = min, \ .midr_range_max = max +#define MIDR_ALL_VERSIONS(model) \ + .def_scope = SCOPE_LOCAL_CPU, \ + .matches = is_affected_midr_range, \ + .midr_model = model, \ + .midr_range_min = 0, \ + .midr_range_max = (MIDR_VARIANT_MASK | MIDR_REVISION_MASK) + const struct arm64_cpu_capabilities arm64_errata[] = { #if defined(CONFIG_ARM64_ERRATUM_826319) || \ defined(CONFIG_ARM64_ERRATUM_827319) || \ From patchwork Fri Jul 12 05:28:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 168889 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp395465ilk; Thu, 11 Jul 2019 22:30:23 -0700 (PDT) X-Google-Smtp-Source: APXvYqx/ImcjrqYy93NZKlJNBPwkGZt2n2btTMBxLqwR+9SQSYktnwwsZYnguInBD+LTG5dLjQ12 X-Received: by 2002:a17:90a:3344:: with SMTP id m62mr9402178pjb.135.1562909423601; Thu, 11 Jul 2019 22:30:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1562909423; cv=none; d=google.com; s=arc-20160816; b=lp/OKkdAyJHUPyIYpJ6IVk7NBTczjgwunxPNtSQetRHf1sUZx0KjKjhHl8MD/dcR0P L+aLq/becr9mzwIr6MKDoCQnxXVwFXDqvlQyGWPVAIkppqmbmyNlkAhJNjtoO4nLwEEB Uqz3OWGDiuW0ojSTIHSvEPTK/hdtCeM6YZsiqZFXXRptsKv8tUx7/vE0Kb2zytfoqkCl Ptd+5ZmG0cAI9EnbZ4TaRZi9wKSSgZO6DYM0ioliSYS/yLxcm0WgZFPEiLdUe/Bt60z2 aESovV59clvNrvAb7h1Uw5FckUEYni6KdYog90uZlLQOCTdfRqos3NE+EFIShqriY1dP YEng== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=mSGnDnoJppey6/ef3bclxREaifXq44bcCaQXzmdFJKI=; b=xwAVJSYgvSQqgkOaPSz73C3d+KIZN16L2mAiCDWneX8DnchqNy1eTTv12Jzh6WppWk 5231TpXxsg5pjpr+uz3as0AcBS3nfoNXKeoQuRvprreTcvA4+mjspM6d84em4vTLAQf2 3mOxrA6FQidqXeWie16rNdBfsU8pQfpHxRvtN7vLrdC8YpxWlGDtDYmq105dPDGxu6ZK kcctfMOjDQ8LsSkZAhs6Y40TnrVvLYfiX1utvGYyIZgb/ePThTX04Tip8Y1KJZUnPtM1 6OVYfaFbp3lufnhUK86oV3GKpgtaOa5BQtz6Dr/B2MkSaL+VDcX8d00y661qMsToLTF+ hdTA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=AzrkWM5i; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Cortex-A57, A72, A73 and A75 are susceptible to branch predictor aliasing and can theoretically be attacked by malicious code. This patch implements a PSCI-based mitigation for these CPUs when available. The call into firmware will invalidate the branch predictor state, preventing any malicious entries from affecting other victim contexts. Co-developed-by: Marc Zyngier Signed-off-by: Will Deacon Signed-off-by: Catalin Marinas Signed-off-by: Viresh Kumar --- arch/arm64/kernel/bpi.S | 24 +++++++++++++++++++ arch/arm64/kernel/cpu_errata.c | 42 ++++++++++++++++++++++++++++++++++ 2 files changed, 66 insertions(+) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/kernel/bpi.S b/arch/arm64/kernel/bpi.S index 06a931eb2673..dec95bd82e31 100644 --- a/arch/arm64/kernel/bpi.S +++ b/arch/arm64/kernel/bpi.S @@ -53,3 +53,27 @@ ENTRY(__bp_harden_hyp_vecs_start) vectors __kvm_hyp_vector .endr ENTRY(__bp_harden_hyp_vecs_end) +ENTRY(__psci_hyp_bp_inval_start) + sub sp, sp, #(8 * 18) + stp x16, x17, [sp, #(16 * 0)] + stp x14, x15, [sp, #(16 * 1)] + stp x12, x13, [sp, #(16 * 2)] + stp x10, x11, [sp, #(16 * 3)] + stp x8, x9, [sp, #(16 * 4)] + stp x6, x7, [sp, #(16 * 5)] + stp x4, x5, [sp, #(16 * 6)] + stp x2, x3, [sp, #(16 * 7)] + stp x0, x1, [sp, #(16 * 8)] + mov x0, #0x84000000 + smc #0 + ldp x16, x17, [sp, #(16 * 0)] + ldp x14, x15, [sp, #(16 * 1)] + ldp x12, x13, [sp, #(16 * 2)] + ldp x10, x11, [sp, #(16 * 3)] + ldp x8, x9, [sp, #(16 * 4)] + ldp x6, x7, [sp, #(16 * 5)] + ldp x4, x5, [sp, #(16 * 6)] + ldp x2, x3, [sp, #(16 * 7)] + ldp x0, x1, [sp, #(16 * 8)] + add sp, sp, #(8 * 18) +ENTRY(__psci_hyp_bp_inval_end) diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index 80765feae955..dbd7b944a37e 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -50,6 +50,8 @@ is_affected_midr_range(const struct arm64_cpu_capabilities *entry, int scope) DEFINE_PER_CPU_READ_MOSTLY(struct bp_hardening_data, bp_hardening_data); #ifdef CONFIG_KVM +extern char __psci_hyp_bp_inval_start[], __psci_hyp_bp_inval_end[]; + static void __copy_hyp_vect_bpi(int slot, const char *hyp_vecs_start, const char *hyp_vecs_end) { @@ -91,6 +93,9 @@ static void __install_bp_hardening_cb(bp_hardening_cb_t fn, spin_unlock(&bp_lock); } #else +#define __psci_hyp_bp_inval_start NULL +#define __psci_hyp_bp_inval_end NULL + static void __install_bp_hardening_cb(bp_hardening_cb_t fn, const char *hyp_vecs_start, const char *hyp_vecs_end) @@ -115,6 +120,21 @@ static void install_bp_hardening_cb(const struct arm64_cpu_capabilities *entry, __install_bp_hardening_cb(fn, hyp_vecs_start, hyp_vecs_end); } + +#include + +static int enable_psci_bp_hardening(void *data) +{ + const struct arm64_cpu_capabilities *entry = data; + + if (psci_ops.get_version) + install_bp_hardening_cb(entry, + (bp_hardening_cb_t)psci_ops.get_version, + __psci_hyp_bp_inval_start, + __psci_hyp_bp_inval_end); + + return 0; +} #endif /* CONFIG_HARDEN_BRANCH_PREDICTOR */ #define MIDR_RANGE(model, min, max) \ @@ -192,6 +212,28 @@ const struct arm64_cpu_capabilities arm64_errata[] = { MIDR_RANGE(MIDR_THUNDERX, 0x00, (1 << MIDR_VARIANT_SHIFT) | 1), }, +#endif +#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR + { + .capability = ARM64_HARDEN_BRANCH_PREDICTOR, + MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), + .enable = enable_psci_bp_hardening, + }, + { + .capability = ARM64_HARDEN_BRANCH_PREDICTOR, + MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), + .enable = enable_psci_bp_hardening, + }, + { + .capability = ARM64_HARDEN_BRANCH_PREDICTOR, + MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), + .enable = enable_psci_bp_hardening, + }, + { + .capability = ARM64_HARDEN_BRANCH_PREDICTOR, + MIDR_ALL_VERSIONS(MIDR_CORTEX_A75), + .enable = enable_psci_bp_hardening, + }, #endif { } From patchwork Fri Jul 12 05:28:19 2019 Content-Type: text/plain; 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Add Broadcom Vulcan implementor ID and part ID in cputype.h. This is to document the values. Signed-off-by: Jayachandran C Acked-by: Will Deacon Acked-by: Catalin Marinas Signed-off-by: Florian Fainelli Signed-off-by: Viresh Kumar --- arch/arm64/include/asm/cputype.h | 3 +++ 1 file changed, 3 insertions(+) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index 2a1f44646048..c6976dd6c32a 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -73,6 +73,7 @@ #define ARM_CPU_IMP_ARM 0x41 #define ARM_CPU_IMP_APM 0x50 #define ARM_CPU_IMP_CAVIUM 0x43 +#define ARM_CPU_IMP_BRCM 0x42 #define ARM_CPU_PART_AEM_V8 0xD0F #define ARM_CPU_PART_FOUNDATION 0xD00 @@ -87,6 +88,8 @@ #define CAVIUM_CPU_PART_THUNDERX 0x0A1 +#define BRCM_CPU_PART_VULCAN 0x516 + #define MIDR_CORTEX_A55 MIDR_CPU_PART(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A55) #define MIDR_CORTEX_A72 MIDR_CPU_PART(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72) #define MIDR_CORTEX_A73 MIDR_CPU_PART(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A73) From patchwork Fri Jul 12 05:28:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 168891 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp395572ilk; Thu, 11 Jul 2019 22:30:28 -0700 (PDT) X-Google-Smtp-Source: APXvYqyAM0hiLXFHkiu2kQTu/oBxV9u/UA0f/Vh0zMYIMAByjLGV4+5PBD5jru9WMki/tKUJ0BHL X-Received: by 2002:a63:4c19:: with SMTP id z25mr8802106pga.47.1562909428482; Thu, 11 Jul 2019 22:30:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1562909428; cv=none; d=google.com; s=arc-20160816; b=pkr8XvLkQwlRwwbWXtpmeBZqL0+Bd16vInOt9AvtAiK9UZgP8pQJZIkqzC9td8BOno w4ysyITofKmEb2me/yjNTgW14setxBdrCMtg9HEJ1rlhM/D5oOoo2xHBijkqZpb00t/O zGHCUyCi7bvQNnQpTeVqcODDtEMctV7aHzV7T7ZU2wu8PhekytXkxyGAC/JM8mtTRgiN KDSDijO+glc199TKzGgvkippZpvHDydl9EI1UCIFST1fYba2Tkg4FRMhqJRoBe2KNR7w ecfBtn0nvsXFODO1u3m3HHyAd46CfZO6XAZVjXYR/eEI4rPexJNgt5rOTuvt09pKHTN4 omoA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=sBbWRB3LgLlv2c3U4FxHDhn97v+yXFInuDLMYZ1aFeE=; b=mG9iLJp1n4QDBGKCKPapAK5TViKXWnQ3TpOf6OcHRvFrk8E3XTiHuVsOQyaXfIS4Z8 4IMlqqaaNd6f7HUyCD+Z+1o1+AGbHtWY3/BffMyENSWILmav+R7Xo6G2Y9ZtsPcnNrDY ZxMiYL+gDZswRVxgBv7OFJda9k9t50S3Qv5aFdv/ld5LIAWkd/Q+xIBGxV7+duNHvnAM +awAiVoZ1+7U0BflqK/MpWsbRs2EoHxRMHRTWDUqqL7E0h8O93+RlCkEmXndWuF5v00s Sb1Kcinn9giLoxCLJ+q2Ntvm8o54fZAANRV9tOIFm/te49tnsK0BVwTKg8luoOzD0Esj bBfQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=LE9qttKz; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e36si5303191pgm.17.2019.07.11.22.30.28; Thu, 11 Jul 2019 22:30:28 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=LE9qttKz; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725966AbfGLFa1 (ORCPT + 13 others); Fri, 12 Jul 2019 01:30:27 -0400 Received: from mail-pf1-f196.google.com ([209.85.210.196]:43560 "EHLO mail-pf1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725791AbfGLFa1 (ORCPT ); Fri, 12 Jul 2019 01:30:27 -0400 Received: by mail-pf1-f196.google.com with SMTP id i189so3785651pfg.10 for ; Thu, 11 Jul 2019 22:30:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=sBbWRB3LgLlv2c3U4FxHDhn97v+yXFInuDLMYZ1aFeE=; b=LE9qttKz9JVHQZJ301vvMUJGamwX7YDgGYxVrR/vnjiJ8Jz/5xxe4200tspVVRXWk+ W7XipnbG6F97cOGxwyGXPdCqkq3BRx2g4y26HaEqjAsFETioKBf/BZTT1PQlDrGjo7ou EAeXfl3TsM9qubCidTFeGydMyrJR/c6bJijftJkl1MWUPIeVdAUp5JN31QVDwcLvHVR4 8urkOnbfh7ph5eojT6bcKlyIEOF7SVTdfu7V8JVCECv1woL27Eib/wR68NZrbXu3wBhJ e58ovEnhDxWGkX3plYNZ+KErAl2nlKIP7jvpIT/lTh6EdP+WvOUY/9tEUQSwyx9u3ttN GtOQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sBbWRB3LgLlv2c3U4FxHDhn97v+yXFInuDLMYZ1aFeE=; b=RDGu8mL5BVL0Y7hjt0vCC1M2usTduKonJCGqTVqE9xNUaOhASBX/m2YALcdzDvw8Gk yu3Ad7ZtNsIKT/R0A4fwQupHlTSaIMxS14Vyn7uDZZTdjgnrztW+wI8eBhtOZsVZsJHV CaxmU3BsqzexcitZO98z4fhjfyBu0Ou0bBCd3v/An1cYe020OvhEOEb1lO31iFsvgy6p qvwy9kdo7pgeQk0JKrDYEutrCLvFxqIrxdRVRpIH+bGSUJIFKmcz+pu6MHvsfTJ+Nszk OhZtrfkd55hhDA5M9kRClbzH6a7AFte/cKLGjgE8SLgfutDJfgWwA0XELGDMGgGOD1Yp hatw== X-Gm-Message-State: APjAAAX1pcZMe4imeiFGhm4Qbf7rRsgkN1LMo1ANlikh36QzGZ6TW4ib j76CFXSqkd4rhMXS7FW1PXW9+oQWZNE= X-Received: by 2002:a65:508c:: with SMTP id r12mr8006992pgp.1.1562909426531; Thu, 11 Jul 2019 22:30:26 -0700 (PDT) Received: from localhost ([122.172.28.117]) by smtp.gmail.com with ESMTPSA id q63sm10762553pfb.81.2019.07.11.22.30.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 11 Jul 2019 22:30:25 -0700 (PDT) From: Viresh Kumar To: stable@vger.kernel.org, Julien Thierry Cc: Viresh Kumar , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Marc Zyngier , Mark Rutland , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: [PATCH v4.4 V2 32/43] arm64: cputype: Add MIDR values for Cavium ThunderX2 CPUs Date: Fri, 12 Jul 2019 10:58:20 +0530 Message-Id: <6565b88d21dbcfbb592fbf7a5a00f20caf2e934f.1562908075.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Jayachandran C commit 0d90718871fe80f019b7295ec9d2b23121e396fb upstream. Add the older Broadcom ID as well as the new Cavium ID for ThunderX2 CPUs. Signed-off-by: Jayachandran C Signed-off-by: Will Deacon Signed-off-by: Catalin Marinas Signed-off-by: Viresh Kumar --- arch/arm64/include/asm/cputype.h | 3 +++ 1 file changed, 3 insertions(+) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index c6976dd6c32a..9cc7d485c812 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -87,6 +87,7 @@ #define APM_CPU_PART_POTENZA 0x000 #define CAVIUM_CPU_PART_THUNDERX 0x0A1 +#define CAVIUM_CPU_PART_THUNDERX2 0x0AF #define BRCM_CPU_PART_VULCAN 0x516 @@ -94,6 +95,8 @@ #define MIDR_CORTEX_A72 MIDR_CPU_PART(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72) #define MIDR_CORTEX_A73 MIDR_CPU_PART(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A73) #define MIDR_CORTEX_A75 MIDR_CPU_PART(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A75) +#define MIDR_CAVIUM_THUNDERX2 MIDR_CPU_PART(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX2) +#define MIDR_BRCM_VULCAN MIDR_CPU_PART(ARM_CPU_IMP_BRCM, BRCM_CPU_PART_VULCAN) #ifndef __ASSEMBLY__ From patchwork Fri Jul 12 05:28:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 168892 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp395635ilk; Thu, 11 Jul 2019 22:30:31 -0700 (PDT) X-Google-Smtp-Source: APXvYqxEhuWlym1fQNBzkIbqgobaMahchHKr9UMeV2LW6FtWXn9KJHF+6QxKS+z0nNmQNkAQhVM8 X-Received: by 2002:a17:90a:32c7:: with SMTP id l65mr9440231pjb.1.1562909431483; Thu, 11 Jul 2019 22:30:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1562909431; cv=none; d=google.com; s=arc-20160816; b=zFjZ8pMOWbGidHLRXDjkLq1AcjXzXLLTifD6gMD1uL3CifOan5oUflrcRAArOV9JQp zlw5gYDCP1FKbRaYc8EJJerRhzVjUjdaspLKu0rIB8Iquhhb+yqcrUYV8d/VGiJ6f+ou vXb2WymFs5thFveqcs4s58lyViU6k0nWVO1PVcHqEeF80pSfSs8W04Qqhjr4XhrlTrSU u/EFUVmCbw1phk+9EgyxT4fSmPQ4Qf5eGnTnKePlzNGDvOZW67XgcP8m1CFAMapOroEW GxzNYowtr3Au6+os6M4bXxSRGdlXzPJLtRN/uf04oNK4GJZDx+cGaUTGf4Z/IZZ0zRps N3ug== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=dkWh8S1DsW6tSZCYoLWe69ClR5UVvKugQ1/Th9fCzhU=; b=RhBCK2cKfpMiOBWFIkesQHdQleFZItUPA6lvjCPNbErXgFGs1/hzwD3gBkardkQ0/o 2bY0Yk8EobZuSvgKHsH78c6iShep4iKYLvxX6LdOnMeFeV4uYid0R6yyzqThEL7gj1Yy rN7KOpX5EEF/lVdQpW39Au/RHmMBD8vewyRIPocFq4fTjtaEDwMqdjXYqrBSqKZqi1d0 vcn5ww1WiISNpN8Saj9TJDpW02j0nhE0nzJTZYkye8iuSUdxXEZlWKXmF4wQuBqZNm0g ZzBNm8kH61QUKiTlInTDqZBB+HJkZcCzuosLof5IFn8RIud7TyCVo0U646Vm5YQBFZOq bvew== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SMwR+6pd; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e36si5303191pgm.17.2019.07.11.22.30.30; Thu, 11 Jul 2019 22:30:31 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SMwR+6pd; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726096AbfGLFaa (ORCPT + 13 others); Fri, 12 Jul 2019 01:30:30 -0400 Received: from mail-pl1-f195.google.com ([209.85.214.195]:44307 "EHLO mail-pl1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725791AbfGLFaa (ORCPT ); Fri, 12 Jul 2019 01:30:30 -0400 Received: by mail-pl1-f195.google.com with SMTP id t14so4188243plr.11 for ; Thu, 11 Jul 2019 22:30:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dkWh8S1DsW6tSZCYoLWe69ClR5UVvKugQ1/Th9fCzhU=; b=SMwR+6pdVG1+jVLkxuQVbtP/+BVTEx6rGEByEY4qdeK029SHABdRrCTMiXb+4nre45 h8O859XSPNC1NRkmJg2+4GipJ9ze5HOA/R6idJQ+Pt7C/gT7400+oVGtmwIU7nb7ULsX Oj54EVb6tOLF1SlsBurQ5iK3J3FAGqldb9vJuYmTP1R4tXxxxiXMf8TsxhbeUBNW3N0J UeWGq6ZtKrNGNghl5q2gRSIQzgEYpgWnrZ7JrGf/e5RvYg1+EE5//gzM/tZ9I+IV8fEQ OSKDS5JI3fNrLgVpfcqmN9DeAephhosWwadHtDNS6bmi0higyU99JwprNFVc7BjMjVJ9 0F+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dkWh8S1DsW6tSZCYoLWe69ClR5UVvKugQ1/Th9fCzhU=; b=k1E8Qwb6lZsNIlx7G/t96LoVxQaB6fXQZkvecmARxwsqJGJBYX8fCGkKLAQ3f/c12J euTQ2xpuGYYpmnoO8GKDu+wkvcBBddc5igPXEDLrDUtQLMaFaOGaYJcVqEQgTyzK7v1j IcvIDJLaD3yDB7pbl3GxBIfwL3/4VyTXVjkq3orb69ptKBrkN4mCLWKMpkdMO9ySHAP9 G+464sh2zShX/ruVJE1YDixjqEk8RC5r8j3b1kDCiT1pXvXF3eTb775WLvgOK0VKJMy3 BhgAWUhny0E6KHx+KdqV83PXNcEiF8FPP5Oyele9c56ocDqgBQ9+YwpsFJaXOezSwcF/ lLDw== X-Gm-Message-State: APjAAAXq7ZkzzCjIJQMiKLPcqObyN/Un5hcUnpjNkGuf0SNehkAC59Sj MblQf2IOkIkuX7d50ifHAZ4nn2lpMnM= X-Received: by 2002:a17:902:9307:: with SMTP id bc7mr8879363plb.183.1562909429452; Thu, 11 Jul 2019 22:30:29 -0700 (PDT) Received: from localhost ([122.172.28.117]) by smtp.gmail.com with ESMTPSA id 14sm6731541pgp.37.2019.07.11.22.30.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 11 Jul 2019 22:30:28 -0700 (PDT) From: Viresh Kumar To: stable@vger.kernel.org, Julien Thierry Cc: Viresh Kumar , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Marc Zyngier , Mark Rutland , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: [PATCH v4.4 V2 33/43] arm64: Branch predictor hardening for Cavium ThunderX2 Date: Fri, 12 Jul 2019 10:58:21 +0530 Message-Id: X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Jayachandran C commit f3d795d9b360523beca6d13ba64c2c532f601149 upstream. Use PSCI based mitigation for speculative execution attacks targeting the branch predictor. We use the same mechanism as the one used for Cortex-A CPUs, we expect the PSCI version call to have a side effect of clearing the BTBs. Acked-by: Will Deacon Signed-off-by: Jayachandran C Signed-off-by: Catalin Marinas Signed-off-by: Viresh Kumar --- arch/arm64/kernel/cpu_errata.c | 10 ++++++++++ 1 file changed, 10 insertions(+) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index dbd7b944a37e..ff22915a2865 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -234,6 +234,16 @@ const struct arm64_cpu_capabilities arm64_errata[] = { MIDR_ALL_VERSIONS(MIDR_CORTEX_A75), .enable = enable_psci_bp_hardening, }, + { + .capability = ARM64_HARDEN_BRANCH_PREDICTOR, + MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), + .enable = enable_psci_bp_hardening, + }, + { + .capability = ARM64_HARDEN_BRANCH_PREDICTOR, + MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), + .enable = enable_psci_bp_hardening, + }, #endif { } From patchwork Fri Jul 12 05:28:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 168893 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp395681ilk; Thu, 11 Jul 2019 22:30:34 -0700 (PDT) X-Google-Smtp-Source: APXvYqxlzCL2xIF08ipb8q7YsK9ekFu2RlvU7eQJHu6lg33zEC1YiD3zgFegMqKvs95xaJNBQLFQ X-Received: by 2002:a17:90a:d151:: with SMTP id t17mr9334368pjw.60.1562909434332; Thu, 11 Jul 2019 22:30:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1562909434; cv=none; d=google.com; s=arc-20160816; b=kBrmV62IjmjIa/tuS9SBoWd1x8ju5TicazbcoT0yOaKF9sMZkLnVN/21Q+f/94+EaU T0SzZrAdHnbgwA+2TKY3RHVPoz+tIpFbCfHbecUCWvvBT9dkP2YagoanBynERvSXPiyJ jhAU2nTTO7oIiIIwb0nQzJmHPCgMYM8SvADDOOOcqlogkprgoeuLMZw+tguDwoqgkzj9 9OLxMMcvVbRD9+Whr5pHuhsEbG1Xif8PhHpGJWGfsbf8cECQWZbbNEkbOGVSYWm/TBMT wH/j0+zbln3OayvbOkMx8YH5CNcqqmvpC9CWH32N2CzC8SraqO4mKHjGw3/LoqK8S3p7 ZySQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=yC2M+WqtpDn8WEqkn0+0Dw3Z53HTrfg3c6ZZe0WXdnU=; b=Hu3cDfzd8pgBamgNXu/u7v+3BPRUCrgdXg0t3O7TDTlCQtX2luasYKf+Zcc0FsKYDx Y+EnwbbsJURfiVGBWhE05bSC5NJxNY+tfnVxUps0En7b7ZYvFETGNN/gZkPS3LVVOYcY +ovsQIMdwRmosS0IfjNmdlH/R2CKgCf+A/ULbonR4fHBBUpw0OhYE8kLdyEv8+ABvI3K dt2mCSjM3v/9NbQpe9kuhUkwGkggqP1YWnLLsoTNfKxdIQs2W9sTNdc7kBrszeRO/Y4e qk72s8zj45ygFB2p94kM9wPgOu6BlI1ZKJftrYfBOd3UKLSa/Pq3lG2b9Y2h3qAkUKH5 gi7g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hnTNOY9k; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Adds helpers to do SMC and HVC based on ARM SMC Calling Convention. CONFIG_HAVE_ARM_SMCCC is enabled for architectures that may support the SMC or HVC instruction. It's the responsibility of the caller to know if the SMC instruction is supported by the platform. This patch doesn't provide an implementation of the declared functions. Later patches will bring in implementations and set CONFIG_HAVE_ARM_SMCCC for ARM and ARM64 respectively. Reviewed-by: Lorenzo Pieralisi Signed-off-by: Jens Wiklander Signed-off-by: Russell King [ v4.4: Added #ifndef __ASSEMBLY__ section to fix compilation issues ] Signed-off-by: Viresh Kumar --- drivers/firmware/Kconfig | 3 ++ include/linux/arm-smccc.h | 107 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 110 insertions(+) create mode 100644 include/linux/arm-smccc.h -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/drivers/firmware/Kconfig b/drivers/firmware/Kconfig index cf478fe6b335..49a3a1185bb6 100644 --- a/drivers/firmware/Kconfig +++ b/drivers/firmware/Kconfig @@ -173,6 +173,9 @@ config QCOM_SCM_64 def_bool y depends on QCOM_SCM && ARM64 +config HAVE_ARM_SMCCC + bool + source "drivers/firmware/broadcom/Kconfig" source "drivers/firmware/google/Kconfig" source "drivers/firmware/efi/Kconfig" diff --git a/include/linux/arm-smccc.h b/include/linux/arm-smccc.h new file mode 100644 index 000000000000..611d10580340 --- /dev/null +++ b/include/linux/arm-smccc.h @@ -0,0 +1,107 @@ +/* + * Copyright (c) 2015, Linaro Limited + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#ifndef __LINUX_ARM_SMCCC_H +#define __LINUX_ARM_SMCCC_H + +#include +#include + +/* + * This file provides common defines for ARM SMC Calling Convention as + * specified in + * http://infocenter.arm.com/help/topic/com.arm.doc.den0028a/index.html + */ + +#define ARM_SMCCC_STD_CALL 0 +#define ARM_SMCCC_FAST_CALL 1 +#define ARM_SMCCC_TYPE_SHIFT 31 + +#define ARM_SMCCC_SMC_32 0 +#define ARM_SMCCC_SMC_64 1 +#define ARM_SMCCC_CALL_CONV_SHIFT 30 + +#define ARM_SMCCC_OWNER_MASK 0x3F +#define ARM_SMCCC_OWNER_SHIFT 24 + +#define ARM_SMCCC_FUNC_MASK 0xFFFF + +#define ARM_SMCCC_IS_FAST_CALL(smc_val) \ + ((smc_val) & (ARM_SMCCC_FAST_CALL << ARM_SMCCC_TYPE_SHIFT)) +#define ARM_SMCCC_IS_64(smc_val) \ + ((smc_val) & (ARM_SMCCC_SMC_64 << ARM_SMCCC_CALL_CONV_SHIFT)) +#define ARM_SMCCC_FUNC_NUM(smc_val) ((smc_val) & ARM_SMCCC_FUNC_MASK) +#define ARM_SMCCC_OWNER_NUM(smc_val) \ + (((smc_val) >> ARM_SMCCC_OWNER_SHIFT) & ARM_SMCCC_OWNER_MASK) + +#define ARM_SMCCC_CALL_VAL(type, calling_convention, owner, func_num) \ + (((type) << ARM_SMCCC_TYPE_SHIFT) | \ + ((calling_convention) << ARM_SMCCC_CALL_CONV_SHIFT) | \ + (((owner) & ARM_SMCCC_OWNER_MASK) << ARM_SMCCC_OWNER_SHIFT) | \ + ((func_num) & ARM_SMCCC_FUNC_MASK)) + +#define ARM_SMCCC_OWNER_ARCH 0 +#define ARM_SMCCC_OWNER_CPU 1 +#define ARM_SMCCC_OWNER_SIP 2 +#define ARM_SMCCC_OWNER_OEM 3 +#define ARM_SMCCC_OWNER_STANDARD 4 +#define ARM_SMCCC_OWNER_TRUSTED_APP 48 +#define ARM_SMCCC_OWNER_TRUSTED_APP_END 49 +#define ARM_SMCCC_OWNER_TRUSTED_OS 50 +#define ARM_SMCCC_OWNER_TRUSTED_OS_END 63 + +#ifndef __ASSEMBLY__ + +/** + * struct arm_smccc_res - Result from SMC/HVC call + * @a0-a3 result values from registers 0 to 3 + */ +struct arm_smccc_res { + unsigned long a0; + unsigned long a1; + unsigned long a2; + unsigned long a3; +}; + +/** + * arm_smccc_smc() - make SMC calls + * @a0-a7: arguments passed in registers 0 to 7 + * @res: result values from registers 0 to 3 + * + * This function is used to make SMC calls following SMC Calling Convention. + * The content of the supplied param are copied to registers 0 to 7 prior + * to the SMC instruction. The return values are updated with the content + * from register 0 to 3 on return from the SMC instruction. + */ +asmlinkage void arm_smccc_smc(unsigned long a0, unsigned long a1, + unsigned long a2, unsigned long a3, unsigned long a4, + unsigned long a5, unsigned long a6, unsigned long a7, + struct arm_smccc_res *res); + +/** + * arm_smccc_hvc() - make HVC calls + * @a0-a7: arguments passed in registers 0 to 7 + * @res: result values from registers 0 to 3 + * + * This function is used to make HVC calls following SMC Calling + * Convention. The content of the supplied param are copied to registers 0 + * to 7 prior to the HVC instruction. The return values are updated with + * the content from register 0 to 3 on return from the HVC instruction. + */ +asmlinkage void arm_smccc_hvc(unsigned long a0, unsigned long a1, + unsigned long a2, unsigned long a3, unsigned long a4, + unsigned long a5, unsigned long a6, unsigned long a7, + struct arm_smccc_res *res); + +#endif /*__ASSEMBLY__*/ +#endif /*__LINUX_ARM_SMCCC_H*/ From patchwork Fri Jul 12 05:28:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 168894 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp395746ilk; Thu, 11 Jul 2019 22:30:37 -0700 (PDT) X-Google-Smtp-Source: APXvYqyU9xTAo97ZTP3xhQeoQ0TXu4ZSMirV1694i3SCo5r17B70T3sBMFsYl15AhlN+Vke1V86V X-Received: by 2002:a63:24c1:: with SMTP id k184mr8853794pgk.120.1562909437019; Thu, 11 Jul 2019 22:30:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1562909437; cv=none; d=google.com; s=arc-20160816; b=gGG8P+f4xiVBMJrt1Ixa6sG21onmLB6cPF3NNO3ulV2HzobygJ1rL8InCjhjysP8kP 4vmWUqWJA4f8Q8vB5wmz0I81uQ/9P4/XBw1BmYalUFtQalb1tW1EQuDysnmGxDKxh+Ih SvJT8XBcU72jvPAivY1tnEAdxoKBTMiHt+2jMpuvtAYV9AG5SQIL5bH65fK24s2Cmzat mVMjZGv1M842T8PYqNg8rMsR7gI4vSwd9yEA6wghfPdMMs+Rq4+xpRpBzjdiDox8XiPw Eu6k/v8c9oKbAkwxyaZAqb482YCox6DZpzeZEIwJph0nI0v14tlZ/sUCfoViZILNdyyX UJCQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=FDb8snX7fHtHRXPBtLwcic7/q7BlhqslXapsBvvT9m4=; b=j3c6y0AdHgDL3PyMJL1KlPhG97ahjDDiYJH0OU7aGrqQzEZ8ZZjYqUUqgf+99vtGjc H0yETlY5eO70isHp+LBcN5s4n7ouOpLGXq2WLl2Z6mLlYIRgJiawCLXQhb2jQvG2ckfv a4T7xQ3WNuWiYooGDrKK/woNkWaRdJV1CueloDEO1cxzy3lG2hxZR0K7p3QBfApysxVs n1KAH7EVXwJEmOhIAfjtxc+Mh0HejG1gbkV5e0g5krvmoJY0YXhwIMzHl6NDsWl6kcAu 3kE6clvMBubSVfL+jrn+TZEpyt4UCUTjCVL1yoSGnzyDoSq70WTBecEtyc9u1K+YN72V sp2w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=eiibal9G; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e36si5303191pgm.17.2019.07.11.22.30.36; Thu, 11 Jul 2019 22:30:37 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=eiibal9G; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726095AbfGLFag (ORCPT + 13 others); Fri, 12 Jul 2019 01:30:36 -0400 Received: from mail-pg1-f195.google.com ([209.85.215.195]:39495 "EHLO mail-pg1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725791AbfGLFag (ORCPT ); Fri, 12 Jul 2019 01:30:36 -0400 Received: by mail-pg1-f195.google.com with SMTP id u17so4003697pgi.6 for ; Thu, 11 Jul 2019 22:30:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=FDb8snX7fHtHRXPBtLwcic7/q7BlhqslXapsBvvT9m4=; b=eiibal9GFko1a+tgQN3krnXtrWdBZuqF3op4VIu+Wf3BT3yWBoqbTx9WQb/SIzb2Pv nU+5d2riU9FFB7ZObi6T0/FmOiVAW5aGYEmZjvrkkPJ2g6yeqttaBIBexfwHx+XltErC Y3DQoi4yokam/JVK9tv8g0c/tsQBw2y1zMoB/JHCIAUoY1gZtZBgHuw03VTQnbdwe9kP Pt6+p3ZXg8pzKllRVC4QKdzpBSOhLptnFhC4kPw4VLGxf9zD3HLpNXMD2tlXjktOiBhV WavqlMtulcslGCSBKhXOA08M969cG9OWXlkrqjc6vZeeITO1cX9t1Zu5KT2rCDtkxCAx U0cg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FDb8snX7fHtHRXPBtLwcic7/q7BlhqslXapsBvvT9m4=; b=RcMLI8Mgk6ZJwQwceFaBbx0YaqypKGclDONy8pwb9N6uQNW1Cz3C7zaMOL1mbT75P8 Ht1yCTV6hmgMPEHC2VZEMvO+pl0C3IF4lppFkmf2qdpaiS3nuTmH0DNTcCJswAEWlOnO JdhbtwhWvxpOhhy5sLJpeslvJVyKXQw/dC6+VwJxGxxJlXTkri2uYGTddA48q/UpBonF bvpQKNEKY9RF5BKU+5RlkvGq5IVj+KIh/rJsnkoVHq/S616U22+PvfHjsLOcvnCzL3sH IJOjqhC9f1qP0hyuXThlIzxHumgCfTVHxbkYLCzwpOkQTFYSSg7pPHaGs5arrK2XyftR KPyw== X-Gm-Message-State: APjAAAUnpHuuNMD0mhzCaS5709RZldKU+bVbRBsaHLM9deZZ0JQZZQFz 0itpCkyJKzZq9sdfZvSUbFgfMQcubp8= X-Received: by 2002:a63:d04e:: with SMTP id s14mr8225037pgi.189.1562909435104; Thu, 11 Jul 2019 22:30:35 -0700 (PDT) Received: from localhost ([122.172.28.117]) by smtp.gmail.com with ESMTPSA id 143sm12297066pgc.6.2019.07.11.22.30.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 11 Jul 2019 22:30:34 -0700 (PDT) From: Viresh Kumar To: stable@vger.kernel.org, Julien Thierry Cc: Viresh Kumar , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Marc Zyngier , Mark Rutland , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: [PATCH v4.4 V2 35/43] arm/arm64: KVM: Advertise SMCCC v1.1 Date: Fri, 12 Jul 2019 10:58:23 +0530 Message-Id: <7c5975b0d2850d2b728f4688a3fedfed6bcbe75c.1562908075.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Marc Zyngier commit 09e6be12effdb33bf7210c8867bbd213b66a499e upstream. The new SMC Calling Convention (v1.1) allows for a reduced overhead when calling into the firmware, and provides a new feature discovery mechanism. Make it visible to KVM guests. Tested-by: Ard Biesheuvel Reviewed-by: Christoffer Dall Signed-off-by: Marc Zyngier Signed-off-by: Catalin Marinas [ Viresh: Picked only arm-smccc.h changes ] Signed-off-by: Viresh Kumar --- include/linux/arm-smccc.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/include/linux/arm-smccc.h b/include/linux/arm-smccc.h index 611d10580340..da9f3916f9a9 100644 --- a/include/linux/arm-smccc.h +++ b/include/linux/arm-smccc.h @@ -60,6 +60,19 @@ #define ARM_SMCCC_OWNER_TRUSTED_OS 50 #define ARM_SMCCC_OWNER_TRUSTED_OS_END 63 +#define ARM_SMCCC_VERSION_1_0 0x10000 +#define ARM_SMCCC_VERSION_1_1 0x10001 + +#define ARM_SMCCC_VERSION_FUNC_ID \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_32, \ + 0, 0) + +#define ARM_SMCCC_ARCH_FEATURES_FUNC_ID \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_32, \ + 0, 1) + #ifndef __ASSEMBLY__ /** From patchwork Fri Jul 12 05:28:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 168895 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp395797ilk; Thu, 11 Jul 2019 22:30:41 -0700 (PDT) X-Google-Smtp-Source: APXvYqzVj8tt8zMRqvu1R5AYX1t8QTIPWjElRhDdcvq3q7LojFRomB0FGLZ3Wm0bJ+Z8SccczUT1 X-Received: by 2002:a63:d4c:: with SMTP id 12mr8851222pgn.30.1562909439978; Thu, 11 Jul 2019 22:30:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1562909439; cv=none; d=google.com; s=arc-20160816; b=xwsOAETVYJEsgu+L9aLss9GGI7CjSP4s1USlhAj3p2NRwBg5uUzvc3HkZH4La8RFfv Ds+wSQLpf92kB2Uo3YEyJe6OsLouWHcKtC5wymSIa882D7jJtFvxA71g9gEXhosJoUNQ NmpD0OmMudJfmaNtk0nDHY09okLNFvKaco1SYRHfa+5TV5MrIYm4LKf6A+/fSByImkpN SCkWfOjy0Falx6q4tQkyG1R92bC/ectyOO+0P2qx8czZhZ7ZviyRaWW6BfnZ3tS6bHj2 E5ajG0KxTj1u5x9EbFMgmLL/Awv+0flsiRmTTsghjk2ORllTa6si5XTizi9BG8cBNGlJ /KPQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=z7GSqiJ6aBNFVvBBcZiH2v3S1Pbs9vo106t8SFNGIe4=; b=xAwmEaohRTAMc4V8vRT401MUaaRW+Fh9+qLsqiBTp6ve8995YPMAW6Dy2z0XwL7wnt uVs5Le8hIfS5v8i7kMucBZ+bnvFJJ4c2JRDQDEaqAgcVWWfFaYKt/WzTrSJyQDG7Wpqn W/2Rk4jJ62WYXJBAfx1CjMtaRVksD+dmvUFDd8xFJ/3yuXsYCwOmGpIiSUDTPAXPUj59 q0yx73LAOAcDSPxJNaVuBTakZ1Ktpr7UyNo/jdSFY51iS5V1af+vDS+1zAr+iDa+xyvD 7TkW93TcuxwoJnT47j6XCp6e6nYTEHsXO3nbS4f7LMrLqUhYQ3o9m93wt3WXfcJL031/ 57Pg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tcAbB1XC; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e36si5303191pgm.17.2019.07.11.22.30.39; Thu, 11 Jul 2019 22:30:39 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tcAbB1XC; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726099AbfGLFaj (ORCPT + 13 others); Fri, 12 Jul 2019 01:30:39 -0400 Received: from mail-pf1-f196.google.com ([209.85.210.196]:34705 "EHLO mail-pf1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725846AbfGLFai (ORCPT ); Fri, 12 Jul 2019 01:30:38 -0400 Received: by mail-pf1-f196.google.com with SMTP id b13so3801093pfo.1 for ; Thu, 11 Jul 2019 22:30:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=z7GSqiJ6aBNFVvBBcZiH2v3S1Pbs9vo106t8SFNGIe4=; b=tcAbB1XCe4vsg0irqnOIM6f7OdPoVlA+nE9DQ3iCELNXazxdKNTX7JqL6YIuNOyzqp 1gZ0aRWd5itgdDqxNwelzN/3pYqDQ3wm++Lq+c/1GsBgxY+xL97+7R3Dv60KKat1CnmZ w+TDTAUdJrCwdEvHHImQh8zsvtQKROHmkviw4P8RSxG8EEK/gtU6buhHkmAvFpf0feFs tYltMKt7PUWT3FXC4X0+Ax7SMaZeuaVfPBXvw3yaXl4A/t6jzB/68xxT9lBHbRBWPKWS wqnaBGkmWANvWl1F2Jrd5SBRnzP5sywS35J9ObCnqvFWnZDPNVVbvFUyUdKONubvfb8s HPbw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=z7GSqiJ6aBNFVvBBcZiH2v3S1Pbs9vo106t8SFNGIe4=; b=SQLukJosbBW8+sUlhaSL1ZfgmADomhD7TjeK3gi5Ruj2qq9HdILaDUQbrTQ+3oujip 8FN2FnWfDLXWlSPO/QxccbUrMP4CEgAw3SPWmdKVyFlYustpYzwAYEhy7sDz54IOTaMZ Rao0MFqYz/6fe1zwmTqdgbAoH+/uu4XzZZeWFxd7vEW9LEHq7Oab2+9p4nzNbkXeZ/KX zy6EhJmkRHoxlWqaDmH2v0xIgDzZVsjgrqe7/s2THJI+DZMVw/Gfd6KibWNoXoj9LIV3 4dW4N+mRnp+v37Bao6aPcxEgMZ9W+CtNkRzXfoovXd3IzVYIyZS79XOumC04vbr+fwpP Z1+g== X-Gm-Message-State: APjAAAWJveUUaUU6QGmxGe1Jl/2KAC1LAK17nu7L0Q6DO6RBlPrs2WQq eFOn0dkqAsdmxhuO8rxmi7dYK6PiqJc= X-Received: by 2002:a65:55c9:: with SMTP id k9mr8788259pgs.142.1562909437702; Thu, 11 Jul 2019 22:30:37 -0700 (PDT) Received: from localhost ([122.172.28.117]) by smtp.gmail.com with ESMTPSA id m4sm9840773pgs.71.2019.07.11.22.30.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 11 Jul 2019 22:30:37 -0700 (PDT) From: Viresh Kumar To: stable@vger.kernel.org, Julien Thierry Cc: Viresh Kumar , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Marc Zyngier , Mark Rutland , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: [PATCH v4.4 V2 36/43] arm64: KVM: Report SMCCC_ARCH_WORKAROUND_1 BP hardening support Date: Fri, 12 Jul 2019 10:58:24 +0530 Message-Id: <7dd90325604da1ca7d424aeff0cd86ee3c18fdff.1562908075.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Marc Zyngier commit 6167ec5c9145cdf493722dfd80a5d48bafc4a18a upstream. A new feature of SMCCC 1.1 is that it offers firmware-based CPU workarounds. In particular, SMCCC_ARCH_WORKAROUND_1 provides BP hardening for CVE-2017-5715. If the host has some mitigation for this issue, report that we deal with it using SMCCC_ARCH_WORKAROUND_1, as we apply the host workaround on every guest exit. Tested-by: Ard Biesheuvel Reviewed-by: Christoffer Dall Signed-off-by: Marc Zyngier Signed-off-by: Catalin Marinas [ Viresh: Picked on only arm-smccc.h changes ] Signed-off-by: Viresh Kumar --- include/linux/arm-smccc.h | 5 +++++ 1 file changed, 5 insertions(+) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/include/linux/arm-smccc.h b/include/linux/arm-smccc.h index da9f3916f9a9..1f02e4045a9e 100644 --- a/include/linux/arm-smccc.h +++ b/include/linux/arm-smccc.h @@ -73,6 +73,11 @@ ARM_SMCCC_SMC_32, \ 0, 1) +#define ARM_SMCCC_ARCH_WORKAROUND_1 \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_32, \ + 0, 0x8000) + #ifndef __ASSEMBLY__ /** From patchwork Fri Jul 12 05:28:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 168896 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp395817ilk; Thu, 11 Jul 2019 22:30:42 -0700 (PDT) X-Google-Smtp-Source: APXvYqwvS54i5VC1sjd49CUA0ajUZLcDdFIdbON9esQPsme04DCzSZ/N6sp+MTxWykbH8uSRRG1Z X-Received: by 2002:a17:90a:710c:: with SMTP id h12mr9235553pjk.36.1562909442375; Thu, 11 Jul 2019 22:30:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1562909442; cv=none; d=google.com; s=arc-20160816; b=Jn7Z18uuSC1LxOrHCD94dtPJL8d43sdGIyCjpdMJjjBSE4vOWa50uGIug3Oo22So7h SCCjC1Um4368KWLtBY3HPEE1HLfpVjq5fRqDn8CIDL4GSxUMkKl4blsZXG0FhH06+NQk QAX9WFdzB7UKitA8E5I8PpEo3s3HOgFbyP/XiJBiS+X1m2/1Ms3943SgxvqEa7iM35+w MCky+cTFL7OhzL0zmtydj0raQwGld8RUR54GXVHMdRsdDB/JVvE5uuqyXF4dTSKbod/v 5+VN7LesBmOsDwZ4wIuLtlJOvb0F+NrrKreU5Ynhs00vPQTpFvR5FCTvJYjHYi/KJP8N aDOQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=lhetsf/v1WHqsODDPiuS8lCaAlBwJqZTnWnIuf4OhuE=; b=rS1ThyLy36QlaWkCmN6Ym7dZvTg91Mea7tJeU1Zhs4wInArpYZbGuXsP4E4k7FGdYP esEQpr8KoT0OtVHGZCestlXwaqqTYqcyRvdrVf5gU0g9WXFQvKGaUDX5L9EsqDDYpyT3 n/t2qtmsF2zXknlsbcZZECHvDbzEv3Iq/XFsOvHxRzTUgwuhlHLOvJMH1dKQws2cYjlc H5Itc4FIiMg8gSzqyviANjlIe7eosIdy1OiABHFgArbYkmyJzS4GTuqE14O+EmvQFCWV KSyt34jYBJeRCETgiXPjx6yXYPBm+Yhaa4d5uAR/ZRPF6N0QdpNG6samBke9NmcrchFM Nkjg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=G2tEld9u; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e36si5303191pgm.17.2019.07.11.22.30.42; Thu, 11 Jul 2019 22:30:42 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=G2tEld9u; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725935AbfGLFal (ORCPT + 13 others); Fri, 12 Jul 2019 01:30:41 -0400 Received: from mail-pg1-f196.google.com ([209.85.215.196]:42785 "EHLO mail-pg1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725791AbfGLFal (ORCPT ); Fri, 12 Jul 2019 01:30:41 -0400 Received: by mail-pg1-f196.google.com with SMTP id t132so3993839pgb.9 for ; Thu, 11 Jul 2019 22:30:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lhetsf/v1WHqsODDPiuS8lCaAlBwJqZTnWnIuf4OhuE=; b=G2tEld9uv2oYMaQUCTBFxqa1q7vQCKFskzW+3vZ7KHoRZZE+eDzTb/9OoIHlmsgi5c dQcUGOLOIGWi7YGfHeUtx8CUU5a3d7VTyMVMNWiB6+JlPzSOxYezRtPnPUWdsotWuoVI YWbywnI5sVGB9p3r2gnWsGDeW8PY73vperHXyfQacTZcENcb9fQTHVIl35QFWMDitbCg hL9iaDqU7Jo8vVmiQg9Q+bRxP3RoTlvcD1ELyEuvVDADwr0Mzy3CbY41NKGps22/HgG4 ur76uc+Vf0fE0iBa00iavivhq6nMmZqiLxgZSnfiIiUfjjtBnFgIo5Vzu9L9WjeOQtOM xs0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lhetsf/v1WHqsODDPiuS8lCaAlBwJqZTnWnIuf4OhuE=; b=dwmEDNvQwqC1/8iACq6RG4kc01MlvpuBnF8DQGx4Kk9FELFRK3f4OJADlJmbhDf0sv V4vV09skfObr9IgKONWrEhFeVPulBct60Q/uUiP8Rb+1tyE7pvpBIRfY6aNCvuF3C+3B D6/uYkv5Y752ABagqAMn1n58/1qiYYr1XfF6cAJrUn3asD+jITnIf4JLU1ipGw2wZ5Tz nZ5gbSxk6PK7zPt4vmy2BZ98cOqOOavUSDdDbzuIkD0nvS6eRExf5S+shj4hJm/i2Mtw ktL+AMuHXF4rcsCxrxaWFcALcHDvxd6fBSvrS/2XEL5XUoI4Z7k6mKUB+yM6bXYH9lU2 aEVw== X-Gm-Message-State: APjAAAWDhDtLPcANVtVU04s04pRhkX3Znvkck0PoFd5e3eHVWCs+FE4w hzhKBUIY5xnlp4ElgG8t0YmZn5yDnDQ= X-Received: by 2002:a17:90a:360c:: with SMTP id s12mr9552818pjb.30.1562909440598; Thu, 11 Jul 2019 22:30:40 -0700 (PDT) Received: from localhost ([122.172.28.117]) by smtp.gmail.com with ESMTPSA id f19sm10134578pfk.180.2019.07.11.22.30.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 11 Jul 2019 22:30:40 -0700 (PDT) From: Viresh Kumar To: stable@vger.kernel.org, Julien Thierry Cc: Viresh Kumar , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Marc Zyngier , Mark Rutland , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: [PATCH v4.4 V2 37/43] firmware/psci: Expose PSCI conduit Date: Fri, 12 Jul 2019 10:58:25 +0530 Message-Id: <896d2efd09dbe687aa3132c5e03f6b11feb6da9b.1562908075.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Marc Zyngier commit 09a8d6d48499f93e2abde691f5800081cd858726 upstream. In order to call into the firmware to apply workarounds, it is useful to find out whether we're using HVC or SMC. Let's expose this through the psci_ops. Acked-by: Lorenzo Pieralisi Reviewed-by: Robin Murphy Tested-by: Ard Biesheuvel Signed-off-by: Marc Zyngier Signed-off-by: Catalin Marinas Signed-off-by: Viresh Kumar --- drivers/firmware/psci.c | 28 +++++++++++++++++++++++----- include/linux/psci.h | 7 +++++++ 2 files changed, 30 insertions(+), 5 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/drivers/firmware/psci.c b/drivers/firmware/psci.c index 290f8982e7b3..7b2665f6b38d 100644 --- a/drivers/firmware/psci.c +++ b/drivers/firmware/psci.c @@ -54,7 +54,9 @@ bool psci_tos_resident_on(int cpu) return cpu == resident_cpu; } -struct psci_operations psci_ops; +struct psci_operations psci_ops = { + .conduit = PSCI_CONDUIT_NONE, +}; typedef unsigned long (psci_fn)(unsigned long, unsigned long, unsigned long, unsigned long); @@ -187,6 +189,22 @@ static unsigned long psci_migrate_info_up_cpu(void) 0, 0, 0); } +static void set_conduit(enum psci_conduit conduit) +{ + switch (conduit) { + case PSCI_CONDUIT_HVC: + invoke_psci_fn = __invoke_psci_fn_hvc; + break; + case PSCI_CONDUIT_SMC: + invoke_psci_fn = __invoke_psci_fn_smc; + break; + default: + WARN(1, "Unexpected PSCI conduit %d\n", conduit); + } + + psci_ops.conduit = conduit; +} + static int get_set_conduit_method(struct device_node *np) { const char *method; @@ -199,9 +217,9 @@ static int get_set_conduit_method(struct device_node *np) } if (!strcmp("hvc", method)) { - invoke_psci_fn = __invoke_psci_fn_hvc; + set_conduit(PSCI_CONDUIT_HVC); } else if (!strcmp("smc", method)) { - invoke_psci_fn = __invoke_psci_fn_smc; + set_conduit(PSCI_CONDUIT_SMC); } else { pr_warn("invalid \"method\" property: %s\n", method); return -EINVAL; @@ -463,9 +481,9 @@ int __init psci_acpi_init(void) pr_info("probing for conduit method from ACPI.\n"); if (acpi_psci_use_hvc()) - invoke_psci_fn = __invoke_psci_fn_hvc; + set_conduit(PSCI_CONDUIT_HVC); else - invoke_psci_fn = __invoke_psci_fn_smc; + set_conduit(PSCI_CONDUIT_SMC); return psci_probe(); } diff --git a/include/linux/psci.h b/include/linux/psci.h index 04b4d92c7791..e071a1b8ddb5 100644 --- a/include/linux/psci.h +++ b/include/linux/psci.h @@ -24,6 +24,12 @@ bool psci_tos_resident_on(int cpu); bool psci_power_state_loses_context(u32 state); bool psci_power_state_is_valid(u32 state); +enum psci_conduit { + PSCI_CONDUIT_NONE, + PSCI_CONDUIT_SMC, + PSCI_CONDUIT_HVC, +}; + struct psci_operations { u32 (*get_version)(void); int (*cpu_suspend)(u32 state, unsigned long entry_point); @@ -33,6 +39,7 @@ struct psci_operations { int (*affinity_info)(unsigned long target_affinity, unsigned long lowest_affinity_level); int (*migrate_info_type)(void); + enum psci_conduit conduit; }; extern struct psci_operations psci_ops; From patchwork Fri Jul 12 05:28:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 168897 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp395876ilk; Thu, 11 Jul 2019 22:30:46 -0700 (PDT) X-Google-Smtp-Source: APXvYqzX+MBKBPvNAFOCNtW2K4D1SNIC81KbQsnkEJQILvEwXGSt55LFuCBaHblhpc1Q9/wCNivV X-Received: by 2002:a17:90a:350c:: with SMTP id q12mr9451102pjb.46.1562909445867; Thu, 11 Jul 2019 22:30:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1562909445; cv=none; d=google.com; s=arc-20160816; b=sB9oWJDqroqGIeEEORNHxI8s9/wddhlm5ru28ttPElhBYGYyDwEpyGHqL+afxzSz1K VIBSwcsxJRQooU+KejknE+KUENh7d1/aMS5GhS3rSeBYC0ISvCwLGflIsWKV+uGwnBa4 C2v2xXYcG9YZRLke0SzlCaafcWdWZcOmsoeOm3ghPEgEY/NsVmJrS0TnWWLh3+FzlSdo ugmszkgtSiv6O3kCXe1L0RA8Yz9PnBbdI1T1brfVWGGm41yeU2JwSj4ofPpxZuBwAUER 0KM9w2JBvKpxmJhweovD8It+t2ZIZcEfTS+CNkxmhDMgXPCdUAqNKzrCdrzCVRZ4S9vE 48VQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=8FgYZ0lVoh76yEFRGdkiTuXxRHgDjc15a9Db0UAG0RM=; b=Tueqf+ngCpVBY8beOJ0itlRIuD/qQYU1aU22op8RtNQzgc6KLeueTNd9LuEsnuIb7f dj8BP3IvWVvrPMXz9t+zV/P0xzd0K+bdUGmBH/LUkmGiSRScnX/ZCZE6UOeo0AEtNvz7 ipeM3hEEuiwQ+0Keq0wPly4NG+e3excP5qD8eWjhs9D0ALgYHVA97h2OzzvuccjK/kxB Qzc2bmksAVZAOhd2XMOeNMePzwNxSzPjJRG3AOd91h5DNBSw8NZI95nujyBwHQSjg8ei hCvgOeIH4hyQnw94KXsoWK3lNqCNPmaWJOJw5drJefzUjQVw1KFiDqHWRv356nMRPV/N gy9w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=uXGGypMH; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e36si5303191pgm.17.2019.07.11.22.30.44; Thu, 11 Jul 2019 22:30:45 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=uXGGypMH; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725846AbfGLFao (ORCPT + 13 others); Fri, 12 Jul 2019 01:30:44 -0400 Received: from mail-pl1-f193.google.com ([209.85.214.193]:35724 "EHLO mail-pl1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725791AbfGLFao (ORCPT ); Fri, 12 Jul 2019 01:30:44 -0400 Received: by mail-pl1-f193.google.com with SMTP id w24so4215733plp.2 for ; Thu, 11 Jul 2019 22:30:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8FgYZ0lVoh76yEFRGdkiTuXxRHgDjc15a9Db0UAG0RM=; b=uXGGypMHVt8OBJK0oz1SIqeyivCTwb+XosVqZO6Z8pfXIWt3o9Wse0MliB8FJK7coj i9zDUx0ssuhIq5bOu1lXzTuwwGoV/cD3u+E+njn76T5BvHXKUm2mKq9DJ9v0NaHXafh1 xwS3cCczzJUArfTjM38b4vB7QivwtkEkDa+Z7k7BJXIjHGE8S1lnPd7GmGCI+/6RfWa2 gV5qZ6dfkwSAF6u5lem0YH7L9RG1d2OKyrWCNhZbDfsBt1q5ZG9zF61cQJhOgEpLSqb7 87zCh43s6vgHb6eZiBjhnREIh4CkzuMShDQt7xfDoKjO7CTAqyP0bKUIyYOzhfk6AVy7 8PKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8FgYZ0lVoh76yEFRGdkiTuXxRHgDjc15a9Db0UAG0RM=; b=gd4SHa+IngRhfA5dAwZXRXhpncKdL+g3vU5MTrTBLiVPByQowLBibXZFfORf4plHwc PbMEil/93JNj+05OkSsd51JnV0YoHBFK+mQ/6W3pm7/2FkssgaIgUfuk0siZUa7w5Kcz vRDS5m7OzQsjsN5yA8Ul7ACENZUvsCUDOPg2dGnjzJUCTn+S5P68KT5RY1K0mtbKCIGO iIh1X5d7DSE3GqES2SjbBXGgdmmVv4UE1VziInNmtf4FAMOcbQL73BRVrqrbolP4KCrd k0AsNxcYBw5Ro9dJnx8BfIKjZN0+tmP6IpY/iZB4KkAXmRC5OV43n/ujK//Z/lSjOO2l LopQ== X-Gm-Message-State: APjAAAUlgMjWYE5GrozAbeTGXZayZaUv1vMZFd3811dE6qHcZgeTF1UG fyt0eYsGW08NShtX4v9+G5WfkLlI6zc= X-Received: by 2002:a17:902:a40c:: with SMTP id p12mr9159340plq.146.1562909443260; Thu, 11 Jul 2019 22:30:43 -0700 (PDT) Received: from localhost ([122.172.28.117]) by smtp.gmail.com with ESMTPSA id n19sm7333448pfa.11.2019.07.11.22.30.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 11 Jul 2019 22:30:42 -0700 (PDT) From: Viresh Kumar To: stable@vger.kernel.org, Julien Thierry Cc: Viresh Kumar , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Marc Zyngier , Mark Rutland , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: [PATCH v4.4 V2 38/43] firmware/psci: Expose SMCCC version through psci_ops Date: Fri, 12 Jul 2019 10:58:26 +0530 Message-Id: <420f2392296122b9a375194e74d212422b00d673.1562908075.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Marc Zyngier commit e78eef554a912ef6c1e0bbf97619dafbeae3339f upstream. Since PSCI 1.0 allows the SMCCC version to be (indirectly) probed, let's do that at boot time, and expose the version of the calling convention as part of the psci_ops structure. Acked-by: Lorenzo Pieralisi Reviewed-by: Robin Murphy Tested-by: Ard Biesheuvel Signed-off-by: Marc Zyngier Signed-off-by: Catalin Marinas [ v4.4: Included arm-smccc.h ] Signed-off-by: Viresh Kumar --- drivers/firmware/psci.c | 28 ++++++++++++++++++++++++++++ include/linux/psci.h | 6 ++++++ 2 files changed, 34 insertions(+) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/drivers/firmware/psci.c b/drivers/firmware/psci.c index 7b2665f6b38d..0809a48e8089 100644 --- a/drivers/firmware/psci.c +++ b/drivers/firmware/psci.c @@ -13,6 +13,7 @@ #define pr_fmt(fmt) "psci: " fmt +#include #include #include #include @@ -56,6 +57,7 @@ bool psci_tos_resident_on(int cpu) struct psci_operations psci_ops = { .conduit = PSCI_CONDUIT_NONE, + .smccc_version = SMCCC_VERSION_1_0, }; typedef unsigned long (psci_fn)(unsigned long, unsigned long, @@ -320,6 +322,31 @@ static void __init psci_init_migrate(void) pr_info("Trusted OS resident on physical CPU 0x%lx\n", cpuid); } +static void __init psci_init_smccc(void) +{ + u32 ver = ARM_SMCCC_VERSION_1_0; + int feature; + + feature = psci_features(ARM_SMCCC_VERSION_FUNC_ID); + + if (feature != PSCI_RET_NOT_SUPPORTED) { + u32 ret; + ret = invoke_psci_fn(ARM_SMCCC_VERSION_FUNC_ID, 0, 0, 0); + if (ret == ARM_SMCCC_VERSION_1_1) { + psci_ops.smccc_version = SMCCC_VERSION_1_1; + ver = ret; + } + } + + /* + * Conveniently, the SMCCC and PSCI versions are encoded the + * same way. No, this isn't accidental. + */ + pr_info("SMC Calling Convention v%d.%d\n", + PSCI_VERSION_MAJOR(ver), PSCI_VERSION_MINOR(ver)); + +} + static void __init psci_0_2_set_functions(void) { pr_info("Using standard PSCI v0.2 function IDs\n"); @@ -368,6 +395,7 @@ static int __init psci_probe(void) psci_init_migrate(); if (PSCI_VERSION_MAJOR(ver) >= 1) { + psci_init_smccc(); psci_init_cpu_suspend(); psci_init_system_suspend(); } diff --git a/include/linux/psci.h b/include/linux/psci.h index e071a1b8ddb5..e5c3277bfd78 100644 --- a/include/linux/psci.h +++ b/include/linux/psci.h @@ -30,6 +30,11 @@ enum psci_conduit { PSCI_CONDUIT_HVC, }; +enum smccc_version { + SMCCC_VERSION_1_0, + SMCCC_VERSION_1_1, +}; + struct psci_operations { u32 (*get_version)(void); int (*cpu_suspend)(u32 state, unsigned long entry_point); @@ -40,6 +45,7 @@ struct psci_operations { unsigned long lowest_affinity_level); int (*migrate_info_type)(void); enum psci_conduit conduit; + enum smccc_version smccc_version; }; extern struct psci_operations psci_ops; From patchwork Fri Jul 12 05:28:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 168898 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp395910ilk; Thu, 11 Jul 2019 22:30:48 -0700 (PDT) X-Google-Smtp-Source: APXvYqwU/Bp+lL585zau3kl3CgtqWWu2huFhrcJZpEKdLMcbGZGH6twpFTHMGGdE/LTFl85zR/v8 X-Received: by 2002:a17:90a:d343:: with SMTP id i3mr9789297pjx.15.1562909447929; Thu, 11 Jul 2019 22:30:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1562909447; cv=none; d=google.com; s=arc-20160816; b=gHqqhvEgYcTSUs7dbgMv7RtYNYQlsYAwoZPWMTA04UYCCTCiVHLzn+I0WpWpTAJAIb SvywdP/Nxcb5cpGnog9/q2dUkvNfpKsbBIGGuk07qjAhrV6MVsDUft0hy49Ho5RstNtr o0NZGrfgEN8xtveH2YFfpywSLDQitmSd4fc9r9XQ7AspLfmZZW9kYkI4uH72KKGH9oOf WF3Wsfn+KhM2s24AiYVO7g8IQhloke0LrNbt1dqPQSoR3odapf6eckwue2Y8R4z0ZlKR tq5CuI0xjpT/RSjjw2Byd77+2v2xqaPKyBR3DTQqbuHtpfo2vdnRtNVuTlKaq4VpLgFU GvSA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=QAkAWOSid7lK0+CYFipQ6VxUVVXehQyD0WFI7UyGT+o=; b=eqJNvLa4sP7AAst+MlJmFxVhm55UcVmsZ6CdZ60mpUj8yIWbfBBQM+jH0kCyqu+MkG oh00mfnZbMjVmwqMplfAJbpzuljRl7LXrS3Q7rSqMK7jyyV2QntPEJeM4LvVOqLZs8bB 6CB/LjaM5mT/kUuEWK99GC8TnDrpjQID0ygUwX1G0KAzTGst7GsSk3oDjUHxVwAxcYq2 rrKVUqk+OJNPseZoL4+3ym14A4ddch/lRHzF8M+PMf1llE4cuWXksUK/g6PD7Q893Xez Re0i07CXNVNUsFInvcgKjG0NuDMpZ39z5nWvisvCdQeBcilklWFBlzASe82YPBbbyfop ybbw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=rbBb9SC7; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e36si5303191pgm.17.2019.07.11.22.30.47; Thu, 11 Jul 2019 22:30:47 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=rbBb9SC7; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725899AbfGLFar (ORCPT + 13 others); Fri, 12 Jul 2019 01:30:47 -0400 Received: from mail-pl1-f193.google.com ([209.85.214.193]:34463 "EHLO mail-pl1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725791AbfGLFar (ORCPT ); Fri, 12 Jul 2019 01:30:47 -0400 Received: by mail-pl1-f193.google.com with SMTP id i2so4216651plt.1 for ; Thu, 11 Jul 2019 22:30:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QAkAWOSid7lK0+CYFipQ6VxUVVXehQyD0WFI7UyGT+o=; b=rbBb9SC7giz0oauYvdP9cYHAqoGTPD+ykkopvCPSbIgttQxtYQqn1F6B5rA5OjrbOf MOKCdYW04llywRPGqJfvEeh4VcYLl/+4Ru/hdae+vjnPM0Uuiuryp5dNor6Mx9/RykRk GcmAEq29koH5jLv1c1LQTyqkDgH46WVu30cCdcE2YJLHSXjx9FUwtVjqTRvKB5UqbxaK xQGQvV+NE6OdjeTjcJxJAv19LEEVjuHp3lKY/t6Dj3nFj6ARNGu/5tp09Z5HmUjEJY0f hyWya3YF02NzZU6T23Q4MHmEjDyyq45W8aEu2vmZIcEosQ2QD0Nl0IP2BkclGU/e/7hE OHFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QAkAWOSid7lK0+CYFipQ6VxUVVXehQyD0WFI7UyGT+o=; b=XIfPQmCBWxj4CS7rXvIyMa6VjWKnVf/u059etTIub2yr0HS+H+USdyK6VE7WtImUjd VVrya3q1+rcVqAD7G/8shKNAOHVdOPzRw8alCPBfvGuw1wRdkxdDuJCJAu9wjo4S4ZRK 1t9d4adgK1iQTaIHeSyfugVlpG50l6QXmMLr0TE47W5bsuAf0amw/3zNoTfdEJRAixsE LvCUa2mjsadraZyTU+U0bAGdK+m6zAIeZkIzFS7JKv2Gl19r43dhWchjfy7sNcxQixtP K6i4xCb2CAIWbOj+G6we/l20AvNFP6uQVe4IBLM//eIDuuRoxHAX1P/XFdIRr69SuRYD BQtA== X-Gm-Message-State: APjAAAUwoa8dgXJCtRa5u6qys4skLOYM5tlb3ou6q4QxB8hJPC39VSiG rl2G4WEfsdVipa4Umlrl0pXwuXjihHM= X-Received: by 2002:a17:902:24c:: with SMTP id 70mr9134247plc.2.1562909446241; Thu, 11 Jul 2019 22:30:46 -0700 (PDT) Received: from localhost ([122.172.28.117]) by smtp.gmail.com with ESMTPSA id b3sm11909341pfp.65.2019.07.11.22.30.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 11 Jul 2019 22:30:45 -0700 (PDT) From: Viresh Kumar To: stable@vger.kernel.org, Julien Thierry Cc: Viresh Kumar , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Marc Zyngier , Mark Rutland , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: [PATCH v4.4 V2 39/43] arm/arm64: smccc: Make function identifiers an unsigned quantity Date: Fri, 12 Jul 2019 10:58:27 +0530 Message-Id: <22d449cd63d5d718d3aec3e55b4805c03592b265.1562908075.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Marc Zyngier commit ded4c39e93f3b72968fdb79baba27f3b83dad34c upstream. Function identifiers are a 32bit, unsigned quantity. But we never tell so to the compiler, resulting in the following: 4ac: b26187e0 mov x0, #0xffffffff80000001 We thus rely on the firmware narrowing it for us, which is not always a reasonable expectation. Cc: stable@vger.kernel.org Reported-by: Ard Biesheuvel Acked-by: Ard Biesheuvel Reviewed-by: Robin Murphy Tested-by: Ard Biesheuvel Signed-off-by: Marc Zyngier Signed-off-by: Catalin Marinas Signed-off-by: Viresh Kumar --- include/linux/arm-smccc.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/include/linux/arm-smccc.h b/include/linux/arm-smccc.h index 1f02e4045a9e..4c45fd75db5d 100644 --- a/include/linux/arm-smccc.h +++ b/include/linux/arm-smccc.h @@ -16,6 +16,7 @@ #include #include +#include /* * This file provides common defines for ARM SMC Calling Convention as @@ -23,8 +24,8 @@ * http://infocenter.arm.com/help/topic/com.arm.doc.den0028a/index.html */ -#define ARM_SMCCC_STD_CALL 0 -#define ARM_SMCCC_FAST_CALL 1 +#define ARM_SMCCC_STD_CALL _AC(0,U) +#define ARM_SMCCC_FAST_CALL _AC(1,U) #define ARM_SMCCC_TYPE_SHIFT 31 #define ARM_SMCCC_SMC_32 0 From patchwork Fri Jul 12 05:28:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 168899 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp395959ilk; Thu, 11 Jul 2019 22:30:51 -0700 (PDT) X-Google-Smtp-Source: APXvYqxTy8pNWyD56scO12u8/HwcT9RmtJyIdTTsAaCwRTjZvIs9FnB7pzLohjhZbBZ65edHMsBP X-Received: by 2002:a17:90b:95:: with SMTP id bb21mr9542646pjb.8.1562909450970; Thu, 11 Jul 2019 22:30:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1562909450; cv=none; d=google.com; s=arc-20160816; b=LOrKnPI2cU0UzSrY+sZg8vfD1t7GvZzIAN+WcopLfElqZoZ2lagONAiE6jVf+pibPB GP3E4g61tkRJak/QJw8+ZAYQ8xxydVSnEiyxxAgMhOU/35lIGQFX9L2hyC021AgDXdjO frOt5cOfLAcla5B59+EbpLR2LAxAkQD5Q8f2OhUgcaLoWK3vH6iLMCdOMnkuwYuaKbyG a/tYv8m2XNNlBM0Hp6sLz+0+haDWmiD12WdPu1e35u0QYIjiMsC3u+JsSwkSNzEkFu3k zG2Cs3r7qcukm/RsppZHb8Vhx7rKd+IL2UpYH85I6YUtXztQIot8Pjm8tW0l0B64wQj1 0rBA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=kulBovnYLz4YjgSJ0sOniJhX8Qcc8ljUXoag6+mJQMI=; b=A46e7QixvIkQ11tJRIldlF/tIX6gtmkAoibvIS+88lQkguQebhBNu7N5iIv37zgpe0 B5cCp/iIDCiNng7YPJnVLUMH+OzqnsqATUMlCt9wd+tn3Gm9tcEJaeW3g0v7LXw2uxDn vSzti5JZllKIDUr0QZOlvpSLvDlKRIlSEpJQWrCnPnDmEBNe4hbxVwey8c0A+zIi24F3 8paxumfwIOP6UuRLcJsWwUotHlVIFW79v3TBI1r53KSsbJXWrVuWn9T2iTo9L8OV28nG q+zHdafoza4xaA71R0ZR4kcoErLAmjHOPpJr03OAwx2gZxdSh+PJFtp92+sMyUH6mJqo JzQA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IB3JJQIu; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e36si5303191pgm.17.2019.07.11.22.30.50; Thu, 11 Jul 2019 22:30:50 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IB3JJQIu; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725939AbfGLFau (ORCPT + 13 others); Fri, 12 Jul 2019 01:30:50 -0400 Received: from mail-pf1-f196.google.com ([209.85.210.196]:32820 "EHLO mail-pf1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725791AbfGLFau (ORCPT ); Fri, 12 Jul 2019 01:30:50 -0400 Received: by mail-pf1-f196.google.com with SMTP id g2so3805217pfq.0 for ; Thu, 11 Jul 2019 22:30:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kulBovnYLz4YjgSJ0sOniJhX8Qcc8ljUXoag6+mJQMI=; b=IB3JJQIuHZFizIZtXA/n0rZ+jWpJAoAWsj6UXhog4Cu3WwWA4r+1mzjeDP0UWlYyUU RFgL0SloPebXsJu8mt3U4ylWXkjD0MJNtbkYp9JE+8QRnpYTZP8ktiBEND77wvW48kDA mfANFSESMn2tuCqWkTeSZiRxstk71UyJPH9T37bM+5q6NhtpdUY6OPy3sLW/7DxsBZBn M3PpWUIWD06CMpTvCRIceM6rg/cDgGnBDL50UycxLRERqYJyaks0hMMG+rn2pM4q06ir d6GmHDoIntf3zGW150E8QhXpG8GxOvmvt2DA+7THz23z808tE2wLjSqM2eqlwTlRAh87 aBbg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kulBovnYLz4YjgSJ0sOniJhX8Qcc8ljUXoag6+mJQMI=; b=bIC35pFh8TbVTaxqZGU6wqhMDsaEg5nEH+fuemXUcQQ1HRwqYnYca3lLTdstS2LPwg oVll+F5iN9kF3MMMhNcNaqFpNKIoXQc96dCx+VZ0PGy9DrJiJpUQ80JY4bWcWF8jbLWm 3zTyLDvQs1aJi1MDttKOatFs9eD0pjrtFMylZqJzd9fyRqOG7zW6/x/gthbUWqBpk18u Isge7rWT2kA1oFpQJEHtaCeZ+ylmJdzi+mxAS4z1tVhdIKve6xrgao4t812HSp9M7vzb pgwnilXMoUdydFOmwA7AsbOM5Ozgz9ThHz4wLRo7fbhux6dYJzIYk8/If1YJxsiPZuxH LjcQ== X-Gm-Message-State: APjAAAXtYAQlp/lczThPxNafaDBXFevHfmkVYm1r/I4jNfJHZP6Jbmgw rg0Hn/BesIURA7ON+XPoGU+uGT1m74M= X-Received: by 2002:a63:7455:: with SMTP id e21mr2804274pgn.439.1562909448746; Thu, 11 Jul 2019 22:30:48 -0700 (PDT) Received: from localhost ([122.172.28.117]) by smtp.gmail.com with ESMTPSA id u134sm6825242pfc.19.2019.07.11.22.30.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 11 Jul 2019 22:30:48 -0700 (PDT) From: Viresh Kumar To: stable@vger.kernel.org, Julien Thierry Cc: Viresh Kumar , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Marc Zyngier , Mark Rutland , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: [PATCH v4.4 V2 40/43] arm/arm64: smccc: Implement SMCCC v1.1 inline primitive Date: Fri, 12 Jul 2019 10:58:28 +0530 Message-Id: X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Marc Zyngier commit f2d3b2e8759a5833df6f022e42df2d581e6d843c upstream. One of the major improvement of SMCCC v1.1 is that it only clobbers the first 4 registers, both on 32 and 64bit. This means that it becomes very easy to provide an inline version of the SMC call primitive, and avoid performing a function call to stash the registers that would otherwise be clobbered by SMCCC v1.0. Reviewed-by: Robin Murphy Tested-by: Ard Biesheuvel Signed-off-by: Marc Zyngier Signed-off-by: Catalin Marinas Signed-off-by: Viresh Kumar --- include/linux/arm-smccc.h | 141 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 141 insertions(+) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/include/linux/arm-smccc.h b/include/linux/arm-smccc.h index 4c45fd75db5d..60c2ad6316d8 100644 --- a/include/linux/arm-smccc.h +++ b/include/linux/arm-smccc.h @@ -122,5 +122,146 @@ asmlinkage void arm_smccc_hvc(unsigned long a0, unsigned long a1, unsigned long a5, unsigned long a6, unsigned long a7, struct arm_smccc_res *res); +/* SMCCC v1.1 implementation madness follows */ +#ifdef CONFIG_ARM64 + +#define SMCCC_SMC_INST "smc #0" +#define SMCCC_HVC_INST "hvc #0" + +#elif defined(CONFIG_ARM) +#include +#include + +#define SMCCC_SMC_INST __SMC(0) +#define SMCCC_HVC_INST __HVC(0) + +#endif + +#define ___count_args(_0, _1, _2, _3, _4, _5, _6, _7, _8, x, ...) x + +#define __count_args(...) \ + ___count_args(__VA_ARGS__, 7, 6, 5, 4, 3, 2, 1, 0) + +#define __constraint_write_0 \ + "+r" (r0), "=&r" (r1), "=&r" (r2), "=&r" (r3) +#define __constraint_write_1 \ + "+r" (r0), "+r" (r1), "=&r" (r2), "=&r" (r3) +#define __constraint_write_2 \ + "+r" (r0), "+r" (r1), "+r" (r2), "=&r" (r3) +#define __constraint_write_3 \ + "+r" (r0), "+r" (r1), "+r" (r2), "+r" (r3) +#define __constraint_write_4 __constraint_write_3 +#define __constraint_write_5 __constraint_write_4 +#define __constraint_write_6 __constraint_write_5 +#define __constraint_write_7 __constraint_write_6 + +#define __constraint_read_0 +#define __constraint_read_1 +#define __constraint_read_2 +#define __constraint_read_3 +#define __constraint_read_4 "r" (r4) +#define __constraint_read_5 __constraint_read_4, "r" (r5) +#define __constraint_read_6 __constraint_read_5, "r" (r6) +#define __constraint_read_7 __constraint_read_6, "r" (r7) + +#define __declare_arg_0(a0, res) \ + struct arm_smccc_res *___res = res; \ + register u32 r0 asm("r0") = a0; \ + register unsigned long r1 asm("r1"); \ + register unsigned long r2 asm("r2"); \ + register unsigned long r3 asm("r3") + +#define __declare_arg_1(a0, a1, res) \ + struct arm_smccc_res *___res = res; \ + register u32 r0 asm("r0") = a0; \ + register typeof(a1) r1 asm("r1") = a1; \ + register unsigned long r2 asm("r2"); \ + register unsigned long r3 asm("r3") + +#define __declare_arg_2(a0, a1, a2, res) \ + struct arm_smccc_res *___res = res; \ + register u32 r0 asm("r0") = a0; \ + register typeof(a1) r1 asm("r1") = a1; \ + register typeof(a2) r2 asm("r2") = a2; \ + register unsigned long r3 asm("r3") + +#define __declare_arg_3(a0, a1, a2, a3, res) \ + struct arm_smccc_res *___res = res; \ + register u32 r0 asm("r0") = a0; \ + register typeof(a1) r1 asm("r1") = a1; \ + register typeof(a2) r2 asm("r2") = a2; \ + register typeof(a3) r3 asm("r3") = a3 + +#define __declare_arg_4(a0, a1, a2, a3, a4, res) \ + __declare_arg_3(a0, a1, a2, a3, res); \ + register typeof(a4) r4 asm("r4") = a4 + +#define __declare_arg_5(a0, a1, a2, a3, a4, a5, res) \ + __declare_arg_4(a0, a1, a2, a3, a4, res); \ + register typeof(a5) r5 asm("r5") = a5 + +#define __declare_arg_6(a0, a1, a2, a3, a4, a5, a6, res) \ + __declare_arg_5(a0, a1, a2, a3, a4, a5, res); \ + register typeof(a6) r6 asm("r6") = a6 + +#define __declare_arg_7(a0, a1, a2, a3, a4, a5, a6, a7, res) \ + __declare_arg_6(a0, a1, a2, a3, a4, a5, a6, res); \ + register typeof(a7) r7 asm("r7") = a7 + +#define ___declare_args(count, ...) __declare_arg_ ## count(__VA_ARGS__) +#define __declare_args(count, ...) ___declare_args(count, __VA_ARGS__) + +#define ___constraints(count) \ + : __constraint_write_ ## count \ + : __constraint_read_ ## count \ + : "memory" +#define __constraints(count) ___constraints(count) + +/* + * We have an output list that is not necessarily used, and GCC feels + * entitled to optimise the whole sequence away. "volatile" is what + * makes it stick. + */ +#define __arm_smccc_1_1(inst, ...) \ + do { \ + __declare_args(__count_args(__VA_ARGS__), __VA_ARGS__); \ + asm volatile(inst "\n" \ + __constraints(__count_args(__VA_ARGS__))); \ + if (___res) \ + *___res = (typeof(*___res)){r0, r1, r2, r3}; \ + } while (0) + +/* + * arm_smccc_1_1_smc() - make an SMCCC v1.1 compliant SMC call + * + * This is a variadic macro taking one to eight source arguments, and + * an optional return structure. + * + * @a0-a7: arguments passed in registers 0 to 7 + * @res: result values from registers 0 to 3 + * + * This macro is used to make SMC calls following SMC Calling Convention v1.1. + * The content of the supplied param are copied to registers 0 to 7 prior + * to the SMC instruction. The return values are updated with the content + * from register 0 to 3 on return from the SMC instruction if not NULL. + */ +#define arm_smccc_1_1_smc(...) __arm_smccc_1_1(SMCCC_SMC_INST, __VA_ARGS__) + +/* + * arm_smccc_1_1_hvc() - make an SMCCC v1.1 compliant HVC call + * + * This is a variadic macro taking one to eight source arguments, and + * an optional return structure. + * + * @a0-a7: arguments passed in registers 0 to 7 + * @res: result values from registers 0 to 3 + * + * This macro is used to make HVC calls following SMC Calling Convention v1.1. + * The content of the supplied param are copied to registers 0 to 7 prior + * to the HVC instruction. The return values are updated with the content + * from register 0 to 3 on return from the HVC instruction if not NULL. + */ +#define arm_smccc_1_1_hvc(...) __arm_smccc_1_1(SMCCC_HVC_INST, __VA_ARGS__) + #endif /*__ASSEMBLY__*/ #endif /*__LINUX_ARM_SMCCC_H*/ From patchwork Fri Jul 12 05:28:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 168900 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp396027ilk; Thu, 11 Jul 2019 22:30:54 -0700 (PDT) X-Google-Smtp-Source: APXvYqwpuBXh46nKrWheA27BFFwueGdpJTe2NyFv32oOraKSKP9eGagVasOSlljRbi/MQVPEoco+ X-Received: by 2002:a63:f50d:: with SMTP id w13mr8583749pgh.411.1562909454029; Thu, 11 Jul 2019 22:30:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1562909454; cv=none; d=google.com; s=arc-20160816; b=yLhMbLe7QNrOfGxAlLLQkM1AwM4jNGI9jjXuI7m92mU51tcosff9lEoVCgIgA9o205 gMPlewroXxu0ENjRu2fIXD6OcVY1FWwUrjvrCthHUyloyy/RBv7nZN1LTvpW52/ka2Fj 5RIveiOO9kO/X8fX/yBb8F8vtHMBTgu6MdHT7/8IeqwJnx7qKj+p5shmMJ/AQYeddtPH NussflbCtHCkbbwR19sTUxEGGvOfKJxO3AlJxVne3TSKHdb941MQFW+mQSwYyYmjXDzK BxZs1dbvzAPZMILs7Sk57zZM4IHsTA/XkHf/qqsl1+8umI2UjoyHgPoKJ85pzqKdU6rm M8Kw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=TheFOcfsNrP/iCpBXsyGMi/69Bi3Htfiid5k4ekGSX4=; b=DkA38s1fY/+DeLmGkaBH0RE+ad7HWgSGmKmDQv1yGz4ieICD4sLHlE7MWf0BdTElwx TvdvDjfJTd+eYl3Y97alqn7Qg20F09xnFBxRfvCTTan7rb2mDvv/r7HERRjsz5eMh6p+ /NF6KkZ6Kp32J95aPmKUL/2TATgnlGOZ7aHhhrDrrm4vCXxhCtKF1bgEt0doOUD0W2/m rA67YV2jRyifZcEamiEKi9psUuOb3bH5KEl3Vuh2O9j4urr7SfHRTlQd/wgFp4c0hkuZ Cmox+brvAJwL0W42yqmkl3XrBD/F2c2pMYB9F4D04rkXyx+b/bVPNG/ARJ7Z3EMioqX5 3n/Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=S8LXzzvb; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e36si5303191pgm.17.2019.07.11.22.30.53; Thu, 11 Jul 2019 22:30:54 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=S8LXzzvb; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726100AbfGLFax (ORCPT + 13 others); Fri, 12 Jul 2019 01:30:53 -0400 Received: from mail-pf1-f194.google.com ([209.85.210.194]:32821 "EHLO mail-pf1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725791AbfGLFaw (ORCPT ); Fri, 12 Jul 2019 01:30:52 -0400 Received: by mail-pf1-f194.google.com with SMTP id g2so3805248pfq.0 for ; Thu, 11 Jul 2019 22:30:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=TheFOcfsNrP/iCpBXsyGMi/69Bi3Htfiid5k4ekGSX4=; b=S8LXzzvbI4rWMCXL7mWrFYvVfsews0FiJkZ2UXCAhQNQUjpLk9GU7zgejZMVjgH9iV htjoAr+3aupsFge2hy/0Ua2bROlHQTKyDR2UzFxqQGhxwUdLHi5TMnwo8h7GnfS1gO6g 1tdisu+r2I8jF43Vz5pX8v5en24zOq+xhFg9ffc91JvR4iUdAyg6fULVG9DqRx2E95/c bx06kZxy7ORzT8nPxeatSFSe1p3Mdav2Kv1aQbPgVAlbm2hMp5qf8q3PIbbydwx+EIC3 svzlMq16thEQxT1mlh2lSd2//A5bWlupAEeGZW7/jQTGiX4WaItDLULAvDbfc07dT1CZ 3EqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TheFOcfsNrP/iCpBXsyGMi/69Bi3Htfiid5k4ekGSX4=; b=l0azv6u2IdAPoer5+HdVqyQDqGRSpIAwkpfIZPpkvWMEeV7X2YiGBzbSqO8m9Qg4Ut BRlSkekCrjsETmO/eYmsC+j4HZVlGdH3Ht3ChU94lky6WNX1soMrK1dvhjTz7WwZZDyz FGOEMz8+alBgBhDtwq3SmsyE8SITs+vJKlWEShP3m+2zpdDMbCTGKj27pnmnvcgg7FN3 qhs9TD6cwWxhhzXyYzAZ8ZQI2SDrgMpigQD9TXeFrhqKuKpP+M+Qx7WP1iQtS7BnZIlp X4fntMjjgVSFEBUdxaqlZym5rJh1M/p1rEH2tnqTquMDv7ykTsbUsECgsxQU2gvTECMe X2yg== X-Gm-Message-State: APjAAAX9oTcP0nIWRWKniib4vZag/q/Jcy5rb7r0IMIyDiojXAURgGHS b4ohs7fNFFqC8lPZM5aGQQh/K8EJKHc= X-Received: by 2002:a63:4c19:: with SMTP id z25mr8804010pga.47.1562909451445; Thu, 11 Jul 2019 22:30:51 -0700 (PDT) Received: from localhost ([122.172.28.117]) by smtp.gmail.com with ESMTPSA id l124sm7218418pgl.54.2019.07.11.22.30.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 11 Jul 2019 22:30:50 -0700 (PDT) From: Viresh Kumar To: stable@vger.kernel.org, Julien Thierry Cc: Viresh Kumar , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Marc Zyngier , Mark Rutland , Will Deacon , Russell King , Vincent Guittot , mark.brown@arm.com Subject: [PATCH v4.4 V2 41/43] arm64: Add ARM_SMCCC_ARCH_WORKAROUND_1 BP hardening support Date: Fri, 12 Jul 2019 10:58:29 +0530 Message-Id: X-Mailer: git-send-email 2.21.0.rc0.269.g1a574e7a288b In-Reply-To: References: MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Marc Zyngier commit b092201e0020614127f495c092e0a12d26a2116e upstream. Add the detection and runtime code for ARM_SMCCC_ARCH_WORKAROUND_1. It is lovely. Really. Tested-by: Ard Biesheuvel Signed-off-by: Marc Zyngier Signed-off-by: Catalin Marinas Signed-off-by: Viresh Kumar --- arch/arm64/kernel/bpi.S | 20 ++++++++++ arch/arm64/kernel/cpu_errata.c | 68 +++++++++++++++++++++++++++++++++- 2 files changed, 87 insertions(+), 1 deletion(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/kernel/bpi.S b/arch/arm64/kernel/bpi.S index dec95bd82e31..c72f261f4b64 100644 --- a/arch/arm64/kernel/bpi.S +++ b/arch/arm64/kernel/bpi.S @@ -17,6 +17,7 @@ */ #include +#include .macro ventry target .rept 31 @@ -77,3 +78,22 @@ ENTRY(__psci_hyp_bp_inval_start) ldp x0, x1, [sp, #(16 * 8)] add sp, sp, #(8 * 18) ENTRY(__psci_hyp_bp_inval_end) + +.macro smccc_workaround_1 inst + sub sp, sp, #(8 * 4) + stp x2, x3, [sp, #(8 * 0)] + stp x0, x1, [sp, #(8 * 2)] + mov w0, #ARM_SMCCC_ARCH_WORKAROUND_1 + \inst #0 + ldp x2, x3, [sp, #(8 * 0)] + ldp x0, x1, [sp, #(8 * 2)] + add sp, sp, #(8 * 4) +.endm + +ENTRY(__smccc_workaround_1_smc_start) + smccc_workaround_1 smc +ENTRY(__smccc_workaround_1_smc_end) + +ENTRY(__smccc_workaround_1_hvc_start) + smccc_workaround_1 hvc +ENTRY(__smccc_workaround_1_hvc_end) diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index ff22915a2865..d5fd7be563bc 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -51,6 +51,10 @@ DEFINE_PER_CPU_READ_MOSTLY(struct bp_hardening_data, bp_hardening_data); #ifdef CONFIG_KVM extern char __psci_hyp_bp_inval_start[], __psci_hyp_bp_inval_end[]; +extern char __smccc_workaround_1_smc_start[]; +extern char __smccc_workaround_1_smc_end[]; +extern char __smccc_workaround_1_hvc_start[]; +extern char __smccc_workaround_1_hvc_end[]; static void __copy_hyp_vect_bpi(int slot, const char *hyp_vecs_start, const char *hyp_vecs_end) @@ -95,6 +99,10 @@ static void __install_bp_hardening_cb(bp_hardening_cb_t fn, #else #define __psci_hyp_bp_inval_start NULL #define __psci_hyp_bp_inval_end NULL +#define __smccc_workaround_1_smc_start NULL +#define __smccc_workaround_1_smc_end NULL +#define __smccc_workaround_1_hvc_start NULL +#define __smccc_workaround_1_hvc_end NULL static void __install_bp_hardening_cb(bp_hardening_cb_t fn, const char *hyp_vecs_start, @@ -121,17 +129,75 @@ static void install_bp_hardening_cb(const struct arm64_cpu_capabilities *entry, __install_bp_hardening_cb(fn, hyp_vecs_start, hyp_vecs_end); } +#include +#include #include +static void call_smc_arch_workaround_1(void) +{ + arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_1, NULL); +} + +static void call_hvc_arch_workaround_1(void) +{ + arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_WORKAROUND_1, NULL); +} + +static bool check_smccc_arch_workaround_1(const struct arm64_cpu_capabilities *entry) +{ + bp_hardening_cb_t cb; + void *smccc_start, *smccc_end; + struct arm_smccc_res res; + + if (!entry->matches(entry, SCOPE_LOCAL_CPU)) + return false; + + if (psci_ops.smccc_version == SMCCC_VERSION_1_0) + return false; + + switch (psci_ops.conduit) { + case PSCI_CONDUIT_HVC: + arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID, + ARM_SMCCC_ARCH_WORKAROUND_1, &res); + if (res.a0) + return false; + cb = call_hvc_arch_workaround_1; + smccc_start = __smccc_workaround_1_hvc_start; + smccc_end = __smccc_workaround_1_hvc_end; + break; + + case PSCI_CONDUIT_SMC: + arm_smccc_1_1_smc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID, + ARM_SMCCC_ARCH_WORKAROUND_1, &res); + if (res.a0) + return false; + cb = call_smc_arch_workaround_1; + smccc_start = __smccc_workaround_1_smc_start; + smccc_end = __smccc_workaround_1_smc_end; + break; + + default: + return false; + } + + install_bp_hardening_cb(entry, cb, smccc_start, smccc_end); + + return true; +} + static int enable_psci_bp_hardening(void *data) { const struct arm64_cpu_capabilities *entry = data; - if (psci_ops.get_version) + if (psci_ops.get_version) { + if (check_smccc_arch_workaround_1(entry)) + return 0; + install_bp_hardening_cb(entry, (bp_hardening_cb_t)psci_ops.get_version, __psci_hyp_bp_inval_start, __psci_hyp_bp_inval_end); + } return 0; } From patchwork Fri Jul 12 05:28:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 168901 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp396063ilk; Thu, 11 Jul 2019 22:30:56 -0700 (PDT) X-Google-Smtp-Source: APXvYqwPemW6CmR/a4YYXJo34w4kxkPaaJtv0jooeXo7fhSaUMp31zdMShEW/sPLNQ2J4pq6mBrw X-Received: by 2002:a65:4841:: with SMTP id i1mr8597951pgs.316.1562909456317; Thu, 11 Jul 2019 22:30:56 -0700 (PDT) ARC-Seal: i=1; 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Now that we've standardised on SMCCC v1.1 to perform the branch prediction invalidation, let's drop the previous band-aid. If vendors haven't updated their firmware to do SMCCC 1.1, they haven't updated PSCI either, so we don't loose anything. Tested-by: Ard Biesheuvel Signed-off-by: Marc Zyngier Signed-off-by: Catalin Marinas [ v4.4: Dropped switch.c changes ] Signed-off-by: Viresh Kumar --- arch/arm64/kernel/bpi.S | 24 ------------------ arch/arm64/kernel/cpu_errata.c | 45 ++++++++++------------------------ 2 files changed, 13 insertions(+), 56 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/kernel/bpi.S b/arch/arm64/kernel/bpi.S index c72f261f4b64..dc4eb154e33b 100644 --- a/arch/arm64/kernel/bpi.S +++ b/arch/arm64/kernel/bpi.S @@ -54,30 +54,6 @@ ENTRY(__bp_harden_hyp_vecs_start) vectors __kvm_hyp_vector .endr ENTRY(__bp_harden_hyp_vecs_end) -ENTRY(__psci_hyp_bp_inval_start) - sub sp, sp, #(8 * 18) - stp x16, x17, [sp, #(16 * 0)] - stp x14, x15, [sp, #(16 * 1)] - stp x12, x13, [sp, #(16 * 2)] - stp x10, x11, [sp, #(16 * 3)] - stp x8, x9, [sp, #(16 * 4)] - stp x6, x7, [sp, #(16 * 5)] - stp x4, x5, [sp, #(16 * 6)] - stp x2, x3, [sp, #(16 * 7)] - stp x0, x1, [sp, #(16 * 8)] - mov x0, #0x84000000 - smc #0 - ldp x16, x17, [sp, #(16 * 0)] - ldp x14, x15, [sp, #(16 * 1)] - ldp x12, x13, [sp, #(16 * 2)] - ldp x10, x11, [sp, #(16 * 3)] - ldp x8, x9, [sp, #(16 * 4)] - ldp x6, x7, [sp, #(16 * 5)] - ldp x4, x5, [sp, #(16 * 6)] - ldp x2, x3, [sp, #(16 * 7)] - ldp x0, x1, [sp, #(16 * 8)] - add sp, sp, #(8 * 18) -ENTRY(__psci_hyp_bp_inval_end) .macro smccc_workaround_1 inst sub sp, sp, #(8 * 4) diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index d5fd7be563bc..2a17789bb963 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -50,7 +50,6 @@ is_affected_midr_range(const struct arm64_cpu_capabilities *entry, int scope) DEFINE_PER_CPU_READ_MOSTLY(struct bp_hardening_data, bp_hardening_data); #ifdef CONFIG_KVM -extern char __psci_hyp_bp_inval_start[], __psci_hyp_bp_inval_end[]; extern char __smccc_workaround_1_smc_start[]; extern char __smccc_workaround_1_smc_end[]; extern char __smccc_workaround_1_hvc_start[]; @@ -97,8 +96,6 @@ static void __install_bp_hardening_cb(bp_hardening_cb_t fn, spin_unlock(&bp_lock); } #else -#define __psci_hyp_bp_inval_start NULL -#define __psci_hyp_bp_inval_end NULL #define __smccc_workaround_1_smc_start NULL #define __smccc_workaround_1_smc_end NULL #define __smccc_workaround_1_hvc_start NULL @@ -143,24 +140,25 @@ static void call_hvc_arch_workaround_1(void) arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_WORKAROUND_1, NULL); } -static bool check_smccc_arch_workaround_1(const struct arm64_cpu_capabilities *entry) +static int enable_smccc_arch_workaround_1(void *data) { + const struct arm64_cpu_capabilities *entry = data; bp_hardening_cb_t cb; void *smccc_start, *smccc_end; struct arm_smccc_res res; if (!entry->matches(entry, SCOPE_LOCAL_CPU)) - return false; + return 0; if (psci_ops.smccc_version == SMCCC_VERSION_1_0) - return false; + return 0; switch (psci_ops.conduit) { case PSCI_CONDUIT_HVC: arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID, ARM_SMCCC_ARCH_WORKAROUND_1, &res); if (res.a0) - return false; + return 0; cb = call_hvc_arch_workaround_1; smccc_start = __smccc_workaround_1_hvc_start; smccc_end = __smccc_workaround_1_hvc_end; @@ -170,35 +168,18 @@ static bool check_smccc_arch_workaround_1(const struct arm64_cpu_capabilities *e arm_smccc_1_1_smc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID, ARM_SMCCC_ARCH_WORKAROUND_1, &res); if (res.a0) - return false; + return 0; cb = call_smc_arch_workaround_1; smccc_start = __smccc_workaround_1_smc_start; smccc_end = __smccc_workaround_1_smc_end; break; default: - return false; + return 0; } install_bp_hardening_cb(entry, cb, smccc_start, smccc_end); - return true; -} - -static int enable_psci_bp_hardening(void *data) -{ - const struct arm64_cpu_capabilities *entry = data; - - if (psci_ops.get_version) { - if (check_smccc_arch_workaround_1(entry)) - return 0; - - install_bp_hardening_cb(entry, - (bp_hardening_cb_t)psci_ops.get_version, - __psci_hyp_bp_inval_start, - __psci_hyp_bp_inval_end); - } - return 0; } #endif /* CONFIG_HARDEN_BRANCH_PREDICTOR */ @@ -283,32 +264,32 @@ const struct arm64_cpu_capabilities arm64_errata[] = { { .capability = ARM64_HARDEN_BRANCH_PREDICTOR, MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), - .enable = enable_psci_bp_hardening, + .enable = enable_smccc_arch_workaround_1, }, { .capability = ARM64_HARDEN_BRANCH_PREDICTOR, MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), - .enable = enable_psci_bp_hardening, + .enable = enable_smccc_arch_workaround_1, }, { .capability = ARM64_HARDEN_BRANCH_PREDICTOR, MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), - .enable = enable_psci_bp_hardening, + .enable = enable_smccc_arch_workaround_1, }, { .capability = ARM64_HARDEN_BRANCH_PREDICTOR, MIDR_ALL_VERSIONS(MIDR_CORTEX_A75), - .enable = enable_psci_bp_hardening, + .enable = enable_smccc_arch_workaround_1, }, { .capability = ARM64_HARDEN_BRANCH_PREDICTOR, MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), - .enable = enable_psci_bp_hardening, + .enable = enable_smccc_arch_workaround_1, }, { .capability = ARM64_HARDEN_BRANCH_PREDICTOR, MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), - .enable = enable_psci_bp_hardening, + .enable = enable_smccc_arch_workaround_1, }, #endif { From patchwork Fri Jul 12 05:28:31 2019 Content-Type: text/plain; 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The arm64 futex code has some explicit dereferencing of user pointers where performing atomic operations in response to a futex command. This patch uses masking to limit any speculative futex operations to within the user address space. Signed-off-by: Will Deacon Signed-off-by: Catalin Marinas Signed-off-by: Viresh Kumar --- arch/arm64/include/asm/futex.h | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) -- 2.21.0.rc0.269.g1a574e7a288b diff --git a/arch/arm64/include/asm/futex.h b/arch/arm64/include/asm/futex.h index 34d4d2e2f561..8ab6e83cb629 100644 --- a/arch/arm64/include/asm/futex.h +++ b/arch/arm64/include/asm/futex.h @@ -53,9 +53,10 @@ : "memory") static inline int -arch_futex_atomic_op_inuser(int op, int oparg, int *oval, u32 __user *uaddr) +arch_futex_atomic_op_inuser(int op, int oparg, int *oval, u32 __user *_uaddr) { int oldval = 0, ret, tmp; + u32 __user *uaddr = __uaccess_mask_ptr(_uaddr); pagefault_disable(); @@ -93,15 +94,17 @@ arch_futex_atomic_op_inuser(int op, int oparg, int *oval, u32 __user *uaddr) } static inline int -futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, +futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *_uaddr, u32 oldval, u32 newval) { int ret = 0; u32 val, tmp; + u32 __user *uaddr; - if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32))) + if (!access_ok(VERIFY_WRITE, _uaddr, sizeof(u32))) return -EFAULT; + uaddr = __uaccess_mask_ptr(_uaddr); asm volatile("// futex_atomic_cmpxchg_inatomic\n" ALTERNATIVE("nop", SET_PSTATE_PAN(0), ARM64_HAS_PAN, CONFIG_ARM64_PAN) " prfm pstl1strm, %2\n"