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([77.252.47.225]) by smtp.gmail.com with ESMTPSA id m15-20020a50ef0f000000b005254b41f507sm3239024eds.32.2023.08.27.04.45.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Aug 2023 04:45:22 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH 1/2] ARM: dts: qcom: sdx65: correct PCIe EP phy-names Date: Sun, 27 Aug 2023 13:45:18 +0200 Message-Id: <20230827114519.48797-1-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Qualcomm PCIe endpoint bindings expect phy-names to be "pciephy": arch/arm/boot/dts/qcom/qcom-sdx65-mtp.dtb: pcie-ep@1c00000: phy-names:0: 'pciephy' was expected Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/qcom/qcom-sdx65.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi index 81d018fe7d9b..93c6c80dc379 100644 --- a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi @@ -337,7 +337,7 @@ pcie_ep: pcie-ep@1c00000 { power-domains = <&gcc PCIE_GDSC>; phys = <&pcie_phy>; - phy-names = "pcie-phy"; + phy-names = "pciephy"; max-link-speed = <3>; num-lanes = <2>; From patchwork Sun Aug 27 11:45:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 717542 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7214EC83F14 for ; Sun, 27 Aug 2023 11:46:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229815AbjH0Lpt (ORCPT ); Sun, 27 Aug 2023 07:45:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37018 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229837AbjH0Lp3 (ORCPT ); Sun, 27 Aug 2023 07:45:29 -0400 Received: from mail-lf1-x129.google.com (mail-lf1-x129.google.com [IPv6:2a00:1450:4864:20::129]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 42C8013E for ; Sun, 27 Aug 2023 04:45:26 -0700 (PDT) Received: by mail-lf1-x129.google.com with SMTP id 2adb3069b0e04-50087d47d4dso3697053e87.1 for ; Sun, 27 Aug 2023 04:45:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1693136724; x=1693741524; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=aa3H2iefcQlYYWOvTv26OeJQbCdCn/zWrEM8kKvHomY=; b=eHY14BrrVoJsqDZDlPmLXbfPcayLOiTnqDAlXbHg7ehMmSIOWMz1H27x6kgwhpWZVC vQfyfuO3Zsp3HGy6YGd4c2geiNp8b2Qh2pQifShJIk3rMFtYo7hpcsS2/a7hM8NNup3g OF8emR+k8et2vMDOu9msuvc5YBA2IuCGLh7GnIj9zvsH4Js/AwP/6p9ghqrv0GeYHs0Y 7nZVo6OZ3sh3Hw5vSO59rMCSBucuC5mehw3KvVWHsKAA7FjaTxc71RnPsG1f1kBK/C/i ZGQvewGK+W60IS8jBZ7ZmtdhQjQ9mMVrhu4wwaXgCqWaALjIxYESrvVJ2P8MF1bouyB+ 3x9A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693136724; x=1693741524; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=aa3H2iefcQlYYWOvTv26OeJQbCdCn/zWrEM8kKvHomY=; b=ebqwxDt5sitl7qV2iwHjLSskJbM8AZn5/CmieuU6PsnaKeztDoAQQujde4UXwol3uj 33kD9fav+eudiAAT4yNBCAfVglzL6fBTMxOcnmKXaRc2rcgVTt8DsE62BSKF4MtlM7Cv /DcVPC4pq1XTdWSQmwFDTaP7Xz7UGuKlTScAKcj8VuoNlsMmgwMXSsSsjDEGqnyoVID2 FIrNhteye2Vd48se98/w02yPX/ajLHGOsCEnJ+GXJD/kuKolaE7w5Tb++TiWpkzK44xW BzX3c+Nbw8h8Q4aUq/LwE0xQPtdTNaKqh6AMOmJaoXEyFZEVHF6b+GuJQsjZqqjgqaP6 iw6g== X-Gm-Message-State: AOJu0YyYrmUiaLyMTMJ2zj3Wd8jKoICWprPYzwEIgluG2aYHsZyUZAa8 h4oqG2IkPOQEAGPZiOfdUddykw== X-Google-Smtp-Source: AGHT+IGwC58vPd6gVaZ2rZzjpBpbfeahrxbw4hICOCqX+x4aGvq7mANdbs1Ik/uE29QdPQiIlixvYg== X-Received: by 2002:a05:6512:304f:b0:500:b890:fb38 with SMTP id b15-20020a056512304f00b00500b890fb38mr554588lfb.24.1693136724245; Sun, 27 Aug 2023 04:45:24 -0700 (PDT) Received: from krzk-bin.. ([77.252.47.225]) by smtp.gmail.com with ESMTPSA id m15-20020a50ef0f000000b005254b41f507sm3239024eds.32.2023.08.27.04.45.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Aug 2023 04:45:23 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH 2/2] ARM: dts: qcom: sdx65: add missing GCC clocks Date: Sun, 27 Aug 2023 13:45:19 +0200 Message-Id: <20230827114519.48797-2-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230827114519.48797-1-krzysztof.kozlowski@linaro.org> References: <20230827114519.48797-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The SDX65 GCC clock controller expects two required clocks: pcie_pipe_clk and usb3_phy_wrapper_gcc_usb30_pipe_clk. The first one is provided by existing phy node, but second is not yet implemented. qcom-sdx65-mtp.dtb: clock-controller@100000: clocks: [[11, 0], [11, 1], [12]] is too short qcom-sdx65-mtp.dtb: clock-controller@100000: clock-names: ['bi_tcxo', 'bi_tcxo_ao', 'sleep_clk'] is too short Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio --- arch/arm/boot/dts/qcom/qcom-sdx65.dtsi | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi index 93c6c80dc379..58635bbc1123 100644 --- a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi @@ -204,8 +204,16 @@ soc: soc { gcc: clock-controller@100000 { compatible = "qcom,gcc-sdx65"; reg = <0x00100000 0x001f7400>; - clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>; - clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>, + <&pcie_phy>, + <0>; + clock-names = "bi_tcxo", + "bi_tcxo_ao", + "sleep_clk", + "pcie_pipe_clk", + "usb3_phy_wrapper_gcc_usb30_pipe_clk"; #power-domain-cells = <1>; #clock-cells = <1>; #reset-cells = <1>;