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[213.113.113.53]) by smtp.gmail.com with ESMTPSA id m18sm2314843lfe.45.2017.01.28.12.48.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 28 Jan 2017 12:48:57 -0800 (PST) From: Linus Walleij To: Hans Ulli Kroll , Florian Fainelli , Bjorn Helgaas Cc: Janos Laube , Paulius Zaleckas , openwrt-devel@openwrt.org, linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, Linus Walleij , devicetree@vger.kernel.org Subject: [PATCH 1/4] PCI: add DT bindings for Cortina Gemini PCI Host Bridge Date: Sat, 28 Jan 2017 21:48:36 +0100 Message-Id: <20170128204839.18330-1-linus.walleij@linaro.org> X-Mailer: git-send-email 2.9.3 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds device tree bindings for the Cortina Systems Gemini PCI Host Bridge. Cc: Janos Laube Cc: Paulius Zaleckas Cc: Hans Ulli Kroll Cc: Florian Fainelli Cc: devicetree@vger.kernel.org Signed-off-by: Linus Walleij --- This can be merged to the PCI tree whenever it is considered fine for inclusion. --- .../devicetree/bindings/pci/cortina,gemini-pci.txt | 64 ++++++++++++++++++++++ 1 file changed, 64 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/cortina,gemini-pci.txt -- 2.9.3 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/pci/cortina,gemini-pci.txt b/Documentation/devicetree/bindings/pci/cortina,gemini-pci.txt new file mode 100644 index 000000000000..e3090d995e1e --- /dev/null +++ b/Documentation/devicetree/bindings/pci/cortina,gemini-pci.txt @@ -0,0 +1,64 @@ +* Cortina Systems Gemini PCI Host Bridge + +Mandatory properties: + +- compatible: should be "cortina,gemini-pci" +- reg: memory base and size for the host bridge +- interrupts: the four PCI interrupts +- #address-cells: set to <3> +- #size-cells: set to <2> +- #interrupt-cells: set to <1> +- bus-range: set to <0x00 0x00> (only root bus) +- device_type, set to "pci" +- ranges: see pci.txt +- interrupt-map-mask: see pci.txt +- interrupt-map: see pci.txt + +Mandatory subnodes: +- One node reprenting the interrupt-controller inside the host bridge + with the following mandatory properties: + - interrupt-controller: see interrupt-controller/interrupts.txt + - #address-cells: set to <0> + - #interrupt-cells: set to <1> + +Example: + +pci@50000000 { + compatible = "cortina,gemini-pci"; + reg = <0x50000000 0x100>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>, /* PCI A */ + <26 IRQ_TYPE_LEVEL_HIGH>, /* PCI B */ + <27 IRQ_TYPE_LEVEL_HIGH>, /* PCI C */ + <28 IRQ_TYPE_LEVEL_HIGH>; /* PCI D */ + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + + bus-range = <0x00 0x00>; /* Only root bus */ + ranges = /* 1MiB I/O space 0x50000000-0x500fffff */ + <0x01000000 0 0 0x50000000 0 0x00100000>, + /* 128MiB non-prefetchable memory 0x58000000-0x5fffffff */ + <0x02000000 0 0x58000000 0x58000000 0 0x08000000>; + interrupt-map-mask = <0xff00 0 0 7>; + interrupt-map = <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */ + <0x4900 0 0 2 &pci_intc 1>, + <0x4a00 0 0 3 &pci_intc 2>, + <0x4b00 0 0 4 &pci_intc 3>, + <0x5000 0 0 1 &pci_intc 0>, /* Slot 10 */ + <0x5100 0 0 2 &pci_intc 1>, + <0x5200 0 0 3 &pci_intc 2>, + <0x5300 0 0 4 &pci_intc 3>, + <0x5800 0 0 1 &pci_intc 0>, /* Slot 11 */ + <0x5900 0 0 2 &pci_intc 1>, + <0x5a00 0 0 3 &pci_intc 2>, + <0x5b00 0 0 4 &pci_intc 3>, + <0x6000 0 0 1 &pci_intc 0>, /* Slot 12 */ + <0x6100 0 0 2 &pci_intc 1>, + <0x6200 0 0 3 &pci_intc 2>, + <0x6300 0 0 4 &pci_intc 3>; + pci_intc: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; +}; From patchwork Sat Jan 28 20:48:37 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 92756 Delivered-To: patch@linaro.org Received: by 10.140.20.99 with SMTP id 90csp812684qgi; Sat, 28 Jan 2017 12:50:58 -0800 (PST) X-Received: by 10.84.149.102 with SMTP id b35mr21395939plh.3.1485636658853; Sat, 28 Jan 2017 12:50:58 -0800 (PST) Return-Path: Received: from bombadil.infradead.org (bombadil.infradead.org. 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[213.113.113.53]) by smtp.gmail.com with ESMTPSA id m18sm2314843lfe.45.2017.01.28.12.49.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 28 Jan 2017 12:49:01 -0800 (PST) From: Linus Walleij To: Hans Ulli Kroll , Florian Fainelli , Bjorn Helgaas Subject: [PATCH 2/4] PCI: add driver for Cortina Gemini Host Bridge Date: Sat, 28 Jan 2017 21:48:37 +0100 Message-Id: <20170128204839.18330-2-linus.walleij@linaro.org> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170128204839.18330-1-linus.walleij@linaro.org> References: <20170128204839.18330-1-linus.walleij@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170128_125025_657182_9A0AF4BC X-CRM114-Status: GOOD ( 21.94 ) X-Spam-Score: -2.7 (--) X-Spam-Report: SpamAssassin version 3.4.1 on bombadil.infradead.org summary: Content analysis details: (-2.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.215.49 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [209.85.215.49 listed in wl.mailspike.net] -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: openwrt-devel@openwrt.org, Paulius Zaleckas , linux-pci@vger.kernel.org, Linus Walleij , Janos Laube , linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org This adds a host bridge driver for the Cortina Systems Gemini SoC (SL3516) PCI Host Bridge. This code is inspired by the out-of-tree OpenWRT patch and then extensively rewritten for device tree and using the modern helpers to cut down and modernize the code to all new PCI frameworks. Tested on the ITian Square One SQ201 NAS with the following result in the boot log (trimmed to relevant parts): OF: PCI: host bridge /pci@50000000 ranges: OF: PCI: IO 0x50000000..0x500fffff -> 0x00000000 OF: PCI: MEM 0x58000000..0x5fffffff -> 0x58000000 gemini-pci 50000000.pci: PCI host bridge to bus 0000:00 pci_bus 0000:00: root bus resource [bus 00] pci_bus 0000:00: root bus resource [io 0x0000-0xfffff] pci_bus 0000:00: root bus resource [mem 0x58000000-0x5fffffff] pci 0000:00:00.0: [159b:4321] type 00 class 0x060000 pci 0000:00:09.0: [1106:3038] type 00 class 0x0c0300 pci 0000:00:09.0: reg 0x20: [io 0xfce0-0xfcff] pci 0000:00:09.0: supports D1 D2 pci 0000:00:09.0: PME# supported from D0 D1 D2 D3hot D3cold pci 0000:00:09.1: [1106:3038] type 00 class 0x0c0300 pci 0000:00:09.1: reg 0x20: [io 0xfce0-0xfcff] pci 0000:00:09.1: supports D1 D2 pci 0000:00:09.1: PME# supported from D0 D1 D2 D3hot D3cold pci 0000:00:09.2: [1106:3104] type 00 class 0x0c0320 pci 0000:00:09.2: reg 0x10: [mem 0x00000000-0x000000ff] pci 0000:00:09.2: supports D1 D2 pci 0000:00:09.2: PME# supported from D0 D1 D2 D3hot D3cold pci 0000:00:0c.0: [1814:0301] type 00 class 0x028000 pci 0000:00:0c.0: reg 0x10: [mem 0x58000000-0x58007fff] PCI: bus0: Fast back to back transfers disabled gemini-pci 50000000.pci: clear all IRQs gemini-pci 50000000.pci: setting up PCI DMA pci 0000:00:00.0: of_irq_parse_pci() failed with rc=-22 pci 0000:00:0c.0: BAR 0: assigned [mem 0x58000000-0x58007fff] pci 0000:00:09.2: BAR 0: assigned [mem 0x58008000-0x580080ff] pci 0000:00:09.0: BAR 4: assigned [io 0x0400-0x041f] pci 0000:00:09.1: BAR 4: assigned [io 0x0420-0x043f] pci 0000:00:09.0: enabling device (0140 -> 0141) pci 0000:00:09.0: HCRESET not completed yet! pci 0000:00:09.1: enabling device (0140 -> 0141) pci 0000:00:09.1: HCRESET not completed yet! pci 0000:00:09.2: enabling device (0140 -> 0142) ieee80211 phy0: rt2x00_set_chip: Info - Chipset detected - rt: 2561, rf: 0003, rev: 000c ieee80211 phy0: Selected rate control algorithm 'minstrel_ht' ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver ehci-pci: EHCI PCI platform driver ehci-pci 0000:00:09.2: EHCI Host Controller ehci-pci 0000:00:09.2: new USB bus registered, assigned bus number 1 ehci-pci 0000:00:09.2: irq 146, io mem 0x58008000 ehci-pci 0000:00:09.2: USB 2.0 started, EHCI 1.00 hub 1-0:1.0: USB hub found hub 1-0:1.0: 4 ports detected uhci_hcd: USB Universal Host Controller Interface driver uhci_hcd 0000:00:09.0: UHCI Host Controller uhci_hcd 0000:00:09.0: new USB bus registered, assigned bus number 2 uhci_hcd 0000:00:09.0: HCRESET not completed yet! uhci_hcd 0000:00:09.0: irq 144, io base 0x00000400 hub 2-0:1.0: USB hub found hub 2-0:1.0: config failed, hub doesn't have any ports! (err -19) uhci_hcd 0000:00:09.1: UHCI Host Controller uhci_hcd 0000:00:09.1: new USB bus registered, assigned bus number 3 uhci_hcd 0000:00:09.1: HCRESET not completed yet! uhci_hcd 0000:00:09.1: irq 145, io base 0x00000420 hub 3-0:1.0: USB hub found hub 3-0:1.0: config failed, hub doesn't have any ports! (err -19) usb 1-1: new high-speed USB device number 2 using ehci-pci usb-storage 1-1:1.0: USB Mass Storage device detected scsi host0: usb-storage 1-1:1.0 scsi 0:0:0:0: Direct-Access USB Flash Disk 1.00 PQ: 0 ANSI: 2 sd 0:0:0:0: [sda] 7900336 512-byte logical blocks: (4.04 GB/3.77 GiB) sd 0:0:0:0: [sda] Write Protect is off sd 0:0:0:0: [sda] Mode Sense: 0b 00 00 08 sd 0:0:0:0: [sda] No Caching mode page found sd 0:0:0:0: [sda] Assuming drive cache: write through sda: sda1 sda2 sda3 sd 0:0:0:0: [sda] Attached SCSI removable disk $ lspci 00:00.0 Class 0600: 159b:4321 00:09.2 Class 0c03: 1106:3104 00:09.0 Class 0c03: 1106:3038 00:09.1 Class 0c03: 1106:3038 00:0c.0 Class 0280: 1814:0301 cat /proc/interrupts CPU0 19: 0 GEMINI 3 Level watchdog bark 30: 4943 GEMINI 14 Edge Gemini Timer Tick 33: 0 GEMINI 17 Level 45000000.rtc 34: 651 GEMINI 18 Level serial 66: 0 GPIO 18 Edge factory reset 144: 0 PCI 0 Edge uhci_hcd:usb2 145: 0 PCI 1 Edge uhci_hcd:usb3 146: 160 PCI 2 Edge ehci_hcd:usb1 Well the EHCI USB hub works fine, I can mount and manage files and the IRQs just keep ticking up. Cc: Janos Laube Cc: Paulius Zaleckas Cc: Hans Ulli Kroll Cc: Florian Fainelli Signed-off-by: Linus Walleij --- This can be merged to the PCI tree whenever it is considered fine for inclusion. --- drivers/pci/host/Kconfig | 7 + drivers/pci/host/Makefile | 1 + drivers/pci/host/pci-gemini.c | 375 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 383 insertions(+) create mode 100644 drivers/pci/host/pci-gemini.c -- 2.9.3 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig index 898d2c48239c..e29c2caf3492 100644 --- a/drivers/pci/host/Kconfig +++ b/drivers/pci/host/Kconfig @@ -60,6 +60,13 @@ config PCI_EXYNOS select PCIEPORTBUS select PCIE_DW +config PCI_GEMINI + bool "Cortina Gemini SL351x PCI roller" + depends on ARCH_GEMINI + depends on ARM + depends on OF + default ARCH_GEMINI + config PCI_IMX6 bool "Freescale i.MX6 PCIe controller" depends on SOC_IMX6Q diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile index bfe3179ae74c..8f007fe7a19d 100644 --- a/drivers/pci/host/Makefile +++ b/drivers/pci/host/Makefile @@ -2,6 +2,7 @@ obj-$(CONFIG_PCIE_DW) += pcie-designware.o obj-$(CONFIG_PCIE_DW_PLAT) += pcie-designware-plat.o obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o +obj-$(CONFIG_PCI_GEMINI) += pci-gemini.o obj-$(CONFIG_PCI_IMX6) += pci-imx6.o obj-$(CONFIG_PCI_HYPERV) += pci-hyperv.o obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o diff --git a/drivers/pci/host/pci-gemini.c b/drivers/pci/host/pci-gemini.c new file mode 100644 index 000000000000..7051dd992114 --- /dev/null +++ b/drivers/pci/host/pci-gemini.c @@ -0,0 +1,375 @@ +/* + * Support for Gemini PCI Controller + * + * Copyright (C) 2017 Linus Walleij + * + * Based on the out-of-tree OpenWRT patch: + * Copyright (C) 2009 Janos Laube + * Copyright (C) 2009 Paulius Zaleckas + * Based on SL2312 PCI controller code + * Storlink (C) 2003 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define GEMINI_PCI_IOSIZE_1M 0x0000 + +#define GEMINI_PCI_PMC 0x40 +#define GEMINI_PCI_PMCSR 0x44 +#define GEMINI_PCI_CTRL1 0x48 +#define GEMINI_PCI_CTRL2 0x4C +#define GEMINI_PCI_MEM1_BASE_SIZE 0x50 +#define GEMINI_PCI_MEM2_BASE_SIZE 0x54 +#define GEMINI_PCI_MEM3_BASE_SIZE 0x58 + +#define PCI_CTRL2_INTSTS_SHIFT 28 +#define PCI_CTRL2_INTMASK_SHIFT 22 + +#define GEMINI_PCI_DMA_MASK 0xFFF00000 +#define GEMINI_PCI_DMA_MEM1_BASE 0x00000000 +#define GEMINI_PCI_DMA_MEM2_BASE 0x00000000 +#define GEMINI_PCI_DMA_MEM3_BASE 0x00000000 +#define GEMINI_PCI_DMA_MEM1_SIZE 7 +#define GEMINI_PCI_DMA_MEM2_SIZE 6 +#define GEMINI_PCI_DMA_MEM3_SIZE 6 + +#define PCI_CONF_ENABLE BIT(31) +#define PCI_CONF_WHERE(r) ((r) & 0xFC) +#define PCI_CONF_BUS(b) (((b) & 0xFF) << 16) +#define PCI_CONF_DEVICE(d) (((d) & 0x1F) << 11) +#define PCI_CONF_FUNCTION(f) (((f) & 0x07) << 8) + +#define PCI_IOSIZE 0x00 +#define PCI_PROT 0x04 +#define PCI_CTRL 0x08 +#define PCI_SOFTRST 0x10 +#define PCI_CONFIG 0x28 +#define PCI_DATA 0x2C + +struct gemini_pci { + struct device *dev; + void __iomem *base; + struct irq_domain *irqdomain; + spinlock_t lock; + struct pci_bus *bus; +}; + +static int gemini_pci_read_config(struct pci_bus *bus, unsigned int fn, + int config, int size, u32 *value) +{ + struct gemini_pci *p = bus->sysdata; + unsigned long irq_flags; + + spin_lock_irqsave(&p->lock, irq_flags); + + writel(PCI_CONF_BUS(bus->number) | + PCI_CONF_DEVICE(PCI_SLOT(fn)) | + PCI_CONF_FUNCTION(PCI_FUNC(fn)) | + PCI_CONF_WHERE(config) | + PCI_CONF_ENABLE, + p->base + PCI_CONFIG); + + *value = readl(p->base + PCI_DATA); + + if (size == 1) + *value = (*value >> (8 * (config & 3))) & 0xFF; + else if (size == 2) + *value = (*value >> (8 * (config & 3))) & 0xFFFF; + + spin_unlock_irqrestore(&p->lock, irq_flags); + + dev_dbg(&bus->dev, + "[read] slt: %.2d, fnc: %d, cnf: 0x%.2X, val (%d bytes): 0x%.8X\n", + PCI_SLOT(fn), PCI_FUNC(fn), config, size, *value); + + return PCIBIOS_SUCCESSFUL; +} + +static int gemini_pci_write_config(struct pci_bus *bus, unsigned int fn, + int config, int size, u32 value) +{ + struct gemini_pci *p = bus->sysdata; + unsigned long irq_flags = 0; + int ret = PCIBIOS_SUCCESSFUL; + + dev_dbg(&bus->dev, + "[write] slt: %.2d, fnc: %d, cnf: 0x%.2X, val (%d bytes): 0x%.8X\n", + PCI_SLOT(fn), PCI_FUNC(fn), config, size, value); + + spin_lock_irqsave(&p->lock, irq_flags); + + writel(PCI_CONF_BUS(bus->number) | + PCI_CONF_DEVICE(PCI_SLOT(fn)) | + PCI_CONF_FUNCTION(PCI_FUNC(fn)) | + PCI_CONF_WHERE(config) | + PCI_CONF_ENABLE, + p->base + PCI_CONFIG); + + switch (size) { + case 4: + writel(value, p->base + PCI_DATA); + break; + case 2: + writew(value, p->base + PCI_DATA + (config & 3)); + break; + case 1: + writeb(value, p->base + PCI_DATA + (config & 3)); + break; + default: + ret = PCIBIOS_BAD_REGISTER_NUMBER; + } + + spin_unlock_irqrestore(&p->lock, irq_flags); + + return ret; +} + +static struct pci_ops gemini_pci_ops = { + .read = gemini_pci_read_config, + .write = gemini_pci_write_config, +}; + +static void gemini_pci_ack_irq(struct irq_data *d) +{ + struct gemini_pci *p = irq_data_get_irq_chip_data(d); + unsigned int reg; + + gemini_pci_read_config(p->bus, 0, GEMINI_PCI_CTRL2, 4, ®); + reg &= ~(0xF << PCI_CTRL2_INTSTS_SHIFT); + reg |= BIT(irqd_to_hwirq(d) + PCI_CTRL2_INTSTS_SHIFT); + gemini_pci_write_config(p->bus, 0, GEMINI_PCI_CTRL2, 4, reg); +} + +static void gemini_pci_mask_irq(struct irq_data *d) +{ + struct gemini_pci *p = irq_data_get_irq_chip_data(d); + unsigned int reg; + + gemini_pci_read_config(p->bus, 0, GEMINI_PCI_CTRL2, 4, ®); + reg &= ~((0xF << PCI_CTRL2_INTSTS_SHIFT) + | BIT(irqd_to_hwirq(d) + PCI_CTRL2_INTMASK_SHIFT)); + gemini_pci_write_config(p->bus, 0, GEMINI_PCI_CTRL2, 4, reg); +} + +static void gemini_pci_unmask_irq(struct irq_data *d) +{ + struct gemini_pci *p = irq_data_get_irq_chip_data(d); + unsigned int reg; + + gemini_pci_read_config(p->bus, 0, GEMINI_PCI_CTRL2, 4, ®); + reg &= ~(0xF << PCI_CTRL2_INTSTS_SHIFT); + reg |= BIT(irqd_to_hwirq(d) + PCI_CTRL2_INTMASK_SHIFT); + gemini_pci_write_config(p->bus, 0, GEMINI_PCI_CTRL2, 4, reg); +} + +static void gemini_pci_irq_handler(struct irq_desc *desc) +{ + struct gemini_pci *p = irq_desc_get_handler_data(desc); + struct irq_chip *irqchip = irq_desc_get_chip(desc); + unsigned int irq_stat, reg, i; + + gemini_pci_read_config(p->bus, 0, GEMINI_PCI_CTRL2, 4, ®); + irq_stat = reg >> PCI_CTRL2_INTSTS_SHIFT; + + chained_irq_enter(irqchip, desc); + + for (i = 0; i < 4; i++) { + if ((irq_stat & BIT(i)) == 0) + continue; + generic_handle_irq(irq_find_mapping(p->irqdomain, i)); + } + + chained_irq_exit(irqchip, desc); +} + +static struct irq_chip gemini_pci_irq_chip = { + .name = "PCI", + .irq_ack = gemini_pci_ack_irq, + .irq_mask = gemini_pci_mask_irq, + .irq_unmask = gemini_pci_unmask_irq, +}; + +static int gemini_pci_irq_map(struct irq_domain *domain, unsigned int irq, + irq_hw_number_t hwirq) +{ + irq_set_chip_and_handler(irq, &gemini_pci_irq_chip, handle_level_irq); + irq_set_chip_data(irq, domain->host_data); + + return 0; +} + +static const struct irq_domain_ops gemini_pci_irqdomain_ops = { + .map = gemini_pci_irq_map, +}; + +static int gemini_pci_setup_irq(struct gemini_pci *p, int irq) +{ + struct device_node *intc = of_get_next_child(p->dev->of_node, NULL); + int i; + + if (!intc) { + dev_err(p->dev, "missing child interrupt-controller node\n"); + return -EINVAL; + } + + p->irqdomain = irq_domain_add_linear(intc, 4, + &gemini_pci_irqdomain_ops, + p); + if (!p->irqdomain) { + dev_err(p->dev, "failed to create Gemini PCI IRQ domain\n"); + return -EINVAL; + } + + irq_set_chained_handler_and_data(irq, gemini_pci_irq_handler, p); + + for (i = 0; i < 4; i++) + irq_create_mapping(p->irqdomain, i); + + return 0; +} + +static int gemini_pci_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct resource *regs; + resource_size_t io_base; + struct resource_entry *win; + struct gemini_pci *p; + struct resource *mem; + struct resource *io; + struct pci_bus *bus; + int irq; + int ret; + u32 val; + LIST_HEAD(res); + + p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL); + if (!p) + return -ENOMEM; + + p->dev = dev; + spin_lock_init(&p->lock); + + regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); + p->base = devm_ioremap_resource(dev, regs); + if (IS_ERR(p->base)) + return PTR_ERR(p->base); + + ret = of_pci_get_host_bridge_resources(dev->of_node, 0, 0xff, + &res, &io_base); + if (ret) + return ret; + + ret = devm_request_pci_bus_resources(dev, &res); + if (ret) + return ret; + + /* No clue what these do */ + pcibios_min_io = 0x100; + pcibios_min_mem = 0; + + /* setup I/O space to 1MB size */ + writel(GEMINI_PCI_IOSIZE_1M, p->base + PCI_IOSIZE); + + /* setup hostbridge */ + val = readl(p->base + PCI_CTRL); + val |= PCI_COMMAND_IO; + val |= PCI_COMMAND_MEMORY; + val |= PCI_COMMAND_MASTER; + writel(val, p->base + PCI_CTRL); + + /* Get the I/O and memory ranges from DT */ + resource_list_for_each_entry(win, &res) { + switch (resource_type(win->res)) { + case IORESOURCE_IO: + io = win->res; + io->name = "Gemini PCI I/O"; + ret = pci_remap_iospace(io, io_base); + if (ret) { + dev_warn(dev, "error %d: failed to map resource %pR\n", + ret, io); + continue; + } + break; + case IORESOURCE_MEM: + mem = win->res; + mem->name = "Gemini PCI MEM"; + break; + case IORESOURCE_BUS: + break; + default: + break; + } + } + + bus = pci_scan_root_bus(&pdev->dev, 0, &gemini_pci_ops, p, &res); + if (!bus) + return -ENOMEM; + p->bus = bus; + + dev_info(dev, "clear all IRQs\n"); + + /* Mask and clear all interrupts */ + gemini_pci_write_config(bus, 0, GEMINI_PCI_CTRL2 + 2, 2, 0xF000); + + /* IRQ - all PCI IRQs cascade off this one */ + irq = platform_get_irq(pdev, 0); + if (!irq) { + dev_err(dev, "failed to get IRQ\n"); + return -EINVAL; + } + + ret = gemini_pci_setup_irq(p, irq); + if (ret) { + dev_err(dev, "failed to setup IRQ\n"); + return ret; + } + + dev_info(dev, "setting up PCI DMA\n"); + val = (GEMINI_PCI_DMA_MEM1_BASE & GEMINI_PCI_DMA_MASK) + | (GEMINI_PCI_DMA_MEM1_SIZE << 16); + gemini_pci_write_config(bus, 0, GEMINI_PCI_MEM1_BASE_SIZE, 4, val); + val = (GEMINI_PCI_DMA_MEM2_BASE & GEMINI_PCI_DMA_MASK) + | (GEMINI_PCI_DMA_MEM2_SIZE << 16); + gemini_pci_write_config(bus, 0, GEMINI_PCI_MEM2_BASE_SIZE, 4, val); + val = (GEMINI_PCI_DMA_MEM3_BASE & GEMINI_PCI_DMA_MASK) + | (GEMINI_PCI_DMA_MEM3_SIZE << 16); + gemini_pci_write_config(bus, 0, GEMINI_PCI_MEM3_BASE_SIZE, 4, val); + + pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci); + pci_bus_assign_resources(bus); + pci_assign_unassigned_bus_resources(bus); + pci_bus_add_devices(bus); + pci_free_resource_list(&res); + + return 0; +} + +static const struct of_device_id gemini_pci_of_match[] = { + { + .compatible = "cortina,gemini-pci", + }, + {}, +}; + +static struct platform_driver gemini_pci_driver = { + .driver = { + .name = "gemini-pci", + .of_match_table = of_match_ptr(gemini_pci_of_match), + }, + .probe = gemini_pci_probe, +}; +builtin_platform_driver(gemini_pci_driver); From patchwork Sat Jan 28 20:48:38 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 92757 Delivered-To: patch@linaro.org Received: by 10.140.20.99 with SMTP id 90csp812862qgi; Sat, 28 Jan 2017 12:51:53 -0800 (PST) X-Received: by 10.84.216.91 with SMTP id f27mr21182126plj.92.1485636713748; Sat, 28 Jan 2017 12:51:53 -0800 (PST) Return-Path: Received: from bombadil.infradead.org (bombadil.infradead.org. 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[213.113.113.53]) by smtp.gmail.com with ESMTPSA id m18sm2314843lfe.45.2017.01.28.12.49.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 28 Jan 2017 12:49:04 -0800 (PST) From: Linus Walleij To: Hans Ulli Kroll , Florian Fainelli , Bjorn Helgaas Subject: [PATCH 3/4] ARM: gemini: select MIGHT_HAVE_PCI Date: Sat, 28 Jan 2017 21:48:38 +0100 Message-Id: <20170128204839.18330-3-linus.walleij@linaro.org> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170128204839.18330-1-linus.walleij@linaro.org> References: <20170128204839.18330-1-linus.walleij@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170128_125028_158329_DAB88BF4 X-CRM114-Status: GOOD ( 11.50 ) X-Spam-Score: -2.0 (--) X-Spam-Report: SpamAssassin version 3.4.1 on bombadil.infradead.org summary: Content analysis details: (-2.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/, no trust [209.85.215.47 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [209.85.215.47 listed in wl.mailspike.net] -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: openwrt-devel@openwrt.org, Paulius Zaleckas , linux-pci@vger.kernel.org, Linus Walleij , Janos Laube , linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org As we have a PCI driver for the Gemini, we should select MIGHT_HAVE_PCI. Cc: Janos Laube Cc: Paulius Zaleckas Cc: Hans Ulli Kroll Cc: Florian Fainelli Signed-off-by: Linus Walleij --- PCI maintainers: this is FYI only, I will funnel this to the ARM SoC tree once we are done with the PCI driver. --- arch/arm/mach-gemini/Kconfig | 1 + 1 file changed, 1 insertion(+) -- 2.9.3 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel diff --git a/arch/arm/mach-gemini/Kconfig b/arch/arm/mach-gemini/Kconfig index 798abb16bb88..91ea52ccf13c 100644 --- a/arch/arm/mach-gemini/Kconfig +++ b/arch/arm/mach-gemini/Kconfig @@ -5,6 +5,7 @@ menuconfig ARCH_GEMINI select GEMINI_TIMER select GPIO_GEMINI select GPIOLIB + select MIGHT_HAVE_PCI select POWER_RESET select POWER_RESET_SYSCON select SERIAL_OF_PLATFORM From patchwork Sat Jan 28 20:48:39 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 92758 Delivered-To: patch@linaro.org Received: by 10.140.20.99 with SMTP id 90csp812892qgi; Sat, 28 Jan 2017 12:52:02 -0800 (PST) X-Received: by 10.98.17.4 with SMTP id z4mr15791836pfi.43.1485636722590; Sat, 28 Jan 2017 12:52:02 -0800 (PST) Return-Path: Received: from bombadil.infradead.org (bombadil.infradead.org. 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[213.113.113.53]) by smtp.gmail.com with ESMTPSA id m18sm2314843lfe.45.2017.01.28.12.49.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 28 Jan 2017 12:49:07 -0800 (PST) From: Linus Walleij To: Hans Ulli Kroll , Florian Fainelli , Bjorn Helgaas Subject: [PATCH 4/4] ARM: dts: add PCI to the Gemini DTSI Date: Sat, 28 Jan 2017 21:48:39 +0100 Message-Id: <20170128204839.18330-4-linus.walleij@linaro.org> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170128204839.18330-1-linus.walleij@linaro.org> References: <20170128204839.18330-1-linus.walleij@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170128_125030_963664_6E39D032 X-CRM114-Status: GOOD ( 12.22 ) X-Spam-Score: -2.0 (--) X-Spam-Report: SpamAssassin version 3.4.1 on bombadil.infradead.org summary: Content analysis details: (-2.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/, no trust [209.85.215.53 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [209.85.215.53 listed in wl.mailspike.net] -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: openwrt-devel@openwrt.org, Paulius Zaleckas , linux-pci@vger.kernel.org, Linus Walleij , Janos Laube , linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org The Cortina Gemini has an internal PCI root bus, add this to the device tree. Cc: Janos Laube Cc: Paulius Zaleckas Cc: Hans Ulli Kroll Cc: Florian Fainelli Signed-off-by: Linus Walleij --- PCI maintainers: this is FYI only, I will funnel this to the ARM SoC tree once we are done with the PCI driver. --- arch/arm/boot/dts/gemini.dtsi | 45 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) -- 2.9.3 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel diff --git a/arch/arm/boot/dts/gemini.dtsi b/arch/arm/boot/dts/gemini.dtsi index 405d6cedf409..df5630958038 100644 --- a/arch/arm/boot/dts/gemini.dtsi +++ b/arch/arm/boot/dts/gemini.dtsi @@ -99,4 +99,49 @@ interrupt-controller; #interrupt-cells = <2>; }; + + pci@50000000 { + compatible = "cortina,gemini-pci"; + reg = <0x50000000 0x100>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>, /* PCI A */ + <26 IRQ_TYPE_LEVEL_HIGH>, /* PCI B */ + <27 IRQ_TYPE_LEVEL_HIGH>, /* PCI C */ + <28 IRQ_TYPE_LEVEL_HIGH>; /* PCI D */ + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + + bus-range = <0x00 0x00>; /* Only root bus */ + /* PCI ranges mappings */ + ranges = /* 1MiB I/O space 0x50000000-0x500fffff */ + <0x01000000 0 0 0x50000000 0 0x00100000>, + /* 128MiB non-prefetchable memory 0x58000000-0x5fffffff */ + <0x02000000 0 0x58000000 0x58000000 0 0x08000000>; + + interrupt-map-mask = <0xff00 0 0 7>; + /* + * The interrupt map is done by sub-device and per-slot. + */ + interrupt-map = <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */ + <0x4900 0 0 2 &pci_intc 1>, + <0x4a00 0 0 3 &pci_intc 2>, + <0x4b00 0 0 4 &pci_intc 3>, + <0x5000 0 0 1 &pci_intc 0>, /* Slot 10 */ + <0x5100 0 0 2 &pci_intc 1>, + <0x5200 0 0 3 &pci_intc 2>, + <0x5300 0 0 4 &pci_intc 3>, + <0x5800 0 0 1 &pci_intc 0>, /* Slot 11 */ + <0x5900 0 0 2 &pci_intc 1>, + <0x5a00 0 0 3 &pci_intc 2>, + <0x5b00 0 0 4 &pci_intc 3>, + <0x6000 0 0 1 &pci_intc 0>, /* Slot 12 */ + <0x6100 0 0 2 &pci_intc 1>, + <0x6200 0 0 3 &pci_intc 2>, + <0x6300 0 0 4 &pci_intc 3>; + pci_intc: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; };