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[217.61.220.45]) by smtp.gmail.com with ESMTPSA id c2sm966244edc.34.2017.06.07.10.12.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 07 Jun 2017 10:12:08 -0700 (PDT) From: Christoffer Dall To: Paolo Bonzini , =?utf-8?b?UmFkaW0gS3LEjW3DocWZ?= Cc: Marc Zyngier , kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, stable@vger.kernel.org, Christoffer Dall Subject: [PULL v2 3/6] KVM: arm/arm64: Handle possible NULL stage2 pud when ageing pages Date: Wed, 7 Jun 2017 19:11:49 +0200 Message-Id: <20170607171152.21874-4-cdall@linaro.org> X-Mailer: git-send-email 2.9.0 In-Reply-To: <20170607171152.21874-1-cdall@linaro.org> References: <20170607171152.21874-1-cdall@linaro.org> Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Marc Zyngier Under memory pressure, we start ageing pages, which amounts to parsing the page tables. Since we don't want to allocate any extra level, we pass NULL for our private allocation cache. Which means that stage2_get_pud() is allowed to fail. This results in the following splat: [ 1520.409577] Unable to handle kernel NULL pointer dereference at virtual address 00000008 [ 1520.417741] pgd = ffff810f52fef000 [ 1520.421201] [00000008] *pgd=0000010f636c5003, *pud=0000010f56f48003, *pmd=0000000000000000 [ 1520.429546] Internal error: Oops: 96000006 [#1] PREEMPT SMP [ 1520.435156] Modules linked in: [ 1520.438246] CPU: 15 PID: 53550 Comm: qemu-system-aar Tainted: G W 4.12.0-rc4-00027-g1885c397eaec #7205 [ 1520.448705] Hardware name: FOXCONN R2-1221R-A4/C2U4N_MB, BIOS G31FB12A 10/26/2016 [ 1520.463726] task: ffff800ac5fb4e00 task.stack: ffff800ce04e0000 [ 1520.469666] PC is at stage2_get_pmd+0x34/0x110 [ 1520.474119] LR is at kvm_age_hva_handler+0x44/0xf0 [ 1520.478917] pc : [] lr : [] pstate: 40000145 [ 1520.486325] sp : ffff800ce04e33d0 [ 1520.489644] x29: ffff800ce04e33d0 x28: 0000000ffff40064 [ 1520.494967] x27: 0000ffff27e00000 x26: 0000000000000000 [ 1520.500289] x25: ffff81051ba65008 x24: 0000ffff40065000 [ 1520.505618] x23: 0000ffff40064000 x22: 0000000000000000 [ 1520.510947] x21: ffff810f52b20000 x20: 0000000000000000 [ 1520.516274] x19: 0000000058264000 x18: 0000000000000000 [ 1520.521603] x17: 0000ffffa6fe7438 x16: ffff000008278b70 [ 1520.526940] x15: 000028ccd8000000 x14: 0000000000000008 [ 1520.532264] x13: ffff7e0018298000 x12: 0000000000000002 [ 1520.537582] x11: ffff000009241b93 x10: 0000000000000940 [ 1520.542908] x9 : ffff0000092ef800 x8 : 0000000000000200 [ 1520.548229] x7 : ffff800ce04e36a8 x6 : 0000000000000000 [ 1520.553552] x5 : 0000000000000001 x4 : 0000000000000000 [ 1520.558873] x3 : 0000000000000000 x2 : 0000000000000008 [ 1520.571696] x1 : ffff000008fd5000 x0 : ffff0000080b149c [ 1520.577039] Process qemu-system-aar (pid: 53550, stack limit = 0xffff800ce04e0000) [...] [ 1521.510735] [] stage2_get_pmd+0x34/0x110 [ 1521.516221] [] kvm_age_hva_handler+0x44/0xf0 [ 1521.522054] [] handle_hva_to_gpa+0xb8/0xe8 [ 1521.527716] [] kvm_age_hva+0x44/0xf0 [ 1521.532854] [] kvm_mmu_notifier_clear_flush_young+0x70/0xc0 [ 1521.539992] [] __mmu_notifier_clear_flush_young+0x88/0xd0 [ 1521.546958] [] page_referenced_one+0xf0/0x188 [ 1521.552881] [] rmap_walk_anon+0xec/0x250 [ 1521.558370] [] rmap_walk+0x78/0xa0 [ 1521.563337] [] page_referenced+0x164/0x180 [ 1521.569002] [] shrink_active_list+0x178/0x3b8 [ 1521.574922] [] shrink_node_memcg+0x328/0x600 [ 1521.580758] [] shrink_node+0xc4/0x328 [ 1521.585986] [] do_try_to_free_pages+0xc0/0x340 [ 1521.592000] [] try_to_free_pages+0xcc/0x240 [...] The trivial fix is to handle this NULL pud value early, rather than dereferencing it blindly. Cc: stable@vger.kernel.org Signed-off-by: Marc Zyngier Reviewed-by: Christoffer Dall Signed-off-by: Christoffer Dall --- virt/kvm/arm/mmu.c | 3 +++ 1 file changed, 3 insertions(+) -- 2.9.0 diff --git a/virt/kvm/arm/mmu.c b/virt/kvm/arm/mmu.c index a2d6324..e2e5eff 100644 --- a/virt/kvm/arm/mmu.c +++ b/virt/kvm/arm/mmu.c @@ -879,6 +879,9 @@ static pmd_t *stage2_get_pmd(struct kvm *kvm, struct kvm_mmu_memory_cache *cache pmd_t *pmd; pud = stage2_get_pud(kvm, cache, addr); + if (!pud) + return NULL; + if (stage2_pud_none(*pud)) { if (!cache) return NULL; From patchwork Wed Jun 7 17:11:50 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoffer Dall X-Patchwork-Id: 103304 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp2042491qgd; Wed, 7 Jun 2017 10:12:35 -0700 (PDT) X-Received: by 10.99.100.135 with SMTP id y129mr3833609pgb.5.1496855555290; Wed, 07 Jun 2017 10:12:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1496855555; cv=none; d=google.com; s=arc-20160816; b=skEKMT0NdegwbDlzOSVpaGIpZz5q7O5R4kwtERqc7Co9TWpMA91PeXLfCOQPspgSXo /ZzNV+TlCYNG+aKEqy5wwgUhpYPWnUx4GPUVO7oWJ/SVAMFvxh9LVwo5oIOxrlopNH5u JKoGAjUiWOpao08ZJuCAocYJIDJ8+ImrCEmRsSQF1LGQIqkZ2n4aqkp8nfj6L2v86klr /pwIWD0vsJ2DD/I0+WYDQbDxOjpAHtY5zmOgCSbcy+HLHVS2EjnjMM/eXjA9iio2TFCy MdbvWQWncHiGhlp0E28mtht+e+9FUPaYEycCIRHpdoyH70jJ3PSv2LgVxVRiEok+fPhW 5/dQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=kSJcxCq52VEJcAP+FSoEreKvX3VzBwSlYqjYM02+oAg=; b=qt4ZhW0a0Fto/GUCgWTcnGcz2WuLGZmwg0S+cFC3ZThLrS7EZnuIgvvmgH4t2+9k1z 6M22YDxdey5WUzgUM3E4QOOjOZi5vlon9WamaiY8LPRNZ1HEYays8jMGTCtH07QnkSfo 4O07cl0OPbJpkoKgF4estKe1RoQYLX+EFpwfWBqPrY14MOj4u4VOo6lxc8pMHOialFdY SqQWHvo3NUPYNbhZnUaZr73FXNwWBPUz3vAhEG//FZnXFOvfW8F+m52KVATFx+S6k5vk 5PO1GNvu9p/VTw/kvnR5rbjvv+rAtqQFw9AivRJkQe79lvmSqg5fQWIomqaWqJvaROht wXbA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[217.61.220.45]) by smtp.gmail.com with ESMTPSA id c2sm966244edc.34.2017.06.07.10.12.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 07 Jun 2017 10:12:09 -0700 (PDT) From: Christoffer Dall To: Paolo Bonzini , =?utf-8?b?UmFkaW0gS3LEjW3DocWZ?= Cc: Marc Zyngier , kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, stable@vger.kernel.org, Christoffer Dall Subject: [PULL v2 4/6] arm64: KVM: Preserve RES1 bits in SCTLR_EL2 Date: Wed, 7 Jun 2017 19:11:50 +0200 Message-Id: <20170607171152.21874-5-cdall@linaro.org> X-Mailer: git-send-email 2.9.0 In-Reply-To: <20170607171152.21874-1-cdall@linaro.org> References: <20170607171152.21874-1-cdall@linaro.org> Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Marc Zyngier __do_hyp_init has the rather bad habit of ignoring RES1 bits and writing them back as zero. On a v8.0-8.2 CPU, this doesn't do anything bad, but may end-up being pretty nasty on future revisions of the architecture. Let's preserve those bits so that we don't have to fix this later on. Cc: stable@vger.kernel.org Signed-off-by: Marc Zyngier Signed-off-by: Christoffer Dall --- arch/arm64/include/asm/sysreg.h | 4 ++++ arch/arm64/kvm/hyp-init.S | 10 ++++++---- 2 files changed, 10 insertions(+), 4 deletions(-) -- 2.9.0 diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 15c142c..b4d13d9 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -286,6 +286,10 @@ #define SCTLR_ELx_A (1 << 1) #define SCTLR_ELx_M 1 +#define SCTLR_EL2_RES1 ((1 << 4) | (1 << 5) | (1 << 11) | (1 << 16) | \ + (1 << 16) | (1 << 18) | (1 << 22) | (1 << 23) | \ + (1 << 28) | (1 << 29)) + #define SCTLR_ELx_FLAGS (SCTLR_ELx_M | SCTLR_ELx_A | SCTLR_ELx_C | \ SCTLR_ELx_SA | SCTLR_ELx_I) diff --git a/arch/arm64/kvm/hyp-init.S b/arch/arm64/kvm/hyp-init.S index 839425c..4072d40 100644 --- a/arch/arm64/kvm/hyp-init.S +++ b/arch/arm64/kvm/hyp-init.S @@ -106,10 +106,12 @@ __do_hyp_init: tlbi alle2 dsb sy - mrs x4, sctlr_el2 - and x4, x4, #SCTLR_ELx_EE // preserve endianness of EL2 - ldr x5, =SCTLR_ELx_FLAGS - orr x4, x4, x5 + /* + * Preserve all the RES1 bits while setting the default flags, + * as well as the EE bit on BE. + */ + ldr x4, =(SCTLR_EL2_RES1 | SCTLR_ELx_FLAGS) +CPU_BE( orr x4, x4, #SCTLR_ELx_EE) msr sctlr_el2, x4 isb From patchwork Wed Jun 7 17:11:51 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoffer Dall X-Patchwork-Id: 103303 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp2042484qgd; Wed, 7 Jun 2017 10:12:34 -0700 (PDT) X-Received: by 10.99.163.25 with SMTP id s25mr33459002pge.191.1496855554171; Wed, 07 Jun 2017 10:12:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1496855554; cv=none; d=google.com; s=arc-20160816; b=YfOrlicXPBHBaYYBBgT/9E8U/UXntiMOT+OydOGd1r5lckXbS6H//+CkV+umawumWR HGjt6OPW0h5jqHDK3jZshCAXoSdMEDHozb7YXHj2rKKnV9bEMdZnLq0D/1lXFt2rf1uw ZxB2qFU49M8zHkiVwoMzbZWrsIpw4xXOPFDnrhPT3eDWKgOIRTREcM2EMDUhdwByMNlG CzcXAdToAduKjV3mDwz1s80CeoFJlddMIIjwFK5zoCMJInxmlbHYCplymtrkgPB3VRCB IMToT9RZIR6dv3At6+srD2/Qo3rehJM4CB/2cZtYGZJQur9aXX7d/Yau+PyT2iTRI+xY Id5Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=OzMas14WKct7ApvdLL7743kw3lJsxKT47nOta7IKK5I=; b=VNIZW7V93VbKD4DSN0UHJytWTOInDno4eoyCDnghaJd6NZ6dsNh2BHXMJ8AbG4qMyQ /HVxYAn63O6oK1qyFBZsy3kZboevWqWEa0TVOw/Eo04WOkxe9Iis/nV81o+mmj/5KfT0 hn/KAGQAxPuxPcW6ywLHYmLL0O2wuuFKuD5rQV6oyk5+NdU4chwzL8u0mDhnVaQZ6qPH /I9mMZARiaSEieHE5ReDI76T8GkWROgE+QktS9+qFz44r1cQrjJtWsv3D2HKE2D93dIN zYPn9P1kASDy0yirDahG5kxIXJwft58hg1/yFBM+3e7qLaoTgMyG2PR0y1wQXStXwliw L4wg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[217.61.220.45]) by smtp.gmail.com with ESMTPSA id c2sm966244edc.34.2017.06.07.10.12.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 07 Jun 2017 10:12:10 -0700 (PDT) From: Christoffer Dall To: Paolo Bonzini , =?utf-8?b?UmFkaW0gS3LEjW3DocWZ?= Cc: Marc Zyngier , kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, stable@vger.kernel.org, Christoffer Dall Subject: [PULL v2 5/6] arm64: KVM: Allow unaligned accesses at EL2 Date: Wed, 7 Jun 2017 19:11:51 +0200 Message-Id: <20170607171152.21874-6-cdall@linaro.org> X-Mailer: git-send-email 2.9.0 In-Reply-To: <20170607171152.21874-1-cdall@linaro.org> References: <20170607171152.21874-1-cdall@linaro.org> Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Marc Zyngier We currently have the SCTLR_EL2.A bit set, trapping unaligned accesses at EL2, but we're not really prepared to deal with it. So far, this has been unnoticed, until GCC 7 started emitting those (in particular 64bit writes on a 32bit boundary). Since the rest of the kernel is pretty happy about that, let's follow its example and set SCTLR_EL2.A to zero. Modern CPUs don't really care. Cc: stable@vger.kernel.org Reported-by: Alexander Graf Signed-off-by: Marc Zyngier Signed-off-by: Christoffer Dall --- arch/arm64/kvm/hyp-init.S | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) -- 2.9.0 diff --git a/arch/arm64/kvm/hyp-init.S b/arch/arm64/kvm/hyp-init.S index 4072d40..3f96155 100644 --- a/arch/arm64/kvm/hyp-init.S +++ b/arch/arm64/kvm/hyp-init.S @@ -108,9 +108,10 @@ __do_hyp_init: /* * Preserve all the RES1 bits while setting the default flags, - * as well as the EE bit on BE. + * as well as the EE bit on BE. Drop the A flag since the compiler + * is allowed to generate unaligned accesses. */ - ldr x4, =(SCTLR_EL2_RES1 | SCTLR_ELx_FLAGS) + ldr x4, =(SCTLR_EL2_RES1 | (SCTLR_ELx_FLAGS & ~SCTLR_ELx_A)) CPU_BE( orr x4, x4, #SCTLR_ELx_EE) msr sctlr_el2, x4 isb From patchwork Wed Jun 7 17:11:52 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoffer Dall X-Patchwork-Id: 103305 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp2042532qgd; Wed, 7 Jun 2017 10:12:40 -0700 (PDT) X-Received: by 10.84.137.1 with SMTP id 1mr29812217plm.128.1496855560213; Wed, 07 Jun 2017 10:12:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1496855560; cv=none; d=google.com; s=arc-20160816; b=jUExo3g29z07bIOHtg1JnB+otTLR0HgMOvDbr5gHyuzb/Q/zfFmmDPzqX+OI6+Gyiq A8dxeL3GfJFhGdxBbHRFRSarJI1rdbux40yaDiMAw6R6u56jJkleL15aOOzCvHlL9aik w0wLI7+y3umNiEaf/To4AnigScM4smxQpZFsWWDHbZUYBXXu3L3wT+LcUT+ln3MCCBNz 3hjvMee8o6v1nGtqunb9VNMUnb+wHnP/0eBJ0hq9pYF5BntiiPzP7hkdbuZNbHGxhDFV Kb3oMrlHZFxHQLBq8u5ZwIMH9N7HDNkReKm0lpAa8A19+guSUXEjQd8A9vzMYi+Ztnh4 3ILA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=MbEVFP7IrvVKcLpxzz1RU+ubSF6bVpUOQ/AZVgWFXm4=; b=Xz4VK6dDbNJk2ahHWQjZEZeLjmFUtB4vdN2izH2dX6gUtHhhGtry3R3kdKUw4ytGhI JQN1ndOdndVV0ilWvjMGIIuieMlrT1d+nXC1qIbwv5SJ1p6Y+3sOXUTE80sOTa/4tRng v6mcF9cz/PVKeGeKhZ3zbDk6mGCMlHRW80UwY1jvS07k/gSGpeSvL2uKsV7jSBIgk1Gs atpsW6ACPKRErOAuLL8enZg/WRQKOuuVMmzSDOeeswWfJRMfufHaPaL989lGCAFrxVPy sB/d5jh7Bw/FtzWtlaQOqJBaqEA9bq2vWgNueuRgtuTv1YBlthLZdTrPQJ41F41UORAB Vgxw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[217.61.220.45]) by smtp.gmail.com with ESMTPSA id c2sm966244edc.34.2017.06.07.10.12.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 07 Jun 2017 10:12:11 -0700 (PDT) From: Christoffer Dall To: Paolo Bonzini , =?utf-8?b?UmFkaW0gS3LEjW3DocWZ?= Cc: Marc Zyngier , kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, stable@vger.kernel.org, Christoffer Dall Subject: [PULL v2 6/6] arm: KVM: Allow unaligned accesses at HYP Date: Wed, 7 Jun 2017 19:11:52 +0200 Message-Id: <20170607171152.21874-7-cdall@linaro.org> X-Mailer: git-send-email 2.9.0 In-Reply-To: <20170607171152.21874-1-cdall@linaro.org> References: <20170607171152.21874-1-cdall@linaro.org> Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Marc Zyngier We currently have the HSCTLR.A bit set, trapping unaligned accesses at HYP, but we're not really prepared to deal with it. Since the rest of the kernel is pretty happy about that, let's follow its example and set HSCTLR.A to zero. Modern CPUs don't really care. Cc: stable@vger.kernel.org Signed-off-by: Marc Zyngier Signed-off-by: Christoffer Dall --- arch/arm/kvm/init.S | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) -- 2.9.0 diff --git a/arch/arm/kvm/init.S b/arch/arm/kvm/init.S index 570ed4a..5386528 100644 --- a/arch/arm/kvm/init.S +++ b/arch/arm/kvm/init.S @@ -104,7 +104,6 @@ __do_hyp_init: @ - Write permission implies XN: disabled @ - Instruction cache: enabled @ - Data/Unified cache: enabled - @ - Memory alignment checks: enabled @ - MMU: enabled (this code must be run from an identity mapping) mrc p15, 4, r0, c1, c0, 0 @ HSCR ldr r2, =HSCTLR_MASK @@ -112,8 +111,8 @@ __do_hyp_init: mrc p15, 0, r1, c1, c0, 0 @ SCTLR ldr r2, =(HSCTLR_EE | HSCTLR_FI | HSCTLR_I | HSCTLR_C) and r1, r1, r2 - ARM( ldr r2, =(HSCTLR_M | HSCTLR_A) ) - THUMB( ldr r2, =(HSCTLR_M | HSCTLR_A | HSCTLR_TE) ) + ARM( ldr r2, =(HSCTLR_M) ) + THUMB( ldr r2, =(HSCTLR_M | HSCTLR_TE) ) orr r1, r1, r2 orr r0, r0, r1 mcr p15, 4, r0, c1, c0, 0 @ HSCR