From patchwork Tue Sep 19 03:53:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 724490 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2937B15BF for ; Tue, 19 Sep 2023 03:54:05 +0000 (UTC) Received: from mail-pj1-x1036.google.com (mail-pj1-x1036.google.com [IPv6:2607:f8b0:4864:20::1036]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A343E10F for ; Mon, 18 Sep 2023 20:54:02 -0700 (PDT) Received: by mail-pj1-x1036.google.com with SMTP id 98e67ed59e1d1-2746ab05409so3223683a91.0 for ; Mon, 18 Sep 2023 20:54:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1695095642; x=1695700442; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=c/pyUqu/Tkd0d14pnWQAKU8r5MyttJS43LfVvYmIT30=; b=D0NTPo3PTexB8W/IdHWW5Ktm5i3YBEEPJElB+DWvAyDTpRUx5SvURiKqsVUg2SYnkc 0qp6Hr1o0SDUHi/fpVoxVPoTNcexh737MjOuo0ITr9GQFh3LrJEQGexx7nECkIbrmRDw aFcpHsdvpkY53fnfgtJOlzQlL02ud0KDbny6FAF4DiLi9QlJoLBYuG94StcEPnIfQxqw HZzoMbCRQYOOFXUAc1s47NCbGv6LNDsV1jPwzd6qsvjwtWetl41VUIGYIR7SDzoz2B+f cZA8Yc5ThsBkq6MOTvhGiSg1MVU2Dw/ZLnZyFBRM7WAP45VjLbucUfIJdRT1xQntHA2K KWyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695095642; x=1695700442; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=c/pyUqu/Tkd0d14pnWQAKU8r5MyttJS43LfVvYmIT30=; b=Z9mPPY3tc7+wJbqqhU+tPGTyxMWc1TVdDeH0i8TrRfFAc7UmsCF+RKNZIjj6dNhwa3 a5oyFqKpzS2S4xjLpnVbsDpJqblhME0494uvuBprOPTWh13iZS9KOrqMfJ1nGu0tYynb /SJIi+NouIMmunCt/dXxkmcdmNV4/9LV7MCVNhlZ7ZD2dZpHBBwvEx3AKudoIctb/8KA W4jclLoGxUE9WL0CnUtHtCcwSI21rgSw7bmdfeeFClCqFPEYfLwrQ2+HBxHivZ6HGEpN 49svyidUDFjVGfWRwdQnEjDy8vrWBtwVFaRI8DaJd1S+I8HtbWYX2Uz9HEtBjc6MQovh q2CQ== X-Gm-Message-State: AOJu0YxrRlkavkm64yrqfCeGPXOMVZCWWLOyETkr2V0Uepn4YjX1OD0B e8GpC2GMY7TQongBI4QtHAC7WQ== X-Google-Smtp-Source: AGHT+IEv2GtqSdnsDMi5LgNHnFDwtL1zsQsjYDdjeBpdLohkB2ds19n77ngsGEre26d9mHroBrq5UQ== X-Received: by 2002:a17:90b:190d:b0:276:7907:ecf with SMTP id mp13-20020a17090b190d00b0027679070ecfmr3278208pjb.36.1695095641908; Mon, 18 Sep 2023 20:54:01 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id 3-20020a17090a034300b00273fc850342sm4000802pjf.20.2023.09.18.20.53.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Sep 2023 20:54:01 -0700 (PDT) From: Anup Patel To: Paolo Bonzini , Atish Patra , Palmer Dabbelt , Paul Walmsley , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Shuah Khan Cc: Andrew Jones , Mayuresh Chitale , devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, Anup Patel Subject: [PATCH 1/7] RISC-V: Detect XVentanaCondOps from ISA string Date: Tue, 19 Sep 2023 09:23:37 +0530 Message-Id: <20230919035343.1399389-2-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230919035343.1399389-1-apatel@ventanamicro.com> References: <20230919035343.1399389-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net The Veyron-V1 CPU supports custom conditional arithmetic and conditional-select/move operations referred to as XVentanaCondOps extension. In fact, QEMU RISC-V also has support for emulating XVentanaCondOps extension. Let us detect XVentanaCondOps extension from ISA string available through DT or ACPI. Signed-off-by: Anup Patel --- Documentation/devicetree/bindings/riscv/extensions.yaml | 7 +++++++ arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/kernel/cpufeature.c | 1 + 3 files changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index 36ff6749fbba..cad8ef68eca7 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -171,6 +171,13 @@ properties: memory types as ratified in the 20191213 version of the privileged ISA specification. + - const: xventanacondops + description: | + The Ventana specific XVentanaCondOps extension for conditional + arithmetic and conditional-select/move operations defined by the + Ventana custom extensions specification v1.0.1 (or higher) at + https://github.com/ventanamicro/ventana-custom-extensions/releases. + - const: zba description: | The standard Zba bit-manipulation extension for address generation diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 0f520f7d058a..b7efe9e2fa89 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -59,6 +59,7 @@ #define RISCV_ISA_EXT_ZIFENCEI 41 #define RISCV_ISA_EXT_ZIHPM 42 #define RISCV_ISA_EXT_SMSTATEEN 43 +#define RISCV_ISA_EXT_XVENTANACONDOPS 44 #define RISCV_ISA_EXT_MAX 64 diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 3755a8c2a9de..3a31d34fe709 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -182,6 +182,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL), __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT), __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT), + __RISCV_ISA_EXT_DATA(xventanacondops, RISCV_ISA_EXT_XVENTANACONDOPS), }; const size_t riscv_isa_ext_count = ARRAY_SIZE(riscv_isa_ext); From patchwork Tue Sep 19 03:53:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 724489 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BF7D0110B for ; Tue, 19 Sep 2023 03:54:17 +0000 (UTC) Received: from mail-pj1-x1032.google.com (mail-pj1-x1032.google.com [IPv6:2607:f8b0:4864:20::1032]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B3E33138 for ; Mon, 18 Sep 2023 20:54:15 -0700 (PDT) Received: by mail-pj1-x1032.google.com with SMTP id 98e67ed59e1d1-2769920fa24so390299a91.1 for ; Mon, 18 Sep 2023 20:54:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1695095654; x=1695700454; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=l4XXbW7JTA+rX6h2wllSUbALMsH935/QgdVn7NuGhB8=; b=SZUfbmyXa9kHcmrS6PWs/XaUTkBZbQTOIGPglqhn6Lo2zx9S7C+r2XWrl28jajAjOw bCAdVYfrmchzZ5tL06KzgzlnqLAHmhTkpTj/dMDodFy7RhYv3zb7CP1oR+nG0j8Efyt6 CmXrUBfguYYWDef5x5GkXBYBKCNTfcDcSYoYhSJvlzoeXraxM3/8WH4+q17MkC7vkQmD EjvEmFIYdVWB3m+4uzMcsR6HWHDwsXLret6PBHINAXlCAodkTGoHNcbqTp4GgXZe94r8 MmDyXUbE9W8rp+fX2a9sztrIvh+c62yAXrX1amP6KpnyjuldUWaElR7cFEXcgn35CSHm YOuQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695095654; x=1695700454; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=l4XXbW7JTA+rX6h2wllSUbALMsH935/QgdVn7NuGhB8=; b=JfoExrgQ8V7j1iEtD74jJ2D7ilKOBiNw2hU9hAxI0h2CUFbBlwUf0CU8jlHDQWsk4J Us2Vx416Hqp+1mqroo27UVP6ydxl3V2hkDK7IIfXzUOJ7k5e32Fg0fOHaNoQz2RfuCWb oIU+gLZqWF4dkcvYsz1DRo6TpYVa9QadFAh9FXjd0HCzytvwsqd0zAlaoZVjfmckOAF0 p2Q8MvOqWPu45mgetmWtENCCfSzF97LCyppodfi/+bYMAbNXR4UoVC5V+li3TIGub9VT I9OKlUDc2oQTHaKxf8uBhCW+4L+uptX5NcEsb4DtdNOBVoyp/A1VIfMjusvQYr/cJqaF bTxA== X-Gm-Message-State: AOJu0YwCqMr37fzqfrKf9TisncXwWdEb4dEAU2F20mvCOrydCDhUjx/D 8OHE4WtsJW4LhtnBQpZTSMgUmw== X-Google-Smtp-Source: AGHT+IER7aDasNv4HryZXs+OqFjdWVOMVvC9oosimk80Dhx9t1V5Xr51sadYHq9bBP2SmlwGRGTGig== X-Received: by 2002:a17:90a:c0f:b0:274:3a86:4c10 with SMTP id 15-20020a17090a0c0f00b002743a864c10mr9217500pjs.29.1695095654352; Mon, 18 Sep 2023 20:54:14 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id 3-20020a17090a034300b00273fc850342sm4000802pjf.20.2023.09.18.20.54.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Sep 2023 20:54:14 -0700 (PDT) From: Anup Patel To: Paolo Bonzini , Atish Patra , Palmer Dabbelt , Paul Walmsley , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Shuah Khan Cc: Andrew Jones , Mayuresh Chitale , devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, Anup Patel Subject: [PATCH 3/7] RISC-V: KVM: Allow XVentanaCondOps extension for Guest/VM Date: Tue, 19 Sep 2023 09:23:39 +0530 Message-Id: <20230919035343.1399389-4-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230919035343.1399389-1-apatel@ventanamicro.com> References: <20230919035343.1399389-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net We extend the KVM ISA extension ONE_REG interface to allow KVM user space to detect and enable XVentanaCondOps extension for Guest/VM. Signed-off-by: Anup Patel --- arch/riscv/include/uapi/asm/kvm.h | 1 + arch/riscv/kvm/vcpu_onereg.c | 2 ++ 2 files changed, 3 insertions(+) diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h index b1baf6f096a3..e030c12c7dfc 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -138,6 +138,7 @@ enum KVM_RISCV_ISA_EXT_ID { KVM_RISCV_ISA_EXT_ZIFENCEI, KVM_RISCV_ISA_EXT_ZIHPM, KVM_RISCV_ISA_EXT_SMSTATEEN, + KVM_RISCV_ISA_EXT_XVENTANACONDOPS, KVM_RISCV_ISA_EXT_MAX, }; diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c index 388599fcf684..17a847a1114b 100644 --- a/arch/riscv/kvm/vcpu_onereg.c +++ b/arch/riscv/kvm/vcpu_onereg.c @@ -40,6 +40,7 @@ static const unsigned long kvm_isa_ext_arr[] = { KVM_ISA_EXT_ARR(SVINVAL), KVM_ISA_EXT_ARR(SVNAPOT), KVM_ISA_EXT_ARR(SVPBMT), + KVM_ISA_EXT_ARR(XVENTANACONDOPS), KVM_ISA_EXT_ARR(ZBA), KVM_ISA_EXT_ARR(ZBB), KVM_ISA_EXT_ARR(ZBS), @@ -89,6 +90,7 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext) case KVM_RISCV_ISA_EXT_SSTC: case KVM_RISCV_ISA_EXT_SVINVAL: case KVM_RISCV_ISA_EXT_SVNAPOT: + case KVM_RISCV_ISA_EXT_XVENTANACONDOPS: case KVM_RISCV_ISA_EXT_ZBA: case KVM_RISCV_ISA_EXT_ZBB: case KVM_RISCV_ISA_EXT_ZBS: From patchwork Tue Sep 19 03:53:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 724488 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B1A1D110B for ; Tue, 19 Sep 2023 03:54:36 +0000 (UTC) Received: from mail-pg1-x532.google.com (mail-pg1-x532.google.com [IPv6:2607:f8b0:4864:20::532]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E1D981AB for ; Mon, 18 Sep 2023 20:54:26 -0700 (PDT) Received: by mail-pg1-x532.google.com with SMTP id 41be03b00d2f7-578b407045bso265425a12.0 for ; Mon, 18 Sep 2023 20:54:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1695095666; x=1695700466; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ZfvmhBSCKy1EtjBZwA/dMnNMj/Sq3SnHobn1iIDa23k=; b=CVlwW+v4ozsvUCXqToXkiNqpHqEKOTWO+P+exSrUP1X9KQCS6R6/Q3DW93TDVuvR9O WpaDr553Xt+fufYlNriKSVt8TZB2EG4Vvvh3d1Dp1bCuT2JkB0J7Xd9Q5bD8MSddNqC0 mZ6dH4oO1kozxpFFzcDa9f1szXHHnjmG5ROp5A7qDBawFW8CfMFQ+XU0xdJSmswlW+S5 ymo37x5KAxwqpXQ9iZeqkpUonJXMBWADuMveDVQ15ROA3EV/HvjH/aucEuU10IFfh8T/ 4zmBBKi1MXXWgpteQTLm1nAV3SPihASotfKSkYc+rlvLM442wT/Zq0JhQe1keEZFPno+ ZT0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695095666; x=1695700466; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZfvmhBSCKy1EtjBZwA/dMnNMj/Sq3SnHobn1iIDa23k=; b=lBlnT6hmqP1TGw8LYk9An36AP9Kpl1YoHpiwDrEl+C3EjG+DJQW/uS1L+qje+R1oPp Q6qAK9GqqZ07KpkzjWQBjarDNhz5vM6E+CcuDwKjcnTAXjBhKCVl6pYWv4nB+x+wCsm6 d0jEitRgEb2HF2mcNBo5DFKXmpuec61DE/e88mLC7skZ8e+cucIVpAZPlzxb3v57GktY uXswfBb+iYQZtwbLnODeVn2koR/cGbDsNNsR4uSYha53sy9IsymAiEsLyyYGBDfreJwI V5VEP6wBObJFwYOHuxbLta9iDhdYh0LdBBwhW0OlRsnOStUIjqVu9EvwB3ZyVyjB/v8F PQWw== X-Gm-Message-State: AOJu0YzCbbmqJ0FU40Lm8ONf8jeq2T0Nbd9qh64PJUXbnQPL/W1+X6Er iQHCCG5zFdakwszZO8IJnBM3OA== X-Google-Smtp-Source: AGHT+IFWOuCFmAAL9BpJh0Ux9/VFPokWaaBfZihC75JvOcaJslymvgs6sdUGv9tDlKZqw185zQ04Vw== X-Received: by 2002:a17:90a:4e81:b0:262:f449:4497 with SMTP id o1-20020a17090a4e8100b00262f4494497mr9895737pjh.2.1695095666229; Mon, 18 Sep 2023 20:54:26 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id 3-20020a17090a034300b00273fc850342sm4000802pjf.20.2023.09.18.20.54.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Sep 2023 20:54:25 -0700 (PDT) From: Anup Patel To: Paolo Bonzini , Atish Patra , Palmer Dabbelt , Paul Walmsley , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Shuah Khan Cc: Andrew Jones , Mayuresh Chitale , devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, Anup Patel Subject: [PATCH 5/7] KVM: riscv: selftests: Add senvcfg register to get-reg-list test Date: Tue, 19 Sep 2023 09:23:41 +0530 Message-Id: <20230919035343.1399389-6-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230919035343.1399389-1-apatel@ventanamicro.com> References: <20230919035343.1399389-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net We have a new senvcfg register in the general CSR ONE_REG interface so let us add it to get-reg-list test. Signed-off-by: Anup Patel --- tools/testing/selftests/kvm/riscv/get-reg-list.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c index 85907c86b835..0928c35470ae 100644 --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c @@ -209,6 +209,8 @@ static const char *general_csr_id_to_str(__u64 reg_off) return RISCV_CSR_GENERAL(satp); case KVM_REG_RISCV_CSR_REG(scounteren): return RISCV_CSR_GENERAL(scounteren); + case KVM_REG_RISCV_CSR_REG(senvcfg): + return RISCV_CSR_GENERAL(senvcfg); } TEST_FAIL("Unknown general csr reg: 0x%llx", reg_off); @@ -532,6 +534,7 @@ static __u64 base_regs[] = { KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(sip), KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(satp), KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(scounteren), + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(senvcfg), KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_RISCV_TIMER_REG(frequency), KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_RISCV_TIMER_REG(time), KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_RISCV_TIMER_REG(compare), From patchwork Tue Sep 19 03:53:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 724487 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9598331A9C for ; Tue, 19 Sep 2023 03:54:57 +0000 (UTC) Received: from mail-pj1-x1031.google.com (mail-pj1-x1031.google.com [IPv6:2607:f8b0:4864:20::1031]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A9A87CFE for ; Mon, 18 Sep 2023 20:54:40 -0700 (PDT) Received: by mail-pj1-x1031.google.com with SMTP id 98e67ed59e1d1-274928c74b0so3167845a91.3 for ; Mon, 18 Sep 2023 20:54:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1695095679; x=1695700479; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=F8aNxqk/Fio7uz5AQcGG5V7O/R7HCZdIqvfTNBjv5gM=; b=R53BJzpDqdwq9Yn3bRu7+0S41nDwtisEOCg6gjrqHqMHW/D42vT3W7QBctOF27UdL6 28F/YKFsFRiz5erDk+2Xfq9TT/fxF7gkllP2zhr2Tbh2Cte4DXMBz9NzdIDZ2nBwhDgf rSk7knd9TFK0h6fvHeGEkTVdNwS6ohLqE87n3K21ynnN47gcRbBtKUImSXWjrAK/+a3L PLZO/r1B5x/Ffk12pusWO8Y39GTLks0r5+j+T+/5K71XCdGmgD4tw5X6vEo27ZI9riIs EWWv5KoOd+tNasPpgtFLTVrAaZk2+HFF0ZHpikj5TbC8ig1/GUlogT84NcmlAP0zMwRR 8wqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695095679; x=1695700479; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=F8aNxqk/Fio7uz5AQcGG5V7O/R7HCZdIqvfTNBjv5gM=; b=onPQV9enJ7AAO8gqtl+9cEHmSSWB15UEPjI5HdfT1nk1VQ+pjPUmivWm8unEAEsJij s8iTtLmydZdM/cHHkwIQyng1EcOMlcrOuVb5HEkMw0KNuwHDGT35n6R/5dLmf9C675zO IPhaHPpZfgXnt69QL2ZZCFZTYsoM3UMEMUAflDra3Hqw22pAOQl/lu2/V8ZcbkFnwdOq wVw/HqoCMlsItSwcJIP8oQMQ0lKTtWzOXXS2Kl4R84RRPC5cXsLs6wv0EYA1Yi128bAs nIIsPgEyCYBwb0slWT4PaY8hZSmnu7b+dlBZxJaRaDSl7L5mZ/GGbppOkl8cdgSmFxRi aukg== X-Gm-Message-State: AOJu0YwFXnVNOHBSYbIUXsKhCyKo2yWOgAO9CtfF2agM/AxBi5wizjdg lc7JFGXd6TTPviNjCTXpsaiVug== X-Google-Smtp-Source: AGHT+IEiYF6goUFLSD0qNIvl8mZDssbeUh0IABgs8W5u4Ug/kGe3A2Yvna7zl18arf+5N6NDqFqfWQ== X-Received: by 2002:a17:90a:5901:b0:268:b7a2:62e8 with SMTP id k1-20020a17090a590100b00268b7a262e8mr10313711pji.7.1695095678874; Mon, 18 Sep 2023 20:54:38 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id 3-20020a17090a034300b00273fc850342sm4000802pjf.20.2023.09.18.20.54.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Sep 2023 20:54:38 -0700 (PDT) From: Anup Patel To: Paolo Bonzini , Atish Patra , Palmer Dabbelt , Paul Walmsley , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Shuah Khan Cc: Andrew Jones , Mayuresh Chitale , devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, Anup Patel Subject: [PATCH 7/7] KVM: riscv: selftests: Add condops extensions to get-reg-list test Date: Tue, 19 Sep 2023 09:23:43 +0530 Message-Id: <20230919035343.1399389-8-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230919035343.1399389-1-apatel@ventanamicro.com> References: <20230919035343.1399389-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net We have a new conditional operations related ISA extensions so let us add these extensions to get-reg-list test. Signed-off-by: Anup Patel --- tools/testing/selftests/kvm/riscv/get-reg-list.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c index 9f464c7996c6..4ad4bf87fa78 100644 --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c @@ -50,6 +50,8 @@ bool filter_reg(__u64 reg) case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZIFENCEI: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZIHPM: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SMSTATEEN: + case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_XVENTANACONDOPS: + case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICOND: return true; /* AIA registers are always available when Ssaia can't be disabled */ case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(siselect): @@ -360,6 +362,8 @@ static const char *isa_ext_id_to_str(__u64 id) "KVM_RISCV_ISA_EXT_ZIFENCEI", "KVM_RISCV_ISA_EXT_ZIHPM", "KVM_RISCV_ISA_EXT_SMSTATEEN", + "KVM_RISCV_ISA_EXT_XVENTANACONDOPS", + "KVM_RISCV_ISA_EXT_ZICOND", }; if (reg_off >= ARRAY_SIZE(kvm_isa_ext_reg_name)) {