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[93.34.89.13]) by smtp.googlemail.com with ESMTPSA id j11-20020a05600c42cb00b0040652e8ca13sm692074wme.43.2023.10.13.10.39.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 10:39:02 -0700 (PDT) From: Christian Marangi To: Ilia Lin , Andy Gross , Bjorn Andersson , Konrad Dybcio , "Rafael J. Wysocki" , Viresh Kumar , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , Stephen Boyd , Sricharan Ramabadhran , Christian Marangi , linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 1/4] dt-bindings: cpufreq: qcom-cpufreq-nvmem: Document krait-cpu Date: Fri, 13 Oct 2023 19:38:51 +0200 Message-Id: <20231013173854.7399-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231013173854.7399-1-ansuelsmth@gmail.com> References: <20231013173854.7399-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Document newly introduced operating-points-v2-krait-cpu compatible to the list of accepted compatible for opp-v2-kryo-cpu nodes. Signed-off-by: Christian Marangi --- Changes v6: * Add this patch --- .../devicetree/bindings/cpufreq/qcom-cpufreq-nvmem.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/cpufreq/qcom-cpufreq-nvmem.yaml b/Documentation/devicetree/bindings/cpufreq/qcom-cpufreq-nvmem.yaml index 7391660a25ac..185e014eaa31 100644 --- a/Documentation/devicetree/bindings/cpufreq/qcom-cpufreq-nvmem.yaml +++ b/Documentation/devicetree/bindings/cpufreq/qcom-cpufreq-nvmem.yaml @@ -46,7 +46,9 @@ patternProperties: - if: properties: compatible: - const: operating-points-v2-kryo-cpu + enum: + - operating-points-v2-krait-cpu + - operating-points-v2-kryo-cpu then: $ref: /schemas/opp/opp-v2-kryo-cpu.yaml# From patchwork Fri Oct 13 17:38:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 733440 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8F783224E4 for ; Fri, 13 Oct 2023 17:39:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="kTOptCow" Received: from mail-wm1-x334.google.com (mail-wm1-x334.google.com [IPv6:2a00:1450:4864:20::334]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 65FB0BF; Fri, 13 Oct 2023 10:39:06 -0700 (PDT) Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-40566f8a093so24099465e9.3; Fri, 13 Oct 2023 10:39:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1697218745; x=1697823545; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+HZyxbaZrzegHjjHG1xEeKX3lyEz0S3pL4gqIEs+3eM=; b=kTOptCowLTvTLbvWXqTuxThm0Uatrwiyz8+h0appWlUFxmJ9DzXvNNxnML+PiHvJbn +Uk9FGNmxhOnIBEgXcM/GL2vyoFw0vWouRVJ0cBw6tHz5SIuXPCoNANuo6x+hKxrelzp NamxFOkeUGHFKzaooqjh/dLE+h776ZN39p3+GcvGA+/eDlUBEEuviPwOrbqhcEM1k2ln q94H/fa0PEEu+1wdoc7hNwa3hGZZxVxvUx7P3MmFuGhRT4HXRTrei1ecrGOVgnQ5NQtl AkRmNChoghwdbiv+G7c/azqEE2R+ZF8lfnMYzea5BN2AUbo6evi0UiX3qKR+uNnomWfl PGvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697218745; x=1697823545; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+HZyxbaZrzegHjjHG1xEeKX3lyEz0S3pL4gqIEs+3eM=; b=JOANor6a+MBVR1TxL17+OHksdKndul6Yj/l4A89qSH+aQoTLdh7dHccAPXQyM1o2jf W399dE61paJWd3ZhKsmSOhLPiNt+y1AB98wz2Sg3CscLGPkMDuBkGoOwgOdF8BFUo7cy B6Wwq6zK0AkuPCszjwrs4XfOVAHpiHydE1BSx+71mXMkDuRLyPO7t6isHwEDD91qRsyM irYHqBTWGlA2NwrVf7zHQZfBTtpsxLrBX4AOV7fyjRbLsFigGYiERZ/qn1QY5dQIS4az 1I74+A9ttPKXPO/3I55pJTYNtKz5STQEcD1EfYurnudrYdSxy+YxAqomVrDcVa1ICZik aACg== X-Gm-Message-State: AOJu0YxLWKNOPc8+/N1gaIYzdCFmLCTcJIbCrqkvWLsG6WRKgPx4h6uU BUlSNOVmc8xk8VeSUJluiJQ= X-Google-Smtp-Source: AGHT+IHVbVmwZE3/otPzs22R6/X6n7J2gWHh+vwuxdJ3uBEXVrVq5NBgLBHqqIkRGdNnsxGSqo5ulg== X-Received: by 2002:a1c:4b18:0:b0:404:4b6f:d705 with SMTP id y24-20020a1c4b18000000b004044b6fd705mr24771845wma.17.1697218744536; Fri, 13 Oct 2023 10:39:04 -0700 (PDT) Received: from localhost.localdomain (93-34-89-13.ip49.fastwebnet.it. [93.34.89.13]) by smtp.googlemail.com with ESMTPSA id j11-20020a05600c42cb00b0040652e8ca13sm692074wme.43.2023.10.13.10.39.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 10:39:04 -0700 (PDT) From: Christian Marangi To: Ilia Lin , Andy Gross , Bjorn Andersson , Konrad Dybcio , "Rafael J. Wysocki" , Viresh Kumar , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , Stephen Boyd , Sricharan Ramabadhran , Christian Marangi , linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Rob Herring Subject: [PATCH v6 2/4] dt-bindings: opp: opp-v2-kryo-cpu: Document named opp-microvolt property Date: Fri, 13 Oct 2023 19:38:52 +0200 Message-Id: <20231013173854.7399-3-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231013173854.7399-1-ansuelsmth@gmail.com> References: <20231013173854.7399-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Document named opp-microvolt property for opp-v2-kryo-cpu schema. This property is used to declare multiple voltage ranges selected on the different values read from efuses. The selection is done based on the speed pvs values and the named opp-microvolt property is selected by the qcom-cpufreq-nvmem driver. Signed-off-by: Christian Marangi Reviewed-by: Rob Herring --- changes v6: * Rebase on top of dependant series * Fix example to use krait Changes v5: * Fix typo in opp items Changes v4: * Address comments from Rob (meaning of pvs, drop of driver specific info, drop of legacy single voltage OPP, better specify max regulators supported) --- .../bindings/opp/opp-v2-kryo-cpu.yaml | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml b/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml index 316f9c7804e4..fd04d060c1de 100644 --- a/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml +++ b/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml @@ -68,6 +68,12 @@ patternProperties: 6: MSM8996SG, speedbin 2 7-31: unused + Bitmap for IPQ806x SoC: + 0: IPQ8062 + 1: IPQ8064/IPQ8066/IPQ8068 + 2: IPQ8065/IPQ8069 + 3-31: unused + Other platforms use bits directly corresponding to speedbin index. clock-latency-ns: true @@ -262,6 +268,22 @@ examples: }; }; + /* Dummy opp table to give example for named opp-microvolt */ + opp-table-2 { + compatible = "operating-points-v2-krait-cpu"; + nvmem-cells = <&speedbin_efuse>; + + opp-384000000 { + opp-hz = /bits/ 64 <384000000>; + opp-microvolt-speed0-pvs0 = <1000000 950000 1050000>; + opp-microvolt-speed0-pvs1 = <925000 878750 971250>; + opp-microvolt-speed0-pvs2 = <875000 831250 918750>; + opp-microvolt-speed0-pvs3 = <800000 760000 840000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <100000>; + }; + }; + smem { compatible = "qcom,smem"; memory-region = <&smem_mem>; From patchwork Fri Oct 13 17:38:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 734737 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C7918224E4 for ; Fri, 13 Oct 2023 17:39:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="ZXBnr0+l" Received: from mail-wm1-x32d.google.com (mail-wm1-x32d.google.com [IPv6:2a00:1450:4864:20::32d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BEBF4A9; Fri, 13 Oct 2023 10:39:07 -0700 (PDT) Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-405524e6768so23952595e9.2; Fri, 13 Oct 2023 10:39:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1697218746; x=1697823546; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Q2snCKtjMSm4tN6lk7reehS7y1VLVQECFr7QjjH/bic=; b=ZXBnr0+lOlZiFifQYucLsPFAbDbtXMxsMLWh0laXR2carz8L+REriUcFIDyXD65FXo 2UEwlnJpZZ0lYDr8ogXT9WP6JqlmrK7JR1evcRP9b4TxubpgDvLVYnuLjpUxdSBHEz/K SYTXlKbJqHnrln7/6WqgjL1dREolPE/1Wm408k3agvX7yPrBB0s6yvQ/It48iUtoqhqi lOUykdBA5VfQEsetxl+ApTJIKKZebgVsVjDqzWcOVBvCASp+LDI8Z1u9WYGQzk+0ce1M lCMuJXc2qfUnYNuKdvNunYyGZztlOtHgG4wYIPqf/qKVDVQHvr2psWL1PqiViO4lii8n i2PQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697218746; x=1697823546; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Q2snCKtjMSm4tN6lk7reehS7y1VLVQECFr7QjjH/bic=; b=DH/xIr0s5KzDjYoVss3XuLUXvuaA/VCTUgHVb33D/dLizGEfuNOaeM4OAquOyaqWFL pnoU3p6bb/DEnNXSORVbByZaQKwVMqgkXam5RNrCnQ014krJv5akMQthjsSRanl4HsGs JFApSE7m7Dj6d1FIElH3QyL22QpAu50dEMPmIRLWgs18TV6YqJBMl9bpWXijObAKIP9g ADdmWQqDw4btGhGR7NoqiTZLt+W3mo6P5R3Yzbiohs1ZtoAYYHPRAucj68keZ9kfR0Sj gSGhD6oi51jb+AQrHAUYy7cwzbAzd9ZWMc35h6lRp6xqyECZNKV87ARrH53bewoCje6U 30lA== X-Gm-Message-State: AOJu0YzbbNw411i8odODHaMHruCN6z++d0+3PxpJ4knhNISzc4ReAWGK fbQXG2M/rzO5FJ8TfzP+tKA= X-Google-Smtp-Source: AGHT+IGOqy/1x7vrK61QVKQRHol8PeNRBAWftt4uCqXFWZyCvgZgCZxGec86TjhBdB93+cKNOfMB3w== X-Received: by 2002:a5d:4204:0:b0:32d:7efc:7e1f with SMTP id n4-20020a5d4204000000b0032d7efc7e1fmr8043939wrq.71.1697218745914; Fri, 13 Oct 2023 10:39:05 -0700 (PDT) Received: from localhost.localdomain (93-34-89-13.ip49.fastwebnet.it. [93.34.89.13]) by smtp.googlemail.com with ESMTPSA id j11-20020a05600c42cb00b0040652e8ca13sm692074wme.43.2023.10.13.10.39.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 10:39:05 -0700 (PDT) From: Christian Marangi To: Ilia Lin , Andy Gross , Bjorn Andersson , Konrad Dybcio , "Rafael J. Wysocki" , Viresh Kumar , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , Stephen Boyd , Sricharan Ramabadhran , Christian Marangi , linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 3/4] cpufreq: qcom-nvmem: add support for IPQ8064 Date: Fri, 13 Oct 2023 19:38:53 +0200 Message-Id: <20231013173854.7399-4-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231013173854.7399-1-ansuelsmth@gmail.com> References: <20231013173854.7399-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net IPQ8064 comes in 3 families: * IPQ8062 up to 1.0GHz * IPQ8064/IPQ8066/IPQ8068 up to 1.4GHz * IPQ8065/IPQ8069 up to 1.7Ghz So, in order to be able to support one OPP table, add support for IPQ8064 family based of SMEM SoC ID-s and correctly set the version so opp-supported-hw can be correctly used. Bit are set with the following logic: * IPQ8062 BIT 0 * IPQ8064/IPQ8066/IPQ8068 BIT 1 * IPQ8065/IPQ8069 BIT 2 speed is never fused, only pvs values are fused. IPQ806x SoC doesn't have pvs_version so we drop and we use the new pattern: opp-microvolt-speed0-pvs Example: - for ipq8062 psv2 opp-microvolt-speed0-pvs2 = < 925000 878750 971250> Fixes: a8811ec764f9 ("cpufreq: qcom: Add support for krait based socs") Signed-off-by: Christian Marangi --- Changes v6: * Rebase on top of dependant series * Fix leaking speedbin nvmem * Fix format_a function to follow new functions * Improve snprintf as suggested from Konrad Changes v5: * Fix leaking speedbin nvmem Changes in v3: * Use enum for SoC version * Dont evaluate speed as its not fused, only pvs Changes in v2: * Include IPQ8064 support --- drivers/cpufreq/qcom-cpufreq-nvmem.c | 67 +++++++++++++++++++++++++++- 1 file changed, 66 insertions(+), 1 deletion(-) diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c index 6b54a674e9ea..eaeff14bbc75 100644 --- a/drivers/cpufreq/qcom-cpufreq-nvmem.c +++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c @@ -32,6 +32,12 @@ #include +enum ipq806x_versions { + IPQ8062_VERSION = 0, + IPQ8064_VERSION, + IPQ8065_VERSION, +}; + struct qcom_cpufreq_drv; struct qcom_cpufreq_match_data { @@ -205,6 +211,61 @@ static int qcom_cpufreq_krait_name_version(struct device *cpu_dev, return ret; } +static int qcom_cpufreq_ipq8064_name_version(struct device *cpu_dev, + struct nvmem_cell *speedbin_nvmem, + char **pvs_name, + struct qcom_cpufreq_drv *drv) +{ + int speed = 0, pvs = 0; + int msm_id, ret = 0; + u8 *speedbin; + size_t len; + + speedbin = nvmem_cell_read(speedbin_nvmem, &len); + if (IS_ERR(speedbin)) + return PTR_ERR(speedbin); + + if (len != 4) { + dev_err(cpu_dev, "Unable to read nvmem data. Defaulting to 0!\n"); + ret = -ENODEV; + goto exit; + } + + get_krait_bin_format_a(cpu_dev, &speed, &pvs, speedbin); + + ret = qcom_smem_get_soc_id(&msm_id); + if (ret) + goto exit; + + switch (msm_id) { + case QCOM_ID_IPQ8062: + drv->versions = BIT(IPQ8062_VERSION); + break; + case QCOM_ID_IPQ8064: + case QCOM_ID_IPQ8066: + case QCOM_ID_IPQ8068: + drv->versions = BIT(IPQ8064_VERSION); + break; + case QCOM_ID_IPQ8065: + case QCOM_ID_IPQ8069: + drv->versions = BIT(IPQ8065_VERSION); + break; + default: + dev_err(cpu_dev, + "SoC ID %u is not part of IPQ8064 family, limiting to 1.0GHz!\n", + msm_id); + drv->versions = BIT(IPQ8062_VERSION); + break; + } + + /* IPQ8064 speed is never fused. Only pvs values are fused. */ + snprintf(*pvs_name, sizeof("speed0-pvsXX"), "speed0-pvs%d", pvs); + +exit: + kfree(speedbin); + return ret; +} + static int qcom_cpufreq_apq8064_name_version(struct device *cpu_dev, struct nvmem_cell *speedbin_nvmem, char **pvs_name, @@ -247,6 +308,10 @@ static const struct qcom_cpufreq_match_data match_data_qcs404 = { .genpd_names = qcs404_genpd_names, }; +static const struct qcom_cpufreq_match_data match_data_ipq8064 = { + .get_version = qcom_cpufreq_ipq8064_name_version, +}; + static const char * apq8064_regulator_names[] = { "vdd-core", NULL @@ -405,7 +470,7 @@ static const struct of_device_id qcom_cpufreq_match_list[] __initconst = { { .compatible = "qcom,apq8096", .data = &match_data_kryo }, { .compatible = "qcom,msm8996", .data = &match_data_kryo }, { .compatible = "qcom,qcs404", .data = &match_data_qcs404 }, - { .compatible = "qcom,ipq8064", .data = &match_data_krait }, + { .compatible = "qcom,ipq8064", .data = &match_data_ipq8064 }, { .compatible = "qcom,apq8064", .data = &match_data_apq8064 }, { .compatible = "qcom,msm8974", .data = &match_data_krait }, { .compatible = "qcom,msm8960", .data = &match_data_apq8064 }, From patchwork Fri Oct 13 17:38:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 733439 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 44B30224F2 for ; Fri, 13 Oct 2023 17:39:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="hMKglrNf" Received: from mail-wr1-x42c.google.com (mail-wr1-x42c.google.com [IPv6:2a00:1450:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 255E5BF; Fri, 13 Oct 2023 10:39:09 -0700 (PDT) Received: by mail-wr1-x42c.google.com with SMTP id ffacd0b85a97d-31c5cac3ae2so2145286f8f.3; Fri, 13 Oct 2023 10:39:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1697218747; x=1697823547; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=j92zsh9SBwqH2Fdc6L1hiUwgh6lWWdZdBcoBjn6jH8s=; b=hMKglrNfOapyAW6/MLhAAvlw/MGdL7ufr5kXFfr5wmbjT+A3u/VojcCzeUn28DMcNJ As5BCON/1IVL991yWSQ9MNuJ7+7aXoBdgNWbT0nrCUqJdLRS312sK2v/TC5NdaCNXzA4 OeDshhVSxZSbxrtA6KBKy/IHFCFvJnoaEuZVF427fHjQNWu6mmGEtL7GNA4o1m+Bb4aR yCK8syxKq+2bTRJaVBd7LEBKWb6i/52e93rxz3N6Q3VLLODoPFWyggZwgbEugh06D1jU y+gDb3fV8kHthPFUbFl6540IoZVkWuqOkbmpnrOmdoUG/OrrLn4SgQ4/r5DHImdLMSrz 5hyw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697218747; x=1697823547; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=j92zsh9SBwqH2Fdc6L1hiUwgh6lWWdZdBcoBjn6jH8s=; b=B0NdGpvKx1jRl51mn6gZ9PGKb4ZF/xEP/DzXBoU/LYkIiHr43ZM2iPM01WoGAA7/WD DprOdAHopJs4mvlNMz2L3cV4kbAo5DUlcbvNN3MOBMdQ7sZLylp2mzW0iJ6GdoAYKA5V CbA5N6zy4NH+e0DFMykjQCXOuq1AWUTnY1rpQ7nl7UGafPrJ2ZA+mSt8CAdmW8HDbsOp AEISNBTIDQDQY6GujMlxaUvh6xHJPhH7m14NWDto6ShbFw6IwlHp5t1Bwm2Zhm1w/Abi wA5NoyZDmaIZMsT19k9DcoaIIwhV1yb/ev+5R8DjC63bk3Vcj8/DTR8Tgc4NiLkN/1m5 xEFA== X-Gm-Message-State: AOJu0YyfVbmmOWFl9V844cpi7QgH9OnWfb+LqhXqyX2/Zltc+c67bmx2 dVTsYyZl2Yhg2YLG2waQIyc= X-Google-Smtp-Source: AGHT+IG4ETJjJ8HGBycc3ZzcoZGV+DGc5LxYsbp8ZAUtaxsLQx4ZXnADZ+5W/M1mU8hoomCKwn8Wng== X-Received: by 2002:adf:f30d:0:b0:32d:8942:9ffa with SMTP id i13-20020adff30d000000b0032d89429ffamr6146012wro.23.1697218747447; Fri, 13 Oct 2023 10:39:07 -0700 (PDT) Received: from localhost.localdomain (93-34-89-13.ip49.fastwebnet.it. [93.34.89.13]) by smtp.googlemail.com with ESMTPSA id j11-20020a05600c42cb00b0040652e8ca13sm692074wme.43.2023.10.13.10.39.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 10:39:06 -0700 (PDT) From: Christian Marangi To: Ilia Lin , Andy Gross , Bjorn Andersson , Konrad Dybcio , "Rafael J. Wysocki" , Viresh Kumar , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , Stephen Boyd , Sricharan Ramabadhran , Christian Marangi , linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 4/4] ARM: dts: qcom: ipq8064: Add CPU OPP table Date: Fri, 13 Oct 2023 19:38:54 +0200 Message-Id: <20231013173854.7399-5-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231013173854.7399-1-ansuelsmth@gmail.com> References: <20231013173854.7399-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Add CPU OPP table for IPQ8062, IPQ8064 and IPQ8065 SoC. Use opp-supported-hw binding to correctly enable and disable the frequency as IPQ8062 supports up to 1.0Ghz, IPQ8064 supports up to 1.4GHz with 1.2GHz as an additional frequency and IPQ8065 supports 1.7GHZ but doesn't have 1.2GHZ frequency and has to be disabled. Signed-off-by: Christian Marangi --- Changes v6: * Use new krait compatible Changes v4: * Readd OPP patch for IPQ8064 --- arch/arm/boot/dts/qcom/qcom-ipq8062.dtsi | 30 +++++++++++ arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi | 67 ++++++++++++++++++++++++ arch/arm/boot/dts/qcom/qcom-ipq8065.dtsi | 65 +++++++++++++++++++++++ 3 files changed, 162 insertions(+) diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8062.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8062.dtsi index 5d3ebd3e2e51..72d9782c3d6f 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq8062.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq8062.dtsi @@ -6,3 +6,33 @@ / { model = "Qualcomm Technologies, Inc. IPQ8062"; compatible = "qcom,ipq8062", "qcom,ipq8064"; }; + +&opp_table_cpu { + opp-384000000 { + opp-microvolt-speed0-pvs0 = <1000000 950000 1050000>; + opp-microvolt-speed0-pvs1 = <925000 878750 971250>; + opp-microvolt-speed0-pvs2 = <875000 831250 918750>; + opp-microvolt-speed0-pvs3 = <800000 760000 840000>; + }; + + opp-600000000 { + opp-microvolt-speed0-pvs0 = <1050000 997500 1102500>; + opp-microvolt-speed0-pvs1 = <975000 926250 1023750>; + opp-microvolt-speed0-pvs2 = <925000 878750 971250>; + opp-microvolt-speed0-pvs3 = <850000 807500 892500>; + }; + + opp-800000000 { + opp-microvolt-speed0-pvs0 = <1100000 1045000 1155000>; + opp-microvolt-speed0-pvs1 = <1025000 973750 1076250>; + opp-microvolt-speed0-pvs2 = <995000 945250 1044750>; + opp-microvolt-speed0-pvs3 = <900000 855000 945000>; + }; + + opp-1000000000 { + opp-microvolt-speed0-pvs0 = <1150000 1092500 1207500>; + opp-microvolt-speed0-pvs1 = <1075000 1021250 1128750>; + opp-microvolt-speed0-pvs2 = <1025000 973750 1076250>; + opp-microvolt-speed0-pvs3 = <950000 902500 997500>; + }; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi index 6198f42f6a9c..54699472f187 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi @@ -30,6 +30,7 @@ cpu0: cpu@0 { next-level-cache = <&L2>; qcom,acc = <&acc0>; qcom,saw = <&saw0>; + operating-points-v2 = <&opp_table_cpu>; }; cpu1: cpu@1 { @@ -40,6 +41,7 @@ cpu1: cpu@1 { next-level-cache = <&L2>; qcom,acc = <&acc1>; qcom,saw = <&saw1>; + operating-points-v2 = <&opp_table_cpu>; }; L2: l2-cache { @@ -49,6 +51,71 @@ L2: l2-cache { }; }; + opp_table_cpu: opp-table-cpu { + compatible = "operating-points-v2-krait-cpu"; + nvmem-cells = <&speedbin_efuse>; + + opp-384000000 { + opp-hz = /bits/ 64 <384000000>; + opp-microvolt-speed0-pvs0 = <1000000 950000 1050000>; + opp-microvolt-speed0-pvs1 = <925000 878750 971250>; + opp-microvolt-speed0-pvs2 = <875000 831250 918750>; + opp-microvolt-speed0-pvs3 = <800000 760000 840000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <100000>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt-speed0-pvs0 = <1050000 997500 1102500>; + opp-microvolt-speed0-pvs1 = <975000 926250 1023750>; + opp-microvolt-speed0-pvs2 = <925000 878750 971250>; + opp-microvolt-speed0-pvs3 = <850000 807500 892500>; + opp-supported-hw = <0x7>; + clock-latency-ns = <100000>; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt-speed0-pvs0 = <1100000 1045000 1155000>; + opp-microvolt-speed0-pvs1 = <1025000 973750 1076250>; + opp-microvolt-speed0-pvs2 = <995000 945250 1044750>; + opp-microvolt-speed0-pvs3 = <900000 855000 945000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <100000>; + }; + + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt-speed0-pvs0 = <1150000 1092500 1207500>; + opp-microvolt-speed0-pvs1 = <1075000 1021250 1128750>; + opp-microvolt-speed0-pvs2 = <1025000 973750 1076250>; + opp-microvolt-speed0-pvs3 = <950000 902500 997500>; + opp-supported-hw = <0x7>; + clock-latency-ns = <100000>; + }; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt-speed0-pvs0 = <1200000 1140000 1260000>; + opp-microvolt-speed0-pvs1 = <1125000 1068750 1181250>; + opp-microvolt-speed0-pvs2 = <1075000 1021250 1128750>; + opp-microvolt-speed0-pvs3 = <1000000 950000 1050000>; + opp-supported-hw = <0x2>; + clock-latency-ns = <100000>; + }; + + opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-microvolt-speed0-pvs0 = <1250000 1187500 1312500>; + opp-microvolt-speed0-pvs1 = <1175000 1116250 1233750>; + opp-microvolt-speed0-pvs2 = <1125000 1068750 1181250>; + opp-microvolt-speed0-pvs3 = <1050000 997500 1102500>; + opp-supported-hw = <0x6>; + clock-latency-ns = <100000>; + }; + }; + thermal-zones { sensor0-thermal { polling-delay-passive = <0>; diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8065.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8065.dtsi index ea49f6cc416d..d9ead31b897b 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq8065.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq8065.dtsi @@ -6,3 +6,68 @@ / { model = "Qualcomm Technologies, Inc. IPQ8065"; compatible = "qcom,ipq8065", "qcom,ipq8064"; }; + +&opp_table_cpu { + opp-384000000 { + opp-microvolt-speed0-pvs0 = <975000 926250 1023750>; + opp-microvolt-speed0-pvs1 = <950000 902500 997500>; + opp-microvolt-speed0-pvs2 = <925000 878750 971250>; + opp-microvolt-speed0-pvs3 = <900000 855000 945000>; + opp-microvolt-speed0-pvs4 = <875000 831250 918750>; + opp-microvolt-speed0-pvs5 = <825000 783750 866250>; + opp-microvolt-speed0-pvs6 = <775000 736250 813750>; + }; + + opp-600000000 { + opp-microvolt-speed0-pvs0 = <1000000 950000 1050000>; + opp-microvolt-speed0-pvs1 = <975000 926250 1023750>; + opp-microvolt-speed0-pvs2 = <950000 902500 997500>; + opp-microvolt-speed0-pvs3 = <925000 878750 971250>; + opp-microvolt-speed0-pvs4 = <900000 855000 945000>; + opp-microvolt-speed0-pvs5 = <850000 807500 892500>; + opp-microvolt-speed0-pvs6 = <800000 760000 840000>; + }; + + opp-800000000 { + opp-microvolt-speed0-pvs0 = <1050000 997500 1102500>; + opp-microvolt-speed0-pvs1 = <1025000 973750 1076250>; + opp-microvolt-speed0-pvs2 = <1000000 950000 1050000>; + opp-microvolt-speed0-pvs3 = <975000 926250 1023750>; + opp-microvolt-speed0-pvs4 = <950000 902500 997500>; + opp-microvolt-speed0-pvs5 = <900000 855000 945000>; + opp-microvolt-speed0-pvs6 = <850000 807500 892500>; + }; + + opp-1000000000 { + opp-microvolt-speed0-pvs0 = <1100000 1045000 1155000>; + opp-microvolt-speed0-pvs1 = <1075000 1021250 1128750>; + opp-microvolt-speed0-pvs2 = <1050000 997500 1102500>; + opp-microvolt-speed0-pvs3 = <1025000 973750 1076250>; + opp-microvolt-speed0-pvs4 = <1000000 950000 1050000>; + opp-microvolt-speed0-pvs5 = <950000 902500 997500>; + opp-microvolt-speed0-pvs6 = <900000 855000 945000>; + }; + + opp-1400000000 { + opp-microvolt-speed4-pvs0 = <1175000 1116250 1233750>; + opp-microvolt-speed4-pvs1 = <1150000 1092500 1207500>; + opp-microvolt-speed4-pvs2 = <1125000 1068750 1181250>; + opp-microvolt-speed4-pvs3 = <1100000 1045000 1155000>; + opp-microvolt-speed4-pvs4 = <1075000 1021250 1128750>; + opp-microvolt-speed4-pvs5 = <1025000 973750 1076250>; + opp-microvolt-speed4-pvs6 = <975000 926250 1023750>; + }; + + opp-1725000000 { + opp-hz = /bits/ 64 <1725000000>; + opp-microvolt-speed0-pvs0 = <1262500 1199375 1325625>; + opp-microvolt-speed0-pvs1 = <1225000 1163750 1286250>; + opp-microvolt-speed0-pvs2 = <1200000 1140000 1260000>; + opp-microvolt-speed0-pvs3 = <1175000 1116250 1233750>; + opp-microvolt-speed0-pvs4 = <1150000 1092500 1207500>; + opp-microvolt-speed0-pvs5 = <1100000 1045000 1155000>; + opp-microvolt-speed0-pvs6 = <1050000 997500 1102500>; + opp-supported-hw = <0x4>; + clock-latency-ns = <100000>; + }; +};