From patchwork Thu Aug 8 08:59:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "\(Exiting\) Baolin Wang" X-Patchwork-Id: 170784 Delivered-To: patch@linaro.org Received: by 2002:a92:512:0:0:0:0:0 with SMTP id q18csp8279691ile; Thu, 8 Aug 2019 02:00:00 -0700 (PDT) X-Google-Smtp-Source: APXvYqx82UyXMec09GK4SCsfESW0QU1IxhTKTxiC8HH5pAbNBqAeNWBB6i0o61xhBPoFZ/pCsv7w X-Received: by 2002:a17:902:566:: with SMTP id 93mr4553449plf.172.1565254800786; Thu, 08 Aug 2019 02:00:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1565254800; cv=none; d=google.com; s=arc-20160816; b=cBIA1nQblCOW5l3UC1ekW5IkNE+13DhPo5T2W6h2o2fgzB37VWKBIYboPWj5Ec22yt r/qKy8sg3fqjEJHvc0wfPHcov1Tx+YRUG+ZgfjuyszMi6w1PLJH5WS3XEiwes14e0GsT rl9KAYtJRnSX+GtoDXlDMsBKzjytcGodNMRvcm9lN3Jh89ZyIx+qvO9USE6NK5Pd1+7L XFj84IP+BRKr07C20LD2Zds4CimlJB3Ft0pnyA3EIEDBXN1+/iJjaMhHrRynmleteiet O232Pf6Bm//wAQSUOghXB8vWMmFxnNTpMsQK1W5Tuegn4y2pSHJc/RRwbWRmDGCto39G thww== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from :dkim-signature; bh=Lo/QmGwP2FIQuGb+OYi0VLHnS1pK1k0BxPE3TRsd2iE=; b=cj8qB6fRDv6dtt/Eh5JV7kJWyRaWCf4p9t8b0DN+7zqiiFJefS4gJUc7cHc8FOlZat g1b24KV1R/VW5OCFhy5RHi7iXKI2XlCr8c/tfA1q0pRZOq50vzK93fqUAOyvi0dsYtAw XWNDGA7hq5FRBOZetWvittbCifarCJM0R6AmmMXkuRqNdNaPEufmVtOfieocFh7jkyIc r1Q/5RY1D79e5qWfF6gk7LB9vbMiqtNjZ63eQR7rYCKlogLoHuFgacq1LcL05VLda+JY 4OjXeKQVsOnbK8M6t1Aywci58A+ohYoZpYAeq1sk64HiD1YmjzhRs7mGZv3fURMqkJCa pV6A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="GqIx/AFQ"; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id o19si37767073pgv.497.2019.08.08.02.00.00; Thu, 08 Aug 2019 02:00:00 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="GqIx/AFQ"; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731178AbfHHI77 (ORCPT + 8 others); Thu, 8 Aug 2019 04:59:59 -0400 Received: from mail-pf1-f193.google.com ([209.85.210.193]:42783 "EHLO mail-pf1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730747AbfHHI77 (ORCPT ); Thu, 8 Aug 2019 04:59:59 -0400 Received: by mail-pf1-f193.google.com with SMTP id q10so43715641pff.9 for ; Thu, 08 Aug 2019 01:59:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=Lo/QmGwP2FIQuGb+OYi0VLHnS1pK1k0BxPE3TRsd2iE=; b=GqIx/AFQB7P1U45E89hpLBVv+3HGsvfUpY9UjDWnEW5YG+ZCcVIe8tPIm+j776p28A Odye8IaM8yvPGIyy8FDrmiAQmBenGBScVxBnPWXKMGJavrBInN45PU+gdj0OCt9fX69b qDR/72w5KxUTcbj0DvdxwJE3K0E6s7RtNmUbmElV8NmqqxG56E4IGCQaPJb2WDnAE73D G57arIvCeLvmJu7LjA9o1OnPwC5W6lCiQsTwmYoNVRPcLYZDoKzTYSWwBI2V6RByphQD J3mv8k6Lp3jxTflA9a2v+OV6CbTB8acoJy8DUd0gMYQdIYxTzTdVVATVfGVrNUaAyODC 18QA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=Lo/QmGwP2FIQuGb+OYi0VLHnS1pK1k0BxPE3TRsd2iE=; b=IFwEoyuACcs4s85jUU/Xx3qPMmfJKQB/AJ8DEHM6D0hLAF0WgEeYcPLyPtx5TzhQrD Uj5VTpCwKGV4imF72kUs5VEu3PCy5ptHkHM2RBQxFJjKbUjyXZ4uILWPkGW43xnuPcoS nhvHQpi0ddltbrhIISyzShggv9L+3VDmvjsfnORo305XOFYDDuoGf0f+rNyFx25SWiOT uCao0AVIkmrKGnlP2Zd5Yl3aq7Talkxz+8lj4nUrQ+HA6wmtPoEUC+3RPhnzM2FyT3lM QKqh0qUpM9YRE/donf6tq9N22HO340hsYUt5v+2aILqARMDlq+dlZCCf+qB8STxsBR1D 4jMg== X-Gm-Message-State: APjAAAUbBR2xL5t5QNHdTI0DNz0NibnHBVq8XsM/sn5PuBIaOpHqRAXq JP4lEN4IPkV6iIpTdLQR/xZmaQ== X-Received: by 2002:a63:e54f:: with SMTP id z15mr11757419pgj.4.1565254798652; Thu, 08 Aug 2019 01:59:58 -0700 (PDT) Received: from baolinwangubtpc.spreadtrum.com ([117.18.48.82]) by smtp.gmail.com with ESMTPSA id b24sm21716254pgw.66.2019.08.08.01.59.55 (version=TLS1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 08 Aug 2019 01:59:58 -0700 (PDT) From: Baolin Wang To: thierry.reding@gmail.com, robh+dt@kernel.org Cc: mark.rutland@arm.com, orsonzhai@gmail.com, zhang.lyra@gmail.com, baolin.wang@linaro.org, vincent.guittot@linaro.org, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/2] dt-bindings: pwm: sprd: Add Spreadtrum PWM documentation Date: Thu, 8 Aug 2019 16:59:38 +0800 Message-Id: <6a38a3655bc8100764d85cb04dea5c2546a311e1.1565168564.git.baolin.wang@linaro.org> X-Mailer: git-send-email 1.7.9.5 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add Spreadtrum PWM controller documentation. Signed-off-by: Baolin Wang --- Documentation/devicetree/bindings/pwm/pwm-sprd.txt | 31 ++++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/pwm-sprd.txt -- 1.7.9.5 diff --git a/Documentation/devicetree/bindings/pwm/pwm-sprd.txt b/Documentation/devicetree/bindings/pwm/pwm-sprd.txt new file mode 100644 index 0000000..e8e0d5a --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/pwm-sprd.txt @@ -0,0 +1,31 @@ +Spreadtrum PWM controller + +Spreadtrum SoCs PWM controller provides 4 PWM channels. + +Required porperties: +- compatible : Should be "sprd,ums512-pwm". +- reg: Physical base address and length of the controller's registers. +- clocks: The phandle and specifier referencing the controller's clocks. +- clock-names: Should contain following entries: + "source": for PWM source (parent) clock. + "pwmn": used to derive the functional clock for PWM channel n (n range: 0 ~ 3). + "enablen": for PWM channel n enable clock (n range: 0 ~ 3). +- #pwm-cells: Should be 2. See pwm.txt in this directory for a description of + the cells format. + +Example: + pwms: pwm@32260000 { + compatible = "sprd,ums512-pwm"; + reg = <0 0x32260000 0 0x10000>; + clock-names = "source", + "pwm0", "enable0", + "pwm1", "enable1", + "pwm2", "enable2", + "pwm3", "enable3"; + clocks = <&ext_26m>, + <&aon_clk CLK_PWM0>, <&aonapb_gate CLK_PWM0_EB>, + <&aon_clk CLK_PWM1>, <&aonapb_gate CLK_PWM1_EB>, + <&aon_clk CLK_PWM2>, <&aonapb_gate CLK_PWM2_EB>, + <&aon_clk CLK_PWM3>, <&aonapb_gate CLK_PWM3_EB>; + #pwm-cells = <2>; + };