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[104.151.91.181]) by smtp.gmail.com with ESMTPSA id l18-20020a056402029200b0053443c8fd90sm15021814edv.24.2023.10.16.01.44.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Oct 2023 01:44:02 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, Jagadeesh Kona Subject: [PATCH 1/2] clk: qcom: gpucc-sm8550: switch to clk_lucid_ole_pll_configure Date: Mon, 16 Oct 2023 11:43:55 +0300 Message-ID: <20231016084356.1301854-1-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.42.0 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Instead of manually specifying the RINGOSC_CAL_L and CAL_L values in the alpha_pll_config.l field, use the proper clk_lucid_ole_pll_configure() function to configure the PLL. Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/gpucc-sm8550.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/clk/qcom/gpucc-sm8550.c b/drivers/clk/qcom/gpucc-sm8550.c index 775e0b931923..420dcb27b47d 100644 --- a/drivers/clk/qcom/gpucc-sm8550.c +++ b/drivers/clk/qcom/gpucc-sm8550.c @@ -39,8 +39,7 @@ static const struct pll_vco lucid_ole_vco[] = { }; static const struct alpha_pll_config gpu_cc_pll0_config = { - /* .l includes RINGOSC_CAL_L_VAL, CAL_L_VAL, L_VAL fields */ - .l = 0x4444000d, + .l = 0x0d, .alpha = 0x0, .config_ctl_val = 0x20485699, .config_ctl_hi_val = 0x00182261, @@ -71,8 +70,7 @@ static struct clk_alpha_pll gpu_cc_pll0 = { }; static const struct alpha_pll_config gpu_cc_pll1_config = { - /* .l includes RINGOSC_CAL_L_VAL, CAL_L_VAL, L_VAL fields */ - .l = 0x44440016, + .l = 0x16, .alpha = 0xeaaa, .config_ctl_val = 0x20485699, .config_ctl_hi_val = 0x00182261, @@ -574,8 +572,8 @@ static int gpu_cc_sm8550_probe(struct platform_device *pdev) if (IS_ERR(regmap)) return PTR_ERR(regmap); - clk_lucid_evo_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config); - clk_lucid_evo_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); + clk_lucid_ole_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config); + clk_lucid_ole_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); /* * Keep clocks always enabled: