From patchwork Tue Aug 13 13:46:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "\(Exiting\) Baolin Wang" X-Patchwork-Id: 171196 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp929707ily; Tue, 13 Aug 2019 06:46:55 -0700 (PDT) X-Google-Smtp-Source: APXvYqzwWGgSrMlTOzGYza+zSLiNtoM+5dMBxu2VR9XhnaRgXn7xtTM+qcPjEu2Ie2zvdfWkmgri X-Received: by 2002:a63:de4c:: with SMTP id y12mr608571pgi.264.1565704014824; Tue, 13 Aug 2019 06:46:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1565704014; cv=none; d=google.com; s=arc-20160816; b=VCsD9gs/ngZG9TZXLdt5YH5ketQWjdysRfa8goeXkK6QWGbTXiZG8HZgtJYTFeUv5/ WU/l2K5wS4QB6m2uNpw1bg+p7MYBQmeMQ8x6AfsIuSV0P1FfZEwXscIPPfll3LpwV+8C B5YNh/hOePabDw6cm1y2YZNEYiyYJYMUhR6+C0yRjs0wNOOZ462if73xXlQppKFpS/+c FTWunH9U5ryUEWfdn9dkhdGFLt1dcPx3rOk5cC9177InAQzTnu72shygK9Vty+1AMTws Lmqyld2PU9cAgnyXA7dJlw8AzEldGFv3lZTO350wrE8MtGSYj6ZlYPg5wMfjPSVEVXM1 YRaA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from :dkim-signature; bh=cHdPS6LfhQ0chTOP4Jgo7vkl2dbGuOfOJrvTrwDU67U=; b=Vs+lZqqNeXMaJbH7wXFgPYs90poy991j2FXOhtiWWXhR/wniC5yZiUP4Hxqnu9bcnr nU+o8rDO3EGbodUPL6cqirgDwsjPvWnzJlV/f81PFeKaCy1XR2RIEHuFKuenxiW0qSNC wFppKqelKR2G7HRGclSZ9lBmGCKGx1jBr5H7ixJ6afhbg2ZfUNIOqVCqdHG8YqDLacka MuXPy3xstULKpzD6lYAhS2B7Ok3yB8wkdpjwtiOG28nGdCE7v+/GMXyKGUgTC1EWiFb7 57DFHmFtRZ0pedKHcuThCwTmhXEvGHAY0x8c8AftsrZAHQOD1CV3hxTgCHYH/UPe6ShD kI3w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="zBgk4VX/"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id j6si69330014pgb.206.2019.08.13.06.46.54; Tue, 13 Aug 2019 06:46:54 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="zBgk4VX/"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729226AbfHMNqx (ORCPT + 28 others); Tue, 13 Aug 2019 09:46:53 -0400 Received: from mail-pg1-f194.google.com ([209.85.215.194]:36851 "EHLO mail-pg1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729117AbfHMNqw (ORCPT ); Tue, 13 Aug 2019 09:46:52 -0400 Received: by mail-pg1-f194.google.com with SMTP id l21so51287094pgm.3 for ; Tue, 13 Aug 2019 06:46:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=cHdPS6LfhQ0chTOP4Jgo7vkl2dbGuOfOJrvTrwDU67U=; b=zBgk4VX//4dk1T3BhqLSAMAWe1tDwqyu9zEyHnfwXMClq8bvZ8KpxxcdahTS+OvPWg ktSqGVOnKCdrrIHvxz8Hk13Ni8Ny9rB/WK/zIh1KCV2gBAcmCmBuVDdhutPw1X3G9FgK 7WRy0jUjeipkxhRvznEl/0FItIb9XI2cwieYWuQ1ZrRLMFKyF30bNXeFo86aVuHSb3OG zZkDx5O4tYbHxVbzfierIdMi1Y1JqhjFQGFfSm7Q6QMRqmJeFEp9CmN3fr9Ugl/fmwcn 23y103lPDsx/v4ScGLYtipqfWh5PNgGbjwRLL9hlMVRPUoEBqMEBTdyZOzAV2YuwWnLF ms9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=cHdPS6LfhQ0chTOP4Jgo7vkl2dbGuOfOJrvTrwDU67U=; b=ogrMSbIyykm4sqNSfPDqKgF8X5z20pYKpByIpMLHRFuBvCbIbCmI60y0pdkH3mwFWl CyPJRSUfp0YnJgqmcAuXgEZr4SQr8IFoWxsrN/oW2zzU+I74QGGGkgn+5XLiJ5bhlDqh JmRiG818ZPoCfMzLNFhHO46mHjx8IDYEFpXp/oj/n6vzzHy2DKb2cxHQEOYrNhoEgtGm n4bjFgkfmBhota2zIsXaCUbwNUxxLfNc/qBHRsQsC0D7l76T4mM2dUcz4yV28ShaKWKn vnWMgxR3P4/m9En12AGPwWuBUuUTTWdqPQIdpFGQwWp2dfXSKKT1EZGgNylsvL+DGKI9 OCAA== X-Gm-Message-State: APjAAAXkoIrmJXGSUKknRw+HSM095C/XvX46UG12yFMG/xuo0V/OzxBs Lx3HVdoSZN+u9d4yWBTC9bFAP3A5WrDXDA== X-Received: by 2002:a63:fe17:: with SMTP id p23mr34436115pgh.103.1565704011820; Tue, 13 Aug 2019 06:46:51 -0700 (PDT) Received: from baolinwangubtpc.spreadtrum.com ([117.18.48.82]) by smtp.gmail.com with ESMTPSA id x67sm114266432pfb.21.2019.08.13.06.46.49 (version=TLS1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 13 Aug 2019 06:46:51 -0700 (PDT) From: Baolin Wang To: thierry.reding@gmail.com, robh+dt@kernel.org Cc: u.kleine-koenig@pengutronix.de, mark.rutland@arm.com, orsonzhai@gmail.com, zhang.lyra@gmail.com, baolin.wang@linaro.org, vincent.guittot@linaro.org, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/2] dt-bindings: pwm: sprd: Add Spreadtrum PWM documentation Date: Tue, 13 Aug 2019 21:46:40 +0800 Message-Id: X-Mailer: git-send-email 1.7.9.5 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add Spreadtrum PWM controller documentation. Signed-off-by: Baolin Wang --- Changes from v1: - Use assigned-clock-parents and assigned-clocks to set PWM clock parent. --- Documentation/devicetree/bindings/pwm/pwm-sprd.txt | 38 ++++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/pwm-sprd.txt -- 1.7.9.5 diff --git a/Documentation/devicetree/bindings/pwm/pwm-sprd.txt b/Documentation/devicetree/bindings/pwm/pwm-sprd.txt new file mode 100644 index 0000000..e6cf312 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/pwm-sprd.txt @@ -0,0 +1,38 @@ +Spreadtrum PWM controller + +Spreadtrum SoCs PWM controller provides 4 PWM channels. + +Required porperties: +- compatible : Should be "sprd,ums512-pwm". +- reg: Physical base address and length of the controller's registers. +- clocks: The phandle and specifier referencing the controller's clocks. +- clock-names: Should contain following entries: + "pwmn": used to derive the functional clock for PWM channel n (n range: 0 ~ 3). + "enablen": for PWM channel n enable clock (n range: 0 ~ 3). +- assigned-clocks: Reference to the PWM clock entroes. +- assigned-clock-parents: The phandle of the parent clock of PWM clock. +- #pwm-cells: Should be 2. See pwm.txt in this directory for a description of + the cells format. + +Example: + pwms: pwm@32260000 { + compatible = "sprd,ums512-pwm"; + reg = <0 0x32260000 0 0x10000>; + clock-names = "pwm0", "enable0", + "pwm1", "enable1", + "pwm2", "enable2", + "pwm3", "enable3"; + clocks = <&aon_clk CLK_PWM0>, <&aonapb_gate CLK_PWM0_EB>, + <&aon_clk CLK_PWM1>, <&aonapb_gate CLK_PWM1_EB>, + <&aon_clk CLK_PWM2>, <&aonapb_gate CLK_PWM2_EB>, + <&aon_clk CLK_PWM3>, <&aonapb_gate CLK_PWM3_EB>; + assigned-clocks = <&aon_clk CLK_PWM0>, + <&aon_clk CLK_PWM1>, + <&aon_clk CLK_PWM2>, + <&aon_clk CLK_PWM3>; + assigned-clock-parents = <&ext_26m>, + <&ext_26m>, + <&ext_26m>, + <&ext_26m>; + #pwm-cells = <2>; + }; From patchwork Tue Aug 13 13:46:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "\(Exiting\) Baolin Wang" X-Patchwork-Id: 171197 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp929780ily; Tue, 13 Aug 2019 06:46:59 -0700 (PDT) X-Google-Smtp-Source: APXvYqznVFS2fjcIQthu5/jUQqDGABrcMvwycMNbHuj1Zv87m4pMB4dPGQ+Ls4D0Ih3WrkNGE4T3 X-Received: by 2002:a17:902:b48c:: with SMTP id y12mr37416818plr.202.1565704018869; Tue, 13 Aug 2019 06:46:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1565704018; cv=none; d=google.com; s=arc-20160816; b=fzYm9ZMW77s20gQEU2bGW1ety3UlSZ+u1kNP4y3iO3W23qmjONK25Yp5Yivm68ONg0 rL79w9uucesb6PsCLuStFhf1AYN6Itv01vtsOWWoEEjdMwLfiRUru1np7r60PFf0is79 JN3i7YrkJEtM/TNqw+lmaPJuB4JVp4z5f7HaGSWAkHA+UTP1/T3yCmabonoHlEtfpDE8 2hF0Q/9r9VG2IzngC+3HET38REM7cGOMBrAKwMi87G0RD1MD0fEHc2bm3zZav2Srjy6G OGscLIEdnmqfXynXtgd4CWWcAUnqFIEyhpOBqFYjC7fRgJHJEwkbXB4QCgsdD5vpr8NT 2bZw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:references :in-reply-to:message-id:date:subject:cc:to:from:dkim-signature; bh=6Y5UWBw0p8ptAHgczcX0XL+vWL0nB66aXZa44FEfPbY=; b=ETb5/lKj8n5d9wizO62rb21QHAQQbjqBz6LfskfCbGRLriytiTM0TRsK/2I0q6Q0vv IGy3/8G793rNsyE9wxD5O6q2Hy3drQIHpsW76ud0/i2wSrXehlBxvtrZGCT99GjKvcHe Kq3Aenyuh2zbWL1SJ0Dj4UliPy5tjLVOL1754avQW0J+YVaEsOgwIwLrQOZY7snMH1qr W09Y63B6Z33RG2e7Z6MXn0Z6ICbDIrVEmh1wWBaHC7QwsYu4HbroYBOpwTzG+KmUPxrw v/SxUO0+hLpxNTSsjwap3MF4Y7Wlph829vdurKFWohtMyWiwyYqo8WPsk9U+sfUoGSjl YqDw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=mRbcdsx8; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Neo Hou Signed-off-by: Baolin Wang --- Changes from v1: - Add depending on HAS_IOMEM. - Rename parameters' names. - Implement .apply() instead of .config(), .enable() and .disable(). - Use NSEC_PER_SEC instead of 1000000000ULL. - Add some comments to make code more readable. - Remove some redundant operation. - Use standard clock properties to set clock parent. - Other coding style optimization. --- drivers/pwm/Kconfig | 11 ++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-sprd.c | 307 ++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 319 insertions(+) create mode 100644 drivers/pwm/pwm-sprd.c -- 1.7.9.5 diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index a7e5751..31dfc88 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -423,6 +423,17 @@ config PWM_SPEAR To compile this driver as a module, choose M here: the module will be called pwm-spear. +config PWM_SPRD + tristate "Spreadtrum PWM support" + depends on ARCH_SPRD || COMPILE_TEST + depends on HAS_IOMEM + help + Generic PWM framework driver for the PWM controller on + Spreadtrum SoCs. + + To compile this driver as a module, choose M here: the module + will be called pwm-sprd. + config PWM_STI tristate "STiH4xx PWM support" depends on ARCH_STI diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 76b555b..26326ad 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -41,6 +41,7 @@ obj-$(CONFIG_PWM_ROCKCHIP) += pwm-rockchip.o obj-$(CONFIG_PWM_SAMSUNG) += pwm-samsung.o obj-$(CONFIG_PWM_SIFIVE) += pwm-sifive.o obj-$(CONFIG_PWM_SPEAR) += pwm-spear.o +obj-$(CONFIG_PWM_SPRD) += pwm-sprd.o obj-$(CONFIG_PWM_STI) += pwm-sti.o obj-$(CONFIG_PWM_STM32) += pwm-stm32.o obj-$(CONFIG_PWM_STM32_LP) += pwm-stm32-lp.o diff --git a/drivers/pwm/pwm-sprd.c b/drivers/pwm/pwm-sprd.c new file mode 100644 index 0000000..067e711 --- /dev/null +++ b/drivers/pwm/pwm-sprd.c @@ -0,0 +1,307 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Spreadtrum Communications Inc. + */ + +#include +#include +#include +#include +#include +#include +#include + +#define SPRD_PWM_PRESCALE 0x0 +#define SPRD_PWM_MOD 0x4 +#define SPRD_PWM_DUTY 0x8 +#define SPRD_PWM_ENABLE 0x18 + +#define SPRD_PWM_MOD_MAX GENMASK(7, 0) +#define SPRD_PWM_DUTY_MSK GENMASK(15, 0) +#define SPRD_PWM_PRESCALE_MSK GENMASK(7, 0) +#define SPRD_PWM_ENABLE_BIT BIT(0) + +#define SPRD_PWM_NUM 4 +#define SPRD_PWM_REGS_SHIFT 5 +#define SPRD_PWM_NUM_CLKS 2 +#define SPRD_PWM_OUTPUT_CLK 1 + +struct sprd_pwm_chn { + struct clk_bulk_data clks[SPRD_PWM_NUM_CLKS]; + u32 clk_rate; +}; + +struct sprd_pwm_chip { + void __iomem *base; + struct device *dev; + struct pwm_chip chip; + int num_pwms; + struct sprd_pwm_chn chn[SPRD_PWM_NUM]; +}; + +/* + * The list of clocks required by PWM channels, and each channel has 2 clocks: + * enable clock and pwm clock. + */ +static const char * const sprd_pwm_clks[] = { + "enable0", "pwm0", + "enable1", "pwm1", + "enable2", "pwm2", + "enable3", "pwm3", +}; + +static u32 sprd_pwm_read(struct sprd_pwm_chip *spc, u32 hwid, u32 reg) +{ + u32 offset = reg + (hwid << SPRD_PWM_REGS_SHIFT); + + return readl_relaxed(spc->base + offset); +} + +static void sprd_pwm_write(struct sprd_pwm_chip *spc, u32 hwid, + u32 reg, u32 val) +{ + u32 offset = reg + (hwid << SPRD_PWM_REGS_SHIFT); + + writel_relaxed(val, spc->base + offset); +} + +static void sprd_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, + struct pwm_state *state) +{ + struct sprd_pwm_chip *spc = + container_of(chip, struct sprd_pwm_chip, chip); + struct sprd_pwm_chn *chn = &spc->chn[pwm->hwpwm]; + u32 val, duty, prescale; + u64 tmp; + int ret; + + /* + * The clocks to PWM channel has to be enabled first before + * reading to the registers. + */ + ret = clk_bulk_prepare_enable(SPRD_PWM_NUM_CLKS, chn->clks); + if (ret) { + dev_err(spc->dev, "failed to enable pwm%u clocks\n", + pwm->hwpwm); + return; + } + + val = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_ENABLE); + if (val & SPRD_PWM_ENABLE_BIT) + state->enabled = true; + else + state->enabled = false; + + /* + * The hardware provides a counter that is feed by the source clock. + * The period length is (PRESCALE + 1) * MOD counter steps. + * The duty cycle length is (PRESCALE + 1) * DUTY counter steps. + * Thus the period_ns and duty_ns calculation formula should be: + * period_ns = NSEC_PER_SEC * (prescale + 1) * mod / clk_rate + * duty_ns = NSEC_PER_SEC * (prescale + 1) * duty / clk_rate + */ + val = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_PRESCALE); + prescale = val & SPRD_PWM_PRESCALE_MSK; + tmp = (prescale + 1) * NSEC_PER_SEC * SPRD_PWM_MOD_MAX; + state->period = DIV_ROUND_CLOSEST_ULL(tmp, chn->clk_rate); + + val = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_DUTY); + duty = val & SPRD_PWM_DUTY_MSK; + tmp = (prescale + 1) * NSEC_PER_SEC * duty; + state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, chn->clk_rate); + + /* Disable PWM clocks if the PWM channel is not in enable state. */ + if (!state->enabled) + clk_bulk_disable_unprepare(SPRD_PWM_NUM_CLKS, chn->clks); +} + +static int sprd_pwm_config(struct sprd_pwm_chip *spc, struct pwm_device *pwm, + int duty_ns, int period_ns) +{ + struct sprd_pwm_chn *chn = &spc->chn[pwm->hwpwm]; + u64 div, tmp; + u32 prescale, duty; + + /* + * The hardware provides a counter that is feed by the source clock. + * The period length is (PRESCALE + 1) * MOD counter steps. + * The duty cycle length is (PRESCALE + 1) * DUTY counter steps. + * + * To keep the maths simple we're always using MOD = SPRD_PWM_MOD_MAX. + * The value for PRESCALE is selected such that the resulting period + * gets the maximal length not bigger than the requested one with the + * given settings (MOD = SPRD_PWM_MOD_MAX and input clock). + */ + duty = duty_ns * SPRD_PWM_MOD_MAX / period_ns; + + tmp = (u64)chn->clk_rate * period_ns; + div = NSEC_PER_SEC * SPRD_PWM_MOD_MAX; + prescale = div64_u64(tmp, div) - 1; + if (prescale > SPRD_PWM_PRESCALE_MSK) + prescale = SPRD_PWM_PRESCALE_MSK; + + /* + * Note: The MOD must be configured before DUTY, and the hardware can + * ensure current running period is completed before changing a new + * configuration to avoid mixed settings. + */ + sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_MOD, SPRD_PWM_MOD_MAX); + sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_DUTY, duty); + sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_PRESCALE, prescale); + + return 0; +} + +static int sprd_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, + struct pwm_state *state) +{ + struct sprd_pwm_chip *spc = + container_of(chip, struct sprd_pwm_chip, chip); + struct sprd_pwm_chn *chn = &spc->chn[pwm->hwpwm]; + struct pwm_state cstate; + int ret; + + pwm_get_state(pwm, &cstate); + + if (state->enabled) { + if (!cstate.enabled) { + /* + * The clocks to PWM channel has to be enabled first + * before writing to the registers. + */ + ret = clk_bulk_prepare_enable(SPRD_PWM_NUM_CLKS, + chn->clks); + if (ret) { + dev_err(spc->dev, + "failed to enable pwm%u clocks\n", + pwm->hwpwm); + return ret; + } + } + + if (state->period != cstate.period || + state->duty_cycle != cstate.duty_cycle) { + ret = sprd_pwm_config(spc, pwm, state->duty_cycle, + state->period); + if (ret) + return ret; + } + + sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_ENABLE, 1); + } else if (cstate.enabled) { + sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_ENABLE, 0); + + clk_bulk_disable_unprepare(SPRD_PWM_NUM_CLKS, chn->clks); + } + + return 0; +} + +static const struct pwm_ops sprd_pwm_ops = { + .apply = sprd_pwm_apply, + .get_state = sprd_pwm_get_state, + .owner = THIS_MODULE, +}; + +static int sprd_pwm_clk_init(struct sprd_pwm_chip *spc) +{ + struct clk *clk_pwm; + int ret, i, clk_index = 0; + + for (i = 0; i < SPRD_PWM_NUM; i++) { + struct sprd_pwm_chn *chn = &spc->chn[i]; + int j; + + for (j = 0; j < SPRD_PWM_NUM_CLKS; ++j) + chn->clks[j].id = sprd_pwm_clks[clk_index++]; + + ret = devm_clk_bulk_get(spc->dev, SPRD_PWM_NUM_CLKS, chn->clks); + if (ret) { + if (ret == -ENOENT) + break; + + dev_err(spc->dev, "failed to get channel clocks\n"); + return ret; + } + + clk_pwm = chn->clks[SPRD_PWM_OUTPUT_CLK].clk; + chn->clk_rate = clk_get_rate(clk_pwm); + } + + if (!i) { + dev_err(spc->dev, "no available PWM channels\n"); + return -EINVAL; + } + + spc->num_pwms = i; + + return 0; +} + +static int sprd_pwm_probe(struct platform_device *pdev) +{ + struct sprd_pwm_chip *spc; + int ret; + + spc = devm_kzalloc(&pdev->dev, sizeof(*spc), GFP_KERNEL); + if (!spc) + return -ENOMEM; + + spc->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(spc->base)) + return PTR_ERR(spc->base); + + spc->dev = &pdev->dev; + platform_set_drvdata(pdev, spc); + + ret = sprd_pwm_clk_init(spc); + if (ret) + return ret; + + spc->chip.dev = &pdev->dev; + spc->chip.ops = &sprd_pwm_ops; + spc->chip.base = -1; + spc->chip.npwm = spc->num_pwms; + + ret = pwmchip_add(&spc->chip); + if (ret) + dev_err(&pdev->dev, "failed to add PWM chip\n"); + + return ret; +} + +static int sprd_pwm_remove(struct platform_device *pdev) +{ + struct sprd_pwm_chip *spc = platform_get_drvdata(pdev); + int ret, i; + + ret = pwmchip_remove(&spc->chip); + + for (i = 0; i < spc->num_pwms; i++) { + struct sprd_pwm_chn *chn = &spc->chn[i]; + + clk_bulk_disable_unprepare(SPRD_PWM_NUM_CLKS, chn->clks); + } + + return ret; +} + +static const struct of_device_id sprd_pwm_of_match[] = { + { .compatible = "sprd,ums512-pwm", }, + { }, +}; +MODULE_DEVICE_TABLE(of, sprd_pwm_of_match); + +static struct platform_driver sprd_pwm_driver = { + .driver = { + .name = "sprd-pwm", + .of_match_table = sprd_pwm_of_match, + }, + .probe = sprd_pwm_probe, + .remove = sprd_pwm_remove, +}; + +module_platform_driver(sprd_pwm_driver); + +MODULE_DESCRIPTION("Spreadtrum PWM Driver"); +MODULE_LICENSE("GPL v2");